65 nm CMOS analog front-end for pixel detectors at the HL-LHC Luigi Gaioni a,c, F. De Canio b,c, M....

65 nm CMOS analog front-endfor pixel detectors at the HL-LHC

Luigi Gaionia,c, F. De Caniob,c, M. Manghisonia,c, Lodovico Rattib,c, Valerio Rea,c, G. Traversia,c

TWEPP 2015 - Topical Workshop on Electronics for Particle Physics 28 September - 02 October, Lisboa

aUniversity of Bergamo

bUniversity of Pavia

cINFN Pavia

1

Outline

• The CHIPIX65 project

• CHIPIX-VFE-1 test structures

• Charge sensitive amplifier

• Charge sensitivity

• Equivalent Noise Charge

• Radiation test

• Threshold discriminator

• Threshold correction circuit

• Conclusions

2L. Gaioni, TWEPP 2015 - Topical Workshop on Electronics for Particle Physics

The CHIPIX65 project

3

• The INFN CHIPIX65 project aims at the development of an innovative 65 nm CMOS chip for pixel detectors in experiments with extreme particle rates and radiation at future High Energy Physics colliders

• This effort is shared at international level with the RD53 Collaboration. CHIPIX65 institutes are part of the funding institutions of RD53 and several key roles of the collaboration are covered by CHIPIX65 members

• In the framework of CHIPIX65 a prototype chip called CHIPIX-VFE-1 has been submitted and a comprehensive characterization activity is ongoing

• This talk is concerned with the design and the experimental characterization of standalone channels, fundamental building blocks for the development of an innovative pixel front-end chip for the HL-LHC

L. Gaioni, TWEPP 2015 - Topical Workshop on Electronics for Particle Physics

Pixel front-end

4

• Single amplification stage for minimum power dissipation

• Krummenacher feedback to comply with the expected large increase in the detector leakage current

• High speed, low power current comparator

• Relatively slow ToT clock – 80 MHz

• 5 bit counter – 400 ns maximum time over threshold

• 30000 electron maximum input charge, ~450 mV preampli output dynamic range

• Selectable gain and recovery current

• Overall current consumption: ~4 uA

CD

CF

VREF

IK

IK/2

Ith

IDAC

5 bit ToT counter

Itr=Gm vout

vout


Submitted test structures

5

preamplifier with MOSFET feedback capacitor

preamplifier with MIM feedback capacitor

preampli (MOSFET feedback cap.) + discri + threshold correction circuit

preampli (MIM feedback cap.) + discri + threshold correction circuit

bias circuits

bias circuits

• Preamplifier output read out through an on-chip analog buffer


Front-end channel configuration

6

charge sensitivity

• 0 high gain (CF=10 fF)

• 1 low gain (CF=20 fF)

IK/2

IK

CF

CD

CINJ

recovery current in the Krummenacher network

• 0 low recovery current (IK=12.5 nA)

• 1 high recovery current (IK=25 nA)

detector emulating capacitor

• 00 CD=0

• 10 CD=50 fF

• 01 CD=100fF

• 11 CD=150 fFcharge injection

• 0 disabled

• 1 enabled


Charge sensitive amplifier

7

• Folded cascode architecture

• Two local feedback networks (M4,M5 and M7,M8) to increase the small signal resistance at the output node

• I1=3 µA, I2=200 nA

0

10

20

30

40

50

60

70

80

1 102 104 106 108

Open-loop Gain [dB]

Frequency [Hz]

Preamplifier gain stage

A0 = 76 dB

f-3dB

= 140 kHz

Simulation data


Response to a MIP signal

• Response of the preamplifier with feedback MOS capacitor (high and low gain and recovery current)

8

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

0 100 200 300 400 500

Preampli output [V]

Time [ns]

- fb MOS cap

- Qin=10 ke-

high Glow I

K

low Ghigh I

K

high Ghigh I

K

low Glow I

K



• Response of the preamplifier with feedback MOS capacitor (varying detector capacitance)

9

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0 20 40 60 80 100

CD=0

CD=50 fF

CD=100 fF

CD=150 fF

Preampli output [V]

Time [ns]

- high gainlow recovery current

- Qin=10 ke-

21.4 ns

33.3 ns

42.2 ns

51.4 ns

• Maximum peaking time tp=51.4 ns for a detector capacitance CD=150 fF

• Reduced peak amplitude and peaking time with respect to post-layout simulations

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0 200 400 600 800 1000

CD=0

CD=50 fF

CD=100 fF

CD=150 fF

G

Preampli output [V]

Time [ns]

post layoutsimulations @ C

D=100 fF


- Qin=10 ke-



• Response of the preamplifier with feedback MIM capacitor (varying detector capacitance)

10

• Slightly faster compared to the feedback MOS cap version of the preamplifier

• Maximum peaking time tp=43 ns for a detector capacitance CD=150 fF

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0 200 400 600 800

CD=0

CD=50 fF

CD=100 fF

CD=150 fF

Preampli output [V]

Time [ns]


- Qin=10 ke-

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0 20 40 60 80 100

CD=0

CD=50 fF

CD=100 fF

CD=150 fF

Preampli output [V]

Time [ns]


- Qin=10 ke-

17.8 ns

29.7 ns

38.9 ns

43.3 ns


Charge sensitivity

• Charge sensitivity, feedback MOS and MIM cap, low recovery current

11

• Standard deviation smaller than 3% of the mean value

• INL smaller than 1.5% in all the configurations

• Slightly higher charge sensitivity for the preamplifier with feedback MIM capacitor

0

50

100

150

200

250

300

350

0 5 10 15 20 25 30

High gainLow gain

Preamplifier Peak Amplitude [mV]

Injected charge [ke-]

CD = 100 fF

S = 10.4 mV/ke-

S = 5.4 mV/ke-

feedback MOS capacitorlow recovery current

0

50

100

150

200

250

300

350

0 5 10 15 20 25 30

High gainLow gain



CD = 100 fF

S = 11.5 mV/ke-

S = 6.0 mV/ke-

feedback MIM capacitorlow recovery current


Detector leakage current

• Charge sensitivity, evaluated for different values of the detector leakage current

12

• Very small variations due to the detector leakage, both for the feedback MOS and MIM cap version of the preamplifier

0

50

100

150

200

250

300

350

0 5 10 15 20 25 30

0 nA10 nA15 nA



CD = 100 fF

feedback MOS capHigh gain, high recovery current

0

50

100

150

200

250

300

350

0 5 10 15 20 25 30

0 nA10 nA15 nA



CD = 100 fF

feedback MIM capHigh gain, high recovery current


Equivalent noise charge

• ENC for preamplifier with MOS and MIM feedback capacitance

13

80

100

120

140

160

180

200

-50 0 50 100 150 200

High gainLow gain

ENC [e rms]

PA input capacitance [fF]

feedback MIM capacitancelow recovery current

• ENC increasing with the preamplifier input capacitance

• Higher ENC for the preamplifier configured in low gain mode

• Measured ENC in fairly good agreement with simulation data

60

80

100

120

140

160

180

200

-50 0 50 100 150 200

High gainLow gainpost-layout

ENC [e rms]


feedback MOS capacitancelow recovery current

high gainsimulationdata


Radiation hardness

14

• No significant changes in charge sensitivity

• ENC increase more pronounced for higher values of the total PA input capacitance

• 24% ENC increase at 800 Mrad, for a total input capacitance of 100 fF

80

100

120

140

160

180

200

220

-50 0 50 100 150 200

fresh500Mrad800Mrad

ENC [e rms]


MOS feedback capacitanceHigh gain, low recovery current

0

50

100

150

200

250

300

350

0 5 10 15 20 25 30

Fresh

500Mrad



CD = 50 fF

feedback MIM capHigh gain, low recovery current

• Test structures have been irradiated to a TID up to 800 Mrad with 10 MeV protons


0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 50 100 150 200 250 300

ttffssfssf

Discriminator Output [V]

Time [ns]

Qin = 10 ke-

Four corners simulation

5

10

15

20

25

30

35

40

1 10

Response time [ns]

Input charge [ke-]

t_response < 25 ns @ Qin > 900 e-

Discriminator output and FE response time

• Problems with test of the channels with discriminator – likely due to the (quite large) custom designed digital buffer used to read out the discriminator signal. Simulation data shown here

15

• Discriminator current consumption ≈ 1 µA

• FE response time < 25 ns for input charge > 900 e- in the tt corner (750 e- threshold)

Simulation data

Simulation data


Threshold correction DAC

16

• Global (chip-wide) threshold setting through external (outside the pixel) bias

• Local threshold tuning through a 4-bit binary weighted DAC

• Power dissipation: ~0.18 uW


Threshold correction DAC

• Input-output DAC characteristic

• INL and DNL for the tested samples

17L. Gaioni, TWEPP 2015 - Topical Workshop on Electronics for Particle Physics

0.28

0.285

0.29

0.295

0.3

0.305

0.31

0 20 40 60 80 100 120 140 160

beforeafter

Threshold [V]

Pixel cell #

Threshold dispersion

18

Simulation data

• Threshold dispersion before correction 380 e-

• Threshold dispersion after correction 35 e-


Conclusions

19

• A prototype chip called CHIPIX-VFE-1 has been submitted in a 65 nm CMOS technology in the framework of the CHIPIX65 project. A comprehensive characterization of the standalone channels has been carried out

• Test focused on the charge preamplifier in its different configurations. Problems with the test of the discriminator. A new chip has been submitted in order to fix such problems. Characterization activity of the discriminator starting in the next weeks

• Small difference from sample to sample in the main charge preamplifier parameters

• With respect to simulation results, experimental ones show a slightly smaller charge sensitivity and a longer peaking time. ENC in fairly good agreement

• Radiation hardness test point out that charge sensitivity is not affected by radiation. A moderate increase in the ENC is detected at extremely high TID levelsL. Gaioni, TWEPP 2015 - Topical Workshop on Electronics for Particle Physics

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65 nm CMOS analog front-end for pixel detectors at the HL-LHC Luigi Gaioni a,c, F. De Canio b,c, M....

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