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VLSI
Design
CMOS Transistor Theory
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EE 447 VLSI Design3: CMOS Transistor Theory 2
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
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EE 447 VLSI Design3: CMOS Transistor Theory 3
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C ((V/(t)->(t = (C/I)(V
Capacitance and current determine speed
Also explore what a degraded level really means
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EE 447 VLSI Design3: CMOS Transistor Theory 4
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < Vtdepletion region
(c)
+-
Vg>Vt
depletion regioninversion regionExample with an NMOS
capacitor
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EE 447 VLSI Design3: CMOS Transistor Theory 5
Terminal Voltages
Mode of operation depends on Vg, Vd, Vs Vgs = Vg Vs Vgd = Vg Vd Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
However, Vds u 0
NMOS body is grounded. First assume source may begrounded or may be at a voltage above ground.
Three regions of operation Cutoff
Linear
Saturation
Vg
Vs Vd
Vgd
Vgs
Vds
-
+
-
+
-
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EE 447 VLSI Design3: CMOS Transistor Theory 6
nMOS Cutoff
Let us assume Vs = Vb No channel, ifVgs = 0
Ids
= 0+-
Vgs
= 0
n+ n+
+-Vgd
p-type body
b
g
s d
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EE 447 VLSI Design3: CMOS Transistor Theory 7
NMOS Linear
Channel forms ifVgs >Vt No Currernt ifVds = 0
Linear Region:
IfVds > 0, Current flows
from d to s ( e- from s to d)
Ids increases linearlywith Vds ifVds >Vgs Vt.
Similar to linear resistor
+-
Vgs>Vt
n+ n+
+-
Vgd = Vgs
+-
Vgs>Vt
n+ n+
+-
Vgs>Vgd>Vt
Vds = 0
0 < Vds < Vgs-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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EE 447 VLSI Design3: CMOS Transistor Theory 8
NMOS Saturation
Channel pinches off ifVds >Vgs Vt.
Ids independent ofVds, i.e., current saturates
Similar to current source
+-
Vgs>Vt
n+ n+
+-
Vgd < Vt
Vds>Vgs-Vt
p-type body
b
g
s d Ids
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EE 447 VLSI Design3: CMOS Transistor Theory 9
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel
How fast is the charge moving
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EE 447 VLSI Design3: CMOS Transistor Theory 10
Channel Charge
MOS structure looks like parallel plate capacitor whileoperating in inversion
Gate oxide (dielectric) channel
Qchannel =
n+ n+
p-t pe od
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs Vd
g
n+ n+
p-t pe od
W
L
tox
SiO2 gate oxide(good insulator, Iox = 3.9)
polysilicongate
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EE 447 VLSI Design3: CMOS Transistor Theory 11
Channel Charge
MOS structure looks like parallel plate capacitor whileoperating in inversion
Gate oxide channel
Qchannel = CV C =
n+ n+
p-t pe od
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-t pe od
W
L
tox
SiO2 gate oxide(good insulator, Iox = 3.9)
polysilicongate
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EE 447 VLSI Design3: CMOS Transistor Theory 12
Channel Charge
MOS structure looks like parallel plate capacitor whileoperating in inversion
Gate oxide channel
Qchannel = CV C = Cg = IoxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
+ n+
p-t pe d
+
Vgd
g te
+ +
s rce
-
Vgs-
dr in
Vds
c nnel-
Vg
Vs Vd
g
n+ n+
p-t pe d
W
L
t x
SiO2 g te xide(g d ins l t r, Iox = 3.9)
polysilicongate
Cox = Iox / tox
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EE 447 VLSI Design3: CMOS Transistor Theory 13
Carrier velocity
Charge is carried by e-
Carrier velocity vproportional to lateral E-fieldbetween source and drain
v= QE Q called mobility E = Vds/L
Time for carrier to cross channel:
t= L/v
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EE 447 VLSI Design3: CMOS Transistor Theory 14
NMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time teach carrier takes to cross
channel
ox 2
2
ds
ds gs t ds
ds gs t ds
QI
t
W VC V V V
LV
V V V
Q
F
!
!
!
ox=W
F
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EE 447 VLSI Design3: CMOS Transistor Theory 15
NMOS Saturation I-V
IfVgd < Vt, channel pinches off near drain
When Vds >Vdsat = Vgs Vt Now drain voltage no longer increases
current
22
2
dsatds gs t dsat
gs t
V I V V V
V V
F
F
!
!
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EE 447 VLSI Design3: CMOS Transistor Theory 16
NMOS I-V Summary
2
cuto
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
I F
F
"
Shockley1st order transistor models (valid forLarge channel devices only)
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EE 447 VLSI Design3: CMOS Transistor Theory 17
Example
For a 0.6 Qm process (MOSIS site)
From AMI Semiconductor
tox = 100
Q = 350 cm2/V*s
Vt = 0.7 V
Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2 P
14
2
8
3.9 8.85 10350 120 /
100 10ox
W W WC A V
L L L F Q Q
y ! ! !
0 1 2 3 4 5
0
0 .5
1
1 .5
2
2 .5
Vds
Ids
(mA)
Vgs = 5
Vgs = 4
Vgs = 3
Vgs = 2
Vgs = 1
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EE 447 VLSI Design3: CMOS Transistor Theory 18
PMOS I-V
All dopings and voltages are inverted for PMOS
Mobility Qp is determined by holes
Typically 2-3x lower than that of electrons Qn
120 cm2/V*s in AMI 0.6 Qm process
Thus PMOS must be wider to provide same current
In this class, assume Qn /Qp = 2
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EE 447 VLSI Design3: CMOS Transistor Theory 19
Capacitance
Any two conductors separated by an insulator havecapacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
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EE 447 VLSI Design3: CMOS Transistor Theory 20
Gate Capacitance
Approximate channel as connected to source
Cgs = IoxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/Qm
n+ n+
p-t pe dy
W
L
ti gate ide
(good ins lator, Iox
. I )
polysilicongate
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EE 447 VLSI Design3: CMOS Transistor Theory 21
Diffusion Capacitance
Csb, Cdb Undesirable, called parasiticcapacitance
Capacitance depends on area and perimeter
Use small diffusion nodes Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process
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EE 447 VLSI Design
3: CMOS Transistor Theory 22
Pass Transistors
We have assumed source is grounded
What if source > 0? e.g. pass transistor passing VDD
VDDVDD
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EE 447 VLSI Design
3: CMOS Transistor Theory 23
NMOS Pass Transistors
We have assumed source is grounded What if source > 0?
e.g. pass transistor passing VDD L
et Vg = VDD Now ifVs >VDD-Vt, Vgs < Vt Hence transistor would turn itself off
NMOS pass transistors pull-up no higher than VDD-Vtn Called a degraded 1 Approach degraded value slowly (low Ids)
PMOS pass transistors pull-down no lower than Vtp Called a degraded 0
VDDVDD
Vs
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EE 447 VLSI Design
3: CMOS Transistor Theory 24
Pass Transistor Ckts
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
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EE 447 VLSI Design
3: CMOS Transistor Theory 25
Pass Transistor Ckts
VDD
VDD Vs VDD-Vtn
VSS
Vs |Vtp|
VDD
VDD
-Vtn VDD-VtnVDD-Vtn
VDD
VDD
VDD
VDD
VDD
VDD
-Vtn
VDD
-2Vtn
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EE 447 VLSI Design3: CMOS Transistor Theory 26
Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay
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EE 447 VLSI Design3: CMOS Transistor Theory 27
RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width
Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kC
R/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
ku
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EE 447 VLSI Design3: CMOS Transistor Theory 28
RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/Qm of gate width
Values similar across many processes
Resistance R } 6 K;*Qm in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 P) Or maybe 1 Qm wide device
Doesnt matter as long as you are consistent
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EE 447 VLSI Design3: CMOS Transistor Theory 29
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2
1
Y 2
1
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EE 447 VLSI Design3: CMOS Transistor Theory 30
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C
2C
R
2
1
Y
C
2C
Y2
1
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EE 447 VLSI Design3: CMOS Transistor Theory 31
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1
Y
C
2C
C
2C
C
2C
RY
2
1
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EE 447 VLSI Design3: CMOS Transistor Theory 32
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1
Y
C
2C
C
2C
C
2C
RY
2
1
d = 6RC