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Chapter 7

Counters and Registers

2

7-1

Asynchronous(ripple)counters

3

Asychronous Counters(Cont.)

Each FF output drives the CLK input of the next FF.

FFs do not change states in exact synchronism with

the applied clock pulses.

There is delay between the responses of successive

FFS.

It is also often referred to as a ripple counterdue

to the way the FFs respond one after another in a

kind of rippling effect.

4

Signal Flow

It is conventional in circuit schematics to draw the

circuits(whenever possible) such that the signal flow

is from left to right, with inputs on the left and

outputs one the right.

In this chapter, we will often break with this

convention, especially in diagrams showing counters.

5

Example

The counter in Figure 7-1 starts off in the 0000

state, and then clock pulses are applied. Some time

later the clock pulses are removed, and the counter

FFs read 0011. How many clock pulses have occurred?

6

Example

The counter in Figure 7-1 starts off in the 0000

state, and then clock pulses are applied. Some time

later the clock pulses are removed, and the counter

FFs read 0011. How many clock pulses have occurred?

Answer:3 or 19 or 163

N*16 + 3 (N is unknown)

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MOD Number

The counter in Figure 7-1 has 16 distinct states,

thus, it is a MOD-16 ripple counter.

The MOD number can be increased simply by adding more

FFs to the counter. That is

MOD number = 2N

Example

A counter is needed that will count the number of

items passing on a conveyor belt. A photocell and

light source combination is used to generate a

single pulse each time an item crosses its path.

The counter must be able to count as many as one

thousand items. How many FFs are required?

8

Frequency division

In any counter, the signal at the output of the last FF(i.e.,the MSB) will have a frequency equal to the input clockfrequency divided by the MOD number of the counter.Such circuits are known as divide-by-N counters.

9 10

Example

The first step involved in building a digital clock

is to take the 60-Hz signal and feed it into a

Schmitt-trigger, pulse-shaping circuit to produce a

square wave as illustrated in Figure 7-3. The 60HZ

square wave is then put into a MOD-60 counter, which

is used to divide the 60-HZ frequency by exactly 60

to produce a 1-HZ waveform. This 1-HZ waveform is fed

to a series of counters, which then count seconds,

minutes, hours, and so on. How many FFs are requiredfor the MOD-60 counter?

11 12

Review Questions

True or False: In an asychronous counter, all FFs

change states at the same time.

Assume that the counter in Figure 7-1 is holding the

count 0101. What will be the count after 27 clock

pulses?

What would be the MOD number of the counter if three

more FFs were added?

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7-2 Counters with MOD NUMBER < 2N

MOD-6 counter produced by clearing a MOD-8 counter whena count of six occurs.

14

State Transition Diagram

15

Example

What will be the status of the LEDs when the counter

is holding the count of five?

What will the LEDs display as the counter is clocked

by a 1-kHz input?

Will the 110 state be visible on the LEDs?

16

Changing the MOD number

Determine the MOD number of the counter in Figure 7-6(a). Also determine the frequency at the D output

17

Changing the MOD number

Construct a MOD-10 counter that will countfrom 0000(zero) through 1001(decimal 9)

18

Decade Counters/BCD counters

Decade counter

Any counter has 10 distinct states, no matter what

the sequence.

BCD counter

A decade counter counts in sequence from

0000(zero) through 1001(decimal 9).

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Example

Construct an appropriate MOD-60 counter.

20

Review Questions

What FF outputs should be connected to the clearing

NAND gate to form a MOD-13 counter?

True of False: All BCD counters are decade counters.

What is the output frequency of a decade counter that

is clocked from a 50-KHz signal?

21

7-3 IC Asynchronous counters

RESET IN OUTPUT

___ ___Ro1 Ro2 | Qd Qc Qb Qa--------------------------

1 1 | 0 0 0 00 X | COUNTX 0 | COUNT

22

23

Example

Show how the 74LS293 should be connected to operate

as a MOD-16 counter with a 10-kHz clock input.

Determine the frequency at Q3.

24

Example

Show how to wire the 74LS293 as a MOD-10 counter

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Example

Show how to wire a 74LS293 as a MOD-14 counter

26

Example

A way to get a MOD-60 counter is shown below. Explainhow this circuit works.

27

Review Questions

A 2-kHz clock signal is applied to of a 74LS293.

What is the frequency at Q3?

What would be the final output frequency if the order

of the counters were reversed in Figure 7-12?

What is the MOD number of a 74HC4040 counter?

What would the notation DIV64 mean on a counter

symbol?

Which outputs would you connect to an AND gate to

convert the 74HC4024 to a MOD-120 counter?

1CP

28

7-4 Asychronous Down counter

29

Review Questions

What is the difference between the counting sequence

of an up counter and a down counter?

Describe how an asynchronous down-counter circuit

differs from an up-counter circuit.

30

7-5 Propagation delay in ripple counters

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Discussion on Ripple Counter

For proper counter operation, we need

pdclock tNT

Asychronous counters are not useful at very highfrequencies, especially for large number of bits.

Another problem caused by propagation delays inasychronous counters occurs when the counteroutputs are decoded, as is discussed later.

32

Review Questions

Explain why a ripple counters maximum frequency

limitation decreases as more FFs are added to the

counter.

A certain J-K flip-flop has tpd=12 ns. What is the

largest MOD counter that can be constructed from

these FFs and still operate up to 10 MHz?

33

7-6 Synchronous(Parallel)

counters

Synchronous(parallel) counters

All of the FFs are triggered simultaneously by the

clock input pulses.

Overcome the problem caused by FF propagation

delay.

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Circuit operation

Only those FFs that are supposed totoggle on that NGT should haveJ=K=1 when that NGT occurs.

35

JK FF

J K Q

0 0 No Change

0 1 0

1 0 1

1 1 Toggle

Synchronous Counter

Q Q J K

0 0 0 d

0 1 1 d

1 0 d 1

1 1 d 0

36

Synchronous Counter Modulo 6

CP

0

1

2

3

4

5

6

Q2

0

0

0

0

1

1

0

Q1

0

0

1

1

0

0

0

Q0

0

1

0

1

0

1

0

J0

1

d

1

d

1

d

K0

d

1

d

1

d

1

J1

0

1

d

d

0

0

K1

d

d

0

1

d

d

J2

0

0

0

1

d

d

K2

d

d

d

d

0

1

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J0 Q2Q1

Q0 00 01 11 10

0

1

1

d

1

d

d

d

1

d

J1 Q2Q1

Q0 00 01 11 10

0

11

d

d

d

d

J2 Q2Q1

Q0 00 01 11 10

0

11

d

d

d

d

K0Q2Q1

Q0 00 01 11 10

0

1

d

1

d

1

d

d

d

1

K1Q2Q1

Q0 00 01 11 10

0

1

d

d 1

d

d

d

d

K2Q2Q1

Q0 00 01 11 10

0

1

d

d

d

d

d

d 1

J0

= 1

J1

= Q2Q0

J2

= Q1Q0

K0

= 1

K1

= Q0

K2

= Q038

Logic diagram

a

Q

Q

b

Q

Q

c

Q

Q

Qa Qb Qc

(LSB) (MSB)

CP

clr clr clr

1

J

K

J

K

J

K

clr

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Synchronous Counter 1 3 5 7 1

CP

0

1

2

3

4

Q2

0

0

1

1

0

Q1

0

1

0

1

0

Q0

1

1

1

1

1

J0

d

d

d

d

K0

0

0

0

0

J1

1

d

1

d

K1

d

1

d

1

J2

0

1

d

d

K2

d

d

0

1

40

J0 Q2Q1

Q0 00 01 11 10

0

1

d

d

d

d

d

d

d

d

J1 Q2Q1

Q0 00 01 11 10

0

1

d

1

d

d

d

d

d

1

J2 Q2Q1

Q0 00 01 11 10

0

1

d

0

d

1

d

d

d

d

K0Q2Q1

Q0 00 01 11 10

0

1

d d d d

K1Q2Q1

Q0 00 01 11 10

0

1

d

d

d

1

d

1

d

d

K2Q2Q1

Q0 00 01 11 10

0

1

d

d

d

d

d

1

d

0

J0

= 1,0

J1 = 1

J2

= Q1

K0

= 0

K1 = 1

K2

= Q1

41 42

Logic diagram

a

Q

Q

b

Q

Q

c

Q

Q

Qa Qb Qc

(LSB) (MSB)

CP

set clr clr

1

J

K

J

K

J

K

clr

0

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(Synchronous Counter)

44

45

.....(Synchronous Counter)

46

47

Advantage of Synchronouscounters over Asychronous

States are changed simultaneously.

Total delay

FFtpd+ANDgate tpd

Actual Ics

74ALS160/162, 74HC160/162: Synchronous decade

counters

74ALS161/163, 74HC161/163: Synchronous MOD-16

counters

48

Example

Determine fmax for the counter of Figure 7-17(a) if

tpdfor each FF is 50ns and tpdfor each AND gate is

20 ns. Compare this value with fmax for a MOD-16

ripple counter.

What must be done to convert this counter to MOD-32?

Determine fmax for the MOD-32 parallel counter.

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Review Questions

What is the advantage of a synchronous counter over

an asynchronous counter? What is the disadvantage?

How many logic devices are required for a MOD-64

parallel counter?

What logic signal drives the J,K inputs of the MSB

flip-flop for the counter of question 2?

50

7-7 Synchronous Down and

UP/Down counters

51

Example

What problems might be caused if the UP/Down signal

changes levels on the NGT of the clock?

52

Presettable counters

53

Synchronous Presetting

Examples of IC counters

74ALS160, 74ALS161, 74ALS612, 74ALS163

74Hc160, 74HC161, 74HC162, 74HC163

54

Review Questions

What is meant when we say that a counter is

presettable?

Describe the difference between asynchronous and

synchronous presetting.

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The 74ALS193/HC193

56

Example

57

Example

58

Variable MOD Number using the

74ALS193/HC193

59

Multistage Arrangement

60

Review Questions

Describe the function of the input PL and P0 to P3.

Describe the function of the MR input

True or False: The 74HC193 cannot be preset while MR

is active.

What logic levels must be present at CPD, PL and MR

in order for the 74ALS193 to count pulses that appear

at CPU?

What would be the maximum counting range for a four-

stage counter made up of 74HC193 Ics?

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7-11 Decoding a counter

Mentally decoding the binary states of the LEDs

Becomes inconvenient as the size of the counter

increases

Electronically decoding

To control the timing or sequencing of operations

automatically without human intervention.

Active-High Decoding

Active-Low Decoding

BCD counter decoding

62

Active-High Decoding

63

Example

How many AND gates are required to decode completely

all of the states of a MOD-32 binary counter? What

are the inputs to the gate that decodes for the count

of 21?

64

Active-LOW Decoding

65

BCD Counter Decoding

66

Review Questions

How many gates are needed to decode a six-bit counter

fully?

Describe the decoding gate needed to produce a LOW

output when a MOD-64 counter is at the counter of 23.

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7-12 Decoding Glitches

68

Strobing

69

Review Questions

Explain why the decoding gates for an asynchronous

counter may have glitches on their outputs.

How does strobing eliminate decoding glitches?

70

Cascading BCD counters

71

7-15 Shift-Register Counters

72

Starting a Ring Counter

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Johnson Counter

74

Decoding A Johnson Counter

75

Review Questions

Which shift-register counter requires the most FFs for a

given MOD number?

Which shift-register counter requires the most decoding

circuitry?

How can a ring counter be converted to a Johnson counter?

True or False:

The outputs of a ring counter are always square waves.

The decoding circuitry for a Johnson counter is simpler

than for a binary counter Ring and Johnson counters are synchronous counters.

How many FFs are needed in a MOD-16 ring counter? How many

are needed in a MOD-16 Johnson Counter?