7520950 Toshiba CN27E90 TV Technical Training Manual

COLOR TELEVISIONCN27E90, CX32E70CN32E90, CN35E15CF35E50, CX35E60CX35E70, CX35E81CN35E90, CN35E95

TECHNICAL TRAINING MANUALN5SS (TG-1, C) CHASSIS

NTDCTV05

PRINTED IN JAPAN Aug. 1995 So

2

Contents

SECTION IOUTLINE ...................................................................... 61. OUTLINE OF N5SS CHASSIS (CN32E90, CN35E90) .................................................................... 72. PC BOARD CONFIGURATION ........................................................................................................ 73. MAJOR SPECIFICATIONS (NEW FUNCTIONS IN ADDITION TO THOSE OF N5SS) ........ 74. MODIFICATIONS ON CHASSIS ..................................................................................................... 75. CONSTRUCTION OF CHASSIS ...................................................................................................... 86. LOCATION OF CONTROLS............................................................................................................ 97. CN32D90 BLOCK DIAGRAM ......................................................................................................... 138. [US, CANADA] SPECIFICATION FOR MODEL's 1995 ............................................................ 14

SECTION IITUNER, IF/MTS/S.PRO MODULE......................... 161. CIRCUIT BLOCK ............................................................................................................................. 172. TUNER ................................................................................................................................................ 183. IF/MTS/S.PRO MODULE................................................................................................................. 194. PIP TUNER ......................................................................................................................................... 23

SECTION IIICHANNEL SELECTION CIRCUIT........................ 241. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM .................................................... 252. OPERATION OF CHANNEL SELECTION CIRCUIT ................................................................ 253. MICROCOMPUTER......................................................................................................................... 264. MICROCOMPUTER TERMINAL FUNCTION ........................................................................... 275. EEPROM (QA02) ............................................................................................................................... 296. ON SCREEN FUNCTION................................................................................................................. 297. SYSTEM BLOCK DIAGRAM ......................................................................................................... 308. LOCAL KEY DETECTION METHOD .......................................................................................... 319. REMOTE CONTROL CODE ASSIGNMENT............................................................................... 3210. ENTERING TO SERVICE MODE ................................................................................................ 3511. TEST SIGNAL SELECTION ......................................................................................................... 3512. SERVICE ADJUSTMENT .............................................................................................................. 3513. FAILURE DIAGNOSIS PROCEDURE ......................................................................................... 3614. TROUBLE SHOOTING CHART .................................................................................................. 38

SECTION IVAUDIO OUTPUT CIRCUIT ..................................... 411. OUTLINE............................................................................................................................................ 422. AUDIO OUT IC .................................................................................................................................. 43

3

SECTION VA/V SWITCHING CIRCUIT .................................... 441. OUTLINE............................................................................................................................................ 452. IN / OUT TERMINALS..................................................................................................................... 453. CIRCUIT OPERATION .................................................................................................................... 45

SECTION VIVIDEO PROCESSING CIRCUIT ............................ 471. OUTLINE............................................................................................................................................ 482. SIGNAL FLOW.................................................................................................................................. 483. CIRCUIT OPERATION .................................................................................................................... 48

SECTION VIIV/C/D/IC ...................................................................... 521. OUTLINE............................................................................................................................................ 532. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE

CONTROLS...................................................................................................................................... 533. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE.......................... 534. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE................................. 535. LOW COST OF IC ............................................................................................................................ 53

SECTION VIIIPIP MODULE ............................................................. 55

SECTION IXSYNC SEPARATION, H-AFC, H-OSCILLATOR CIRCUITS .............................. 581. SYNC SEPARATION CIRCUIT ...................................................................................................... 592. H AFC (Automatic Frequency Control) CIRCUIT......................................................................... 603. H OSCILLATOR CIRCUIT ............................................................................................................. 61

SECTION XVERTICAL OUTPUT CIRCUIT ............................. 631. OUTLINE............................................................................................................................................ 642. V OUTPUT CIRCUIT ....................................................................................................................... 65

4

SECTION XIHORIZONTAL DEFLECTION CIRCUIT.............. 691. OUTLINE............................................................................................................................................ 702. HORIZONTAL DRIVE CIRCUIT................................................................................................... 703. BASIC OPERATION OF HORIZONTAL DRIVE ........................................................................ 714. HORIZONTAL OUTPUT CIRCUIT ............................................................................................... 745. HIGH VOLTAGE GENERATION CIRCUIT................................................................................. 796. X-RAY PROTECTION CIRCUIT ................................................................................................... 827. OVER CURRENT PROTECTION CIRCUIT................................................................................ 838. KINK CORRECTION CIRCUIT.....................................................................................................84

SECTION XIIDEFLECTION DISTORTION CORRECTION CIRCUIT (Side DPC Circuit) .............................. 851. DEFLECTION DISTORTION CORRECTION IC (TA8859P) .................................................... 862. SIDE DPC............................................................................................................................................ 873. DIODE MODULATOR CIRCUIT ................................................................................................... 884. ACTUAL CIRCUIT ........................................................................................................................... 89

SECTION XIIICLOSED CAPTION/EDS CIRCUIT ....................... 921. OUTLINE............................................................................................................................................ 932. DATA TRANSMISSION FORMAT ................................................................................................ 933. DISPLAY FORMAT........................................................................................................................... 944. CIRCUIT OPERATION .................................................................................................................... 95

SECTION XIVPOWER CIRCUIT ..................................................... 981. OUTLINE............................................................................................................................................ 992. RECTIFYING CIRCUIT AND STANDBY POWER SUPPLY................................................... 1003. MAIN SUPPLY CIRCUIT............................................................................................................... 1004. OUTLINE OF CURRENT RESONANT TYPE SUPPLY ........................................................... 1015. FUNDAMENTAL THEORY........................................................................................................... 1016. ACTUAL CIRCUIT ......................................................................................................................... 1027. OTHER POWER CIRCUIT ........................................................................................................... 1058. PROTECTOR MODULE (Z801) .................................................................................................... 106

5

SECTION XVDSP CIRCUIT .......................................................... 1091. ORIGINS OF DOLBY SURROUND ............................................................................................. 1102. THE DOLBY MP MATRIX ............................................................................................................ 1103. THE DOLBY SURROUND DECODER .........................................................................................1114. DSP CIRCUIT ...................................................................................................................................1115. DSP (Digital Surround Processor) IC ............................................................................................. 1146. SURROUND CIRCUIT ................................................................................................................... 1167. INPUT BALANCE CIRCUIT ......................................................................................................... 1168. MATRIX CIRCUIT ......................................................................................................................... 1179. FILTER CIRCUIT (ANTI-ALIAS FILTER)................................................................................. 11710. DSP CIRCUIT (DELAY) ............................................................................................................... 11811. 7 kHz LOW PASS FILTER ........................................................................................................... 11912. DOLBY NR CIRCUIT ................................................................................................................... 12013. DSP FRONT ADDITION CIRCUIT ............................................................................................ 12114. BUS CONVERTER ........................................................................................................................ 12215. NEUTRAL BIAS ............................................................................................................................ 12216. AUDIO OUTPUT AMPLIFIER (For Rear SP) .......................................................................... 12317. TROUBLESHOOTING CHART ................................................................................................. 124

SECTION XVIFAILURE DIAGNOSIS PROCEDURES............... 1251. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES........................................... 1262. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES......................................... 1273. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT .............................. 1284. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ........................... 1295. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE ............................................................. 1306. VIDEO CIRCUIT DIAGNOSIS PROCEDURES......................................................................... 131

6

SECTION IOUTLINE

7

1. OUTLINE OF N5SS CHASSIS(CN32E90, CN35E90)

The N5SS chassis is a complete bus control type chassis where the deflection circuit is controlled by a newlydeveloped I2C-bus line control system.

2. PC BOARD CONFIGURATION

(1) Signal unit(2) Power/def unit(3) A/V, CRT-D, SP-TERM(4) CCD, comb (CN32E90)

Digital comb (CN35E90)(5) D.S.P unit(6) C.C, EDS/R.G.B SW

3. MAJOR SPECIFICATIONS (NEWFUNCTIONS IN ADDITION TO THOSEOF N5SS)

(1) EOS (Extended-Data-Service)(2) Center-Ch-Audio-Input provided

4. MODIFICATIONS ON CHASSIS(1) Serviceability improved with direct, front access system

employed.(2) One touch cabinet securing (CN32E90) to the chassis.(3) Improved serviceability with the bus control system

employed for the defection circuits.(4) Improved serviceability with the white balance bus

control system employed.(5) Digital comb/CCD miniaturized into a socketable size.

8 Fig. 1-1

5. CONSTRUCTION OF CHASSIS

REAR AMP circuit

CONVERTER trans

POWER/DEF circuit

H.OUT

H.OUT trans

DPC circuit

V. OUT

RF SW

A/V circuit

CRT circuit

PIP circuit

CCD circuit

DPC circuit

EDS, RGB SW circuit

AUDIO OUT

IF/MTS/A-PROmodule

SIGNAL circuit

9

6. LOCATION OF CONTROLS6-1. TV Set

For specific use of each control, consult the corresponding page numbers in brackets.

Fig. 1-2

POWER

Front View

Press to openthe door

Behind the door

VIDEO/AUDIO INjacks <VIDEO 3>

DEMO button

MENU button

CHANNEL buttons

VOLUME-/+buttons

buttons

ANT/VIDEO buttonADV button

POWER indicator

POWER button

Remote sensor

10

Fig. 1-3

Rear view

ANTenna terminals

EXTernal SPEAKERterminals

MAIN SPEAKERswitch

REAR SPEAKERterminals

S-VIDEO IN jack <VIDEO 1>

VARiable AUDIO OUTjacks

VIDEO AUDIO OUTjacks

PIP AUDIO OUTjacks

VIDEO/AUDIO IN jacks<VIDEO 2>

VIDEO/AUDIO IN jacks<VIDEO 1>

11

6-2 Location of Controls (Remote Control)

Only the buttons that are used to operate the TV set are described here.For details on the use of each control, refer to pages in brackets.

Fig. 1-4

SET UP button

OPTION button

EXIT button

CHANNEL buttons

Aim at the remote sensor on the TV

Learn/Transmit indicator

EDS button

TV/CABLE/VCR/AUX switchSet to "TV" to control the TV.

TV/VIDEO

Channel Number buttons

PIP function buttons

AUDio button

PICture button

RESET button

ANT 1/2 button

C.CAPT button

CYS/SBS button

Learning buttons

You can use these eightbuttons only as Learningfunction buttons.They are not affected by Mode selection (TV/CABLE/VCR/AUX).

To operate buttons inside the cover,slide the cover down and toward you.

TIMER button

RECALL button

POWER button

MUTE button

VOLUME buttons

RTN buttons

-\+ buttonsFAV -/+ buttons

DSP/SUR button

DSP F/R button

LEAR/USE switch

12

6-3 Monitor Panel

This TV set is equipped with S-VIDEO INPUT jacks,VIDEO/AUDIO INPUT jacks, VIDEO/AUDIO OUTPUTjacks, VARIABLE AUDIO OUTPUT jacks, PIP AUDIOOUTPUT jacks and EXTERNAL SPEAKER terminals forconnecting your desired video/audio equipment.

, , VIDEO 1/VIDEO 2/VIDEO 3 IN Jacks —provide for direct connection of video devices(VCR, video disc player, camcorder, etc.) withvideo/audio outputs.

, S-VIDEO IN Jacks —provide for direct S-videoconnection from an VCR or a video discplayer. The TV's VIDEO 1/3 audio jacks canalso be used to connect the VCR's audio cables.

VIDEO/AUDIO OUT Jacks --- provide fixed-level audio and video outputs from whatever isdisplayed on the screen.

VARIABLE AUDIO OUT Jacks --- feedvolume-controlled stereo audio out fromwhatever is displayed on the screen, allowsconnection of audio amplifier and lets you adjustsound level with TV's remote.

PIP AUDIO OUT Jacks — provide fixed-levelaudio outputs from whatever is displayed on thePIP window screen.

EXTERNAL SPEAKER Terminals — providefor direct connection of external speakers.

MAIN SPEAKER Switch — lets you turn offTV's built-in speakers so that sound will insteadcome through speakers connected toEXTERNAL SPEAKER terminals.

REAR SPEAKER Terminals — provide fordirect connection of the supplied SurroundSpeakers.

TV Front

TV Rear

10 11 1 2 8 6

74935

Fig. 1-5

13

7. CN32D90 BLOCK DIAGRAM

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VOLTAGE REG.OVER VOLTAGEOVER HEAT STR-

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Fig. 1-6

14

8. [US, CANADA] SPECIFICATION FOR MODEL's 1995

CHASSIS C C C C C

MODEL Nbr CN27E90 CX32E70 CN32E90 CE35E15 CF35E50DERIV

SPECIFICATION HITACHI TDD TDD *TDD *TDD

1 Picture Tube *FST-D/T NF-D/T NF-D/T *FST-D/T FST-D/T2 Channel Capacity 181ch 181ch 181ch 181ch 181ch3 C. Caption ● ● ● ● ●

4 MTS with dbx ● ● ● ● ●

5 Bass, Tre, Balance ● ● ● ● ●

6 Sub-Audio-Program ● ● ● ● ●

7 Remote band unit *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Unive (36k) *Unive (36k)8 Picture-in-Picture ● (2TN) ● (2TN) ● (2TN) *● (1TN) ● (1TN)9 LED Indicators (RED) ● (Power) ● (Power) ● (Power) *● (Power) ● (Power)

10 Local Keys 8key 8key 8key 8key 8key

11 Dolby Surround — — ● — —12 Dig-Sound Processor — — ● (DSP4ch) — —13 Front Surround ● ● — ● ●

14 Cyclone ABX ● — ● — —15 Sub-Bass-System — ● — — —

16 Audio Output *10Wx2 & 13W 10Wx2 10Wx2 & 10Wx2 10Wx213W & 5Wx2

17 Speaker Size & Nbr *80x120x2 70x130x2 80x120x2 70x130x2 70x30x2 & 100R (Hon) 100R & REAR

18 Comb Filter *● (GLS) ● (CCD) ● (CCD) ● (CCD) ● (GLS)19 Dy-Quadruple Focus — — — — —20 Scan Velocity Modu ● ● ● ● ●

21 Vert Contour Corre ● ● ● ● ●

22 Black Level Expand ● ● ● ● ●

23 Flesh Tone Correct *● ● ● ● ●

24 Dynamic Noise Reduc *● ● ● ● ●

25 Picture Preference ● ● ● ● ●

26 Horiz Resolution 650 700 700 800 800

27 Parental-Ch Lock ● ● ● ● ●

28 Channel Label (32ch) ● ● ● ● ●

29 3-Language Display ● ● ● ● ●

30 Clock/Off-Timer *●/● ●/● ●/● ●/● ●/●31 Favorite Channel *● *● *● *● *●

32 Extended-Data-Servi *● *● *● *● *●

33 Star-Sight-decoder — — — — —

34 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1) ● (1)35 Audio, Video-In/Out 1+2/— 1+2/1 1+2/1 *3/1 3/136 Front AV Jack *● ● ● — —37 Variable Audio Out ● ● ● ● ●

38 2-RF Input ● ● ● — —39 Ext Speaker Term ● ● ● ● ●

40 PIP Audio Out Jack — *— *● — —41 Center-Ch-Aud-Input — *● *— — —

42 Speaker-Box -- — ● SS-SR94 — —43 Others — — — — —

*Cabinet NEW CX32D70 CN32D90 *CE35D10 CF35D50

PARTS SUPPLY (ISO) — — — — —

*GENERAL

*SOUND

*PICTURE

*OTHER

*TERMS

*AC

CRT

15

CHASSIS C C C C C

MODEL Nbr CX35E60 CX35E70 CX35E81 CN35E90 CN35E95CONSOLE CINEMA

SPECIFICATION TDD TDD TDD TDD TDD

1 Picture Tube FST-D/T NF-D/T NF-D/T NF-D/T NF-D/T2 Channel Capacity 181ch 181ch 181ch 181ch 181ch3 C. Caption ● ● ● ● ●

4 MTS with dbx ● ● ● ● ●

5 Bass, Tre, Balance ● ● ● ● ●

6 Sub-Audio-Program ● ● ● ● *●

7 Remote band unit *A-Univ (42k) *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Intelig+EZ8 Picture-in-Picture ● (2TN) ● (2TN) ● (2TN) ● (2TN) ● (2TN)9 LED Indicators (RED) ● (Power) ● (Power) ● (Power) ● (Power) ● (Power)

10 Local Keys 8key 8key 8key *8key *8key

11 Dolby Surround — — — ● ●

12 Dig-Sound Processor — — — ● (DSP4ch) ● (DSP4ch)13 Front Surround ● ● ● — —14 Cyclone ABX — — — ● ●

15 Sub-Bass-System ● ● ● — —

16 Audio Output 10Wx2 10Wx2 10Wx2 10Wx2 10Wx2& 13W, 5Wx2 & 13W, 5Wx2

17 Speaker Size & Nbr 70x130x2 70x130x2 70x130x2 80x120x2 & 80x120x2 &*100R, REAR *120R, REAR

18 Comb Filter ● (DIG) ● (DIG) ● (DIG) ● (DIG) ● (DIG)19 Dy-Quadruple Focus ● ● ● ● ●

20 Scan Velocity Modu ● ● ● ● ●

21 Vert Contour Corre ● ● ● ● ●

22 Black Level Expand ● ● ● ● ●

23 Flesh Tone Correct ● ● ● ● ●

24 Dynamic Noise Reduc ● ● ● ● ●

25 Picture Preference ● ● ● ● ●

26 Horiz Resolution 800 800 800 800 800

27 Parental-Ch Lock ● ● ● ● ●

28 Channel Label (32ch) ● ● ● ● ●

29 3-Language Display ● ● ● ● ●

30 Clock/Off-Timer ●/● ●/● ●/● ●/● ●/●31 Favorite Channel *● *● *● *● *●

32 Extended-Data-Servi *● *● *● *● *●

33 Star-Sight-decoder — — — — —

34 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1+1) ● (1+1)35 Audio, Video-In/Out 1+2/1 1+2/1 1+2/1 1+2/1 1+2/136 Front AV Jack ● ● ● ● ●

37 Variable Audio Out ● ● ● ● ●

38 2-RF Input ● ● ● ● ●

39 Ext Speaker Term ● ● ● ● ●

40 PIP Audio Out Jack — *— *— *● *●

41 Center-Ch-Aud-Input — *● *● *— *—

42 Speaker-Box — — — ● SS-SR94 ● SS-SR9443 Others — *VCR-Storate — *VCR-Stora

*Cabinet C35D60 CX35D70 NEW (DAX) CN35D90 NEW (BLK)

PARTS SUPPLY (ISO) — — — — —

*GENERAL

*SOUND

*PICTURE

*OTHER

*TERMS

*AC

CRT

16

SECTION IITUNER, IF/MTS/S.PRO MODULE

17

1. CIRCUIT BLOCK

Fig. 2-1 Block diagram

1-1. Outline

(1) RF signals sent from an antenna are converted intointermediate frequency band signals (video: 45.75 MHz,audio: 41.25 MHz) in the tuner. (Hereafter, these signalsare called IF signals.)

(2) The IF signals are band-limited in passing through aSAW filter.

(3) The IF signals band-limited are detected in the VIFcircuit to develop video and AFT signals.

(4) The band-limited IF signals are detected in the SIFcircuit and the detected output is demodulated by theaudio multiplexer, developing R and L channel outputs.These outputs are fed to the A/V switch circuit.

(5) A sound processor (S.PRO.) is provided.

1-2. Major Features

(1) The VIF/SIF circuit is fabricated into a small module byusing chip parts considerably.

(2) As the tuner, EL466L that which contains an integratedPLL circuit is employed.

(3) Wide band double SAW filter F1802R used.(4) FS (frequency synthesizer) type channel selection system

employed.

(5) VIF/SIF circuit uses PLL sync detection system toimprove performances shown below:• Telop buzz in video over modulation• DP, DG characteristics (video high-fidelity

reproduction)• Cross color characteristic (coloring phenomenon at

color less high frequency signal objects)(6) HIC SBX1637A-22 is used in the audio multiplexer

circuit to minimize the size with increased performance.(7) As a sound control processor, TA1217N is used. I2C-

bus data control the DAC inside the IC to performswitching of the audio multiplexer modes.

EL466L

Tuner

RF AGC

IF/MTS/S.PRO Module MVUS34S

SIFoutput Sound

MultiplexCircuit

SAWFilter

VIF/SIFCircuit S.PRO Circuit

AFT output

TP12Video output

To A/V switch circuit

TVR-OUT

TVL-OUT

C-IN

R-IN L-IN

R-OUT L-OUT(L+R)-OUT

C-OUT

18

2. TUNER

2-1. Outline(1) Type name: EL466L(2) Applicable 181CH(3) I2C-bus version(4) PLL-integrated

Fig. 2-2 Tuner terminal layout

Terminal No. Name

1 32V

2 5V

3 S-CLOCK

4 S-DATA

5 ADDRESS

6 IF OUT

7 BM (9V)

8 RF AGC

9 VT

2-2. Operation of the Tuner2-2-1. Receiver Channels

VHF 2~13CHUHF 14~69CH 181CH in totalCATV A-6~, J~W, AA~BBB, 65~92, 100~127CH

2-2-2. Terminals (Tuner section)

Name Function

IF OUT IF outputs (P=45.75 MHz, C=42.17 MHz,S=41.25 MHz)

BM Tuner power supply (9V)

RF AGC Gain control terminal to obtain constantIF output

VT Control voltage to select channels

2-2-3. Tuner VT Voltage (unit: V)

(1) VHF (2) UHF

CH VT voltage (TYP)

2 1.4

6 6.4

A-2 12.8

B 20.0

C 1.4

I 3.5

10 5.6

J 7.6

N 9.7

R 11.8

W 14.2

FF 17.9

LL 24.2

CH VT voltage (TYP)

MM 1.1

QQ 2.2

WW 4.0

14 5.8

20 7.8

26 9.2

32 10.8

38 12.5

44 13.9

50 15.0

56 17.2

62 19.4

69 23.6

* VT voltage not indicated for a channel falls betweenthose values for channels just upper and lower the channel.

PLL SelectionEL466L

Tuner Section

1 2 3 4 5 6 7 8 9

19

3. IF/MTS/S.PRO MODULE

The IF/MTS/S.PRO module (MVUS34S) limits bandwidthof IF signals and detects video and audio signals. The moduleconsists of IF amplifiers, SAW (surface acoustic wave)filter, and PIF IC. The SAW filter has a wideband responseto improve picture quality and audio buzz characteristic and,develops separate outputs of video and audio signals. ThePIF IC employs a PLL complete sync detection + audio splitcarrier system.

3-1. IF/MTS/S.PRO Module (MVUS34S)3-1-1. Module Terminal Layout

3-1-2 Video PIF CircuitA PIF detector switching carrier is oscillating at a frequencyadjusted to 45.75 MHz with L051 (VCO CW coil) under noRF signal input. When an RF signal enters, an IF videocarrier is fed to APC section from IF AMP inside the IC, andthe detector switching carrier is adjusted by the APC, VCO,etc. in the PLL circuit so that its frequency and phase arematched to those of the IF video carrier to perform precisesync detection. Thus processed video output is developed atpin 21.

PLL lock speed is automatically controlled by adding thevideo signal at pin 21 to pin 1. That is, since the video signalis not output at operations of power on, CH switching, etc.,the APC filter between pin 16 and GND consists of C022 andC053, and R018, and the filter effect decreases, thus increasingPLL lock speed.Next, when a video out exists, the internal resistance is short-circuited and the APC filter consists of C022 and C053,internal resistance, and R018. As a result, the filter effectincreases and the PLL lock speed decreases. Consequently,under normal signal reception, phase of the detector switchingcarrier is locked in a stable condition if an IF video carrier islost for a short time due to over modulation, etc. By combiningsuch a PLL complete sync detection system and a widebandSAW filter shown in Fig. 2-4, a wideband (4.2 MHz) videodetection output with less beat interference will be obtained.

3-1-3. Audio PIF CircuitThe IF signal fed through Q003 (Fig. 2-4) enters an audiosection of the SAW filter (Z001) which has an IF bandwidthfor dedicated audio signals, and only the audio signal of41.25 MHz is fed to pin 7. The signal is sync-detected withthe detection carrier completely synchronized with the IFvideo carrier and pin 14 develops a 4.5 MHz SIF signal. Byusing the PLL split carrier system just stated, audio signalswith less buzz by the video signal will be reproduced. The 4.5MHz SIF enters pin 15 through a 4.5 MHz filter, Z003 andpin 9 develops a FM-detected audio signal.

Pin No. Name Pin No. Name

1 GND 15 DAC-OUT2

2 IF-IN 16 R-IN

3 NC 17 C-IN

4 +9V 18 L-IN

5 RF AGC 19 GND

6 AFC 20 SCL

7 VIDEO OUT 21 SDA

8 ADR SW 22 W-OUT

9 MPX OUT 23 C-OUT

10 --- 24 L-OUT

11 --- 25 GND

12 TV R-OUT 26 R-OUT

13 DAC-OUT1 27 +9V

14 TV L-OUT

Fig. 2-3 IF/MTS/S.PRO module terminal layout

27 12 9 1

20

Fig. 2-4 IF/MTS/S. PRO circuit diagram

SIF BANDWIDTH

S Q 0 0 2

Q 0 0 3

IF AMP G A I N – 1 4 d B

Z001 S A W

FILTER

F1802R

S C P

41 .25M 45 .75M V IDEO IF BANDWIDTH

G N D I F - I N N . C + B ( 9 V ) R F A G C A F C V I D E O O U T A D R S W M

Z003 4 .5MHz S IF S IGNAL

FM DET . COIL L053

15 11 12

9

7

5

4

2

1

14 .

22

13 16 20

21

23

18

17 .

S I F L I M I T FM DET.

S I F D E T A P C V C D

IF A M P

A G C

V I D E O D E T .

L051 VCO C W C O I L

R 1 5 1 TO SOUNDM P X I C

L502 AFT COIL

R 0 2 1 TP12

Q 0 0 4 Z002

R 0 2 2

R F A G C R 0 5 1

1 2 3 4 5 6 7 8 9

LOCKCONTROL

-15dB

-6dB

R018

C022

C053

C106

21

3-1-4. Audio Multiplex Demodulation CircuitThe sound multiplex composite signal FM-detected in thePIF circuit enters pin 12 of HIC (hybrid IC) in passingthrough the separation adjustment VR RV2 and amplified.After the amplification, the signal is split into two: one entersa de-emphasis circuit, and only the main signal with the L-R signal and a SAP signal removed enters the matrix circuit.At the same time, the other passes through various filters andtrap circuits, and the L-R signal is AM-demodulated, and theSAP is FM-demodulated.

Then, both are fed to the matrix circuit. At the same time,each of the stereo pilot signal fH and the SAP pilot signal 5fHis also demodulated to obtain an identification voltage. Withthe identification voltage thus obtained and the user controlvoltage are used to control the matrix.The audio signals obtained by demodulating the soundmultiplex signal develop at pin 10 and 11 of HIC and developthe terminals of 12 and 14 of the module.

Fig. 2-5 Block diagram of MVUS32S

Note:Of the mode selection voltages, switching voltages for STE,SAP, MONO do not output outside the module.They are used inside the module to control the BUS.

Table 2-1 Matrix for broadcasting conditions andreception mode

Broad- SwitchingOutput OSD display

casted mode12 pin 14 pin

Stereo SAP(R) (L)

Stereo STE R L O XSAP R L O XMONO L+R L+R O X

Mono STE L+R L+R X XSAP L+R L+R X XMONO L+R L+R X X

Stereo STE R L O O+ SAP SAP SAP O O

SAP MONO L+R L+R O O

Mono STE L+R L+R X O+ SAP SAP SAP X O

SAP MONO L+R L+R X O

M V U S 3 2 S

M P X O u t

D A C - o u t 1 D A C - o u t 2 (RFSW)

TV TV L -Ou t

9 10 11 12 13 14 14

To AV se lec t c i r cu i t

N o t u s e d f o r C N 3 2 E 9 0 .

(SURR OFF)R-Out

Monitor the inputpin for multiplex

sound IC

Stereo 0V

Other 0V

SAP 0V

Other 0V

OFF 0V

ON 9V

RF1 0V

RF1 9V

TV waveform detection TV waveform detectionoutput (L)output (R)

22

3-1-5. A.PRO Section (Audio Processor)The S.PRO section has following functions.(1) Woofer processing (L+R output)(2) High band, low band, balance control(3) Sound volume control, cyclone level control(4) Cyclone ON/OFF

All these processing are carried out according to the BUSsignals sent from a microcomputer.

Fig. 2-6 shows a block diagram of the A.PRO IC.

Fig. 2-6 A.PRO block diagram

TA1217N

Lin

Rin

Cin

Win

SDA

SGL

TONE CONTROL

LPF

CenterLEVEL

WooferLEVEL

VOLUME

BALANCE

I C2 D/A

CONV

I/O

Lout

Rout

Cout

Wout

SAP det.

STE det.

R-in C-in L-in SCL SDA W-out O-out L-out R-out

From From From A/V Dolby A/V

Q670 Q640 Q670 Q670

9V

16 17 18 19 20 21 22 23 24 25 26 27

Via QS101

4 5 6 7 31 24 23 22 19

17

16

15

14

13

12

11

26

25

18

10

30 9 8 281 27 29 22 32 33

30

34

2

3

20

21

23

4. PIP TUNER

Fig. 2-7 Terminal No. Name

1 NC

2 32V

3 S-CLOCK

4 S-DATA

5 NC

6 ADDRESS

7 5V

8 RF AGC

9 9V

10 AUDIO

11 GND

12 AFT

13 NC

14 GND

15 VIDEO

Fig. 2-8 Tuner terminal layout

4-1. OutlineThe PIP tuner (EL922L) consists of a tuner and an IF blockintegrated into one unit. The tuner receives RF signalsinduced on an antenna and develops an AFT output, videooutput, and audio output.The tuner has receive channels of 181 as in the tuner for themain screen and it is also controlled through the I2C-bus.As the IC for the IF, a PLL complete sync detection plusaudio inter carrier system are employed.

TUNERSECTION

SAWFILTER

VIF/SIFCIRCUIT

RF AGC

AFTOUTPUT

VIDEOOUTPUT

AUDIOOUTPUT

Lable

NameLot No.

1 15

24

SECTION IIICHANNEL SELECTION CIRCUIT

25

1. OUTLINE OF CHANNEL SELECTIONCIRCUIT SYSTEM

The channel selection circuit in the N5SS chassis employsa bus system which performs a central control by connectinga channel selection microcomputer to a control IC in eachcircuit block through control lines called a bus. In the bussystem which controls each IC, the I2C bus system (two linebus system) developed by Philips Co. Ltd. in the Netherlandshas been employed.The ICs controlled by the I2C bus system are : IC for audiosignal processing (QN06), IC for V/C/D signal processing(Q501), IC for A/V switching (QV01), IC for non volatilememory (QA02), Main and sub U/V tuners (H001, HY01),IC for deflection distortion correction (Q302), IC for PIPsignal processing (QY04), IC for DSP (QM01), IC forclosed caption control (Q701).

Differences from N4SS chassis are as follows;1. On-screen function inside microcomputer is used.

Separate IC is not used for on-screen.2. The microcomputer does not have the closed caption

function, but controls separate IC for closed caption.3. The system uses two channels of I2C bus. One is only

for non-volatile memory.

2. OPERATION OF CHANNELSELECTION CIRCUIT

Toshiba made 8 bit microcomputer TLCS-870 series for TVreceiver, TMP87CS38N-3152 is employed for QA01.With this microcomputer, each IC and circuit shown beloware controlled.

(1) CONTROL OF AUDIO SIGNAL PROCESS IC (QN06Toshiba TA1217N)

• Adjustments for volume, treble, bass and balance• Selection between surround mode and DSP mode,

and level adjustment• Level adjustment of BAZOOKA system• Audio muting during channel selection or no signal

reception.

(2) CONTROL OF VIDEO/CHROMA/DEF SIGNALPROCESS IC (Q501 Toshiba TA1222N)

• Adjustments for uni-color, brightness, tint, colorgain, sharpness and PIP uni-color

• Setting of adjustment memory values for sub-brightness, sub-color and sub-tint, etc.

• Setting of memory values for video parameterssuch as white balance (RGB cutoff, GB drive) andgcorrection, etc.

• Setting of video parameters of video modes(Standard, Movie, Memory)

(3) CONTROL OF A/V SWITCH IC (QV01 ToshibaTA1219N)

• Preforms source switching for main screen andsub screen

• Performs source switching for TV and three videoinputs

(4) CONTROL OF NON-VOLATILE MEMORY IC(QA02 Microchip 24LC04BI/P)

• Memorizes data for video and audio signaladjustment values, volume and woofer adjustmentvalues, external input status, etc.

• Memorizes adjustment data for white balance(RGB cutoff, GB drive), sub-brightness, sub color,sub tint, etc.

• Memorizes deflection distortion correction valuedata adjusted for each unit.

(5) CONTROL OF U/V TUNER UNIT (H001 MatsushitaEL466L, HY01 Toshiba EL922L)

• A desired channel can be tuned by transferring achannel selection frequency data (divided ratiodata) to the I2C bus type frequency synthesizerequipped in the tuner, and by setting a band switchdata which selects the UHF or VHF band.

(6) CONTROL OF DEFLECTION DISTORTIONCORRECTION IC (Q302 Toshiba TA8859P)

• Sets adjustment memory value for verticalamplitude, linearity, horizontal amplitude,parabola, corner, trapezoid distortion.

(7) CONTROL OF PIP SIGNAL PROCESS IC (QY04Toshiba TC9083F)

• Controls ON/OFF and position shift of PIP.

(8) CONTROL OF DIGITAL SOUND PROCESSOR IC(QM04 Yamaha YSS238-D)

• Performs mode switching of DSP.

(9) CONTROL OF CLOSED CAPTION/EDS (QM01Motorola XC144144P)

• Controls Closed Caption/EDS.

26

3. MICROCOMPUTER

Microcomputer TMP87CS38N-3152 has 60k byte of ROMcapacity and equipped with OSD function inside.The specification is as follow.

• Type name : TMP87CS38N-3152• ROM : 60k byte• RAM : 2k byte• Processing speed : 0.5m s (at 8MHz with Shortest

command)• Package : 42 pin shrink DIP• I2C-BUS : two channels• PWM : 14 bit x 1, 7 bit x 9• ADC : 8 bit x 6 (Successive comparison system,

Conversion time 20ms)• OSD

Character kinds : 256Character display : 24 characters x 12 linesCharacter dot : 14 x 18 dotsCharacter size : 3 kinds (Selected by line)Character color : 8 colors (Selected by character)Display position : Horizontal 128 steps, Vertical

256 stepsThis microcomputer performs functions of AD converter,reception of U/V TV and OSD display in one chip.

IIC device controls through I2C bus. (Timing chart : See fig.3-1)

• LED uses big current port for output only.• For clock oscillation, 8MHz ceramic oscillator is used.• I2C has two channels. One is for EPROM only.• Self diagnosis function which utilizes ACK function of

I2C is equipped• Function indication is added to service mode.• Remote control operation is equipped, and the control

by set no touch is possible. (Bus connector in theconventional bus chassis is deleted.)

• Substantial self diagnosis function(1) B/W composite video signal generating function

(micom inside, green crossbar added)(2) Generating function of audio signal equivalent

to 1kHz (micom inside)(3) Detecting function of power protection circuit

operation(4) Detecting function of abnormality in IIC bus

line(5) Functions of LED blink indication and OSD

indication(6) Block diagnosis function which uses new VCD

and AV SW

Fig. 3-1

SDA

SCL 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9

STARTCONDITION

STOPCONDITION

ADDRESS R/W Ack DATA Ack DATA Ack

Approx.180mS Some device may have no data,or may have data with several bytes continuing.

27

4. MICROCOMPUTER TERMINAL FUNCTION

Fig. 3-2

TMP87CS38N3152 (QA01)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

I

O

O

O

O

O

O

O

I

O

IO

I

I

I

I

I

I

O

O

I

IO

O

I

I

I

I

O

I

I

O

I

I

I

O

O

O

O

GND

BAL

REM OUT

MUTE

SP MUTE

NC

POWER

LED

NC

NC

SCL0

SDA0

SYNC VCD

NC

AFT2

AFT1

KEY-A

KEY-B

SGV

SGA

GND

GND

P40 (PWM0)

P41 (PWM1)

P42 (PWM2)

P43 (PWM3)

P44 (PWM4)

P45 (PWM5)

P46 (PWM6)

P47 (PWM7)

P50 (PWM8/TC2)

P51 (SCL1)

P52 (SDA1)

P53 (AINO/TC1)

P54 (AIN1)

P55 (AIN2)

P56 (AIN3)

P60 (AIN4)

P61 (AIN5)

P62

P63

VSS

VDD

P57

P32

P57

SDA0

SCL0

(TC3)P31

(RXIN)P30

P20

RESET

XOUT

XIN

TEST

0SC2

0SC1

VD

HD

Y/BL

B

G

R

VDD

ACP

NC

GND

SDA1

SCL1

SYNC AV1

RMT IN

SW IN

RESET

XOUT

XIN

TEST

0SC1

0SC2

VSYNC

HSYNC

Ys

BOUT

GOUT

ROUT

IIC- BUS

IIC -BUS

28

<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >>

No. Terminal Name Function In/Out Logic Remarks

1 GND 0V2 BAL INPUT BALANCE Out PWM out

3 REM OUT REMOTE CONTROL Out Remote control outputSIGNAL OUT

4 MUTE SOUND MUTE OUT Out Sound mute output

5 SP MUTE SPEAKER MUTE Out In muting = H

6 DEF POW Out

7 POWER POWER ON/OFF OUT Out Power control In ON=H

8 LED POWER LED OUTPUT Out Power LED on-controlLED lighting=L

9 POWER LNB Out 0V

10 LNB DET In 0V

11 SCL() IIC BUS CLOCK OUT Out IIC bus clock output 0

12 SDA() IIC BUS DATA IN/OUT In/Out IIC bus data input/output 0

13 SYNC VCD H SYNC INPUT In Main picture H. sync signal input14

15 AFT2 IN In Sub tuner AFT S-curve input

16 AFT1 UV MAIN S-CURVE In Main tuner AFT S-curveSIGNAL signal input

17 KEY A LOCAL KEY INPUT In Local key detection: 0 to 5V

18 KEY B LOCAL KEY INPUT In Local key detection: 0 to 5V

19 SGV TEST SIGNAL OUT Out Test signal output In normal=L 0V

20 SGA TEST AUDIO OUT Out Test audio output In normal=L 0V

21 VSS POWER GROUNDING — 0V: Gounding voltage 0V

22 R R Out At display on:Pulse

23 G G Out At dispaly on:Pulse

24 B B Out At dispaly on:Pulse

25 Y/BL BL Out At dispaly on:Pulse

26 HSYNC In HSYNC for OSD display Pulse

27 VSYNC In VSYNC for OSD display Pulse

28 OSC1 DISPLAY CLOCK Out 4.5MHz Pulse

29 OSC2 DISPLAY CLOCK In Pulse

30 TEST TEST MODE In GND fixed 0V

31 XIN SYSTEM CLOCK In System clock input 8MHz pulse

32 XOUT SYSTEM CLOCK Out System clock output 8MHz 8MHz pulse

33 RESET SYSTEM RESET In System reset input (In reset=L) 5V

34 SW IN

35 RMT IN REMOTE CONTROL IN In remote control pulse input=L In reception ofSIGNAL INPUT remote pulse

36 SYNC AV1 HSYNC INPUT In External H. sync signal input Pulse

37 SCL1 IIC BUS CLOCK OUT Out IIC bus clock output 1 Pulse

38 SDA1 IIC BUS DATA IN/OUT In/Out IIC bus data input/output 1 Pulse

39 GND 0V

40 NC

41 ACP NSYNC INPUT In AC pulse input

42 VDD POWER — 5V 5V

29

5. EEPROM (QA02)

EEPROM (Non volatile memory) has function which, in spite of power-off, memorizes the such condition as channel selectingdata, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits. Type name is 24LC04BI/P or ST24C04CB6, and those are the same in pin allocation and function, and are exchangeable each other. This IC controlsthrough I2C bus. The power supply of EEPROM and MICOM is common. Pin function of EEPROM is shown in Figure 3-3.

Fig. 3-3

6. ON SCREEN FUNCTION

ON SCREEN FUNCTION indicates data like channel, volume. Formerly, exclusive use of OSD IC was used, but in N5SS,OSD function is involved in microcomputer. Pin function concerning on-screen is shown in figure 3-4. Oscillation clock of OSDis approx. 4.5MHz. 9MHz which becomes twice in microcomputer is dot clock. For oscillation coil, TRF1160D (LA02) is used.

Fig. 3-4

1

2

3

4

8

7

6

5

A0

A1

A2

Vss

Vcc + 5V

NC

SCL

SDAI2C-BUS line

Device adressGND

EEPROM(QA02)

OSC2

OSC1

VD

HD

Y/BL

B

G

R

QA01

O

I

I

I

O

O

O

O

29

28

27

26

25

24

23

22

OSC2 OSC OUT

OSC1 OSC IN

VSYNC H. SYNC SIGNAL

HSYNC V. SYNC SIGNAL

Ys/Ym HALF TONE SIGNAL

BOUT

GOUT COLOR SIGNAL

ROUTVG

30

7. SYSTEM BLOCK DIAGRAM

Fig. 3-5

QA01TMP87CS38N-3152

QA02

SCL 0

SDA 0

HSYNC

VSYNC

R

G

B

YS/TM

RMT OUT

MUTE

SP MUTE

SDA 1

SCL 1

RMT

KEY-A

KEY-B

RST

VDD

GND

VSS

POWER

ACP

LED

XIN

XOUT

OSCI

OSCO

SGV

SGA

SYNC-AV1

AFT1 IN

SYCN-AV2

AFT2 IN

11

12

26

27

22

23

24

25

3

4

5

38

37

35

17

18

33

42

1

21

7

41

8

31

32

28

29

19

20

36

16

13

2

KEY SWITCH

REMOTESENSOR

UNIT

MAIN U/V TUNEREL446L

H001

SDA SCL

HY01

SUB U/V TUNEREL922L

SDA SCL

SDA SCL

SDA SCL

VCDTA1222

Q501

H002

IF/MPXMVUS345

27 28

21 20

SDA SCL

QV01

AV SWTA1219N

26 27

QM01

DSP

SDA SCL

6.1MHz

CLOCK

SIGNALOUTPUT

8MHz

CLOCK

SYNC DET.

AFT DET.

SYNC DET.

AFT DET.

MAIN SCREEN

SUB SCREEN

MEMORY24LC04B1/P

SDA SCL

5 6

H. SYNC PULSE

VSYNC PULSE

REMOTE CONTROLOUTPUT

SOUND MUTE

SPEAKER MUTE

Q701

C/C, EDSXC144144PDATA CLK

DPC UNIT

DATA CLK

QY04

PIP CONTROL

DATA CLK

6 5

POWERSUPPLYCIRCUIT

VIDEO SIGNALPROCESSCIRCUIT

31

8. LOCAL KEY DETECTION METHOD

Local key detection in the N5SS chassis is carried out byusing analog like method which detectsa voltage appears at local key input terminals (pins 17, 18) ofthe microcomputer when a key ispushed. With this method using two local key input terminals( pins 17,18), key detection up tomaximum 14 keys will be carried out.

The circuit diagram shown left is the local key circuit. As canbe seen from the diagram, whenone of key among SA-01 to SA-08 is pressed, each of twoinput terminal (pins 17, 18) developesa voltage Vin corresponding to the key pressed. (The voltagemeasurement and key identificationare carried out by an A/D converter inside the microcomputerand the software.

Fig. 3-6. Local key assignment

Key No. Function Key No. Function

SA-02 POWER SA-01 DEMO START/STOP

SA-03 CH UP

SA-04 CH DN

SA-05 VOL UP

SA-06 VOL DN

SA-07 ANT/VIDEO, ADV

SA-08 MENU

Table 3-1. Local key assinment

15 16

S15-1

S15-2

S15-3

S15-4

S15-5

S15-6

S15-7

S16-1

S16-2

S16-3

S16-4

S16-5

S16-6

S16-7

32

9. REMOTE CONTROL CODE ASSIGNMENT

Custom codes are 40-BFH

CodeApplicable

Applicable Conti-Function to remoteto TV set nutycontrol

00H 0 Channel01H 1 Channel02H 2 Channel03H 3 Channel04H 4 Channel05H 5 Channel06H 6 Channel07H 6 Channel08H 8 Channel09H 8 Channel0AH 100 Channel0BH ANT 1/20CH RESET0DH AUDIO0EH PICTURE/FUNC0FH TV/VIDEO

10H MUTE11H CHANNEL SEARCH12H POWER13H MTS14H ADD/ERASE15H TIMER/CLOCK16H AUTO PROGRAM17H CHANNEL RETURN18H DSP/SUR (TV/CATV)19H CONTROL UP1AH VOLUME UP1BH CHANNEL UP1CH RECALL1DH CONTROL DOWN1EH VOLUME DOWN1FH CHANNEL DOWN

40H PIP LOCATE 41H PIP LOCATE 42H PIP LOCATE43H PIP LOCATE 44H CARVER45H SURROUND UP46H SURROUND DOWN47H VOCAL ZOOM48H CHANNEL LOCK49H4AH PIP CHANNEL UP4BH PIP CHANNEL DOWN4CH PIP STILL/RELEASE4DH PIP ZOOM, ZOOM SIZE4EH PIP LOCATE4FH PIP SOURCE


CodeApplicable


50H PIP STILL51H PIP ON/OFF52H Do not use. Old type core power ON53H PIP SWAP54H PIC SIZE55H DSP F/R56H WIDE/SCROLL57H CAPTION58H EXIT59H CYCLONE, SBS5AH SER UP5BH OPTION5CH SUB WOOFER UP5DH SUB WOOFER DOWN5EH5FH

80H MENU81H EDS82H ADV UP83H ADV DWN84H85H86H87H88H PIP CONTROL89H8AH8BH8CH8DH8EH8FH

90H91H92H93H94H Do not use. Old type core power ON95H96H97H NOISE CLEAN98H99H9AH PIP VOLUME UP9BH9CH PIP CONTROL9DH9EH PIP VOLUME DOWN9FH

33


Code Applicable Conti-Functionto TV set nuty

A0H SUB-BRIGHT ADJUSTMENTA1H G. DRIVE ADJUSTMENTA2H B. DRIVE ADJUSTMENTA3HA4H CUTOFF DRIVE 40H INITIALIZING, HORIZONTAL ONE LINE

A5H R. CUTOFF ADJUSTMENTA6H G. CUTOFF ADJUSTMENTA7H B. CUTOFF ADJUSTMENTA8H MEMORY ALL AREA INITIALIZEA9H PIP BRIGHT ADJUSTMENTAAH SUB CONTRAST ADJUSTMENTABH HOR, VER PICTURE POSITON ADJUSTMENTACH SUB COLOR ADJUSTMENTADH SUB TINT ADJUSTMNETAEH ADJUSTMENT-UPAFH ADJUSTMENT-DOWN

B0H HORIZONTAL ONE LINE: SERVICEB1H DSP ON/OFFB2H TEXT-1B3H TV/PIP VIDEO CHANGE-OVERB4H CAPTION-1B5HB6HB7H TV/CABLE CHANGE-OVER IN SAME TIME ON MAN AND SUB

B8H HOTEL SETTING MENUB9H DATA 4 TIMES SPEED UPBAH DATA 4 TIMES SPEED DOWNBBH CHANGE-OVER OF HOTEL/NORMALBCH PIP CENTERBDH M MODEBEH CAPTON OFFBFH ALL CHANNEL PRESET


CodeApplicable


C0HC1HC2HC3HC4H PIP LOCATE C5H PIP LOCATE C6H PIP LOCATE C7H PIP LOCATE C8H PIP STROBEC9H PIP STROBE SPEEDCAH PIP CHANNEL SEARCHCBHCCHCDHCEHDFH

D0HD1HD2H Do not use. Old type core power OND3HD4HD5HD6HD7H PIP VIDEO ADJ.D8H STILL, FRAME ADVANCED9HDAH SPEEDDBHDCH ZOOMDDHDEHDFH

34


Code Applicable Conti-Functionto TV set nuty

E0H PINCUTION/EW CORER (PARA/CNR)E1H VERTICAL S-CUVE CORRECTION/VERTICAL M-CURVE CORRECTION (VSC/FVC)

E2HE3HE4HE5HE6HE7HE8HE9HEAH HORIZONTAL WIDTH (WID/PARA)EBH TRAPEZOIDE CORRECTION (TRAP)ECH TEST TONEEDH DOLBYEEH 3 DIMENTIONAL Y/C SEPARATIONEFH DPC

E0H STANDARD (HEIGHT LINEARITY) (VLIN/HIT)E1H WIDE (HEIGHT LINEARITY) (VLIN)F2H SCROOLF3H WIDE 1, 2, 3F4HF5HF6HF7HF8HF9HFAHFBHFCHFDHFEHFFH

35

10. ENTERING TO SERVICE MODE

1. PROCEDURE(1) Press once MUTE key of remote hand unit to

indicate MUTE on screen.(2) Press again MUTE key of remote hand unit to keep

pressing until the next procedure.(3) In the status of above (2), wait for disappearing of

indication on screen.(4) In the status of above (3), press MENU (Channel

setting) key on TV set.

2. Service mode is not memorized as the last-memory.3. During service mode, indication S is displayed at upper

right corner on screen.

11. TEST SIGNAL SELECTION

1. In OFF state of test signal, SGA terminal (Pin 20) andSGV terminal (Pin 21) are kept “L” condition.

2. The function of VIDEO test signal selection is cyclicallychanged with VIDEO key (remote unit).

Test Signal No. Name of Pattern

0 Signal OFF1 All black signal + R single color (OSD)2 All black signal + G single color (OSD)3 All black signal + B single color (OSD)4 All black signal5 All white signal6 W/B7 Black cross bar8 White cross bar9 Black cross hatch10 White cross hatch11 White cross dot12 Black cross dot13 H signal (bright area)14 H signal (dark area)15 Black cross + G

(3) SGA (audio test signal) output should be squarewave of 1kHz.

12. SERVICE ADJUSTMENT

1. ADJUSTMENT MENU INDICATION ON/OFF :MENU key ( on TV set)

2. During display of adjustment menu, the followings areeffective.a) Selection of adjustment item :

POS UP/DN key (on TV/remote unit)b) Adjustment of each item :

VOL UP/ DN key (on TV / remote unit)c) Direct selection of adjustment item

R CUTOFF : 1 POS (remote unit)G CUTOFF : 2 POS (remote unit)B CUTOFF : 3 POS (remote unit)

d) Data setting for PC unit adjustmentSUB CONTRAST : 4 POS (remote unit)SUB COLOR : 5 POS (remote unit)SUB TINT : 6 POS (remote unit)

e) Horizontal line ON/OFF :VIDEO (TV)f) Test signal selection : VIDEO (remote unit)* In service mode, serviceable items are limited.

3. Test audio signal ON / OFF : 8 POS (remote unit)* Test audio signal : 1kHz

4. Self check display : 9 POS (remote unit)* Cyclic display (including ON/OFF)

5. Initialization of memory :CALL (remote unit) + POS UP (TV)

6. Initialization of self check data :CALL (remote unit) + POS DN (TV)

7. BUS OFF :CALL (remote unit) + VOL UP (TV)

36

13. FAILURE DIAGNOSIS PROCEDURE

Model of N5SS chassis is equipped with self diagnosis function inside for trouble shooting.1. CONTENTS TO BE CONFIRMED BY CUSTOMER

Contents of self diagnosis Display items and actual operation

A. DISPLAY OF FAILURE INFORMATION Power indicator lamp blinks and picture does not come.IN NO PICTURE(Condition of display)

1. When power protection circuit operates; 1. Power indicator red lamp blinks. (0.5 seconds interval) 2. When I2C-BUS line is shorted; 2. Power indicator red lamp blinks. (1 seconds interval)

If these indication appears, repairing work is required.

2. CONTENTS TO BE CONFIRMED IN SERVICE WORK (Check in self diagnosis mode)

Contents of self diagnosis Display items and actual operation

Contents of self diagnosis Display items and actual operation <Countermeasure in case that phenomenon always arises.> B.Detection of shortage in BUS line (Example of screen display) C.Check of comunication status in BUS line D.Check of signal line by sync signal detection E. Indication of part code of microcom.(QA01) F. Number of operation of power protection circuit

SELF CHECKNo. 2390XXXX Part code of QA01POWER : 000000 Number of operation of

power protection circuitBUS LINE : OK Short check of bus lineBUS CONT : OK Comunication check of

buslineBLOCK : UV V1 V2

QV01, QV01S

E F

B C

D

Fig. 2-4

3. EXECUTING SELF DIAGNOSIS FUNCTION[CAUTION](1) When executing block diagnosis, get the desired input mode (U/V BS VIDEO1,2,3) screen, and then enter the self diagnosis

mode.(2) When diagnos other input mode, do again diagnosis operation.

(PROCEDURE)(1) Set to service mode.(2) Pressing “9” key on remote unit displays self diagnosis result on screen.

Every pressing changes mode as below.

SERVICE mode SELF DIAGNOSIS mode

(3) To exit from service mode, turn power off.

37

4. UNDERSTANDING SELF DIAGNOSIS INDICATIONIn case that phenomenon always arises. See figure 3-4 .

Item Contents Instruction of results

BUS LINE Detection of bus line short Indication of OK for normal result, NG for abnormal

Indication of OK for normal resultIndication of failure place in abnormality(Failure place to be indicated)QA02 NG, H001 NG, Q501 NG, H002 NGQV01 NG, Q302 NG, QY02 NG, HY01 NGQD04 NG, QM01 NG, Q701 NG

BUS CONT Communication state of bus line Note 1. The indication of failure place is only one placethough failure places are plural. When repair of afailure place finishes, the next failure place is indicated. (The order of priority of indication is left side.)

BLOCK:BS The sync signal part in *Indication by colorUV1 each video signal supplied from • Normal block : GreenUV2 each block is detected. • Non diagnosis block : Cyan

V1 Then by checking the existence orV2 non of sync part, the result of self

diagnosis is displayed on screen.Besides, when “9” key on remoteunit is pressed,diagnosis operationis first executed once.

<Clearing method of self diagnosis result>In the error count state of screen, press “CHANNEL DOWN” button on TV set pressing “DISPLAY” button onremote unit.

[CAUTION]All ways keep the following caution, in the state ofservice mode screen.• Do not press “CHANNEL UP” button. This will cause

initialization of memory IC. (Replacement of memory IC isrequired.

• Do not initialize self diagnosis result. This will change useradjusting contents to factory setting value. ( Adjustment isrequired.)

WhiteYellow

CyanGreen

MagentaRed

Blue

( COLOR BAR SIGNAL)Color elements are positioned in sequence of high brightness.

<Method utilizing inner signal> (VIDEO INPUT 1 terminal should be open.)(1) With service mode screen, press VIDEO button on remote unit. If inner video signal can be received, QV01 and after are normal.(2) With service mode screen, press “8” button on remote unit. If sound of 1kHz can be heard, QV01 and after are normal.* By utilizing signal of VIDEO input terminal, each circuit can be checked. (Composite video signal, audio signal)

38

14. TROUBLE SHOOTING CHART(1) TV DOES NOT TURNED ON

TV does not turned on.

Relay sound

Check of voltage at pin 7 of QA01(DC 5V).

8MHz oscillation waveformat pin 32 of QA01.

Pulse output at pins 37 and 38 of QA01.

Check relay driving circuit.

Check power circuit.

Check OSC circuit.

Replace QA01.

Voltage check at pin 32 of QA01(DC 5V)

Check reset circuit.

Replace QA01.

YES

NG

NG

NG

NG

OK

NO

OK

OK

OK

39

(2) NO ACCEPTION OF KEY-IN

(3) NO PICTURE (SNOW NOISE)

Key on TV

Voltage change at pins 17, 18 ofQA01 (5V to 0V).

Replace QA01.

Check key-in circuit.

NG

OK

NG

OK

Remote unit key

Pulse input at pin 35 of QA01,When remote unit key is pressed.

Replace QA01 Check tuner power circuit.

NG

OK

No picture

Voltage at pins of +5V, and 32V.

Check H001. Check tuner power circuit.

40

(5) NO INDICATION ON SCREEN

(4) MEMORY CIRCUIT CHECK

NG

NG

OK

OK

Memory circuit check

Voltage check at pin 8 of QA02 (5V).

Pulse input at pins 5 and 6 of QA02in memorizing operation.

Replace QA02.

Adjust items of TV set adjustment.

Note: Use replacement parts for QA02.


Check QA01.

NG

NG

OK

OK

OK

No indication on screen.

Check of character signal at pin 23 of QA01. (5VP-P)

Input of OSC waveform at pin 29 of QA01with indication key pressed.

Check of sync signal at pins 26, 27 of QA01.

Replace QA01.

Check V/C/D circuit.

Check OSC circuit.

Check sync circuit.

41

SECTION IVAUDIO OUTPUT CIRCUIT

42

1. OUTLINE

Configuration of the audio circuit and signal flow are givenin Fig 4-1.

Fig. 4-1

PIPOUTPUT

A/V PCB

ICV01VIF+MTS+S.PRO

MODULE

R

L

R

L

LRLR

LR

L

R

L

RVIDEO 1

VIDEO 2

VIDEO 3

FOR PIPIF MODULE

AUDIO

L

RPIP OUT(AUDIO)

R L

R L

R L

R

L

R L

DSPCIRCUIT

VIF+MTS+A.PROMODULE

R

L

R

L

W

Q670

R

L

W

12

14

EQ

ER

AS

AR

AI

AJ

6

7

111339

1517

29

31

2

1

35

37

16

18

25

24

22

2

4

1

12

2

11

MOTHERTV

CHILDTV

VIDEO 1

VIDEO 2

VIDEO 3(FRONT INPUT)

VARIABLEAUDIO OUTPUT

TERMINAL

VIDEOOUTPUT

TERMINAL

R out

L out

W out

43

2. AUDIO OUT IC2-1. OUTLINEIn the model, CN32E90, the main amplifiers and wooferoutput amplifiers use bipolar IC TA8256H and develop outpowers of 10W x 2+13W.

2-2. THORY OF OPERATION2-2-1. Operatin of TA8256HThe TA8256H is a modified version of TA8128AH used inthe N4SS chassis as an audio ouput IC. In the TA8256H, onechannel is added and a total of 3 channels can be used, butperformance for each channel is the same as that of theTA8218H. Fig. 4-2 shows a block diagram of the IC.

Fig. 4-2

AMP-2

AMP-3

AMP-1

111

7

5

12

10

84

3

2

47mF

1mF

47mF

1mF

RR

1mF

WW

6 9

RIPPLE FILTER Vcc4k

30k

350W

PREGND

350W

4k30k

30k4k

350W

20kW

MUTING

OUTPUT-3

(S) or (W)

OUTPUT-3

OUTPUT-2

POW GND

(R)

Vcc25.5V

470mF

2.2W

0.12mFRL (L)

RL (R)

470mF

0.12mF

2.2W

(mute)

(mute Tc)

1000mF

RL (W)2.2W

0.12mF

LL

44

SECTION VA/V SWITCHING CIRCUIT

45

1. OUTLINE

A/V switching circuit performs change-over of video andaudio signals from tuner and external input. The selectingoperation is controlled by microcomputer through IIC bus.

2. IN / OUT TERMINALS

INNER INPUT U/V Tuner (Main)U/V Tuner (Sub) .................................. For sub picture (PIP)

EXTERNAL INPUT VIDEO1 With S-terminalVIDEO2VIDEO3 (Front) With S-terminal ........ Excepting CF35E50, CL37E56, CE35E15VIDEO3 (Back) .................................. Only for CF35E50, CL37E56, CE35E15

OUTPUT VIDEO OUTPUT (V, L, R) .................... Excepting CN27E90AUDIO ON SUB-PICTURE ................... Only for CN32E90, CN35E90, CN35E95

3. CIRCUIT OPERATION

This circuit consists of A/V SW IC; TA1218N (QV01), andselects signals from U/V tuner (Main), U/V tuner (Sub),E1, E2 and E3.

3-1 COMPOSITE VIDEO SIGNALThe selected video signal is output to pin 38 of QV01, andseparated by comb filter into Y and C. The resulted signalis input to pins 30 and 32 of QV01, and is output to pins 36and 34 to be supplied to Q501 (V/C/D).Video signal for sub picture is output to pin 42 of QV01, andis supplied to PIP unit (ZY01).

3-2 S-VIDEO SIGNALWhen a cable is connected to S-VIDEO terminal, innerswitch of S-VIDEO terminal is shorted to ground to turn offthe transistor (QV05 for VIDEO1 input) for S-VIDEOterminal detection. Then chroma input terminal (Pin 14 forVIDEO1 input) of QV01 turns open. From pins 36 and 34(Y/C output) of QV01, Y/C signal of selected source isoutput.

46

AV SW CIRCUIT

Fig. 5-1

TUNR/IMA L/R V out

TIFV Aout

QV01 TA1218NEQ

VIDEO 3

VIDEO 1

VIDEO 2

PIP AUDIOOUT

MONITOROUT

PIP

V in

Y in

C in

Q501

Y out

C out

V in

COMBFILTER

SYNC inQA01

L/R in

DSP

18

17

16

15

14

13

12

11

10

9

8

7

6

5

2

1

26

28

29

30

31

32

34

35

36

37

38

42

C in

R in

S in

L in

C in

R in

S in

L in

V in

R in

L in

V in

R in

L in

PIP R out

PIP L out

SYNC OUT

PIP TV in

PIP L in

Y in

PIP R in

C out

R out

Y out

L out

H out

PIP V out

C in

47

SECTION VIVIDEO PROCESSING CIRCUIT

48

1. OUTLINE

This circuit converts and amplifies video signal (Luminanceand chroma signals) separated into Y/C, to original colorsignal, and is supplied to CRT Drive circuit.

2. SIGNAL FLOW

Signal flow chart is shown in fig. 6-2 Block diagram.(1) Luminance signal is input to pin 15 of Q501, and enters

into delayline inside Q501 to be output to pin 4.(2) Chroma signal is input to pin 13, and I/Q signal which

is demodulated in color, is output to pins 5 and 6, andnext supplied to pins 51 and 52.

(3) The signal is processed on luminance and chroma

signals, and is converted to original color signal (R,G,B)by RGB matrix. Next the signal is superimposed withOSD signal to be output to pins 41, 42 and 43, and issupplied to CRT Drive circuit.

(4) The signal for Scan Modulation is processed withdifferential in Q501 to be output to pin 48 Besides, atterminal for adjustment TP501, luminance and chromasignals are automatically output according to the selecteditems of service mode.

3. CIRCUIT OPERATIONAll processing operation of video signal are done insideQ501. The outline of Q501 (TA1222N) is explained in thenext section. Here, major terminals excepting input/outputterminals of Q501 are described.

49

Terminals concerning Video / Chroma circuit of Q501 are explained here.

# 1 CW OUTPUT 3.58MHz which is synchronized to burst signal is output, and is used for clock of comb filter.# 2 SCP OUTPUT The signal which is superimposed with burst gate pulse and blanking pulse is output. It is not

used in this time.# 3 SECAM CONTROL When receiving SECAM (Color system of East Europe) signal, it produces DC output. It is not

used in this time.# 4 Y1 OUTPUT Luminance signal of Y1 input (# 15) is output through delay line.# 5 Q OUTPUT Chroma signal of #13 is demodulated in IQ, and Q signal is output.# 6 I OUTPUT I signal of those of IQ demodulated is output.# 7 1H DL CONTROL Color demodulation control signal of PAL, SECAM system (European color system) is output.

It is not used in this time.# 8 XTAL 3 Crystal oscillator terminal. Not used.# 9 XTAL 2 Ditto# 10 XTAL 1 3.58MHz crystal oscillation terminal.# 11 APC FILTER Color sync. phase detecting terminal.# 12 Vcc 1 5V source (chroma line) terminal# 13 C INPUT Color signal input terminal# 14 GND Grounding terminal of chroma circuit# 15 Y1 INPUT Luminance signal input terminal# 32 PIP Ys Input terminal for switching pulse signal of PIP signal# 33 PIP B Input terminal of PIP RGB signal# 34 PIP G Ditto# 35 PIP R Ditto# 36 OSD Ys Input terminal for switching pulse signal of OSD signal# 37 OSD B Input terminal for OSD RGB signal# 38 OSD G Ditto# 39 OSD R Ditto# 40 Vcc 2 +9V source terminal# 41 B OUTPUT RGB output terminal# 42 G OUTPUT Ditto# 43 R OUTPUT Ditto# 44 GND Ground terminal of Y, color difference, RGB circuits# 45 ABL Input terminal for ABL control# 46 Vcc 3 +9V source terminal# 47 Ym Input terminal for half tone control pulse which is supplied from

microcomputer# 48 VSM Output terminal of velocity modulation signal# 49 APL DET Detects average level of video signal for correcting DC transmission# 50 BLACK DET Detects black area in video signal for black expanding circuit# 51 I INPUT Input signal for I signal of IQ demodulation signal# 52 Q INPUT Input signal for Q signal of IQ demodulation signal# 53 Y2 INPUT Input terminal for Y-picture control circuit# 54 COL Terminal for peak hold of color limiter# 55 DAC 1 Test point (TP501) output terminal# 56 DAC 2 External circuit control terminal (Not used)

50

Fig. 6-1 TA1222N VCD IC PIN LAYOUT CHART

0.6V(P

)

TO

CO

MB

1V(P

-P)

4.43orN

M 3.58

300mV

(P)

1V(P

)1V

(P)

pullor R

+B

7.5V7.5V

(AF

C)

1.0V(D

IR)

<S

DA

><

SC

L><

5V

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

5655

5453

5251

5049

4847

4645

4443

4241

4039

3837

3635

3433

3231

3029

CW OUTPUTCOLOR IDENT. OUTPUT

SCP OUTPUT

SECAM CONTROL

Y1 OUTPUT

Q OUTPUT

I OUTPUT

1H DL CONTROL

XTAL 3

XTAL 2

XTAL 1

APC FILTER

Vcc 1 (+5V)

CHROMA INPUT

CHROMA GND

Y1 INPUT

V. SEP.

SYNC INPUT

SYNC OUTPUT

DEF GND

AFC 1

32 x FH

DEF Vcc (+9V)

H. OUT

BENDING CORRECT

AFC PULSE INPUTBLK INPUT

DIGITAL GND

SDA

SCL

DAC 2 (2bit)

DAC 1 (1bit)MONITOR OUTPUT

COLOR LIMITER

Y2 INPUT

Q INPUT

I INPUT

BLACK PEAK HOLD

APL DET.

VSM OUTPUT

Ym INPUTPOWER OFF INPUT

Vcc 3

ABL INPUT

Y, COLOR DIFFERENCE,RGB GND

R OUTPUT

G OUTPUT

B OUTPUT

Vcc 2 (+9V)

R ANALOG OSD INPUT

G ANALOG OSD INPUT

B ANALOG OSD INPUT

Ys ANALOG OSD INPUT

R INPUT

G INPUT

B INPUT

Ys INPUT

VP OUTPUT

HD OUTPUTEXTERNAL BPP INPUT

DAC GND

1V(P

)

2.5V(P

)(typ)

2.8V(P

)(typ)from

OS

D mC

om0.5V

(P)(typ)

from P

IP/T

EX

T 0.5V

(P)(typ)

8H

1yb

V(P

) denotes value ofpeak to peak.

300mV(P)

51

Fig. 6-2 Block diagram of Video Processing circuit

Fro

m A

/V B

oard

C Y

C Y Syn

c

Q

I

Y

Y

I

/Q

V

M

CO

LOR

DE

MO

D.

DE

LAY

LIN

E

SY

NC

/DE

FP

RO

CE

SS

ING

RG

BM

AT

RIX

RG

BS

W

VE

LOC

ITY

MO

DU

LAT

ION

CR

T D

RIV

E

Q50

1 V

/C/D

H.O

UT

VP

TP

501

OS

D

R

G

B

Y

s

Ym

3938

3736

4755

3123

171513

56

453

5251

48

43 42 41

CO

LO

R S

IGN

AL

PR

OC

ES

SIN

G

LU

MIN

AN

CE

SIG

NA

LP

RO

CE

SS

ING

Mic

roco

mpu

ter

OS

Dor

ED

S o

r C

.C

52

SECTION VIIV/C/D/IC

53

1. OUTLINEThis IC enables more precise picture setting than that of former IC (TA8845N) by means of large scale employmentof IIC bus, and reduces many peripheral components by containing filters inside.The main features (comparing TA8845) are as follows.

2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURECONTROLS

(Soft method of picture making)(Former/TA8845N) TA1222N

* Black expanding start point External constant BUS control* DC transmission correction quantity point External constant BUS control* Black level correction quantity External constant BUS control* Each ABCL characteristic External constant BUS control

3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE(Employment of automatic adjustment circuit by Fsc to absorb deviation / Employment of deviation aborbing method by high S/N filter and mask triming using fixed CR)

(Former/TA8845N) TA1222N* Y-DL Apa-con DL inside Inside* Chroma TOF/BPF External Inside*Velocity modulation processing circuit External Inside* Fsc trap for chroma demodulation output External Inside

4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE(Circuit operation by extremely low current / Employment of leak current cancel circuit / Employment of detection circuit which does not suffer from influence of stray capacity)

(Former/TA8845N) TA1222N* Chroma ACC / killer filter External Inside* Y / color difference clamp filter External Inside* Filter for filter automatic adjustment External Inside* AFC 2 filter External Inside

5. LOW COST OF IC* Involving peripheral components inside ——> Down sizing of chip ——> Newly employment (NPN Tr area ratio to former : -25%) of miniature process (PLAS-1 S process)* Involving peripheral components inside——>Increasing of power consumption——>2 power supply system

(5V / 9V used)* Involving peripheral components inside ——> Reducing of number of elements ——> Employment of new

circuit (1) Reducing of gate (change of preset method) of register for IIC decoder (2) Reducing of DAC elements (employment of rudder type DAC + temperature compensation circuit) (3) Deletion of chroma CW, ACC (employment of 90 degree shift phase circuit with automatic adjustment)

54

VCD BLOCK DIAGRAM (TA1222N)

17

SY

NC

IN

H. V.SYNC SEP

V. Sep 16

20

AF

C1

PHASE DET<APC-1>

21

3'5

" V

CD

32 FM VCO

25

BL

K/A

FC

IN

H. BLK

24

BE

ND

ING

C

OR

RE

CT

ION

PHASE DET<APC-2>

19 22 23

GND (DEF) VCC (DEF)

H. PHASESHIFT

H. DRIVE

Da

f vC

C

H.

ou

t

H. DUTYSW

Y.COUNT DOWN

Y.P OUT 31 VER OUT

SYNCOUT 18 SYNC OUT

27 SDA

D/ACONVERTER

REGISTER

DELAY LINE S WDELAY LINE

I2C BUSDECODER

26 GND

19 SCL

4 Y1 OUT

TOK29 GND

GAMMACORRECTION

BLACKLEVEL COR.

BLACKSTRETON

Y. CLAMP 53 Y2 OUT

30 BLACK PEAKHOLD

39 APL DET

28 VM OUTSRT

26

B.CRESTORE

A.P.L DET BLACKPEAK DET

WHITEPEAK DET

SHARPNESSDELAY LINE HPF TM AMP VM MUTE

SHARPNESSCONTROL T. NR AMP SUB CONT UNI COLOR

VCC (98)

5 Q OUTWPS HALF TONE CLAMP

6 Y OUT

33 B IN

34 G IN

35 R IN

36 OSD Ys IN

37 OSD B IN

38 OSD G IN

39 OSD R IN

22 Ys IN

25 ABL IN

RGB BRIGHT

CLAMP CONTRAST

YS SW

CLAMP OSD AMP

YS SW

RGBMATRIX

SWPEAK

ACL DET ABCL AMP

DRIVE CLAMP BLK

RGB OUTCUT OFF

41 42 43

B O

UT

G O

UT

R O

UT

VCC (98) GND

46 4447

YM

IN

POWER OFF INYM SW

30

HD

OU

T/B

LA

CK

EX

PA

ND

MA

TR

IX

HD OUTEXT EFP IN

2

SC

P O

UT

(SA

ND

CA

ST

LE)

S.C.POUT

DAC 1/2COLOR

SYS IDENT

1H DLCONTROLCW OUT

SECAMCONTROL

7

1H

DL

CO

NT

RO

L(F

OR

PA

L)

1

CW

OU

T/

CO

LO

R I

DE

NT

.

3SECAM CONTROL(FOR SECAM)

56

55

54

DAC 2

DAC 2

COLOR LIMITER

52Q IN

51I IN

HI BRIGHTCOLOR

COLORPEAK DET

CDE COLORGAMMA

IQ/UVCLAMP

FRESHCOLOR

IQ UVCONVERT

SW

UNI COLOR COLOR TINF DELAYTIME

AXISG-Y MATRIX CLAMP

HALFTONE

8

9

10

11

X tal-3 (PAL)

X tal-2 (PAL)

X tal-1 (3.58MHz)

APC FILTER

FILTERAUTO ADJ

LPHFSC TRAP

CHROMAVCO

CWMATRIX

CHROMADEMOD.

CHROMABLK

P/N IDENTBETAPC DET

ACC DETSUB

COLOR

129V

34GND

13CHROMA IN

GND

VCC

(88)

ACC AMP TOF SW

SW

SW

BPF

FDC TRAPDELAYLINE

SYNC CHIPCLAMPY IN 15

V.SYNC SEP

V. SEPH.

COUNT DOWNH.

PARABOLA

55

SECTION VIIIPIP MODULE

56

4V

0V

4.8V

4.1V

3.0V10µS

6V

-0.9V

1µS4.2V

0V

Or

B CHASSIS C CHASSIS

PIN I/O NAME PIN I/O NAME

1 0 YS 9 I 5V

2 - NC 10 I GND

3 I GND 11 I VD

4 O R OUT 12 I HD

5 O G OUT 13 I/O SCL

6 O B OUT 14 I/O SCL

7 I GND 15 - NC

8 I PIP VIDEO

PMUS 02H (SN:23148232)

4.8V

4.1V

4.8V

4.1V

4.8V

2.8V

350µS

0V4.2V

B-Y OFFSET

R-Y OFFSET

TINT

RY54 RY55 RY50

15

14

13

12

11

10

987654321

57

8 36 14

13

12

10

11

51

49

47

78

76

67

65

64

18

16

19

18

16

23

24

25

4

5

6

11

12

VIDEOIN

B-YOUT

R-YOUT

Y-OUT

HD

VD

QY01mPC 1832GT(PIP V/C/D)

QY03TC9083F

(PIP PROCESSOR)

SLICE

WAVE FORMMODULATION

RY55 RY54

PMUS02H<BLOCK DIAGRAM OF PIP MODULE>

BI

RI

YI

HDCN

VDCN

BO

RO

YO

HDPN

VDPN

B-YINR-YIN

YIN

R OUT

G OUT

B OUT

QY01mPC1832GT(PIP V/C/D)

R OUT

G OUT

B OUT

PIP VIDEO

VD

HD

58

SECTION IXSYNC SEPARATION, H-AFC,H-OSCILLATOR CIRCUITS

59

1. SYNC SEPARATION CIRCUIT

The sync separation circuit separates a sync signal from avideo signal and feeds it to an H and V deflection circuits.The separation circuit consists of an amplitude separation (Hand V sync separation circuit) and a frequency separationcircuit (V sync separation circuit) which performs theseparation by using a frequency difference between H and V.In the N5SS chassis, all these sync separation circuits arecontained in a V/C/D IC (TA1222N).Fig. 9-1 shows a block diagram of the sync separation circuit.

Fig. 9-1 Sync separation circuit block diagram

Fig. 9-2 Synchronous separation by auto slider system

1-1. Theory of Operation1-1-1. Auto slicer type synchronous separation circuitWhen a synchronizing signal is separated, synchronousseparation is made from the beginning with constant voltagein the conventional synchronous separation circuit. The autoslider type circuit employed in this time makes synchronousseparation at a constant rate against the synchronizing signalamplitude. (See Fig. 9-2)In this method, even if an abnormal signal with smallamplitude is applied, stable synchronizing performance canbe obtained without separating pedestal.

17

Sync input

Compositevideosignal

Q501

H. V SYNCSEPARATION

CIRCUIT

V SYNCSEPARATION

CIRCUIT

WAVEFORMSHAPEING

CIRCUIT

H sync siganl

V sync signal(Reset pulse)

B

A

D

B

Pedestal Level

a: Corect Sync. Signal

Sync Separation Level A:B=C:Db: Small Amplitude Sync. Signal

60

1-1-2. V Sync Separation CircuitTo separate a V sync signal from the composite sync signalconsisting of V and H sync signals mixed, two stages ofintegration circuits are provided inside the IC. The circuitconsists of a differential circuit and a Miller integrationcircuit, and has following functions.(1) Removes H sync signal component.(2) Maintain stable V sync performance for a tape recorded

with a copy guard.(3) Stabilized V sync performance under special field

conditions (poor field, ghost, sync depressed, adjacentchannel best).

The V sync signal separated in this stage is processed in awaveform shape circuit and then used as a reset pulse in theV division circuit as stated later.

2. H AFC (Automatic Frequency Control)CIRCUIT

A sync system which performs synchronization with eachwaveform of the sync signal as performed in a sync systemin the V circuit is called a direct type sync system. However,if the synchronization for the H oscillator is carried out withthis method, the H oscillator synchronizes with externalnoises and the H synchronization will be disturbed. Toprevent this, an output of the H oscillator is compared witha reference H sync signal to detect deviations of frequencyand phase. The H oscillator is automatically controlled withthe detected output averaged. This circuit is called an AFCcircuit.In the N4SS chassis, a conventional AFC circuit is notemployed but a new double AFC circuit built-in the TA1222Nis used. Fig. 9-3 shows the AFC circuit and the block diagramof the circuit.

Fig. 9-3 H AFC circuit block diagram

First, phases of a 32 fH counted-down signal and a H syncsignal contained in broadcasting signal are compared in theAFCI loop and the loop develops an H pulse signal for theAFCII loop. That is, when a phase deference 01 exists incomparison of the phase of fH signal developed by countingdown the 32 fH signal and the phase of H sync signal of thebroadcasting signal, an error signal corresponding to thephase different is detected and a correction voltage ???1corresponding to the error output is generated. With thiscorrection voltage, the 32 fH oscillator circuit is controlled.The correction (control) voltage for the oscillator varies indirection of positive or negative corresponding to phase leador lag of the fH pulse (developed by counting down) from theH sync signal. As the H oscillator (32 x fH), a voltagecontrolled oscillator (VCO), oscillation frequency and phaseof which can be controlled with the control voltage is used.Next, an H pulse signal is created from the fH signal counteddown, and the pulse is used instead of the H sync signal in theAFCII circuit. The AFCII circuit differs in the loop of thecount down circuit and H output circuit.The AFCII circuit compares phase of a H BLK pulse createdby waveform shaping a AFC pulse from the FBT and a phaseof the H pulse, and detects an error component correspondingto the phase difference 02 (if exist) and develops acorrection voltage V2 corresponding to the error, therebycontrolling the phase of Q501 H out.The H output control voltage varies in a positive or negativedirection corresponding to the phase lead or lag of the H BLKpulse from that of the H pulse. The phase of H out is variedwith the control voltage to make synchronization with the Hpulse phase.The purpose of the double AFC circuit employed this time isto improve horizontal jitter under signal reception in a poorelectrical field. The jitter in the poor field strength and

SYNC SEPARATIONCIRCUIT

PHASE DETECTIONCIRCUIT

32 x fHVCO

H COUNT DOWN(DIVIDING)

AFC I LOOP

PHASE DETECTIONCIRCUIT

AFC II LOOP

H DRIVEH OUTPUTCIRCUIT

FBT PULSE(AFC PULSE)

61

distortion due to phase difference are incompatible. Thatis,to improve the jitter under poor field strength, responsespeed must be slowed by lowering the AFC sensitivity. Onthe other hand, to improve distortion due to the phasedifference, the response must be increased by increasing theAFC sensitivity.In a conventional AFC circuit, setting of the sensitivity iscarried out at one part only, so an compromise point for bothcharacteristics must be found. However, with the doubleAFC circuit employed this time, for the jitter the AFCI loopworks best with decreasing the sensitivity and for the phasedistortion the AFCII loop works with increasing thesensitivity.

3. H OSCILLATOR CIRCUIT

3-1. OutlineA 503 kHz (32 x fH) voltage controlled type oscillator witha ceramic oscillation element is used to generate a clockpulse and the clock is counted down, thereby obviating theneed of adjustments for both the H and V deflection processcircuit.

3-2. Theory of Operation(1) The H sync signal used as a reference signal enters from

the sync separation circuit to the AFCI circuit. At thesame time, the fH pulse created by counting down the32 x fH pulse generated in the ceramic oscillator entersthe H AFCI circuit. Phase difference between these twosignals enters an integration circuit (low pas filter)connected to pin 4 and converted into a DC voltage(AFC voltage).

Fig. 9-4

17 20 21

SYNCIN

2VP-P

H Vcc

SYNCSEPARATION

CIRCUIT

H AFC ICIRCUIT

32 x fHVCO

H COUNTDOWN

H AFC IICIRCUIT

TA1222N

62

(2) The AFC voltage controls frequency (32 x fH) of theoscillator (VCO).Fig. 9-5 shows the control characteristics of the VCO.

(3) The H output is obtained by dividing the 32 x fH (503kHz) of the oscillator with flip-flops. Fig. 9-6 shows theblock diagram of this count down circuit.

(4) The V output is created by dividing the 32 x fHoscillator output into 1/8, and then by counting the 4 xfH pulse with a vertical counter which is reset with a Vreset pulse (V sync output signal stated under syncseparation).

(5) That is, the V output is not created by simply countingdown the H by performing V synchronization with a Vreset pulse entering within a window provided for Vsynchronization --- called direct type sync system, thus,the circuit can work for non standard signals.

Fig. 9-5

Fig. 9-6 Block diagram of H, V count down circuits

High

Low

Low High AFC voltage (V)

32 x fH VCO32fH

X 1/8 X 1/4 H OUTPUT

V OUTPUTV

COUNTER

Resetpulse

V syncsignal V WAVEFORM

SHAPECIRCUIT

4fH fH

63

SECTION XVERTICAL OUTPUT CIRCUIT

64

1. OUTLINE

As can be seen from the block diagram, the sync circuit andthe V trigger circuit are contained in Q501 (TA1222N), andthe sawtooth generation circuit and amplifier (V drive circuit)contained in Q302 (TA8859AP). The output circuit andpump-up circuit circuits are included in Q301 (TA8427K).

Fig. 10-2

1-1. Theory of OperationThe purpose of the V output circuit is to provide a sawtoothwave signal with good linearity in V period to the deflectionyoke.When a switch S is opened, an electric charge charged up to areference voltage VP discharges in an constant current rate, anda reference sawtooth voltage generates at point a. This voltageis applied to (+) input (non-inverted input) of an differentialamplifier, A. As the amplification factor of A is sufficientlyhigh, a deflection current flows so that the voltage V2 at pointC becomes equal to the voltage at point a.

Fig. 10-1 Block diagram of V deflection circuit

31

15

14

13

3

6

8

7 6

4

1 5

2

3

C322

R329

Q501C321

R320

Q302

+9VD309

+27V

R301

R330

C319

C314

Q301

Q312 Q311

R309 C308

D301 C313

R303

L301 R336

R307 L462

R306

R313C306

R344

+27VR305

C305R304

C307

Vp S: SwitchDifferentialamplifier

C2

R3

V2c

R1 C2 R2

a

V1

L

65

2. V OUTPUT CIRCUIT

2-1. Actual Circuit

Fig. 10- 3

2-2. Sawtooth Waveform Generation2-2-1. Circuit OperationThe sawtooth waveform generation circuit consists of asshown in Fig. 10-4. When a trigger pulse enters pin 13, it isdifferentiated in the waveform shape circuit and only thefalling part is detected by the trigger detection circuit, to thewaveform generation circuit is not susceptible to variationsof input pulse width.The pulse generation circuit also works to fix the V rampvoltage at a reference voltage when the trigger pulse enters,so it can prevent the sawtooth wave start voltage fromvariations by horizontal components, thus improvinginterlacing characteristics.

Fig. 10-4

31

15

14

13

3

6

8

7 6

4

1 5

2

3

C322

R329

Q501C321

R320

Q302

+9VD309

+27V

R301

R330

C319

C314

Q301

Q312 Q311

R309 C308

D301 C313

R303

L301 R336

R307 L462

R306

R313C306

R344

+27VR305

C305R304

C307

13

14 15 16

R329 C321 C322 C323

5Vp

DC=0V

WAVEFORMSHAPE

TRIGGERDET.

PULSEGAIN

V. LAMP AGC

66

2-3. V Output

2-3-1. Circuit OperationThe V output circuit consists of a V driver circuit Q302,Pump-up circuit and output circuit Q301, and external circuitcomponents.(1) Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4

output stage connected in a SEPP amplifies the currentand supplies a sawtooth waveform current to a deflection

yoke. Q3 turns on for first half of the scanning periodand allows a positive current to flow into the deflectionyoke (Q3 1DY C306 R305 GND), and Q4turns on for last half of the scanning period and allowsa negative current to flow into the deflection yoke(R305 C306 DY Q4). These operations areshown in Fig. 10-5.

Fig. 10-6 Output stage operation waveform

Fig. 10-5 V output circuit

(2) In Fig. 10-6 (a), the power Vcc is expressed as a fixedlevel, and the positive and negative current flowing intothe deflection yoke is a current (d) = current (b) + (c) inFig. 10-6, and the emitter voltage of Q3 and Q4 isexpressed as (e).

(3) Q3 collector loss is i1 x Vce1 and the value is equal tomultiplication of Fig. 10-6 (b) and slanted section ofFig. 10-6 (e), and Q4 collector loss is equal tomultiplication of Fig. 10-6 (c) and dotted section of Fig.10-6 (e).

V 3

V 7

V 2

1

4

2

7

36

Q2

Q4

BIASCIRCUIT

Q3

Q301

+27VD301 C308

D308

D309 R309

DY

C306

R305 Q3 ON

Q4 ON

GND

GND

50V

27V

GND

27V

GND

50V

Power Vcc

Q3

Q4

Q2

i1

i2

Vce 1

GND (b) Q3 Collector current i1

GND (c) Q4 Collector current i2

GND (d) Deflection yoke current i1+i2

VpVcc1/2 Vcc

GND

(e)

(a) Basic circuit

67

(4) To decrease the collector loss of Q3, the power supplyvoltage is decreased during scanning period as shownin Fig. 10-7, and VCE1 decreases and the collector lossof Q3 also decreases.

Fig. 10-8

(6) Since pin 7 of a transistor switch inside Q301 is connectedto the ground for the scanning period, the power supply(pin 3) of the output stage shows a voltage of (VCC-VF), and C308 is charged up to a voltage of (VCC-VF--VR) for this period.

(7) First half of flyback periodCurrent flows into L462 D1 C308 D308 VCC(+27V) GND R305 C306 L462 in this order,and the voltage across these is:VP=VCC+VF+(VCC-VF-VR)+VF about 50V isapplied to pin 3. In this case, D301 is cut off.

(8) Last half of flyback periodCurrent flows into VCC switch D309 C308Q301 (pin 3) Q3 L462 C306 R305 in this order,and a voltage ofVP=VCC-VCE (sat)-VF+(VCC-VF-VR)-VCE (sat),about 40V is applied to pin 3.

(9) In this way, a power supply voltage of about 27V isapplied to the output stage for the scanning period andabout 50V for flyback period.

Fig. 10-7 Output stage power supply voltage

(5) In this way, the circuit which switches power supplycircuit during scanning period and flyback period iscalled a pump-up circuit. The purpose of the pump-upcircuit is to return the deflection yoke current rapidlyfor a short period (within the flyback period) by applyinga high voltage for the flyback period. The basic operationis shown in Fig. 10-8.

Q3 Collector loss decreasesby amount of this area

Power supplyfor flyback period (Vp)

Power supplyfor scanning period(Vcc)

Scanning period

Flyback period

6 3

7

2

6 3

7

2

D301 C308

D308Q301

D309 R309

Switch

Q3

Q4

D1

L462

C306

R305

D301 C308

Q301

D309 R309

Q3

Q4

D1

L462

C306

R305

Switch VR

Last half

(a) Scanning period (b) Flyback period

First half

68

2-4. V Linearity Characteristic Correction

2-4-1. S-character Correction(Up-and Down-ward Extension Correction)

A parabola component developed across C306 is integratedby R306 and C305, and the voltage is applied to pin 6 ofQ302 to perform S-character correction.

2-4-2. Up-and Down-ward Linearity BalanceA voltage developed at pin 2 of Q301 is divided withresistors R307 and R303, and the voltage is applied to pin 6of Q301 to improve the linearity balance characteristic.Moreover, the S-character correction, up- and down-wardbalance correction, and M-character correction are alsoperformed through the bus control.

69

SECTION XIHORIZONTAL DEFLECTION CIRCUIT

70

1. OUTLINE

The H deflection circuit works to deflect a beam from left toright by flowing a sawtooth waveform of 15.734 kHz into theDY H deflection coil.

2. HORIZONTAL DRIVE CIRCUIT

The H drive circuit works to start the H output circuit byapplying HVCC (Q501 DEF power source) to pin 22 ofQ501 (TA1222N) and a bias to the H drive transistor Q402at the main power on.

2-1. Theory of Operation(1) When the power switch is on, the main power supply of

125V starts to rise. At the same time, AF power supply25V also rises.

(2) With 25V line risen, Q430 base voltage which is createdby dividing the audio power with R433 and D430 alsorises. Then, the transistor Q430 turns on and the HVCCis applied from the audio power line through R432 andD431 to pin 22 of Q501.

Fig. 11-1 H drive circuit block diagram

81 81 22

R432 Q430 D431

R433D430

BB80

BB81

L400

SIGNAL C431 C430 D490

H Vcc

Q501

71

3. BASIC OPERATION OF HORIZONTALDRIVE

A sufficient current must flow into base of the horizontaloutput transistor to rapidly make it into a saturated (ON)condition or a cut off (OFF) condition. For this purpose, adrive amplifier is provided between the oscillator circuit andthe output circuit to amplify and to waveshape the pulsevoltage.

3-1. Theory of Operation(1) The horizontal drive circuit works as a so called switching

circuit which applies a pulse voltage to the outputtransistor base and makes the transistor on when thevoltage swings in forward direction and off in reversedirection.

(2) To turn on the output transistor completely and to makethe internal impedance low, a sufficiently high, forwarddrive voltage must be applied to the base and heavy basecurrent ib must be flown. On the contrary, to completely

turn off the transistor, a sufficiently high, reverse voltagemust be applied to the base.

(3) When the transistor is on (collector current is maximum)condition with the sufficiently high forward voltageapplied to the base, the transistor can not be turned offimmediately, if a reverse base bias is applied to the basebecause minority carriers storaged in the base can notbe reduced to zero instantly. That is, a reverse currentflows through an external circuit and gradually reducesto zero. The time lag required for the base current todisappear is called a storage time and falling time.

(4) To shorten the storage time and the falling time, asufficiently high reverse bias voltage must be applied toallow a heavy reverse current to flow. This operationalso stabilizes operation of the horizontal outputtransistor.

Fig. 11-2

(a)

ib

V

+

0

-

+

0

-

On period OFF period

t Input waveform (b)

t Base current (c)

Forwardcurrent

Reversecurrent

Fallingtime

Storagetime

72

3-2. Drive System3-2-1. ON drive systemWhen the drive transistor is on, the horizontal output transistoralso turns on.

Merit:• The base current can be precisely controlled without

being affected by variation of pulse width which iscaused by the horizontal oscillator circuit and the drivecircuit.

Demerit:• It is difficult to flow a reverse bias current to the horizontal

output transistor to eliminate its storage carrier for transientperiod of on to off period for the horizontal outputtransistor.

3-2-2. OFF drive systemWhen the drive transistor is on, the horizontal output transistoris off.

Merit:• Energy balance between on and off periods of the drive

circuit is better, and the circuit can be simplified.• Reverse base current of the horizontal output transistor

can be controlled easily.

Demerit:• Base-emitter forward current flowing into the horizontal

output transistor is susceptible to on-period variation ofthe drive transistor.

Fig. 11-3 Fig. 11-4

H OSC

H driver

H output

ON(OFF)

ON(OFF)

+B

H OSC

H driver

H output

ON(OFF)

ON(OFF)

+B

73

3-3. Circuit Description

In the N5SS chassis, the off drive system is employed.(1) When Q1 inside Q501 is turned on, Q402 base is

forward biased through 9 Vpin 22 of Q501 (H.VCC) pin 23 of Q501 (H. Out) R411/R410 resistordivider, and then, Q402 collector current flows through125V R416 T401. In this case, the H outputtransistor Q404 turns on with the base-emitter reversebiased because of the off drive system employed.

(2) On the contrary, when Q1 inside IC501 is off (pin 8 is0V), base-emitter bias of Q402 becomes 0V and Q402turns off, and a collector pulse as shown in Fig. 11-5develops at the collector.The voltage is stepped down and Q404 is forwardbiased with this voltage, thus turning on Q404.

(3) In this way, by stepping down the voltage developed atprimary winding of the drive transformer and byapplying it to Q404, a sufficient base current flows intoQ404 base, thereby switching the Q404.

Fig. 11-5

Q501

22

23

1 3

2 4

Q1

H. Vcc

D490 C431

R410

R411

9V

Q402H drive

transistor

C417

R415

T401H drive

transistor

Q404H outputtransistor

V1V2

0V

0V

VCP

Q402OFF

Q402ON

R416

C416

+125V

C43

+

74

4. HORIZONTAL OUTPUT CIRCUIT

The horizontal output circuit applies a 15.734 kHz sawtoothwave current to the deflection coil with mutual action of thehorizontal output transistor and the damper diode, and deflectsthe electron beam from left to right in horizontal direction.

Fig. 11-6

IC501

H. out

Q1 23 33

10

5

2

3

1

HV

8

S-charactorcapacitor

Hlinearity

coilM-charactorcorrection

Resonatcapacitor

Diode modulator circuit

To DPC output

SIGNAL DEF/POWER PCB

TP-33

BB31

R411R410

C413

C416 R416

125V

Q402H drive

R415

C417

T401H drive

transformer

Q404H output

(With damper diode)

T461FBT

L462Deflection yoke

(H coil)

C463

D461

C444

C440

C442

C467C423 L442

L441

R441

+

C464+

L461

75

4-1. Theory of Operation4-1-1. Operation of Basic Circuit(1) To perform the horizontal scanning, a 15.734 kHz

sawtooth wave current must be flown into the horizontaldeflection coil. Theoretically speaking, this operationcan be made with the circuit shown in Fig. 11-7 a andb.

(2) As the switching operation of the circuit can be replacedwith switching operation of a transistor and a diode, thebasic circuit of the horizontal output can be expressedby the circuit shown in Fig. 11-7 a. That is, the transistorcan be turned on or off by applying a pulse across thebase emitter. A forward switching current flows for on-period, and a reverse switching current flows throughthe diode for off-period. This switching is automaticallycarried out. The diode used for this purpose is called adamper diode.

Description of the basic circuit1. t1~t2:A positive pulse is applied to base of the output transistorfrom the drive circuit, and a forward base current is flowing.The output transistor is turned on in sufficient saturationarea. As a result, the collector voltage is almost equal to theground voltage and the deflection current increases fromzero to a value in proportionally. (The current reachesmaximum at t2, and a right half of picture is scanned up tothis period.)

2. t2:The base drive voltage rapidly changes to negative at t2 andthe base current becomes zero. The output transistor turnsoff, collector current reduces to zero, and the deflectioncurrent stops to increase.

3. t2~t3:The drive voltage turns off at t2, but the deflection currentcan not reduce to zero immediately because of inherentnature of the coil and continues to flow, gradually decreasingby charging the resonant capacitor C0. At the same time, thecapacitor voltage or the collector voltage is graduallyincreases, and reaches maximum voltage when the deflectioncurrent reaches zero at t3. Under this condition, all electro-magnetic energy in the deflection coil at t2 is transferred tothe resonant capacitor in a form of electrostatic energy.

4. t3~t4:Since the charged energy in the resonant capacitor dischargesthrough the deflection coil, the deflection current increasesin reverse direction, and voltage at the capacitor graduallyreduces. That is, the electrostatic energy in the resonantcapacitor is converted into a electromagnetic energy in thisprocess.

5. t4:When the discharge is completed, the voltage reduces tozero, and the deflection current reaches maximum value inreverse direction. The t2~t4 is the horizontal flyback period,and the electron beam is returned from right end to the leftend on the screen by the deflection current stated above. Theoperation for this period is equivalent to a half cycle of theresonant phenomenon with L and C0, and the flyback periodis determined by L and C0.

Fig. 11-7

a H output basic circuit

b H output equivalent circuit

H outputtransistor

D Co L

DeflectionyokeResonant

capacitor

Damperdiode

Vcc

Vcc

SW1 SW2 Co L

76

6. t4~t6:For this period. C0 is charged with the deflection currenthaving opposite polarity to that of the deflection currentstated in "3.", and when the resonant capacitor voltageexceeds VCC, the damper diode D conducts. The deflectioncurrent decreases along to an exponential function(approximately linear) curve and reaches zero at t6. Here,operation returns to the state described under "1.", and theone period of the horizontal scanning completes. For thisperiod a left half of the screen is scanned.In this way, in the horizontal deflection scanning, a currentflowing through the damper diode scans the left half of thescreen; the current developed by the horizontal outputtransistor scans the right half of the screen; and for theflyback period, both the damper diode and the output transistorare cut off and the oscillation current of the circuit is used.Using the oscillation current improves efficiency of thecircuit. That is, about a half of deflection current (one fourthin terms of power) is sufficient for the horizontal outputtransistor.

Fig. 11-8

A

B

C

D

E

F

G

H

t1 t2 t3 t4 t5 t6

0

0

0

0

0

0

0

0

TRbase voltage

TRbase current

TRcollector current

Ddampercurrent (SW2)

Switchcurrent(TR, SW1)

Resonantcapacitorcurrent (Co)

Deflectioncurrent (Lo)

TRcollectorvoltage

77

4-1-2. Linearity Correction (LIN)(1) S-curve Correction (S Capacitor)Pictures are expanded at left and right ends of the screen evenif a sawtooth current with good linearity flows in the deflectioncoil when deflection angle of a picture tube increases. Thisis because projected image sizes on the screen are differentat screen center area and the circumference area as shown inFig. 11-9. To suppress this expansion at the screencircumference, it is necessary to set the deflection angle @to a large value (rapidly deflecting the electron beam) at thescreen center area, and to set the deflection angle @ to a smallvalue (scanning the electron beam slowly) at thecircumference area as shown in Fig. 11-9.In the horizontal output circuit shown in Fig. 11-10, capacitorCS connected in series with the deflection coil LH is to blockDC current. By properly selecting the value of CS and bygenerating a parabolic voltage developed by integrating thedeflection coild current across the S capacitor, and by varyingthe deflection yoke voltage with the voltage, the scanningspeed is decreased at beginning and end of the scanning, andincreased at center area of the screen. The S curve correctionis carried out in this way, thereby obtaining pictures withgood linearity.

Fig. 11-9

Fig. 11-10

q2 q1

t2 t1

t2 = t1q2 q1<

q2 q1

t2 t1

t2 > t1q2 q1=

(a) S-character correction (b)

TRD Co

Cs

LH

Deflection coil

(a) H output circuit

(b) Sawtooth wave current

(c) Voltage across LH Fast deflection

Slow deflection

(d) Synthesized current

Vcc

78

(2) Left-right Asymmetrical Correction (LIN coil)In the circuit shown in Fig. 11-11 a, the deflection coilcurrent iH does not flow straight as shown by a dotted line inthe figure b if the linearity coil does not exist, by flows asshown by the solid line because of effect of the diode for afirst scanning (screen left side) and effect of resistance of thedeflection coil for later half period of scanning (screen rightside). That is, the deflection current becomes a sawtoothcurrent with bad linearity, resulting in reproducing ofasymmetrical pictures at left and right sides of the screen (leftside expanded, right side compressed).When a horizontal linearity oil L1 with a current characteristicas shown in figure c is used, left side picture will becompressed and right side picture will be expanded becausethe inductance is high at the left side on the screen and lowat the right side. The left-right asymmetrical correction iscarried out in this way, and pictures with good linearity in

total are obtained.

4-1-3. Horizontal Linearity, M-character CorrectionCircuit

Since deflection angle increases with size of picture tubeincreases, a M character trend which compresses a pictureimage at beginning and end of the scanning will occur. A Mcharacter linearity correction circuit is provided in the N5SSas shown in Fig. 11-12. The M character linearity correctionis carried out by connecting a series resonant circuit inparallel with the S capacitor and flowing a resonant current

Fig. 11-11 Linearity coilFig. 11-12

(a)

(b) Deflection coil current

Deflection coil current

(iH)

0 Characteristic of D

Resistance of LH

(c) Linearity coil characteristic

Linearity coil characteristic

Inductance(mH)

(Left) (Right)

(Left) (Right)Current (A)

TRD Co

LH

Deflectioncoil

FBT

VcciH Li

CsS-charactercapacitor

TRD Co

LH

LI

L

CCs

(b) Sawtooth wave current

Fast Slow Fast Slow Fast

(c) Synthesized current

79

which has two times the H oscillator frequency.

5. HIGH VOLTAGE GENERATIONCIRCUIT

The high voltage generation circuit develops an anode voltagefor the picture tube, focus, screen, CRT heater, video output(210V) and so on by stepping up the pulse voltage developedfor flyback period of the horizontal output circuit with theFBT, and supplies the power to various circuit.

Fig. 11-13

10

9

4

7

6

3

2

1

5

Auxiliarywinding

Primarywinding

AFCblanking

Heater

+27V

-27.5V

+210V

+125V

C310

C303

D302

C460 D460

R327

R469

D406

C446

C448

D404

C463

T401

CRTanode

Focus

ScreenABL

H deflection coilL462

R441

C442

L441

01000VP-P

1H(15.75KHz)

80

5-1. Theory of Operation

5-1-1. +210VFor the flyback period, pulses are stacked up to DC +125Vwith FBT, and the voltage is rectified by D406 and filteredby C446.

5-1-2. +27VPin 4 of the FBT is grounded and the shaded area of negativepulse developed for opposite period of the flyback period isrectified, thus developing better regulation power supply.

5-1-3. -27VAs a power for the DPC circuit, a negative pulse signal isrectified by D460 and filtered with C460, thus developingthe -27V.

5-1-4. High voltageSingular rectification system which uses a harmonics non-resonant type FBT is employed and a better high voltageregulation is obtained, so amplitude variation of picturesbecomes low.

Fig. 11-14

Fig. 11-16

Fig. 11-15

+115V

0

10

4

7

8

2

1

0

0

0

For +27V

G

FE

D

C

B

A

E

DC

BA

G

FPrimary

Auxiliary

Picturetube anode

EO

ABL

EH

Pulse

Stackedpulse of4 block

1H15.735KHz

Picturetube capacitor

81

5-2. Operation Theory of the Harmonic Non-Resonant System and Tuned Waveforms

The high voltage coil is of film multi-layer winding type andthe coils are isolated into seven blocks. Each block isconnected through a diode.The basic operation is described in the case of 4 blocksconstruction for simplification. Positive or negative pulsedetermined by stray capacitance of each coil develops at

terminal points ( , , , , , GF , G ) of each coilas shown in Fig. 11-16, and these pulses are stacked asshown, thus developing the high voltage.Moreover, a capacitance between the internal and externalcoatings of the picture tube works as a smoothing capacitor.Focus voltage is obtained at point EO.The FBT is turned to a harmonic of 15 times the fundamental

Fig. 11-17 Tuned waveforms

Flybackpulse

63.5ms AC0

AC0

AC0

Referencewave45 KHz

Harmonics15 times675 KHz

Tunedwaveform

11ms

20ms

1 122ms 22x10

= = 45KHz

Becomes 45 KHz x 15 = 675KHzthis is determined by coil inductance capacitance and stray of FBT.

(In case of 3X) (In case of 15X)

Hightvoltage

Focuscurrent

Picture tube current

E E

In case of 15 times the harmonics as compared with 3 times the harmonics, average conduction peiod of the high voltage diode is wider.As a result, high voltage variations are suppressed.

82

frequency, and the turned waveform is shown in Fig. 11-17.

6. X-RAY PROTECTION CIRCUIT

1. OutlineIn case picture tube using high voltage, when high voltagerises abnormally due to components failure and circuitmalfunction, there is possible danger that X-RAY leakageincreases to affect human body. To prevent it, X-RAYprotection circuit is equipped.

2. OperationFigure 10-18 shows the circuit diagram. Supposing highvoltage rises abnormally due to some reason, pulse at pin 9of T461 also rises, and detection voltage Eb rectified byD471 and C471 in X-RAY protection circuit rises. When Ebrises, emitter voltage of Tr10 divided by R25 and R26 inprotector module becomes higher than [zener voltage (6.2V)of ZD6 + Tr10 VBE ]. This causes Tr10 turns on to supplybase current to Tr9. Then Tr9 turns on. By this Tr6 and Tr6turn on to make ON/OFF pulse at pin 7of QA01 in low level,QB30 and Q843 turns off, then relay SR81 turns off. Tr6 andTr7 are in thyristor-connection, and 5V of power holdsprotection operation until main power switch is turned off.During circuit operation, power LED near main powerswitch blinks in red. Caution : To restart TV set, repair failure

Figure 11-18 X-RAY protection circuit

15

16

12

13 9

5V

12VMICOMQA01#7

RELAYSR81

Q843 QB30

RB30

R9

R10

R21

R12

R25 R472 T461

D471R26

R20

D3ZD6

C471

Tr10Tr7 Tr9

Tr6

Tr5

C474

C1

R11

R22

ED

+

83

first.

7. OVER CURRENT PROTECTIONCIRCUIT

1. Outline If main power (125V) current increases abnormally due tocomponents failure, there is possible danger of the secondarydamage like failure getting involved in other part failure, andabnormal heating. To prevent this, over current protectioncircuit is equipped, which detects current of main B line toturn off power relay in abnormal situation.

2. OperationFig. 11-19 shows over current protection circuit. When thecurrent of main B line increases abnormally due to theshortage in load of main B line, voltage drop arises acrossR470. By this voltage drop, when base-emitter voltage of Tr8 in protector module (Z801) becomes appprox. 0.7V ormore, Tr 8 turns on, and the voltage by divided ratio of R15and R16 is applied to cathode of ZD4. When this voltagebecomes higher than zener voltage of ZD4, ZD4 turns on tosupply base current to base of Tr 6 via R14. This causes Tr5 ON and voltage at pin 16 of Z801 becomes Low. Therefore,QB30 and Q843 turns off to set SR81 OFF. Tr 6 and Tr 7 inZ801 are in thyristor- connection, and power 5V-1 suppliedat pin 15 keeps protection operation for standby power untilmain power switch is turned off. During circuit operation,power LED near main power switch blinks in red. Caution :

Fig. 11-19 Over current protection circuit

Z801PROTECTOR MODULE

16

15

17

2 1

5V

MICONQA01#7

RELAYSR81

Q843

R830

Q830

MAIN B

R470 F470

To T461

R479 R472

C472

R16

R15R14

R12

R11

R9

R10ZD4

C1

Tr6

Tr5

Tr7Tr8

Z801PROTECTION MODULE

84

To restart TV set, repair failure first.

8. KINK CORRECTION CIRCUIT

1. OutlineIn the N5SS chassis, a kink correction circuit is employed tocorrect a kink generating when receiving a black and whitepattern.In the black and white pattern cross hatch shown in Fig. 11-20, when the picture changes from black to white during fieldscan period, a current Is flows rapidly in secondary of theFBT and a current IP flows in reverse direction during scanperiod (due to transformer coupling) in the primary winding.This current works to increase the voltage across S charactercorrection capacitor CS. As a result, the deflection currentdecreases by I1 as shown in Fig. 11-21 and the raster movestoward left, thus causing the kink as shown in Fig. 11-22. Onthe contrary, when the picture changes from black to white,

the reverse operation will occur.

2. Circuit DescriptionTo correct the kink damping circuit is added between themain B power line and the S character capacitor as shown inFig. 11-23.In Fig. 11-24, a capacitor C441 is charged with a DC currentiB through Q442 connected to MAIN B during the flybackperiod. When the voltage across C441 and S charactercorrection capacitor increases during the scan period, thediode D442 conducts and reduces the voltage across C442 tothe original voltage level, thereby suppressing shift of theraster.

Fig. 11-24

Fig. 11-20Fig. 11-23

Fig. 11-21

Fig. 11-22

Cs+

-lp ls

FBT

l1

Kink in the cross bar pattern

Q404C444 C440 L642

C442 C441

D442 R442

T461

C448SIDE DPCL461

C464C467

D461

Kink CorrectionCircuit

L462

Vcs

Vcs

C442C441

D442

R442

MAINB

T461

C448

iB

85

SECTION XIIDEFLECTION DISTORTION

CORRECTION CIRCUIT(Side DPC Circuit)

86

1. DEFLECTION DISTORTIONCORRECTION IC (TA8859P)

1-1. OutlineThe deflection distortion correction IC (TA8859AP), incombination with a V/C/D IC (TA8859AP) which has a Vpulse output, performs correction for various deflectiondistortions and V output through the I2C bus control. All theI2C bus controls are carried out by a microcomputer and canbe controlled with the remote control.

1-2. Functions and FeaturesThe IC has functions of V RAMP voltage generation, Vamplitude automatic switching (50/60 Hz), V linearitycorrection, V amplification, EHT correction, side pincushioncorrection, I2C bus interface, etc. and controls followingitems through the I2C bus lines.(1) V amplitude(2) V linearity

(3) V S-character correction(4) V picture position (neutral voltage setting)(5) V M-character correction(6) V EHT correction(7) H amplitude(8) L and R pin-cushion distortion correction I (entire area)(9) L and R pin-cushion distortion correction II (corner

portions at top and bottom)(10) H trapezoid distortion correction(11) H EHT correction(12) V AGC time constant switching

1-3. Block DiagramFig. 12-1 shows a block diagram of the basic circuit.

Fig. 12-1

V. Trigger-in

(Bus Control Signal) SDA SCL

10

9

12

13

14 15 16 5 3

2

4168

+12V

Control ThroughBus

EW-Drive

V Drive V. Feedback EHT INPUT EW Feedback

WaveformShape

TriggerDet

PuiseGen.

V. Rame A G CV. AGC TimeConstant SW

H. Trapezoid DistortionCorrection

L-R PincushionDistortion Correction I

L-R PincushionDistortion Correction II

(Top & Bottom Comer Section)

H.EHTCorrction

H. AmplitudeAdj.

H.EHTInput

V. EHTCorrection

V. ScreenPosition

V. AmplitudeAdj.

V. M-CharacterCorrection

V. LinearityCorrection

V. S-CharacterCorrection

Logic

87

2. SIDE DPC

2-1. OutlineSince the deflection coil used in 29 and 34" type of N5SSchassis is not a DPC free type left and right pin-cushiondistortion must be corrected with a circuit.If the distortion is not corrected, pin-cushion distortion asshown in Fig. 12-2 (a) will occur.To correct this distortion, a H deflection current must bemodulated in a form of parabola for V sync period.The compensation circuit using a diode modulator systemwhich has a large amount of compensation ability is used inN4SS chassis.The correction circuit in N5SS chassis is of a negative typeand the diode modulator develops a negative voltage.Accordingly, a negative power supply is used in the amplifier

and the output circuit.The circuit can be controlled through the I2C bus. That is, theparabola waveform and DC voltage obtained by controllingE/W output (pin 2) of Q302 (TA8859P) through the bus isshifted in their levels by zener diodes (D464, D465, D466)to use them as a negative power source. The voltage is addedto the amplifier and the output circuit (Q462, Q460) andmodulates the voltage at CD11 in the diode modulatorcircuit. Thus developed parabola voltage is a negative voltageand the sum with the main B voltage (VB) is applied acrossthe S character capacitor. This voltage works as a powersupply for the H deflection yoke and the H deflection currentis modulated as shown in Fig. 12-2 (b), thus correcting theleft and right pin-cushion distortion.

Fig. 12-3 Diode modulator type side DPC circuit

(b) H deflection current(a) Left and right pin-cushion distortion

Fig. 12-2

V. Sync

H. Sync

3 13

9

10

4

2

Q501V/C/DIC

TA1222N

Q302E/W IC

TA8859P

PARABORAVOLTAGE

GEN.

WAVEFORMPROCESS

R343

9V

R465

R341

D464 D466

D465

Q461

-B

Q462

Q460

H. DY

H. out FBT

+VB

Buscontrol(Frommicrocomputer)

AMP output circuit

S charactercapacitor

Diode mdulator circuit

L461

C464

88

3. DIODE MODULATOR CIRCUIT

Fig. 12-4 shows a basic circuit of the diode modulator usedin the N5SS.A key point in the N5SS chassis shown in Fig. 12-4 is todevelop a negative pulse at point B.In this circuit, a current loop of the resonant circuit forflyback period is shown by an arrow, and the energy storedin LDY is transferred to resonant capacitors Cr, Crm inpassing through Cr, Crm, Cs when the scanning completes.As a result, a positive, horizontal pulse as shown in Fig. 12-5 (a) will appear at Cr, and the current flows into Crm withthe direction as shown. Then a pulse as shown in Fig. 12-5 (b)develops at the point B.On the other hand, since constant amplitude pulses across Cr,as shown in Fig. 12-5, are applied to the primary winding, the

high voltage of FBT also develops a constant voltage.When the negative pulse developed at the point B is integratedwith Lm and Csm, its average value appears at Csm as anegative voltage.By modulating this voltage to have the parabolic curve withQ460, a waveform of Vm is obtained as shown in Fig. 12-6.As a result, the voltage Vs which is the sum of the powersupply voltage VB and the Vm is applied across the S-curvecapacitor Cs. The Vs becomes as a power source for thedeflection yoke, and the waveform modulated in the parabolicform, as shown in Fig. 12-2 (b), is applied to the horizontaldeflection yoke and corrects the left-right pin-cushiondistortion.

Fig. 12-4 Fig. 12-5

Fig. 12-6

A

B

HOUT

DD Cr

DM

LDY

FBT

VBCs Vs

Crm CsmQ460 Vm

Lma) Waveform at point A

b) Waveform at point B

VS

VB

0Vm

89

Fig. 12-7

4. ACTUAL CIRCUIT

In the actual circuit, the resonant capacitor is split into two asshown in Fig. 12-7. One, C440, is inserted between thecollector of the H. OUT transistor and ground and anotherC444 inserted between the collector and emitter. In Fig. 16-7, C440 is expressed as C1 and C444 as C2, and the resonantcurrent path for the flyback period is shown by arrows.In a conventional circuit, when brightness of a picture tubevaries, high voltage current varies and the high voltage alsovaries. As a result, horizontal amplitude also varies.However, in this circuit, the horizontal amplitude variationcan be suppressed to near zero if the high voltage currentvaries with variation of the high voltage.When the scanning period completes, the energy stored inthe deflection yoke LDY is transferred to the resonantcapacitor in a form of current Iy. In this case, the current issplit into two; Iy1 passing through C1, C3 and Iy2 passingthrough C2. In the same way, the energy stored in theprimary winding of the FBT is transferred to the resonantcapacitor in the form of Ip. In this case, the current (path) isalso split into two; Ip1 passing through C1 and Ip2 passingthrough C2, C3. Concequently, the current differencesbetween Iy1 and Ip2 (Iy1-Ip2) passes through C3.When the high voltage current IH reduces with a darkpicture, the current Ip in the primary circuit decreases, so Ip1and Ip2 also decrease. However, a current flowing into (Iy1-Ip2) increases as Ip2 decreases. As a result, the pulsedeveloping at the point B increases and the voltage Vm atCsm also increases as shown in Fig. 12-8. That is, when adark picture appears, the voltage across S-curve capacitor Csincreases as shown in Fig. 12-8, the high voltage rises, andthe horizontal amplitude is going to decrease. But, as Vsincreases, the deflection yoke current increases and thisworks to increase the horizontal amplitude. Accordingly, ifthe brightness of picture changes, the horizontal amplitude ismaintained at a constant value. This is one of the fine featuresthe circuit has.

Fig. 12-8

FBT

IH

VB

VmCsm

C3

VSCS

Lm

C2

IP2

IY1

IY1

C1

IY

IP2IP1

LDYH.OUT

IP

VS

VB

0Vm

90

4-1. Basic Operation and Current Path4-1-1. Later Half Scanning PeriodWhen the power is turned on, the power supply voltage VBis applied to Cs and Csm, and the Cs acts as a power sourcefor a later half of the scanning period for which the H. OUTtransistor is turned on, and the deflection current Iy flows inthe path as shown below

4-1-2. First Half Scanning PeriodWhen the base drive current decreases and the H. OUTtransistor is turned off, each energy stored in LDY, Lm, Lpof FTB is transferred to C1, C2 and C3, respectively, and theresonant current becomes zero at a center of the flybackperiod. Then, VA and VB pulses show a maximum amplitude.

Fig. 12-10

Fig. 12-9 Fig. 12-11

Fig. 12-12

H.OUT

VA

FBT

LDY

lP

Cs

VB

VB

DM

IM LM

IDC

CSM+

IY

+

Voltage & current waveform in H period.

IY

VA

0

0

0

0

IDC

IM

VB

VAFBT

LDY lP

Cs

VBVB

IM LM

IDC

CSM

IY

IY2IP2

C2C1IP1

IY

VA

0

0

0

0

IDCIM

VB

0C1C2

0C3

C1: IY1+IP1C2: IY2+IP2

C3: IP2-IY1-IM

91

4-1-3. Later Half of Flyback PeriodAll energy in the coil has been transferred to the resonantcapacitors at the center of the flyback period, and the voltageshows the maximum value. However, during next half of theflyback period, the energy of the resonat capacitor isdischarged as a reverse current through respective coil.When the discharge has been completed, VA and VB becomeszero, and the deflection current in reverse direction becomesthe maximum.

4-1-4. First Half of Scanning PeriodWhen the flyback period completes, the damper diode DDand the modulation diode DM turn on, and the Iy and Improportionally decrease from the maximum value to zero.The H. OUT transistor is turned on just preceding at thecenter of the scanning period, and repeats the steps 4-1-1through 4-1-4 stated above.

Fig. 12-13 Fig. 12-15

Fig. 12-14

Fig. 12-16

IP1IP2

C1 C2

VA

L.O.P.T

IY

IY2

LDY

IP

CS

VBVB

LM

IDC

C3IM

CSM

IY1

Iy

VA

0

0

0

0

IDCIM

VB

0C1C2

0C3

C1: IY1+IP1C2: IY2+IP2

C3: IP2-Iy1-IM.

DD

VA

FBT

IY

LDY

CS

VBVB

LM

IM

CSM

IMDM

Voltage & current waveform in H period.

IY

VA

0

0

0

0

IDC

IM

VB

92

SECTION XIIICLOSED CAPTION/EDS CIRCUIT

93

1. OUTLINE

CC / EDS circuit extracts data of CC (Closed Caption) andEDS (Extended Data Services) from input video signal,and decode them to generate display signal. Major feature ofCC/EDS circuit of TG1-C chassis is as follow.(1) Employing 1 chip decoder of stand alone type(2) Acceptable of field 2 data ( CAPTION 3, 4 TEXT 1,

2 EDS) as well as field 1 data ( CAPTION 1, 2 TEXT1, 2)

(3) Display of text mode extends from 8 rows to 15 rows.(4) Extended character display of 64 kinds standing for

Spanish and the like.(5) Representing Background attributes (8 colors +

transparent)

2. DATA TRANSMISSION FORMAT

CC/EDS data is transmitted being superimposed on line 21,field 1 (21H) and field 2 (284H). Waveform of line 21is shown in fig. 13-1. Line 21 signal is composed of data of7 cycle clock-run-in, start bit and 16 bit (8bits x 2 bytes).

Fig. 13-1 Line 21 waveform

10_50±0.5ms

10.076ms

12_910ms

4.15±0.1ms 33.764ms

0.12ms

20ms

PARITY

PARITY

b1 b3 b5 b7 b1 b3 b5 b7 b2 b4 b6 b2 b4 b6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

94

3. DISPLAY FORMAT

Character display area of caption mode and text modeconsists of 32 characters x 15 rows as shown in fig. 13-2.On front and back of each row, 1 character blank area isrespectively added. In caption mode, up to 8 rows among15 rows can be displayed at the same time. Characters in textmode are displayed in black box of 34 characters x15 rows. EDS display format is shown in fig. 13-3. The itemcan be displayed only when data of the item is transmitted.

Fig. 13-3 EDS display format

Fig. 13-2 Caption / Text display area

SCREEN

LINE 43

LINE 237

ROW1

ROW15

1 CHARACTER BLANK AREA 32 CHARACTERS 1 CHARACTER BLANK AREA

(Green)

(White, Slant, Unerline)

(Cyan)

Network Name

Program Name

Prog. Length

(Yellow)

Prog. Type

(Cyan)

Call Letters

Time In Show

(Green)

(Cyan)

Program Description (4rows)

(Character background: black)

95

4. CIRCUIT OPERATION

Block diagram of CC / EDS circuit is shown in figure 13-4,and block diagram of QM01 is shown in figure 13-5.Video signal which is input to pin 9 of UM01 is changed to1 Vp-p signal which is band-limited to 600kHz by theinput circuit, and it is supplied to pin 7 of QM01. InsideQA01, line 21 signal is extracted from input video signal,and is recovered on clock and data. Recovered data isdecoded by command processor and converted to displaysignal of R, G, B, Ys in Output Logic section. The displaysignal is output at pins 18, 2, 3 and 17 in the CMOS levelof positive polarity. The display output and OSD areswitched by QR01 in UM01, and the selected signal is senttoV/C/D IC. When the display of CC/EDS and OSD aresuperimposed, OSD is the first priority. H. sync signal withnegative CMOS level is input to pin 5 of QM01. This signalbecomes the standard signal of PLL circuit in IC.Loop filter for PLL circuit is connected to pin 9. QM01 iscontrolled by I2C bus connected to pins 14 and 15.

96

Fig. 13-4 CC /EDS circuit block diagram

UV

01 A

/V M

OD

ULE

V-A

V

EH

QA

01 u

CO

M

SC

L1

SD

A1

37 38

R G B

22 23 24

2 3

6 5

SC

L1

SD

A1

SC

L2

SD

A2

15 14

SC

K

SD

A

Vid

eoin

AT

TLP

F7

VID

EO

QM

01 C

C/E

DS

DE

CO

DE

R

5 13 17 18 2 3

BO

X R G B

HIN

VIN

INV

ER

TE

R

QR

01 R

GB

SW

ITC

H

2 5 3 14

1A 2A 3A 4A

1 3 6 10 13

A/B

1B 2B 3B 4B

4 7 0 12

1Y 2Y 3Y 4YO

SD

-YS

OS

D-R

OS

D-G

OS

D-B

36 37 38 39

OS

D Y

S

OS

D R

OS

D G

OS

D B

30 31

HD

OU

T

VP

OU

T

Q50

1 V

/C/D

UM

01 E

DS

/CC

/RG

B S

W.

HD

VD

Ys

OU

T

R O

UT

G O

UT

B O

UT

9

13 14 18 19 20 21

251611 12

SC

K

SD

A

Q89

- I2

C B

UF

FE

R

97

Fig. 13-5 Q

M01 block diagram

V

COMP Video 7

8

CSYNC

Sllce Level

Clamp

Data Sllcer

+5V

12

VDD

Sllced DataData Recovery

DLCK

Data CLKRecovery

Data MOD&

XFR BUF

SYNC Sllcer

COMP SYNC Timing Logic Command Processor

and

Decoder Control

DisplayRAM

CHARROM

Vertical CTRAnd Control

HorizontalCounter Output

Logic

R

G

B

Box

18

2

3

17

SM

S

SE

N

SC

K

SD

A

SD

O

6 4 15 14 16

DOT CLK

Vss AVSS

1 11

Phase/FreqDET

PFD LoopFIL

LoopFilter

VCO

HIN 5 9LPF

13

VIN

98

SECTION XIVPOWER CIRCUIT

99

1. OUTLINE

Block diagram of power circuit is shown in fig. 14-1. Powercircuit consists of stand-by power supply (powertransformer) which supplies power to microcomputer, andmain power supply which supplies power to H. OUT,AUDIO OUT and signal process circuits. Power for V. OUT,VIDEO OUT and the like is supplied from flybacktransformer of H. deflection circuit. Power (+12V fromconverter transformer) for signal process circuit are suppliedfrom 9V-2, 9V-1, 5V-2 and 5V-3 lines by 3 terminal regulatorand 4 terminal regulator with switch which are equippedin latter stage. The characteristics of this system are thatmain supply newly employs current resonant type which issmaller and more highly effective than conventional type ofRCC switching type, and employs protector module (Z801)which includes protection circuit and error amp. for secondaryoutput detection in one package.

Fig. 14-1 Power block diagram

L901 R808

F801 T801T840

POWERTRANS

TPW1459AZ

+12V

D840

Q840 +5V-1 MICOM PERIPHERALS

SR81F860

D801 R861

Q801 VOLTAGE REGU.OVER VOLTAGE

PROTECT

Q843SW

QB30SWQA01 (25)

PHOTO COUPLER

TLP621 (GRL)

R883

T862CON-VERTERTRANS.

TPW3335A8

+26V

AUDIO OUTAND H.VCC

+12V

Q420 9V-1 (TUNER, IMA, E/W, VCD)

Q832 9V-2 (COMB, DSP)

Q830 5V-2 (TUNER, COMB, VCD)

Q831 (POP, RGBSW)

R101

+32V (H001HY01. HF01)

R479

R470

R4721 2

3 16

16

14

Z801PROTECTOR

HIC1013C471

R472

D471HEATER

VELOCITYMOD.

F470 +B(+125V)

+200V

+27V+27V

R370Q370

OVER VOLTAGEPROTECTOR

(Q462) -27V

T461

4132AD BE

100

2. RECTIFYING CIRCUIT AND STANDBYPOWER SUPPLY

Rectifying circuit is a circuit to generate dc from ac 120V.D899 is a varistor to absorb surge (ex. lightning) aroseon ac line. When surge arises, the circuit let surge by-pass viaroute shown in figure 13-2 to protect the followingcircuit. C801 and T801 are a filter circuit to suppressabnormal radiation. Degaussing circuit using thermistor isequipped at after SR81 relay. R811 is a damping resistor toremove light regulator noise. D801 is a bridge rectifier

diode and performs rectification and smoothing togetherwith C810. R801 is a resistor to regulate inrush currentand to suppress rush current in switch-on. T840 is standbypower transformer. D840 and C840 performs rectifyingand smoothing to make approx. 12V for relay driving, andQ840 regulator makes +5V to supply to microcomputerand also to output the reset signal of microcomputer.

3. MAIN SUPPLY CIRCUIT

This circuit is a current resonant switching power circuitusing hybrid IC Q801 (STR-Z3201). The current resonantpower supply realizes small, highly effective and low noisepower. Output of main supply are for H. deflection circuit(+125V), for audio output circuit( +25V) and for signalprocessing circuit (Low B, +12V). The supply (Low B,+12V)for signal processing circuit is equipped with 3 terminalregulator and 4 terminal regulator with switch in the followingstage, to supply 9V-1, 9V-2, 5V-2 and 5V-3 to signalprocessing circuit.Audio output supply and signal processing circuit supplylines are equipped with protecting fuses F899 (for audiooutput line), F890 (for signal processing circuit line) whichbreaks in circuit failure like short of load. And F860breaks to protect the circuit in the failure of primary circuit(break of Q801).

Fig. 14-2 Rectifying circuit and standby power supply

F801 D899 C801

T801

D801

R810

C810

+3V-1QB30Q863

SR81Q840

+5V (to MICOM)

ResetC840

T840 D340 C843

C842

1

2

5

43

Surge

L901

R811

Rectified output

MICOMPOWER

THERMISTOR

101

4. OUTLINE OF CURRENT RESONANTTYPE SUPPLY

Basic configuration of current resonant type power supplyused in CN32E90 is shown on figure 14-3. Basic operationis as follow. Primary winding of converter trans and resonantcapacitor are connected in series to consist of LC seriesresonant circuit. And this is drived by push-pull of two powerMOS FET’s. Converter transformer operates in forwardmode. Just when primary switching device turns ON,converter trans produces the secondary output.Automatic voltage control operation is done in such way that+B voltage is detected by error amp. to be fed back tothe primary OSC circuit via photo coupler, then controlsfrequency.

Fig. 14-4. LC series resonating circuit Fig. 14-5. Characteristic

5. FUNDAMENTAL THEORY

Voltage generating on L of LC series resonant circuit hascharacteristic which varies with frequency peaking at resonantpoint f= 1/ (2p LC ) [Hz] as shown in figure 14-4. Thecircuit utilizes this characteristic to control outputvoltage. Actual operation is done at higher frequency thanresonant point. By this operation, variable range of voltageacross L ranges from maximum voltage of resonant point topower line voltage.

Fig. 14-3. Basic diagram

OSC

DRIVE

PHOTOCOUPLER

+B

ERRORAMP

VL

e

VL (v)

e

Resonant pointFrequency

1f= 2p LC

102

6. ACTUAL CIRCUIT

Two MOS FET’s, driver which drives FET’s and frequency control IC are combined inside HIC (Q801 ).Converter transformer T862 is designed to have loose coupling between the primary and the secondary, and to havesome extent of leakage inductance. This is the reason why L and C (leakage inductance and resonant capacitor) areresonated during period that rectifying circuit (diode) connected to the secondary winding conducts. Rectifyingcircuit of the secondary winding uses double wave rectifier considering current balance of switching device, becauseconverter transformer is driven in push-pull. The function of STR-Z3201 is explained below. Fig. 14-6 showsblock diagram and figure 14-7 shows waveforms at main terminals.

<<FUNCTION OF HIC>>(1) Output switching element

Uses two power MOS FET’s, and operates in push-pull. Voltage across the switching element does not increase more thanpower line voltage basically, and therefore, element of low rating voltage (enduring 200V) is used.

(2) Driving circuitDrives output switching element. MOS FET is specially used for driving element of high side, and to drive this, bootstrapcircuit is equipped.

(3) Dead timeTo avoid that two switching element turns ON at the same time in push-pull operation, dead time is arranged.

(4) CT terminal (Pin 5) About basic oscillationVariable frequency oscillator is equipped inside frequency control IC, charge and discharge of the capacitor C862connected to this terminal decide oscillation frequency and dead time. This oscillator generates triangle wave signal withlow level of 2.5V(TYP) and with high level of 4V(TYP). Charging time of oscillator becomes output-on period, anddischarging time becomes dead time.

(5) RT terminal (Pin 5) About lowest oscillation frequencyLowest oscillation frequency is decided by capacitor C862 connected to pin 4 and resistor R867 connected to this terminal.

(6) CONT terminal (Pin 6) About frequency controlCurrent flowing out of this terminal varies charging current of oscillating capacitor C862. Therefore, flowing of CONTterminal current corresponding to feedback quantity from photo coupler (Q862) varies charging time of C862 and controlsoscillation frequency. Maximum oscillation frequency is decided by R864 connected to CONT terminal.

(7) Css terminal (Pin 8) About soft startCapacitor (C866) and resistor (R863) for soft start are connected to make TV start at high frequency in the time of poweron and gradually make frequency lower. This function suppresses rush current in POWER MOS FET output and providesstable starting of TV.

(8) CD terminal (Pin 9)Latch circuit detects abnormal operation to hold the status of operation seizing, and if following condition as a result ofdetecting abnormal operation comes, the latch circuit begins to start.*In operation of over voltage protection (OVP) circuit*In operation of thermal shock detection (TSD) circuit*In operation of over current protection (OCP) circuit*In going down and no recovery of Main +B output voltageUntil latch function begins to operate, the charging time of capacitor C869 connected to CD terminal (Pin 9) is utilizedto produce delay time. To release the latch function after operating once, turn off power and turn on again.

(9) OC terminal (Pin 12) About over current protection (OCP) functionThis is to detect current in LC series resonant circuit, and to suppress over current to stop operation.

(10) Over voltage protection (OVP) circuitThis is to make latch circuit operate when voltage at Vcc terminal (Pin 10) exceeds 22V (TYP).

(11) Thermal shock detection (TSD) circuitThis is to make latch circuit operate when temperature inside IC exceeds 150°C.

103

<< BLOCK DIAGRAM AND PIN FUNCTION >>

Table 14-1. STR-Z3201 pin function

Pin No. Symbol Function

1 VIN Half bridge power input

2 G(H) High side MOS FET gate

3 HO High side gate drive output

4 GND Control section ground

5 CT Capacitor connection terminal for oscillation

6 CONT Oscillator control terminal

7 RT Resistor connecting terminal for oscillation

8 Css Capacitor connecting terminal for soft start

9 CD Capacitor connecting terminal for delay latch, ON-OFF terminal

10 Vcc Control section power terminal

11 LO Low side gate drive output

12 OC Over current detecting terminal

13 G(L) Low side MOS FET gate

14 COM Half bridge ground

15 OUT Half bridge output

16 VB High side gate drive power input

Fig. 14-6. STR-Z3201 block diagram

10 16 3 2

1

15

14

131147568

12

9CD

OC

Vcc VB HO G(H)

VIN

OUT

COM

Css CONT CT RT GND LO G(L)

TSD OVP START

LogicR1

R2

DELAY LATCH REF

OCOSC

CONTROL OSC

R4 R3

104

Fig. 14-7 Waveform at each pin

DATE TIME

=4V

=2.5VCT PIN VOLTAGE

OSC OUT SIGNAL

(PIN11)LOW SIDEGATE VOLTAGE

(PIN2)HIGH SIDEGATE VOLTAGE

ON OFF

OFF ON

(PIN 15)PUSH-PULLOUT VOLTAGE

(PIN 15)PUSH-PULLOUT CURRENT

OA

OV

=VIN PIN VOLTAGE(PIN 1)

105

7. OTHER POWER CIRCUIT

Power supply circuits excepting main and standby supplycircuits are explained here. Power supplied from T461(Flyback transformer) of H. deflection circuit is shown infigure 13-8. Flyback transformer supplies 200V for videooutput from pin 3, 27V for V. out circuit from pin 6, and -27Vfor side DPC circuit from 5 pin respectively.Resistors (R327, R462) inserted in each line are protectingresistor which fuses in abnormal situation like load short.

Fig. 14-8. Other power circuit

10

9

5

4

7

6

3

2

1 8

-27V

+27V

200V

R642

C461

AFCBLANKING

FBTANODE

HEATER

FOCUS

SCREEN

ABL

D460

+B

C448

Q404Collector

D406

C310 D302

R327

C3\7

106

line, Tr8 turns on to supply base current into Tr6 throughZD4. In case of X-RAY protection circuit, when high voltageincreases abnormally, Tr10 and Tr9 turns on to supply basecurrent into Tr6 through D3, then this causes Tr6 and Tr5turn on to make power signal from microcomputer in lowlevel. Besides, by the positive feedback that turning on ofTr6 causes Tr7 turn on to make base current flow to Tr6, aslong as 5V is supplied to pin15, Tr5, Tr6 and Tr7 continuesto be on to keep safety. Therefore the operation is notreleased by remote control, but continues until AC cord ispulled and inserted. When this module operates, red blinkingof power LED shows the operation of protection circuit.

8. PROTECTOR MODULE (Z801)

CN32E90 employs protector module which combines in onepackage protection circuits for X-RAY protection and overcurrent protection, and error amplifier for +B voltagedetection. This is for the purpose of small size andstandardization of protection circuit, and what were discretecircuits in conventional chassis are arranged into module.Equivalent circuit is shown in figure 14-9. A section is erroramplifier for +B voltage detection, B section is over currentprotection circuit and C section is X-RAY protection circuit.D section forces power signal from microcomputer to set inlow level by the signal from protection circuits, and to turnOFF the power relay and keep it. Actually in case of overcurrent protection circuit, when over current flows in +B

Fig. 14-9 Protector module equivalent circuit

Q862

R890

POWER

C470

+BR470

R472 R479

C474

X-RAY

+25V over voltage protection+27V over currentprotection

+25V

5 3 16 15 6 2 1 14 12 13 11

7 17

A

B

CTr1

R2

R3

ZD1

D

R9

R10 Tr7

Tr6

Tr5 R11

R14

ZD4

R12

C1

R15

R16 D1

Tr8

R19

Tr9 Tr10

R20

D3

R21 R22

R26

R25 R23

5V-1

Pins 4, 8, 9,10: No connection

Pin14: Gate terminal Protection circuit begins to operate with 1.5V or more of this termianl voltage.

107

TROUBLESHOOTING CHART OF POWER CIRCUIT

No raster

Fuse F801 breaks

Fuse F860 breaks

Check/Repair AC circuit

Is the following point short?

#1-#14, #1-#15,#14-#15 of Q801

Replace F801

ReplaceQ801, F860

Replace F860

Check relay SR81

Instantly turns ON andthen turns OFF immediately

Voltage across C810Check/RepairD801, R810C810

Check/RepairT840, D840

Check voltage acrossC840

Does pin 15 of Q801operate in switching? Voltage across C868 Check/Repair

C868, D864,R871, D876,R861

Check/ReplaceQ801, C870, T862Check/Repair

T840 or 5V-1using circuit

Voltage at pins 4and 5 5V?

Instantly switchingand then stopsimmediately

Check/Repair Q801, C862, Q862Z801, D883, D884, R864

Check QA01(pin 7), QB30

Is base voltage ofQ843 high level? (4.3V)

Power LEDblinks in red.

Check/Repair Q843, SR81

Voltage across C889

Voltage across C897

Check/Repair F899, D885,D886, audio power line

Check/Repair F890, D891, D892

Voltage across C884jumps instantly to

140V or more

Check/Repair Q801, D883,D884, Z801, R883, R884,Q862, R864

Is voltage at pin 22 (H-Vcc)of Q501 9V?

Z801 makes over current protection circuit,X-RAY protection circuit and +27V overvoltage protection circuit operate

Check deflection circuit

Check peripherals of startcircuit Q430 and audio Vcc

Check R920 andCRT Drive board

Does heater light?

Check peripherals ofQ501 and video out circuit

YES

YES YES

YES

YES

NG

NGNG

NG

NG

YES

NG

NG

OK

OK

OK

OK

OK

OK

No

NoNo

No

No

OK

No

917 23

10

18 24

25

1119

26

112

2027 31

213

28

314

30

3221

224 15

33

5

1634

6

35

7

36

NG

37

38

108

(No RASTER)

No RASTER

Check/ReplaceF470, Q404 Check F470 Is the status of power

LED?

Is voltage at pin 22 (H-Vcc)of Q501 9V?

Check peripherals ofstart circuit Q430and audio Vcc

Check R920CRT Drive board

Does heater light?

Check peripherals ofQ501 and video outcircuit

Short R370 and turnpower on again

(See note below.)

Check peripherals of V.outcircuit Q301 and +27V line

Open R472 and turnpower on again

(See note below.)

Short R470 and turnpower on again

(See note below.)

Check protector moduleZ801 and power circuit

Check H. out circuit;C440, C444 and X-RAYprotection circuit(including Z801)

Check main B line andH. out circuit (Q404, 4T461)

Note: Do not take time, check within short time.

NG

NG

NG

OK

OK

OK

Red lights

LEDRed blinks

LEDRed blinks

F470 blinks

Red blinks

Red blinks

Red blinks

14

8

10

5

2

3 6

7

13

15

17

19

21

22

23

109

SECTION XVDSP CIRCUIT

110

Fig. 15-1 Conceptual Dolby Stereo/Dolby Surround encoder

into left, center equally into left and right, and right intoright-playing a Dolby Stereo soundtrack over two speakersreproduces the entire encoded soundtrack. There is but oneexception: the surround signal, though audible, is notreproduced in its proper spatial perspective. When the firsthome decoder was developed in 1982, its goal was to restorethis lone missing dimension.Before we discuss decoders, it is necessary to see how the MPMatrix encoder works. Referring to the conceptual diagramin Fig. 15-1, the encoder accepts four separate input signals;left, center, right, and surround (L, C, R, S), and creates twofinal outputs, left-total and right-total (Lt and Rt).

The L and R inputs go straight to the Lt and Rt outputs withoutmodification, and the C input is divided equally to Lt and Rtwith a 3 dB level reduction (to maintain constant acousticpower). The S input is also divided equally between Lt and Rt,but it first undergoes three additional processing steps:a. Frequency bandlimiting from 100 Hz to 7 kHz.b. Encoding with a modified from of Dolby B-type noise

reduction.c. Plus and minus 90-degree phase shifting is applied to

create a 180-degree phase differential between thecomponents feeding Lt and Rt.

It is clear there is no loss of separation between the left and rightsignals; they remain completely independent. Not so obviousis that there is also no theoretical loss of separation between thecenter and surround signals. Since the surround signal isrecovered by taking the difference between Lt and Rt, theidentical center channel components in Lt and Rt will exactlycancel each other in the surround output. Likewise, since thecenter channel is derived from the sum of Lt and Rt, the equaland opposite surround channel components will cancel eachother in the center output.The ability for this cancellation technique to maintain highseparation between center and surround signals requires theamplitude and phase characteristics of the two transmissionchannels to be as close as possible. For instance, if the center

1. ORIGINS OF DOLBY SURROUND

Dolby Stereo movies and Dolby Surround video and televisionprograms include an additional sonic dimension overconventional stereo productions. They are made using a DolbyMP (Motion Picture) Matrix encoder, which combines fourchannels of audio into a standard two-channel format, suitablefor recording or transmitting the same as regular stereo programs.To recapture the dimensional properties brought by theadditional channels, a Dolby Surround decoder is used. Inthe theatre, a professional decoder is part of the Dolby Stereocinema processor used to play 35 mm stereo optical prints.The decoder recovers the left, center, and right signals forplayback over three front speakers, and extracts the surroundsignal for distribution over an array of speakers wrappedaround the sides and back of the theater. (These samespeakers may also be driven from four of the six discretetracks on 70 mm Dolby Stereo magnetic prints, but in thiscase no decoder is needed.)Home viewing of movies on video has become extremelypopular, and with the advent of stereo VCR's, stereo televisionand digital video discs, the audio side of the video presentationhas improved considerably, inviting the use of full-rangesound reproduction. The ability to deliver high quality audioin these formats made it easy to bring MP Matrix-encodedsoundtracks into the home as well, thus establishing thefoundation for Dolby Surround.

2. THE DOLBY MP MATRIX

One of the original goals of the MP Matrix was to enableDolby Stereo soundtracks to be successfully played in theatersequiped for mono or two-channel stereo sound. This allowsmovies to be distributed in a single optical format, andfurtheremore results in complete compativility with homevideo media without requiring separate soundtrack mixes.Since the three front channels of the MP Matrix are assembledin virtually the same way as a conventional stereo mix --- left

Left

Center

Right

++

++

-3dB Surround -3dB B.P.F DOLBY NRENCORDER

++

++

+90 DEG

-90 DEG

Lt

Rt

111

channel components in Lt are not identical to the ones in Rtas a result of a channel balance error, center information willcome out of the surround channel in the form of unwantedcrosstalk.

3. THE DOLBY SURROUND DECODER

This leads us to the original Dolby Surround decoder. Theblock diagram in Fig.1 5-2 shows how the decoder works.Except for level and channel balance corrections, the Ltinput signal passes unmodified and becomes the left output.The Rt input signal likewise becomes the right output. Lt andRt also carry the center signal, so it will be heard as a"phantom" image between the left and right speakers, andsounds mixed anywhere across the stereo soundstage will bepresented in their proper perspective. The center speaker isthus shown as optional since it is not needed to reproduce thecenter signal.

The L-R stage in the decoder will detect the surround signalby taking the difference of Lt and Rt, then passing it througha 7 kHz low-pass filter, a delay line, and complementaryDolby noise reduction. The surround signal will also bereproduced by the left and right speakers, but it will be heardout-of-phase which will diffuse the image.Since the heart of the decoding process is a simple L-Rdifference amplifier, it is referred to generically as a "passive"decoder. This is to distinguish it from decoders using activeprocesses to enhance separation which are known as "active"decoders.

Fig. 15-2 Passive surround decoder block diagram

4. DSP CIRCUIT

A surround component (L-R) is extracted from L, R audiosignals coming through the AV SW in the matrix circuit asshown in Fig. 15-3. The surround component enters the DSPcircuit through the LPF.The signal is A/D converted, delayed by an arbitrary time of0~100 msec (every 3.2 msec) by digital process and then D/A converted and outputs from the DSP IC. The DSP ICdevelops two outputs; (LO) for FRONT (LO) and (RO) forREAR and each output is controlled by the microcomputerfor each surround mode. The output signal (LO) for FRONTis added and subtracted with the input signal in a matrixcircuit and output from the front speaker in passing throughthe audio processor and main amplifiers.At the same time, the output signal (RO) for REAR is fe?? tothe Dolby NR circuit, but switched to "Dolby surround"mode, and then output from the rear speaker in passingthrough audio processors and rear main amplifiers.In this case, the DSP stands for not only a simple digitalsurround processor but also a digital surround field processor.That is, it works to give a simple surround effect but to giveeffect as if the listener can feel reality suitable for theprograms. For example, it aims to give the listeners a realitymatching to each program they are enjoying in their homelistening room so that they can obtain reality of big concerthall or feel as if they are watching a move at a reserved seatin a movie theater.

INPUTS OUTPUTS

Lt

Rt

INPUTBALANCECONTROL

LEVELCONTROL

MASTERLEVEL

CONTROL

ANTI-ALIAS

FILTER

MODIFIEDB-TYPE NRDECODER

AUDIODELAY

7 kHzLOW PASS

FILTER

Optical passive center siganal

DELAY SET

L+R

L+R

L L

R R

C

C

S

S

Left

Right

Center

Surround

112

Fig. 15-3 Block diagram of DSP circuit

Fro

mA

/V S

W

INL R

QD

08In

put B

alan

ceQ

D01

Inpu

t Buf

fer

12

1

4

10

8

R

L

6

5

7

3

(L-R

)

1

3

1LP

FLP

F

QD

01Q

D01

QD

02

QD

03 D

SP

IC Y

M71

28 B

A/D

VC

TO

DIG

ITA

L D

ELA

Y

4 CO

NT

BU

SC

ON

VE

RT

QD

04

Fro

m M

icro

com

pute

r

VL VR

D/A

D/A

LO

RO

Buf

fer

Buf

fer

D

Q06

7 QD

05

QD

05LO

8 QD

061 6

12

QD

07

DQ

02

L-R

Dol

by N

RQ

640

Rea

r A

mp +

SL R

Spe

aker

QD

02D

SP

Fro

nt A

dditi

on C

ircui

tQ

670

Fro

nt a

mp

L R

57 8

109

L R L+R

L+S

R-S

L R

Spe

aker

Syc

rone

(Sup

er w

oofe

r)

Aud

ioP

roce

ssor

(H00

2)

LPF

LPF

MA

TR

IX(L

-R C

IRC

UIT

)

31

57

37

3

914

113

As shown in Fig.1 5-4, a sound emitted in a sound field canbe classified as a direct sound which directly reaches ears ofa listener, and reflected sound which comes after collisionwith a wall as shown by dotted line or comes after severaltimes of collision as shown by double dotted lines. Thelisteners are determining that they are listing in what type oflocation by perceiving time difference and volume level

difference between the direct sound and the reflected sound.For more detail, this situation can be expressed with thedirect sound, initial reflection sound coming after one timeof reflection, and trains of reverberation sound in later periodas shown in Fig. 15-5.The DSP circuit develops these initial reflection sound andthe reverberation sound artificially and add them to theoriginal sounds, thereby creating rhe effect that allows thelisteners in the home listening room to feel as if they arelistening in an original location.The DSP IC YM7128B has eight separate output taps andtheir delay time and the output levels can be specifiedseparately, so, various sound fields can be selected byvarying the initial reflection sound. Moreover, the IC has aninternal feedback loop which controls the delay time and theoutput level in considering the later time reverberationsound.

Fig. 5-4 Fig. 5-5

Direct Sound

Initial ReflectionSound

ReverberationSound

Sound Level

Direct Sound

Initial Reflection Sound

Reverberation Sound

Time

114

5. DSP (Digital Surround Processor) IC

Input signal entered into analog input pin 4 of DSP IC QD03(YM7128B) is converted to 14 bit digital signal with thesampling frequency 23.6 kHz by A/D converter of 14 bitfloating system, and enters digital delay circuit throughdigital attenuator VM and doubler.The digital delay circuit has nine output taps, and the delaytime of each tap can be controlled independently, also eachtap position can be switched by T0 to T8 register.In a minute, the T0 output passes through the primary FIR(Finite Impulse Response) type low pass filter, and reduction

processing is performed by VC, then it feed-backed to thedelay input after it is added to the doubler described above.The output of eight taps T1 to T8 is added after performingreduction processing by GL1~GL8, GR1~GR8, and reductionprocessing is performed by the digital attenuator VL or VR,and an analog output is created by D/A converter afterpassing through digital filter, comes out from pin 7 or 8.The digital attenuated value, delay time and the coefficientof FIR type low pass filter are set by writing the data on theregister.This process is performed by loading three data from submicrocomputer to microcomputer interface.This unit has four modes as surround mode. The settingvalues are described in Table 15-1.

Table 15-1 DSP control factor

Mode OFF DOLBY THEATER STADIUM NIGHT CLUB CONCERT UNITControl SURROUND HALL HALL

-VM (IN) - ¥ P-0 P0 P0 P0 P0 dB

VL (LO) -¥ P0~ -¥ P0~ -¥ P0~ --¥ P0~ --¥

VR (RO) P0 P0 P0 P0 P0

VC (Echo) -¥ -¥ M-6 M-10 M-8

GL1 P-4 M-2 M-2 P-2

2 M-6 -¥ P-4 P-10

3 P-12 P-6 P-16

4 P-12 M-10 -¥

5 -¥ -¥

6

7

8

GR1 P0

2 -¥ P0

3 P-18

4 -¥

5 P-2 P-6 P-4

6 M-2 M-6 P-8

7 P-8 M-10 P-8

8 P-10 P-12 P-14

T0 (Delay) 0 0 0 100.0 19.4 51.6 msec

1 19.4 12.9 93.6 12.9 71.0

2 0 38.7 100.0 19.4 83.9

3 71.0 100.0 22.6 100.0

4 87.1 0 29.0 0

5 29.0 6.5 64.5

6 45.2 9.7 80.7

7 83.9 25.3 90.4

8 100.0 35.5 100.0

C0 (Filter) 0 0.71875 0.59375 0.875 —

1 0.28125 0.40625 0.125 —

115

Fig. 15-6

QD03

CD22

FromInput LPF

CD15

RD26

CD23

CV

AIN

CH

/TI

VDD

DIN AO SCI

From Bus convert (ICD04)

REFERENCEVOLTAGE

GENERATION

DIGITAL DELAYVM

VC

C1

C2

D5

4

3

6

15 14 13 10 9

8

7

2

1

11 12 16

XD01

CD27 RD32 CD29

D01

CD28

RD33

XO XI /IC Vss

AVDD

LD01

LO

DC26

DC25

RO

VSS AVSS

VL

VR

2fs

2fs

To LPF Output(For FRONT ch)

To LPF Output(For REAR ch)

TIMING GENERATION

GL1

GL2

GL3

GL4

GL5

GL6

GL7

GL8

GL1

GL2

GL3

GL4

GL5

GL6

GL7

GL8

+B (5V)

A/DCONVERTER

D/ACONVERTER

D/ACONVERTERMICROCOMPUTER

INTERFACE

CD21 CD20

T8 T7 T6 T5 T4T3 T2T1

T0

116

6. SURROUND CIRCUIT

The surround circuit used in this model has the modes shownin Table 15-2 of the modes, description will be given for 5mode. The description will be made according to itemsshown below.

7. INPUT BALANCE CIRCUIT

Fig. 15-8 shows the input balance circuit.The input balance circuit is to adjust gain of Lch and Rch sothat (L-R) component in the matrix circuit becomes zero.Adjustment by the input balance volume control on theremote hand unit.

Surround Mode Assumed sound fieldFront Rear

CONCERT HALL Concert hall O O

THEATER Movie theater O O

NIGHT CLUB Disco, Night club O O

STADIUM Baseball stadium O O

Dolby Surround Dolby surround soft X O

OFF Off X X

Fig. 15-7

Fig. 15-8

Table 15-2

[dB] 0

-8

M i n C e n t e r C o n t r o l

Lch R c h

Response

A/V SW

L OUT

R OUT

CD041m50V

RD2315K

CD05

22m4V

RD2456K

CD061m50V

Input balance control

+

QD08

+9V

L

R

LehInput buffer

RehInput buffer

CD0922m16V

21

3

5

7

9

11

1314

12

10

4

6

8

117

8. MATRIX CIRCUITFig.15-9 shows the matrix circuit.The matrix circuit is to create a surround signal of (L-R) fromthe Lch and Rch signals. According, if a monaural signalenters, L-R=0, showing no surround effect exists.

9. FILTER CIRCUIT (ANTI-ALIASFILTER)

Fig. 15-10 shows the filter circuit.The filter circuit is to cut frequencies higher than 7 kHz inconsidering processing capacity of the DSP circuit (delay)connected to next stage, and two stages of the filters areemployed in this unit.

Fig. 15-9

Fig. 15-10

Lch IN

REF

Rch IN

Lch OUT

Surround OUT(L-R)

Rch OUT

CD021m50V (NP)

CD031m50V (NP)

CD0239K

CD0339K

CD1539K

RD1339K

QD01Buffer

12

1314

98

10

5

6

7

RD1439K

CD1633K

QD01Buffer

QD01

RD1710K

RD1810K

RD1910K RD20

10KRD2110K

RD2210K

QD01QD023

23

2

CD11M2700P

CD12M6800P

CD10390P

CD13M2700P

CD14M6800P

CD16390P

118

10. DSP CIRCUIT (DELAY)Fig.1 5-11 shows the DSP circuit.The DSP circuit delays the surround signal entered by a timeof digital delay determined for each mode and then outputsthe signal. The DSP circuit is controlled with 3 line-bus datafrom the sub-microcomputer. The DSP circuit develops twotype of outputs; one for front addition and the other for rearoutput. Details of the outputs are shown in Table 15-2.

Fig. 15-11

Bus data

Surround IN(L-R)

LPF

LPF

Rear OUT

Front OUT

DSPQD

YM7128B

DIN AD SCI XI XO

Ycc CH IN CY Lo Ro

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

119

11. 7 kHz LOW PASS FILTERThe DSP outputs are received at inputs of high impedancevoltage followers and then fed to 7 kHz LPFs. Since L andR components of the DSP output are processed in timesharing by the D/A converter, the LO and RO outputs mustbe received at the high impedance input circuits. The LPFswhich receives the signals consist of OP amplifiers.

Fig. 15-12

QD03

Front(Addition circuit)

Rear(Dolby NR circuit)

DSPLO

DSPRO

7

8

CD321m50V

CD341m50V

CD2633P

RD311M

REF

RD341M

CD2533P

3

2

3

2

5

6

5

6

1

17

7

QD05

QD06

QD05

QD06

RD3010K

RD2910K

RD2810K

CD31M3300P

CD30820P

RD4710K

RD4610K

RD4510K

CD17M6800P

CD39M5600P

CD19M2700P

CD18390P

120

12. DOLBY NR CIRCUITFig. 15-13 shows the Dolby NR circuit.The Dolby NR circuit used in this unit is a modified B typefor Dolby surround and the operation characteristics areshown in Fig. 15-14.

Fig. 15-14

Fig. 15-13

CD3510m16V

CD381m50V

CD464.7m16V

(NP)

Rear OUT

DolbyN.R

Rear IN

QD07TA7629P

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

RD485.6K

RD492.2K

RD2547K

RD2733K

REF

12

13

14

RD65150

CD45M5600P

QD02

RD6147K

CD43M4700P

CD44M0.027

RD6047K RD66

18K

ENCODE

DECODE (Dolby NR)

[dB]

[dB]

Response

Response

f [Hz]

f [Hz]

121

13. DSP FRONT ADDITION CIRCUITFig. 15-15 shows the front addition circuit for the surroundsignal. In the DSP operation of this model, the surroundsignal is added to the front channel to provide the surroundeffect if rear speakers are not used.In practice, the front addition surround signal output fromthe DSP circuit is added to Lch with the phase non-invertedand to Rch with the phase inverted.

Fig. 15-15

OUT

OUT

RD0120K

RD0516K

Lch IN

Surround(L-R)

Rch IN

RD0916K

RD1015K

RD0715K

RD0415K

RD0627K

RD0824K

Lch

Rch

QD02

QD02

Lch OUT

REF

Rch OUT

5

6

7

9

10

8

122

14. BUS CONVERTERThe bus converter receives I2C-bus data sent from the mainmicrocomputer and converts them into DSP control data.The data are transferred to the data input of the DSP.

15. NEUTRAL BIASTo develop a neutral bias voltage for the OP amplifier, +B(12V) is divided with resistors.

Fig. 15-16

Fig. 15-17

4 3 2 1

5 6 7 8

To DSP (QD03)

RD421K

RD431K

RD441K

+5V

ICD0316 pin

RD39100

RD38100

From main microcomputer

QD04

DIN

AD

SC

I

GN

D

Vcc

RE

SE

T

SC

L

SD

A

RD121K

RD111K

+B

REF

CD01100m16V

123

16. AUDIO OUTPUT AMPLIFIER (For Rear SP)

The audio amplifier develops 5.0W two circuit.

Fig. 15-18

3

1

2

4 7

6

5

Rear INPUT

Mute

Ripple Filter Vcc

Pre GND PW-GND

Vcc

SURROUNDSPEAKERTERMINAL

Q640 TA8213K

C6550.12m

R6852.2W

C652470m35V

R6601.5W(5W)

C6501000m35V

C646100m25V

R640 6.8K

C6471000P

C6412.2m50V

R6411.8K

R64722K

R644100K

C6492.2m50V

Q6412SC2878A

C64547m25V

124

17. TROUBLESHOOTING CHART

NG

NG

NG

NG

OK

OK

OK

OK

No sound.

Is power supplied +5V, +12V lines?

Are input signals applied to 13 , 14 terminals?

Are inputs applied to pins 14 , 8 of QD01?

Do output pins L 10 , R 11 develop outputs?

Check Sound volume control circuit (H002) and Frontpower amplifier circuit (Q670).

Check Power supply circuit.

Check A/V SW output.

Check Input Buffer (QD01).

Check DSP front addition circuit (QD02).

NG

NG

NG

NG

OK

OK

OK

OK

No rear sound.

Is rear sound component contained in the input signal?

Is input applied to pin 4 of QD03?

Do pin 7 and 8 of QD03 develop outputs?

Does Sout 6 develop the output?

Check Sound volume control circuit (H002) and Rearpower amplifier circuit (Q640).

Rear sound is not developed as Adaptive matrix circuit is actuated.Use an effective source.

Check L-R matrix circuit (QD01) and Anti-alias Filter (QD01 & 02).

Check DSP (QD03) and DSP control data.

Check LPF (QD06) and Dolby NR circuit (QD07 & 02).

125

SECTION XVIFAILURE DIAGNOSIS PROCEDURES

126

1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES

No raster.

Check main powervoltage. (125V?)

Check voltageat pin 32 of 0501.

Check wafeformat pin 23 of IC501.

Check and repairH drive circuit,H output circuit,FBT circuit, etc.

Check X-Ray circuit,protection circuit.

To "Start circuit diagnosis".

Check and repair C403D490, Q501 (TA1222N)

Start circuit diagnosis

Start circuit diagnosis.

Check D431cathode voltage.

OK

NG

NG

OK

Check voltageat pin 22 of Q501.

Check and repairQ501 (TA1222N).

NG

OK

Check voltage ofAudio + B line.

Check and repairpower supply circuit.

Check and repair R432, Q430,D431 and D430.

Check and repair C430, C431,D490 and L400.

OK

127

2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES

No vertical scanning

Horizontal one line.

Check +27V power supply.

Check voltage at+ leed of C306

More than 20V

NG

OK

Check pin 13 input ofQ302 with

synchronous scope.

5Vp 5Vp

Check pin 31 output ofQ501 with

synchronous scope.

OK

NG OK

Check pin 15 of Q302with synchronous scope.

Check DEF + Vcc pin 22of Q501 is 9.0V. V/C + Vcc,

pin 40 and 46 of Q501 is 9.0V.

OK

1.5V

Check output circuit. Replace Q501.

NG

OK

Check pin 3 ofQ302 is +9V.

Replace Q302

Check and repair 910V D420, Q421, Q420 and R424.

Check, repair and replaceC310, D302, Q301, R327.

Check and repair L462R313, R304, R305, R306, R307 in vertical ourput circuit.

Check and repair Q302.

NG

Normal:15V

128

3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT

OK

Left-Right pin-cushiondistortion correction isnot carried out.

Check voltage across C460on DPC circuit. (-27V)

-27V:NG

OK

OK

OK

-27V

Paraborawaveform

Paraborawaveform

Paraborawaveform

Check waveformat Q461 collector.

Check waveformat Q462 collector.

Check waveforms at Q462emitter Q460 collector.

Check, replace or repairC467, C464, D461, L461

Parabola waveformis not observed



Check and repair R469output circuit.

Check and repair around Q461.

Check and repair D464, D465,D466, R343, R341, R465.

Check and repair aroundQ460, Q462

129

4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES

NG

OK

X-ray protection circuit doesnot work (When X - Rterminals are connected).

Check voltage at D471cathode. (20 - 22V?)

Check and repair Z801.

Check and repair D471, R472.Check and repair around pin9 of FBT.

130

5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE

• 125V line becomes over voltage, thyristor D862 comes in to failure, and when Q863 does not turn on, D888 is short-circuitedand intermittent oscillation occurs. To protect the circuit a double protection system is employed.

• When the overvoltage protection circuit is working. never turn on the power with the protection circuit disabled.High voltage will be stepped up and secondary breakdown may occur.

Operation of protection circuitfor Thyrister D862. (SR81 Relay turns on but immediately turns off.)

Power on with D870opened. (Do not turn on

for a long period.)

With SW turned on,check 125V line voltage

with oscilloscope.

SR81 turns on for a short timebut immediately turns off.

Higher than 130V.

Higher than 35V.

Higher than 24.1V.

Less than 130V

Less than 35V

Less than 24.1V

With SW turned on,check 24.5V line voltage

with oscilloscope.

With SW turned on,check voltage across C471

with oscilloscope.

Check C867, D862, D878,Q863, R874, R875, R877,and repair.

Check over-current protection circuit,H output and repair D870, Q870,R870 - R873, R876, R881.

Check over-voltage protection circuit(125V) and D846, D878, Q801, Q841,Q845, Q862 and repair.Check broken pattern in feedback loop.

Check over voltage protection circuit(24,5V) (125V rectification line opened, or 24.5V line leaded light.)Check rectification line (T862 -C889),Q610, pattern connectors connected toQ610, and repair.

Check X-ray protection circuit, H outputcircuit, X-ray protection detector circuit,and repair.

131

6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES

Failure Phenomena Reference Item

No picture OSD and picture do not appear. (A)

OSD is OK, picture does not appear. (B)

OSD is OK, picture does not appear. (A/V circuit is defective.) (C)

Picture of only VHF/UHF of main screen does not appear. (D)

Picture of only VHF/UHF of sub screen does not appear. (E)

No color After Q501, no color (F)

A/V, comb, etc. (G)

* Diagnosis of video signal through VIDEO input is done by inner video signal SGV as well.In this time, do not connect any cable to VIDEO 1.

132

(A) OSD AND PICTURE DO NOT APPEAR

NG

NG

NG

NG

NG

NG

Check that heater or CRT lights.

Power supply of CRT Drive board.9V, 200V

Check waveform of TP-47R, G, B.

Check waveform of TP-46R, G, B.

Check Q501 power.Pins 22, 40, 46---------- 9VPin 12---------------------- 5V

OK

OK

OK

OK

OK

OK

Check waveform of I2C bus line.

Check Q501 and peripherals.

Check R920 (heater resistor) andpower/def circuit.

Check power/def circuit.

Check CRT and power/defcircuit.

Check Q907, Q910 and blankingcircuit. (pow/def board)

Check power line and power/def circuit.

Check I2C bus line and QA01 (MICOM).

Check QA01 and periheral circuit.

133

(B) OSD IS OK, PICTURE DOES NOT APPEAR

Check waveform at pin 53 (Y2 input)of Q510. Approx. 0.7VP-P

OK

NG

OK

OK

OK

NG

NG

NG

NG

NG

NG

OK OK

OK

Check waveform at pin 4 (Y1 output)of Q510. Approx 0.7VP-P

Check waveform at pin 15 (Y1 output)of Q501. Approx 1VP-P

Check waveform of comb Y output.2VP-P

Check A/V circuit. Go to (C).

Check I2C bus line waveformat pins 27, 28 of Q501.

Check C203.

Check Q501.

Check waveform of comb Y input. 2VP-P

Check waveform of comb Y input.0.4 VP-P (3.58MHz)

Check Comb Board.

Check Q501.

Check I2C bus lineand QA01.

Check A/V circuit.Go to (C).

Check Q501.

134

(B) OSD IS OK, PICTURE DOES NOT APPEAR (A/V CIRCUIT IS DEFECTIVE)

OK

OK

OK

OK

NG

NG

NG

NG

Check waveform at pin 36 (Y-AV)or QV01. 2VP-P

Check waveform at pin 30 (Y-Comb) or QV01.

Check waveform at pin 38 (V-AV) or QV01.

Check input waveform. 1VP-P

Video1 Pin 12 of QV01 Video2 Pin 10 of QV01 Video3 Pin 16 of QV01

Go to (D), (E)

Check QV01.

Check QV01.

Check Q501. Go to (B).

Check Comb filter. Go to (B).

135

(D) PICTURE OF ONLY VHF/UHF OF MAIN SCREEN

Picture of only VHF/UHF of main screendoes not appear

Check waveform at pin 7of H002.

Check power voltage at pin 4of H002. 9V

Check waveform at pin 2of H002.

Check power voltage of H001. Pin3 9V Pin8 5V Pin9 32V

Check waveformat pin 7 of QV01. Replace QV01

Check/Replace QV40, QV41,QV42, QV43.

Check power circuit

Check power circuit

Replace H002

OK OK

OK

NG

NG

NG

NG

NG

OK

OK

Replace H001.

136

(E) PICTURE ONLY VHF/UHF OF SUB SCREEN DOES NOT APPEAR(B) OSD ISOK, PICTURE DOES NOT APPEAR

Picture of only VHF/UHF of main screen does not appear

Check waveform at pin 15of HY01.

Check power voltage of HY01. Pin9 9V Pin7 5V Pin2 32V

Check waveformat pin 28 of QV01.

OK OK

OK

NG

NG

NG

Replace QV01.

Check CV09,RV12.


Replace HY01.

137

(F) NO COLOR (AFTER Q501)

OK

NG

OK

OK

OK

OK

NG

NG

NG

NG

NG

Check waveform at pin 13 of Q501.Burst: 0.3 to 0.6 VP-P

Check power supply of Q501.Pin 1=5V, Pins 22, 40, 46=9V

Check waveform at pins 5, 6 of Q501.Color bar: approx. 0.6VP-P

Check waveform at pins 51, 52 of Q501.Color bar: approx. 0.6VP-P

Check waveform of I2C bus line.

Check Q501.

Check Q503 and A/V circuit.

Check power/def circuit.

Check Q501 and pins 10, 11peripherals.

Check C514, C515.

Check I2C bus line, and check busdata, micom memory, etc.

138

(G) NO COLOR (A/V, COMB)

OK

NG

NG

NG

NG

OK

OK

Check waveform of video output.(or check monitor picture.)

Check waveform at pin 34 of QV01.

Check waveform at pin 32 of QV01.Burst: 0.3 to 0.6 VP-P

Check Q501.

Check comb filter.

Check QV01.

Check QV01. Check U/V tuner,IMA module, etc.

Check input waveform as noted below. VIDEO 1 pin 14 of QV01 VIDEO 2 pin 10 of QV01 VIDEO 3 pin 18 of QV01

OK

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7520950 Toshiba CN27E90 TV Technical Training Manual

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