8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 E E D D C C B B A A DESCRIPTION REV DATE PAGES PAGE DESCRIPTION 2 Title, Notes, Rev. History 1 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5 6 A1 All INITIAL REVISION A RELEASE Blank Page Arria 10 SoC FPGA Development Kit Board Blank Page 1 26 27 28 29 PAGE DESCRIPTION 40 41 42 43 30 31 32 33 35 36 37 38 39 34 44 45 46 47 48 49 50 51 52 53 54 57 56 55 58 61 60 59 62 65 64 63 66 69 68 67 70 73 72 71 74 77 76 75 78 81 80 79 82 85 84 83 86 Block Diagram Clock Block Diagram I2C BUS Block Diagram Arria10 XCVR_1C_1D Arria10XCVR1E_1F_1G Arria10XCVR1H_1I_1J PCIe x8 Connector 10/100/1000 SGMII PHYA 10/100/1000 SGMII PHYB SFP+ Port A SFP+ Port B DisplayPort (x4) SD Transmit/Receive FMC Port A Con FMC Port B Con Arria102K_2J_HPS_DDR3_DDR4 Arria102L_HPS_SHAREDIO Arria10_DedicatedIO_CONF 10/100/1000 RGMII PHY BOOTFLASH_TRACEDebug HPS HILO 40-bit USB Ports HPS UART PORT Arria102A_2I_1V8IO Arria103H_3G_FMCA_V57.1A Arria103F_3E_FMCA_V57.1B Arria103A_FMCB_IO Arria103C_3D_HILO_IOA Arria103B_HILO_IOB DB9RS232 HILO 72-bit 5M2210 System Controller USB Blaster II -1 USB Blaster II -2 PLL PLL (2) Clock Cleaner Reset Circuit User IO Clock RES MUX I2C_MUX PDN Diagram Power Sequence MAINSwitch_12V_DC_12V 12Vto5V M12Vto3V3A M12Vto3V3B 3V3to2V5 3V3to1V8 A10switch_12V_3V3 BLANK 12Vto0V9_A 12Vto0V9_B 3V3toHPS0V95 3V3to0V95 3.3Vto1V0 3V3toHILOHPSVDD 3V3toHILOVDD 3V3toHILOVDDQ 3V3toFMCAVADJ 3V3toFMCBVADJ FMCSwitch_3V3 2V5_1V8Switch 3V3IOSwitch 3V3_1V8Discharge Load Currentmeasurement Power DAC_ADCcontroller Core Power Decoupling IO Power Decoupling DC3V3currentsensors Arria10_Power Arria10_GROUND Blank Page 1 MAXV_FPGA_IO BLANK A1.1 22 Change RGMII reference clock source, pull up to 1v8 40 DP clock netname is changed 42 LED resitors are changed to 100ohm 6,52,57 Change ED8101 I2C address to 0X0E and 0X10 55,68,69 Change DMP3098L to DMG2305UX, 28 Change netnames 45 Change Header to 0.1inch header 55 Add logic to turn off A10 power when MAXV need be reprogrammed. 55,68 Change PMOS to NMOS for reducing ON resistance ADD two LDOs for U31 56 51 ADD Linear LDOs for U24 19 HPS DM_alert bit postions are modified based on Quartus report 38 Move Mictor trace JTAG into 1.8 Bank of Max2 36 Connect 3V3 to BANK4 05 Update Clock diagram A2 21 Add 1K PULL UP resistors for MSEL[0..2], HPS,NPOR, HPSNRST ( only in SCH) 25 Change R98 and R99 to 1K ohm 22 Change R367 and R378 to 4.7K ohm 74 Change R646 pull up voltage to I01V8, Change R674 to 100K ohm 51 Need Install U74,Install D44, R156, DNI R157 Based on FB 282099 45 Change LCD address to 0x28 56 Install D43 60 Update the sense RC netowrk values based on FB 261730, add +-15% voltage adjustable range 59 Update the sense RC netowrk values based on FB 261730 66 Update the sense RC netowrk values based on FB 261730 64 Update the sense RC netowrk values based on FB 261730 63 Update the sense RC netowrk values based on FB 261730 62 Update the sense RC netowrk values based on FB 261730 54 Update the sense RC netowrk values based on FB 261730 57 Change remote senseing point to FGPA pins 60 Change R495 value from 240K to 226K for generating 1.03V output 57 Change ED8101P01QI to ED8101P04QI for 0.95V output 52 Change ED8101P02QI to ED8101P05QI for 0.95V output 51,52,56,57 Change R5258, R5243, R5045 & R5055 from 2K to 1.5K based on FB302118 22 Change Linear LDO from LTC3026 to LTC3026-1 A3 21 Change R676 to 22.0 ohm, and R679 to 0 ohm Title Size Document Number Rev Date: Sheet of A2 Arria 10 SoC FPGA Development Kit Board B 1 78 Tuesday, July 21, 2015 150-0321304 (6XX-44294R) Altera Corporation,101 innovation Dr, San Jose, CA 95134 Copyright (c) 2014, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of A2 Arria 10 SoC FPGA Development Kit Board B 1 78 Tuesday, July 21, 2015 150-0321304 (6XX-44294R) Altera Corporation,101 innovation Dr, San Jose, CA 95134 Copyright (c) 2014, Altera Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of A2 Arria 10 SoC FPGA Development Kit Board B 1 78 Tuesday, July 21, 2015 150-0321304 (6XX-44294R) Altera Corporation,101 innovation Dr, San Jose, CA 95134 Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Transcript
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Block DiagramClock Block DiagramI2C BUS Block Diagram Arria10 XCVR_1C_1DArria10XCVR1E_1F_1GArria10XCVR1H_1I_1JPCIe x8 Connector10/100/1000 SGMII PHYA10/100/1000 SGMII PHYBSFP+ Port ASFP+ Port BDisplayPort (x4)SD Transmit/ReceiveFMC Port A ConFMC Port B ConArria102K_2J_HPS_DDR3_DDR4Arria102L_HPS_SHAREDIOArria10_DedicatedIO_CONF10/100/1000 RGMII PHYBOOTFLASH_TRACEDebugHPS HILO 40-bitUSB PortsHPS UART PORTArria102A_2I_1V8IOArria103H_3G_FMCA_V57.1AArria103F_3E_FMCA_V57.1BArria103A_FMCB_IOArria103C_3D_HILO_IOAArria103B_HILO_IOBDB9RS232HILO 72-bit5M2210 System Controller
USB Blaster II -1USB Blaster II -2PLLPLL (2)Clock Cleaner
A1.1 22 Change RGMII reference clock source, pull up to 1v840 DP clock netname is changed42 LED resitors are changed to 100ohm6,52,57 Change ED8101 I2C address to 0X0E and 0X1055,68,69 Change DMP3098L to DMG2305UX,28 Change netnames 45 Change Header to 0.1inch header55 Add logic to turn off A10 power when MAXV need be reprogrammed. 55,68 Change PMOS to NMOS for reducing ON resistance
ADD two LDOs for U315651 ADD Linear LDOs for U2419 HPS DM_alert bit postions are modified based on Quartus report38 Move Mictor trace JTAG into 1.8 Bank of Max236 Connect 3V3 to BANK405 Update Clock diagram
A2 21 Add 1K PULL UP resistors for MSEL[0..2], HPS,NPOR, HPSNRST ( only in SCH)25 Change R98 and R99 to 1K ohm22 Change R367 and R378 to 4.7K ohm74 Change R646 pull up voltage to I01V8, Change R674 to 100K ohm51 Need Install U74,Install D44, R156, DNI R157 Based on FB 28209945 Change LCD address to 0x2856 Install D4360 Update the sense RC netowrk values based on FB 261730, add +-15% voltage adjustable range59 Update the sense RC netowrk values based on FB 26173066 Update the sense RC netowrk values based on FB 26173064 Update the sense RC netowrk values based on FB 26173063 Update the sense RC netowrk values based on FB 26173062 Update the sense RC netowrk values based on FB 26173054 Update the sense RC netowrk values based on FB 26173057 Change remote senseing point to FGPA pins60 Change R495 value from 240K to 226K for generating 1.03V output57 Change ED8101P01QI to ED8101P04QI for 0.95V output52 Change ED8101P02QI to ED8101P05QI for 0.95V output51,52,56,57 Change R5258, R5243, R5045 & R5055 from 2K to 1.5K based on FB30211822 Change Linear LDO from LTC3026 to LTC3026-1
A3 21 Change R676 to 22.0 ohm, and R679 to 0 ohm
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B1 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B1 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B1 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 SoC FPGA Development Kit Board
B2 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
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Arria 10 SoC FPGA Development Kit Board
B2 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
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A2
Arria 10 SoC FPGA Development Kit Board
B2 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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B3 78Tuesday, July 21, 2015
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Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
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A2
Arria 10 SoC FPGA Development Kit Board
B3 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B3 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 Dev Kit Block Diagram
Title
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Arria 10 SoC FPGA Development Kit Board
B4 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B4 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B4 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 Dev Kit Clock Connection
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Arria 10 SoC FPGA Development Kit Board
B5 78Friday, September 11, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B5 78Friday, September 11, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B5 78Friday, September 11, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 Dev Kit I2C bus Connection
Application of two I2C masters in PMVID bus
Title
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A2
Arria 10 SoC FPGA Development Kit Board
B6 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B6 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B6 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Quartus IO Standard = BLVDS TX -> DIFF SSTL-1.8 RX -> LVDSFogBugz Case 135234 & 147387
1) TX uses diff sstl18 configuration, which is able to meet peak-to-peak differential voltage and common mode voltage spec for DP.2) RX uses LVDS input, but user need to ensure pin voltage at NF receiver end is <1.9v. a. If the channel is AC couple, then user need to choose the correct Vbias_RX so that Vpin < 1.9v. The spec is 0 – 2v, which is quitewide. Selecting Vbias_Rx at 2v region will cause NF device to have reliability issue. b. If the channel is DC couple, user need to make sure TX common mode voltage + ground reference differences between Tx and Rx will notcause Vpin for NF to be higher than 1.9v.
Usually 3.3V forDP, but Arria 10is 1.8V LVDS.
0.5A maximum current
DP_HOT_PLUG
DP_ML_LANE_P0DP_ML_LANE_N0
DP_ML_LANE_P1DP_ML_LANE_N1
DP_ML_LANE_P2DP_ML_LANE_N2
DP_ML_LANE_P3DP_ML_LANE_N3
DP_AUX_CPDP_AUX_CN
DP_AUX_CHR_PDP_AUX_CHR_N
DP_AUX_CP
DP_3p3V_CONFIG2
VBIAS_DP
DP_ML_LANE_CP1DP_ML_LANE_CN1
DP_ML_LANE_CN3DP_ML_LANE_CP3
DP_ML_LANE_CP2DP_ML_LANE_CN2
DP_ML_LANE_CN0DP_ML_LANE_CP0
DP_RTN
DP_3p3V_CONFIG1
DP_AUX_CHB_PDP_AUX_CHB_N
IO_1V8 36,37,68IO_3V3 69,74
DP_ML_LANE_P0 9DP_ML_LANE_N0 9
DP_ML_LANE_P1 9DP_ML_LANE_N1 9
DP_ML_LANE_P2 9DP_ML_LANE_N2 9
DP_ML_LANE_P3 9DP_ML_LANE_N3 9
DP_CONFIG136DP_CONFIG236
DP_HOT_PLUG36
DP_ON36
DP_OCn36
DP_AUX_CH_P 27DP_AUX_CH_N 27
DP_AUX_DE 36
DP_AUX_D 36
DP_AUX_REn 36
DP_AUX_R 36
GND_DP
GND_DP GND_DP
IO_1V8
IO_3V3IO_3V3
IO_1V8
DP_3V3
IO_3V3
DP_3V3
DP_3V3
DP_3V3
IO_3V3
Title
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A2
Arria 10 SoC FPGA Development Kit Board
B15 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B15 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B15 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C1330.1uF
R224 100K
C8784.7nF
C856 0.1uFC855 0.1uF
R225 100K
C137 0.1uF
R211DNI
C893
2.2uF
R793 0
J46
0472720024
ML_LANE_0P1
ML_LANE_0N3
GND5
ML_LANE_2P7
ML_LANE_2N9
GND11
GND2
ML_LANE_1P4
ML_LANE_1N6
GND8
ML_LANE_3P10
ML_LANE_3N12
CONFIG214 CONFIG113
AUX_CH_P15
GND16
HP_DETECT18
DP_PWR20
AUX_CH_N17
RTN19
MH121
MH222 MH3
23
MH424
C848
10uF
R218 22.0
R22010K
R212DNI
C854 0.1uF
R806 100K
VDD GND IO6 IO5
IO3 IO4IO2IO1
D37
824016467
4
81 2 3
56
R7651M
R21949.9
C888
0.1uF
C859 0.1uF
U27
SN65MLVD200AD
4D
3DE
1R
2RE_n
6 A
7 B
GND5
VCC8
C1340.1uF
C847
0.1uF
C2453 0.1uF
U28
TPD2EUSB30D-
2D+1
GND3
R750DNI
C138 0.1uF
R21649.9
U71
MAX14523B
IN5
OUT4
ON7 GND
8FLAG2
NC26
SETI3NC1
1
GND_PAD9
R22310K
R790 1M
C830
0.1uF
R792 100K
C858 0.1uF
C860 0.1uF
R791 1M
VDD GND IO6 IO5
IO3 IO4IO2IO1
D38
824016467
4
81 2 3
56R217 22.0
C857 0.1uF
R802
280K
1%
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SDI Cable Driver, Equalizer, and SMB
75 Ohm Single-Ended Impedance
MODE_SEL = 0 -> HARDWARE MODE
DISABLE SDO1 ->
Layout Notes (M23428) SDI Cable Driver:- The RSET resistor should be located close to pin 5. - Remove GND under pin 5 and the RSET resistor.- The 49.9-ohm resistors should be placed close to device pins 16 and 1 (SDIP/SDIN).
Layout Notes (M22544) SDI Cable Equalizer:- The AGC 33nF capacitor should be located close to the device pins 8 and 9 (AGC+/AGC-). - Clear GND under the AGC 33nF capacitor.
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B45 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B45 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
B1
2x16 LCD BOM I2C
C331
0.1uF
J28
DNI
11
33
55
77
22
44
66
88
99
1010
C314
0.1uF
R614 0
R402 0
R387
DNI
R380
4.7K
R605 0
C320
0.1uF
R377 0
R51 4.7K
C321
0.1uF
C309
0.1uFC338
0.1uF
R397 0
C310
0.1uF
R395
4.7K
R50 0
U5
DS1339C
SDA16
SCL1
GND15
VCC3
VBACKUP14
SQW/INT2
NC54
NC65
NC76
NC87
NC98
NC109
NC410 NC311 NC212 NC113
C330
0.1uF
R606 DNI
R389 0
R399 200
U43
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R386
4.7K
R394
4.7K
R410
4.7K
R615 DNI
R385 0
C315
0.1uF
BT1
12
R375 0
C1562
2200pf
U45
24LC32A
A01
A12
A23
GND4
VCC8
WP7
SCL6
SDA5
R374
4.7K
U48
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
U44
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R398 0
R379
4.7K
J35
LCD_HEADER
123456789
10
R401
4.7K
R388 0
C18 0.1uF
R29 0
U46
MAX1619
ADD16
ADD010
SMBCLK14
SMBDATA12DXP
3
DXN4
VCC1
OVERTn9
ALERTn11
STBYn15 GND1
2
GND27
GND38
NC15
NC213
NC316
R757
4.7K
C2350
0.1uF
R776
4.7K C873
0.1uF
R396
DNIR376
4.7K
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A A
A10 SOC DEV KIT PDN Diagram
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B46 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B46 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B46 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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A10 SOC Power Sequence
1. If the VCC voltage level is different from VCCT_GXB, VCCR_GXB, and orVCCRAM, then ramp VCC first followed by VCCT_GXB, VCCR_GXB, and VCCRAM (In any order) within group 12. All Power rails must ramp completely to full rail voltage within the Tramp (0.2ms to 4ms)3.VCCBAT (1.2-1.8V) can be powered up/down at any time and is not shown in the power sequence4.The Power down sequence is the reverse of the power up sequence
Title
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A2
Arria 10 SoC FPGA Development Kit Board
B47 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B47 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B47 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
8
8
7
7
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6
5
5
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4
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1
E E
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B48 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B48 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B48 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
12V ATX INPUT (12.5A)
16A 1A
4A
1A
10A
Input connector for 200 Watt AC/DC Adapter 12V Power PMOS Switches
3v/ms
3v/ms
3v/ms
3v/ms
Adapter_DC_12V
MAIN_GATE
FMCB_EN35
PCIE_EN35
FMCA_EN35
FMCB_12V 18
PCIE_12V 10
FMCA_12V 17
MAIN_12V 27,50,51,52,55,68
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B49 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B49 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B49 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
D41
B530C
Q39MMBT2222A-7-F
CE
B
R68610
Q9
DMP3098L
S
D
G
C8821uF
R520849.9K
R79549.9K
R53531.00k
R80810K
C8791uF
Q30MMBT2222A-7-F
CE
B
R80749.9K
Q31MMBT2222A-7-F
CE
BQ37MMBT2222A-7-F
CE
B
C64
330uF25V
R78610
R75610
C899
0.1uF
C1021uF
R5354
1.00k
R73510
J31
PCIe 2x4 ATX
12V1
12V2
12V3
GND8
SENSE14 SENSE06
GND5
GND7
R16249.9K
R68510K
C67
330uF25V
R775100K
Q8Si7635DP
1
567
4
8
23
TP90
Q35DMP3098L
S D
G
Q34DMP3098L
S D
G
SW5SW_SLIDE_DPDT
1
236
5
4
TP26
R187100K
TP103
R53741.00k
R78110
C63
330uF25V
TP114
TP104
TP84
R80310K
R75549.9K R785
49.9K
C777
0.1uF
R796100K
R17110
R78010
J36
PD-40S
GND3VOUT2VOUT1
GND4
SGND5
SGND6
SGND7
SGND8
SGND9
R172100K
C65
330uF25V
R79449.9K
Q42MMBT2222A-7-F
CE
B
R19610
TP113
R5375
1.00k
TP24
R68749.9K
C898
0.1uF
Q36
DMP3098L
S
D
G
R77349.9K
Q12Si7635DP
1
567
4
8
23
R77410
Q38
DMP3098L
S
D
G
R52131.00k
R5214
1.00k
C8721uF R810
49.9K
Q41MMBT2222A-7-F
CE
B
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0402
0402
0402
Output capacitors chosen for smallest footprint. For lower Vout ripple option, use two 47uF/1206/X5R capacitors.
PVIN = 12V
Connect input and output caps to GND plane through mulitple vias. (See the Gerber files.)
0402X7R
A single through-hole via connects these AGND pins to the GND plane.
0402X7R
0402X7R
X7R
0402/X7R
0402
0402
0402
Cin: 22u 1206 25V X5R
0402
VOUT = 5V
Rclx and Rfs chosenfor 12Vin/1.2Vout
0402 or0201
12V to 5V Converter
1.5A
PO_EN
5V0_Pgood 35
IO_5V11,12,22,25,45,71
MAIN_12V 49
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B50 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B50 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B50 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C834
TP100
R709
100k
R728560
C8051uF R696
49.9K
TP105
TP92
R5508DNI
TP93
C7881uF
R503080.6k
TP102
C79622nF
R69514.3K
C787 47nF
F1 1AC78556pf
C786680PF
R70810K
C840
R70768.1K0402
R69110K
R7104.75k
U66EN2342QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
2626
NC
(SW
)27
27
NC
(SW
)28
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
PG
ND
34
S_OUT48
S_IN47
BGND46
VDDB45
BTMP44
PG43
AVINO42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
NC
(SW
)61
61
AG
ND
60
NC
5959
FQA
DJ
58
RC
LX57
SS
56
EA
OU
T55
VFB
54
AG
ND
53
AG
ND
52
AV
IN51
EN
AB
LE50
PO
K49
GN
D_P
AD
69
R6924.7
C795
0.22uF
R70630.1K0402
R7050
C835
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206
1206
1206
All output capsshould becombination1206/0805footprint
PWMOFF#
AGND
Current Sensing
VOUT
ISEN
6A
30A
12V to 3V3 Converter (40A MOSFET)
VCC1
VCC2
PAU1_SW
PAISNSP 52
PAISNSN 52
PAVFBP 52
PAPWM52
PATSEN52
3V3 37,38,44,53,54,55,65,69,71
MAIN_12V49
PA3V3 52
PALSE52
PAVFBN 52
3V3
PA1V8
PA3V3
MAIN_12V
MAIN_12V
MAIN_12VPA3V3
PA3V3
PA1V8MAIN_12V
PA1V8
PA1V8
PA3V3
MAIN_12V
PA1V8
MAIN_12V
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B51 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B51 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B51 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R1510
R160
DNI
C87 DNI
C751 22uF
R5506118K
R5249DNI
R5254
1.00k
C723DNI
U60
EY1602SI-ADJ
IN1
NC22
NC33
EN4
OUT8
ADJ7
NC66
GND5
EP
AD
9
TP72
C707
C08
05
DNI
C752 22uF
R120 0
C1566
22uF
C81 1uF
C1564
2200pf
C750 22uF
D44SL03-GS08
C69DNI
U74
LT3061
REF_BYP1
ADJ2
OUT13
OUT24
IN25
IN16
SHDNn7
GND18
GND29
C15680.01uF
R152
511
C638DNI
C83 1uF
R148
DNI
C749 DNI
R5258
1.5K
R571
590
C84 DNI
C98DNI
C748 22uF
TP61
C89 1uF
C95
0.22uF
R146 0
C7247uF
C672DNI
C722DNI
R132 DNI
R157 DNI
C1569
C08
05
10uF
U24ET4040
NC11
VCC_GND2
PWM3
OFF#4
ISEN5
REFIN6
NC77
TSEN/FAULT8
BGND9
BGND10
NC1111
NC1212
VIN
15
VIN
16
VIN
17
PG
ND
18
PG
ND
19
PG
ND
20
VC
C_G
D21
VC
C_G
D22
NC
2323
SW37
SW36
SW35
SW34
SW33
SW32
SW31
SW30
SW29
SW28
SW27
SW26
VC
C46
NC
4545
VIN
44
PG
ND
43
PG
ND
42
PG
ND
41
VC
C_G
D40
VC
C_G
D39
NC
3838
PHASE13
BOOT14
SW25
SW24
VIN
47
GN
D_P
AD
248
SW
49
R150 10K
C76100uF
TP73
C50422uF
C7347uF
L5
130nH
C80 1uF
C88 1uF
C637DNI
C753 DNI
C724DNI
C15670.01uF
R1590
R5250
DNI
R131 DNI
C721DNI
C636DNI
R550759K
C7447uF
C96
0.22uF
C79 DNI
R147 0
C7147uF
R121 0
C671DNI
R5262
1.00k
TP25
R5502
1.5
R1580
R5237DNI
U62
DNI
IN1
NC22
NC33
EN4
OUT8
ADJ7
NC66
GND5
EP
AD
9
C708DNI
C518
C08
05
10UFR5251
1.00k
C90 1uF
TP83
C82 1uF
R156 0
C92 DNI
C75100uF
C91 0.1uF
C931uF
TP23
C754 22uF
C94DNI
R5503
1.5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Address = b'0001110'
12V to 3V3 Converter (Controller)
PAPWM 51
PATSEN51
PAISNSP51
PAISNSN51
PA3V3 51PAVFBP51
PMbus_SDA_3V3 27,45,57,73
PMbus_SCL_3V3 27,45,57,73
PMbus_ALTERTn 35,45,57,73
MAIN_12V49
3V3_Pgood 35
PALSE 51
PAVFBN51
PA3V3
MAIN_12V
PA3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B52 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B52 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B52 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R549
DNI
R548
DNI
C4814.7uFC0402
C435
0.1uF
C469
0.1uFC4684.7uFC0402
R5243
1.5K
C467
DNI
R5430
R4980
R547
DNI
C449
DNI
TP63
R544100k
R4991.69k
C4514.7uFC0402
C4804.7uFC0402
TP65
TP64
R49720K
R546100k
R52391.00k
TP66
TP67
R545
4.7K
R54222K
R50949.9
U57ED8101P05QI
AGND1
VREFP2
VFBP3
VFBN4
ISNSP5
ISNSN6
TEM
P7
VIN
8
AD
DR
09
AD
DR
110
PW
M11
LSE
12
AD
CV
RE
F24
AV
DD
1823
VD
D50
22
VD
D33
21
VD
D18
20
GN
D19
SCL18
SDA17
SMBALERT16
GPIO015
CONTROL14
PGOOD13
GP
AD
25
R50810K
C450
22pF
R52701.00k
TP62
C4914.7uFC0402
R541
4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206 1206
0402
0402
0402
0402
VIN = 2.4 - 6.6 VDC
A single through-hole test point connects the AGNDpin to the GND plane.
Connect the output cap to the GND plane through multiple vias
Connect the input cap to the GND plane through multiple vias.(see the Gerber files)
X5RX5R
2A
2A
3V3 to 2V5 Converter
PDEN
2V5out
2V5_Pgood 35
3V3 35,42,51
2V538,68,71
2V5I_P71
2V5I_N71
3V3
2V5
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B53 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B53 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B53 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C1251uF
R7360
R202
0.001
R737
100k
C798 47uF
R732DNI
R744
200k
R7450
TP96
C797 22uF
C82615nF
U68EN6337QI
NC(SW)71
NC(SW)62
NC33
NC44
VOUT5
VOUT6
VO
UT
7
VO
UT
8
VO
UT
9
VO
UT
10
VO
UT
11
NC
(SW
)12
PG
ND
13
PG
ND
14
PG
ND
15
PG
ND
16
PG
ND
17
PG
ND
18
PV
IN19
NC2525
NC2424
NC2323
NC2222
PVIN21
PVIN20
NC
(SW
)138
NC
(SW
)237
NC
(SW
)336
NC
(SW
)435
NC
(SW
)534
AV
IN33
AG
ND
32
VFB
31
SS
30
RLL
M29
PO
K28
EN
AB
LE27
LLM
/SY
NC
26
GN
D_P
AD
39
TP95
R738
86.6k
R195 10KC827
15pF
R201 10K
TP101
C111 47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206
1206
0402
Connect the input and output caps to the GND plane through mulitple vias.(Please see the Gerber files.)
X5R
X5R
X5R
0201X5R
1206 X5R
1206 X5R
A single through-hole viaconnects the AGNDpin to the GND plane.
0402
0402
0402
0201
0.999V
10A
0402
3.3V to 1.8V Converter
8A
5A
1V8_OUT
1V8_Pgood 35
3V3 35,42,51
1V8DAC_P 73
1V8DAC_N 73
1V8SENSP73
1V8SENSN73
1V823,38,39,55
A10_1V8I_P71
A10_1V8I_N71
1V8
3V3
3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B54 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B54 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B54 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R723
100k
R69915k
TP109
C841 47uF
R7150
TP97
C862 47uF
R7140
R712 10K
R758100
R701
DNI
C789 15nF
R713
5.49k
C850 47uF
R759100
C7990.22uF
R700
DNI
TP160
C874
0.22uF
TP33
C842 47uF
R711 DNI
U67EN63A0QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1919
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
VO
UT
25
VO
UT
26
VO
UT
27
VO
UT
28
NC
2929
NC
(SW
)30
30
NC
(SW
)31
31
PG
ND
32
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
S_IN56
BGND55
VDDB54
NC5353
NC5252
PVIN51
PVIN50
PVIN49
PVIN48
PVIN47
PVIN46
PVIN45
PVIN44
PVIN43
NC
7676
NC
7575
NC
7474
NC
7373
NC
7272
NC
(SW
)71
71
NC
(SW
)70
70
EN
_PB
69
FQA
DJ
68
NC
(XR
EF)
67
VS
EN
SE
66
SS
65
EA
OU
T64
VFB
63
M/S
62
AG
ND
61
AV
IN60
EN
AB
LE59
PO
K58
PG
ND
38S
_OU
T57
PVIN42
PVIN41
PVIN40
PVIN39
NC1515
NC1616
NC1717
NC1818
GN
D_P
AD
77
R698160k
R258
0.00025
R271 10KR6970
C78027pF
R272 10K
R522980.6K
C849 47uFC1721uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Typical 12V good threshold voltage is 10.62V. Typcial 12V bad threshold voltage is 10.11V
9A 3.5A10A
A10 12V,3V3 and 1V8 PMOS Switches
J58 need be shorted if MAXV is not programmed
10A
A10_12V 56,57,73MAIN_12V49
A10_EN35
A10_main_3V3 56,58,59,60,62,63,64,66,67
10V_Fail_n 35
10V_good 35
3V335,42,51
1V835,54
A10_main_1V8 56,68
3V3
3V3
A10_12V
3V3
1V8
MAIN_12V
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B55 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B55 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B55 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
TP88
C1561
100uF6.3V
R69310K
U39
TPS3700
OUTA1
OUTB6
VDD5
INA+3
INB-4
GND2
R68210
Q40MMBT2222A-7-F
CE
B
R5971.00k
Q44
SiRA00DP
1567
4
8
23
R608100K
Q28MMBT2222A-7-F
CE
B
TP68
TP42
TP69
J58
CON2
12
TP45
C20
0.1uF
TP37
TP44
R68149.9K
R694
10K
R680100K
C8940.01uF
C5990.01uF
TP87
R5210K
Q46MMBT2222A-7-F
CE
B
Q27
SiRA00DP
1567
4
8
23
C7741uF
R5449.9
R277100K
Q29MMBT2222A-7-F
CE
B
R273100K
R2781.00k
R54911.00k
R5325.5K
TP89
R60710K
C779
0.1uF
C1560
100uF6.3V
Q10Si7635DP
1
567
4
8
23
R5510K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206
1206
1206
All output capsshould becombination1206/0805footprint
PWMOFF#
AGND
Current Sensing
VOUT
ISEN
4.5A
30A
12V to 0.9V Converter (40A MOSFET)
VCC1
VCC2
0.95V output
PLU1_SW
A10_12V55
A10_0V9 74,76
PLISNSP 57
PLISNSN 57
PLVFBP 57
A10_Main_3V355
A10_main_1V855
PLPWM57
PLTSEN57
PLLSE57
PLVFBN 57
PL_3V3 57
A10_12V
A10_0V9
A10_12V
A10_12V
A10_12VPL_1V8
PL_3V3
PL_3V3
PL_3V3
PL_3V3
PL_1V8
PL_1V8
PL_1V8
PL_1V8 A10_12V
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B56 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B56 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B56 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R5515 DNI
C143 1uF
C150 1uF
R5511118K
C869 DNI
R231
511
C866 22uF
C140 1uF
C865 DNI
C868 22uF
C1571
22uF
C11747uF
C12347uF
C139 DNI
R238 0
R240
DNI
R2520
C147 DNI
C819DNI
R2510
C808DNI
R551259K
C144 DNI
C162
0.22uF
R5513280K
TP29
R5505
1.5
C870 22uF
C838DNI
R2420
U31ET4040
NC11
VCC_GND2
PWM3
OFF#4
ISEN5
REFIN6
NC77
TSEN/FAULT8
BGND9
BGND10
NC1111
NC1212
VIN
15
VIN
16
VIN
17
PG
ND
18
PG
ND
19
PG
ND
20
VC
C_G
D21
VC
C_G
D22
NC
2323
SW37
SW36
SW35
SW34
SW33
SW32
SW31
SW30
SW29
SW28
SW27
SW26
VC
C46
NC
4545
VIN
44
PG
ND
43
PG
ND
42
PG
ND
41
VC
C_G
D40
VC
C_G
D39
NC
3838
PHASE13
BOOT14
SW25
SW24
VIN
47
GN
D_P
AD
248
SW
49
C806DNI
C126100uF
C1575
22uF
C1570
C08
05
10UF
R5504
1.5
C809DNI
R5055
1.5K
C818DNI
D43SL03-GS08
C11847uF
C839DNI
R5516
1.00k
C807DNI
C15720.01uF
R214 DNI
C127100uF
R551461.9K
R239 0
R5496 0
U75
LT3061
REF_BYP1
ADJ2
OUT13
OUT24
IN25
IN16
SHDNn7
GND18
GND29
R186 0
C837DNI
C1565
2200pf
C15730.01uF
C163
0.22uF
R253
DNI
C142 1uF
C152 DNIC141 1uF
C1574
C08
05
10UF
L10
130nH
R5059
1.00k
R250 DNI
C836DNI
C867 22uF
C148 1uF
C165DNI
R213 DNI
C15760.01uF
C149 1uF
C1601uF
TP30
TP32
C151 1uFU76
LT3061
REF_BYP1
ADJ2
OUT13
OUT24
IN25
IN16
SHDNn7
GND18
GND29
R241 10K
C161DNI
C15770.01uF
C864 22uF
C12447uF
R249 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Address = b'0010000'
12V to 0.9V Converter (Controller)
0.95V Output Controller
A10_12V55
A10_0V9_EN 35
PLPWM 56
PLTSEN56
PLISNSP56
PLISNSN56
PL_3V3 56PLVFBP56
PMbus_SDA_3V3 27,45,52,73
PMbus_SCL_3V3 27,45,52,73
PMbus_ALTERTn 35,45,52,73
P0V9Pgood 35
PLLSE 56
A10_VCCLSENSE74
A10_GNDSENSE74
PLVFBN56
A10_12V
PL_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B57 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B57 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B57 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R2740
C8904.7uFC0402
R276100k
TP38
C8864.7uFC0402
R25420K
TP35
C8914.7uFC0402
TP36
R762DNI
R275
DNI
R779DNI
R2550
TP39
R50721.00k
R2330
TP41
R2690
R80049.9
R80110K
R2320
TP40
U34ED8101P04QI
AGND1
VREFP2
VFBP3
VFBN4
ISNSP5
ISNSN6
TEM
P7
VIN
8
AD
DR
09
AD
DR
110
PW
M11
LSE
12
AD
CV
RE
F24
AV
DD
1823
VD
D50
22
VD
D33
21
VD
D18
20
GN
D19
SCL18
SDA17
SMBALERT16
GPIO015
CONTROL14
PGOOD13
GP
AD
25R2701.5K
C885
22pF
TP34
C169
0.1uF
R763DNI
C166
0.1uF
C887
DNI
R50401.00k
C892
DNI
C8974.7uFC0402
C1704.7uFC0402
R5045
1.5K
R812100k
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206 1206
0402
0402
0402
0402
VIN = 2.4 - 6.6 VDC
A single through-hole test point connects the AGNDpin to the GND plane.
Connect the output cap to the GND plane through multiple vias
Connect the input cap to the GND plane through multiple vias.(see the Gerber files)
For a PWM application RLLM pin can float, and LLM/SYNC has to be tied to GND.
X5RX5R
2A
1A
3.3V to 0.95V Converter
PPEN
0V95out
P0V95Pgood 35
0V9574,76
A10_Main_3V3 55
A10_0V95_EN 35,73
A10_0V95I_P71
A10_0V95I_N71
0V95
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B58 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B58 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B58 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C767 22uF
R66949.9
C76015nF
R135
0.001
R655
750K
TP81
C740
15pF
C739 47uF
TP86
R668DNI
R657
100k
R652
200k
TP85
R6500
R133 10K
R134 10K
TP74
C771uF
U64EN6337QI
NC(SW)71
NC(SW)62
NC33
NC44
VOUT5
VOUT6
VO
UT
7
VO
UT
8
VO
UT
9
VO
UT
10
VO
UT
11
NC
(SW
)12
PG
ND
13
PG
ND
14
PG
ND
15
PG
ND
16
PG
ND
17
PG
ND
18
PV
IN19
NC2525
NC2424
NC2323
NC2222
PVIN21
PVIN20
NC
(SW
)138
NC
(SW
)237
NC
(SW
)336
NC
(SW
)435
NC
(SW
)534
AV
IN33
AG
ND
32
VFB
31
SS
30
RLL
M29
PO
K28
EN
AB
LE27
LLM
/SY
NC
26
GN
D_P
AD
39
C78 47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDCConnect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
Optional EAOUT test pointis used for monitoring purposes only.
0201X5R
0402
1206 X5R
0402
0.896V
3A
1.5A
3.3V to 0.9V converter ( HPS Core)
HPS_0V95outHPS_0V9574,76
A10_Main_3V3 55
HPS_Pgood 35
A10_0V95_EN 35,73
A10_0V95DAC_P 73
A10_0V95DAC_N 73
A10_0V95SENSP73
A10_0V95SENSN73
A10_HPS0V95I_N71
A10_HPS0V95I_P71
HPS_0V95
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B59 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B59 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B59 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
TP94
R665
1.78M
J30
CON2
12
R702160kR170 10K
R66649.9
R161 10K R68915k
C991uF
C773 47uF C759 22uF
TP78
R169
0.001
R683 DNI
C775 15nF
R656
100k
TP79
R688 10K
R6770
U65EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQA
DJ
60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
PO
K50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
TP77
R667324K
R141100
R7030
C772 47uF
R142100
R14010K
C7570.22uF
R684
3.57k
C85
0.22uF
C758 22uF
R153
DNI
TP80
C78122pF
R143
DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206
1206
0402
Connect the input and output caps to the GND plane through mulitple vias.(Please see the Gerber files.)
X5R
X5R
X5R
0201X5R
1206 X5R
1206 X5R
A single through-hole viaconnects the AGNDpin to the GND plane.
4A
0402
0402
0402
0201
Feedback network configured for 3.3Vin /1.0Vout 0.999V
10A
0402
3.3V to 1.0V Converter
+-15% rangeUpdate the value to 226K from 240K for 1.03V output
1.03V output
A10_1V0OUT
PFEN
A10_Main_3V3 55
A10_1V074,77
A10_1V0DAC_P 73
A10_1V0DAC_N 73
A10_1V0SENSP73
A10_1V0SENSN73
A10_1V0_EN 35,73
1V0_Pgood 35
A10_1V0I_P71
A10_1V0I_N71
A10_Main_3V3
A10_1V0
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B60 78Tuesday, July 28, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B60 78Tuesday, July 28, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B60 78Tuesday, July 28, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R460
100k
C456 47uF
TP60
R494
DNI
R5040
TP15
TP58
R50312k
R502160k
TP59
R48810K
C455 47uF
C454 47uF
C45227pF
R495226K
U56EN63A0QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1919
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
VO
UT
25
VO
UT
26
VO
UT
27
VO
UT
28
NC
2929
NC
(SW
)30
30
NC
(SW
)31
31
PG
ND
32
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
S_IN56
BGND55
VDDB54
NC5353
NC5252
PVIN51
PVIN50
PVIN49
PVIN48
PVIN47
PVIN46
PVIN45
PVIN44
PVIN43
NC
7676
NC
7575
NC
7474
NC
7373
NC
7272
NC
(SW
)71
71
NC
(SW
)70
70
EN
_PB
69
FQA
DJ
68
NC
(XR
EF)
67
VS
EN
SE
66
SS
65
EA
OU
T64
VFB
63
M/S
62
AG
ND
61
AV
IN60
EN
AB
LE59
PO
K58
PG
ND
38S
_OU
T57
PVIN42
PVIN41
PVIN40
PVIN39
NC1515
NC1616
NC1717
NC1818
GN
D_P
AD
77
R110 10K
R109 10K
C427 47uF
R511 10K
R5100
R493DNI
R506100
TP19
C426 47uF
R505
3.57k
R4252
0.00025
C4180.22uF
C457
0.22uF
R512 DNI
R496100
C453 15nF
C661uF
R48949.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B61 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B61 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B61 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V2SET
1V5SET
1V35SET
3A
1.5A
3.3V to HPS HILO VDD converter
HILOHPS_VDDOUT
PIEN
HILOHPS_VDD24,74,77
HILOHPS_VDDPGood 35
IO_EN 35,73
A10_Main_3V3 55
HILOHPSSENSP73
HILOHPSSENSN73
HILOHPSDAC_P 73
HILOHPSDAC_N 73
HILOHPS_1V2_SETn24
HILOHPS_1V35_SETn24
HILOHPS_1V5_SETn24
A10_HPSVDDI_P71
A10_HPSVDDI_N71
HILOHPS_VDD
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B62 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B62 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B62 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R462160k
R425
240K
R91100
C41422pF
TP51
R4330
R451 10K
R87100
C3510.22uF
C56
0.22uF
TP56
R4630
R442
5.49k
R436191K
R88
DNI
R426
390K
R89
DNI
TP50
C375 15nF
TP54
R45615k
R450 DNI
C365 47uF
C352 22uF
R4410
C353 22uF
R95 10K
TP57
C366 47uF
R96 10K
R431
976K
C581uF
TP55
R5131
100k
U52EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQA
DJ
60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
PO
K50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
R94
0.001
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
4A
1.7A
3.3V to HILO VDD converter
1V3SET
PGEN
HILO_VDDOUTHILO_VDD34
HILO_VDDPGood 35
IO_EN 35,73
A10_Main_3V3 55
HILOVDDSENSP73
HILOVDDSENSN73
HILOVDDDAC_P 73
HILOVDDDAC_N 73
HILO_1V25_SETn34
HILO_1V2_SETn34
HILO_1V5_SETn34
HILO_1V35_SETn34
HILO_1V8_SETn34
HILO_1V30_SETn34
A10_HLVDDI_P71
A10_HLVDDI_N71
HILO_VDD
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B63 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B63 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B63 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R145 10K
R155
0.001
R6390
U63EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQA
DJ
60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
PO
K50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
C709 15nF
R5160
487K
TP76
R130
DNI
R622
137K
R623
240K
R129
DNI
TP70
R624
390K
R638191K
R635 10K
R626
976K
C765 47uF
R5169
100k
R163100
C7320.22uF
C766 22uF
R636 DNI
R154100
TP71
R63415k
C755 47uF
R6370
R648
5.49k
C97
0.22uFR647160k
TP75
C756 22uF
TP82
R144 10K
R6490
C861uF
C72522pF
R627
649K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
3A
1.5A
3.3V to HILO VDDQ converter
A single through-holevia/test point connects AGND pin to the GND plane.
1V3SET
HILO_VDDQOUTHILO_VDDQ34,74,77
HILO_VDDQPGood 35
IO_EN 35,73
A10_Main_3V3 55
HILOVDDQSENSP73
HILOVDDQSENSN73
HILOVDDQDAC_P 73
HILOVDDQDAC_N 73
HILOQ_1V2_SETn34
HILOQ_1V25_SETn34
HILOQ_1V30_SETn34
HILOQ_1V35_SETn34
HILOQ_1V5_SETn34
HILOQ_1V8_SETn34
A10_HLVDDQI_P71
A10_HLVDDQI_N71
HILO_VDDQ
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B64 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B64 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B64 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C492 15nF
R559
100k
U59EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQA
DJ
60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
PO
K50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
TP18
R557191K
C529 47uF
TP21
C4950.22uF
TP20
R5580
C530 22uF
R119100
R526
649K
R118100
R111 10K
TP17
R527
976K
R108
DNI
C70
0.22uF
C681uF
R107
DNI
R553 10K
TP16
R530
240K
R112 10K
R551160k
R114
0.001
TP22
R528
390K
C49422pF
R554 DNI
R55215k
R555
5.49k
R531
137K
C564 47uF
R5680
C565 22uF
R5560R529
487K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
3A
0.02A
3A
0.02A
FMC 3.3V PMOS SwitchesFMCB_3V3 72
FMCB_aux3V3 18
FMCA_3V3 72
FMCA_aux3V3 17
FMCA_EN35
FMCB_EN35
FMCA_AUXEN35
FMCB_AUXEN35
3V335,42,51
3V3
3V3
3V3
3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B65 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B65 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B65 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Q13
DMG2305UX
S
D
G
Q3
SiSS23DN
1
567
4
8
23
R1410
Q17
DMG2305UX
S
D
G
R110
C1771uF
R610
TP4
Q1
SiSS23DN
1
567
4
8
23
TP3
R2100K
TP5R2310
TP10
TP2
Q16
DMG2305UX
S
D
G
TP1
C1871uF
R24100K
Q14
DMG2305UX
S
D
G
Q4
SiSS23DN
1
567
4
8
23
R410
R5100K
TP8
R1910
C1781uF
TP6
R25100K
C1861uF
R310
Q2
SiSS23DN
1
567
4
8
23
R1810
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
6A3A
3.3V to FMC A VADJ converter
PJEA
FMCAVADJOUT
PJEN
FMCAVADJ17,36,74,77
FMCAVADJPGood 35
FMCA_EN 35
A10_main_3V3 55
FMADAC_P 73
FMADAC_N 73
FMASENSP73
FMASENSN73
FMAVADJI_P71
FMAVADJI_N71
FMCAVADJA10_main_3V3
A10_main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B66 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B66 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B66 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R777
5.49k
C896 22uF
R811
137K
R7980
R261
DNI
C883 47uF
R76015k
R260
DNI
TP112R7870
R799
390K
R788
976K
R761 10KC880 15nF
U70EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQA
DJ
60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
PO
K50
PG
ND
34S
_OU
T49
GN
D_P
AD
69 TP115
R805
240K
C86322pF
C1641uF
TP111
R752160k
R243 10K
R797191K
C9000.22uF
R234 10K
C895 22uF
TP110
C884 47uF
R244
0.001
R256100
TP116
R257100
J42
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
R789
649K
C167
0.22uF
R778 DNI
TP108
R7510
R804
100k
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
4A
2A
3.3V to FMC B VADJ converter
FMCBVADJOUT
PKEN
FMCBVADJ18,36,74,77
FMCBVADJPGood 35
FMCB_EN 35
A10_main_3V3 55
FMBDAC_P 73
FMBDAC_N 73
FMBSENSP73
FMBSENSN73
FMBVADJI_P71
FMBVADJI_N71
FMCBVADJ
A10_main_3V3
A10_main_3V3
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B67 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B67 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B67 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C829 47uF
TP107
C844 22uF
TP99
J32
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
C828 47uF
TP31
R200100
R215
DNI
R206100
C817 15nF
R720
137K
R205
DNI
C1191uF
C128
0.22uF
R739191K
C8450.22uF
R193 10K
R72515k
R730 DNI
R192 10K
R7460
C843 22uF
TP98
C80022pF
R194
0.001
R718
390K
U69EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQA
DJ
60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
PO
K50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
R733
5.49k
R717
649K
R729 10K
R719
240K
R716
976K
R747
100k
R7400
R726160k
TP106
R7240
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1A 1A
5A 5A
4A 4A
2.5V and 1.8V IO SwitchesIO_2V5 11,12,16,22,24,34,39,41,45
IO_EN35,73
IO_1V8
11,12,15,20,21,22,23,25,27,39,40,74,77
PLL_1V8 70,74,77
A10_1V8_EN35,73
2V535,53
A10_main_1V855
MAIN_12V49
2V5
PLL_1V8
A10_main_1V8
A10_main_1V8
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B68 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B68 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A2
Arria 10 SoC FPGA Development Kit Board
B68 78Tuesday, July 21, 2015
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
