8 7 6 5 4 3 2 1 REV SCHEMATIC,MLB - InformaticaNapoliK18_MLB 07/28/2009 DDR3 SO-DIMM Connector B 26...

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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPDCK

DESCRIPTION OF REVISION


SCHEMATIC,MLBPVT, 3/18/10

1 OF 80

051-8563

A.13.0

1 OF 109

2010-03-18

FireWire Constraints

Ethernet Constraints

MCP Constraints 2

K69_MLB 48 WELLSPRING 2

AUDIO: CODEC/REGULATOR

55

FSB/DDR3 Vref Margining

31

FireWire LLC/PHY (FW643E)

FireWire Port & PHY Power34

SATA Connectors

Internal USB Support

SecureDigital Card Reader

41

BOM Configuration

K69_MLB

T27_MLB

SCHEM,MLB_LDO,K6

08/27/2009

Thermal Sensors55

45 T27_MLB

09/30/2009

Current Sensing54

44 T27_MLB

08/27/2009

Voltage Sensing53

43 T27_MLB

08/21/2009

K6 SMBUS CONNECTIONS52

42 T27_MLB

08/27/2009

LPC+SPI Debug Connector51

41 T27_MLB

09/02/2009

SMC Support50

40 T27_MLB

09/02/2009

SMC49

39 T27_MLB

08/27/200948

38 T27_MLB

08/27/2009

External USB Connectors46

37 T27_MLB

08/06/200945

36 T27_MLB

07/28/2009

FireWire Connector43

35 T27_MLB

12/15/200942

T27_MLB

07/20/2009

33 T27_MLB

07/28/2009

Ethernet Connector40

32 T27_MLB

08/20/2009

Ethernet PHY (Caesar II/IV)39

T27_MLB

09/30/200935

30 T27_MLB

07/28/2009

RIGHT CLUTCH CONNECTOR34

29 T27_MLB

09/29/200933

28 T27_MLB

06/19/2009

DDR3 BYTE/BIT SWAPS-K632

27 K18_MLB

07/28/2009

DDR3 SO-DIMM Connector B31

26 T27_MLB

07/28/2009

DDR3 SO-DIMM Connector A29

25 T27_MLB

07/28/2009

SB Misc28

24 T27_MLB

08/06/2009

MCP Graphics Support26

23 T27_MLB

08/15/2009

MCP Standard Decoupling25

22 T27_MLB

11/23/2009

MCP89 GFX Core Rail Gating24

21 T27_MLB

11/23/2009

MCP89 Memory Rail Gating23

20 T27_MLB

08/06/2009

MCP Power & Ground20

19 T27_MLB

11/23/2009

MCP HDA, LPC & MISC19

18 T27_MLB

11/23/2009

MCP SATA, USB & Ethernet18

17

11/05/2009

MCP Graphics17

16 T27_MLB

11/05/2009

MCP PCIe Interfaces16

15 T27_MLB

08/06/2009

MCP Memory Interface15

14 T27_MLB

11/05/2009

MCP CPU Interface14

13 T27_MLB

07/28/2009

eXtended Debug Port (mini-XDP)13

12 T27_MLB

11/23/2009

CPU Decoupling12

11 T27_MLB

07/20/2009

CPU Power & Ground11

10 T27_MLB

08/27/2009

CPU FSB10

9 T27_MLB

07/20/2009

SIGNAL ALIAS9

8 K24_MLB

07/22/2009

Power Aliases8

7 K24_MLB

07/20/2009

FUNC TEST7

6 K24_MLB

07/20/2009

Revision History5

5 K24_MLB

07/20/20094

4 K24_MLB

08/19/2009

Power Block Diagram3

08/19/2009

System Block Diagram2

2 K69_MLB

109

T27_MLB

08/06/2009

K6/K69 PCB Rule Definitions80

108

T27_MLB

09/08/2009

K6/K69 Specific Constraints79

106

T27_MLB

07/28/2009

SMC Constraints78

105

T27_MLB

07/20/2009

77

104

T27_MLB

11/23/2009

76

103

T27_MLB

08/27/2009

75

102

T27_MLB

08/03/2009

MCP Constraints 174

101

T27_MLB

08/03/2009

Memory Constraints73

100

T27_MLB

08/03/2009

CPU/FSB Constraints72

98

T27_MLB

07/28/2009

LCD Backlight Support71

97 08/27/2009

LCD Backlight Driver70

94

K24_MLB

07/20/2009

DisplayPort Connector69

93

K69_MLB

08/12/2009

DISPLAYPORT SUPPORT68

90

K24_MLB

07/20/2009

LVDS CONNECTOR67

79

T27_MLB

08/27/2009

Power FETs66

78

T27_MLB

11/24/2009

Power Sequencing65

77

T27_MLB

09/30/2009

Misc Power Supplies64

76

K24_MLB

07/20/2009

CPU VTT(1.05V) SUPPLY63

75

T27_MLB

08/18/2009

MCP VCore Regulator62

74

K24_MLB

07/20/2009

IMVP6 CPU VCore Regulator61

73

T27_MLB

08/06/2009

1.5V/1.35V LVDDR3 Supply60

72

K24_MLB

07/20/2009

5V/3.3V SUPPLY59

70

T27_MLB

07/29/2009

PBus Supply & Battery Charger58

69

K24_MLB

07/20/2009

DC-In & Battery Connectors57

68

AUDIO

08/27/2009

AUDIO: JACK TRANSLATORS56

67

AUDIO

08/25/2009

AUDIO: JACK

66

AUDIO

07/17/2009

AUDI0: SPEAKER AMP54

65

AUDIO

07/17/2009

AUDIO: HEADPHONE FILTER53

63

AUDIO

07/17/2009

AUDIO: LINE INPUT FILTER52

62

AUDIO

08/31/2009

51

61

T27_MLB

10/21/2009

SPI ROM50

59

T27_MLB

07/20/2009

Sudden Motion Sensor (SMS)49

58

T27_MLB

08/03/2009

57

T27_MLB

08/15/2009

WELLSPRING 147

56

K24_MLB

07/20/2009

Fan4605/20/2009

Table of Contents1

1 K17_MLB

SyncContents(.csa) Date

Page Contents(.csa) Date

SyncPage

3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:


36

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DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

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2 1


Apple Inc.

PAGE


A

B

C

345678

D

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8 7 5 4 2 1

PG 17

USB

(UP TO 12 DEVICES)

6

J1300

J6750,6700

PG 56

U6633, U6623, U6613

PG 55PG 53

Mic

U6880

PG 54

Filter

PG 53

Filter

PG 52

Amps

PG 15

DISPLAY PORT

J3401

AIR PORT

PG 29

PG 70

J9400

J4501

PG 38

PG 68

PG 29 PG 32

J4000

E-NET

E-NET

BMC5764M

U3900

PG 18

PG 15,18

PG 17

PG 16

MAC

PG 18

PG 18

PG 12

ConnectorsPG 37PG 29

IR PG 38PG 47 PG30 PG38

7

USB EXTERNAL

J4600, J4610

810

RGB OUT

11

9

HDMI OUT

Card reader

J4890

Blue Ray dec KEYBOARD

J3500U5701J3401 J4890

PG 29

LPC+SPI Conn

PG 46

PG 46

J5601

PG 50

U5535,U5515

PG 45

PG 58,59

J6950,U7000

DC/BATT

Conns

Line In HEADPHONE

Amp

Audio

PG 18

PG 18

DDR3-1067/1333MHZMEMORY

1067/1333 MHz

PG 10

XDP CONN

J1300

PENRYNPG 12

64-Bit

2.X OR 3.X GHZ

INTEL CPU

U1000

PG 9

2 UDIMMs

J9000

CONN

LVDS

CONN

Conn

4

TMDS OUT

2

CLK

SATA

PCI

LPC

3

SATA

Audio

Codec

FSB

POWER SUPPLY

Conn

PG 31

GB Speaker

HD

ODD

Conn

SYNTH

SPI

PG 18

MAIN

J2900

DIMM

PG 25,26

J5100SerFanADCB,0 BSB

PWR

Misc

PG 14

GPIOs

1.05V/3GHZ.

1.05V/3GHZ.

PG 38

FSB INTERFACE

SMB

HDA

NVIDIA

SMB

10

5

U1400

DVI OUT

PCI-E

UP TO 20 LANES3

PG 17

LVDS OUT

DP OUT

AirPort

CONN

SATAJ4500

MCP

U6100

SMC

PG 39

SPI

U4900

Boot ROM

Prt

PG 51 FAN CONN AND CONTROL

POWER SENSE

CPU,MCP,TEMP SENSOR

CAMERA TRACKPAD/ Bluetooth

CTRLJ3401

J3401

PCI-E

U6201

SYNC_MASTER=K69_MLB SYNC_DATE=08/19/2009

System Block Diagram

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D

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8 7 5 4 2 1

MAX8840

PP1V05_S0_MCP_PLL_REG

MCP89

POWER SYSTEM ARCHITECTURE

CHGR_BGATE

BATTERY CHARGER

DELAY

RC

DELAY

RC

DELAY

DELAY

RC

RC P1V8S0_EN

MCPCORES0_EN

CPUVTTS0_EN

P1V5S0_EN

DDRVTT_EN

16-5

16-6

PM_SLP_S3_L

16-3

16-4

AP_PWR_ENQ7890

(9 TO 12.6V)

3S2P

PM_SLP_S3_L

U1400

PM_SLP_S4_L

MCP89 11

15

DELAYRC

11-2

RCDELAY

11-3

11-1

J6950

SMC_ADAPTER_EN

PM_SLP_S3_L

SMC_DCIN_ISENSE

PBUSVSENSE_EN

PPVBAT_G3H_CONN

P5VS0_EN

DELAY

PM_WLAN_EN_L

Q7890,Q7891

RC P3V3S0_EN

(S0)

(S0)

16-2

16-1

16-1

16

04-1

=DDRREG_EN

=DDTVTT_ENS5

S3

U7300

MCPCORES0_EN

VOUT2

TPS51116

0.75V

VOUT1

02

VIN

14

EN

VIN

02

1.5V

P5VS3_EN_L

P3V3S3_EN

DDRREG_EN

BKLT_EN

U4900

SMC

Q7055

PBUS SUPPLY/

ISL6259U7000

P60

P16

PPVBAT_G3H_CHGR_R

ENA

VIN

02

LP8545U9701

(S5)

04SMC_PM_G2_EN

VOUT

U7840

01

PPBUS_G3H

AR7020

ADAPTERAC

IN

DCIN(16.5V)

F69056A FUSE

01

A VINENABLES

(S5)CHGR_EN

PP18V5_DCIN_CONN

VOUT

PPVBAT_G3H_CHGR_REG

R7050

Q7085

Q7080

P3V3S5_EN_L

PPVOUT_SW_LCDBKLT

MCP_CORE

ISL9563A

MCPDDROUT

Q7930

SMC_BATT_ISENSE

P5VS3_EN_L

IMVP_VR_ON_R

25

02

U7500

8A FUSE

F7040

VOUT

(1A MAX CURRENT)PP0V75_S0_REG

(25A MAX CURRENT)

PPMCPCORE_S0_R

(12A MAX CURRENT)

20

PP1V5_S3_REG

EN

U7750ISL8009B

PP1V5R1V35_SW_MCP

VIN

21

VOUT

R7525

PP0V9_S5_REG

PPMCPCORE_S0_REG

P3V3S0_EN

Q7930

U7720

ST1S12G12R1.2V

U7710

ISL8009B

U7740

1.8VTPS62202

U7760

1.5V

EN2

05

VINEN1

02

3.3V

TPS51125

P5V3V3_PGOOD

PGOOD1,2

U7201

(RT)5V

VREG3

(5.5A MAXVOUT2

VOUT1

VR_ON

U7100

VIN

PGOOD

ISL9504B

VOUT

CPU VCORE

SMC_CPU_ISENSE

PP3V3_S5_REG

PP5V_S3_REG(13A MAX CURRENT)

VR_PWRGOOD_DELAY

CURRENT)

P3V3S3_EN

Q7910

28

V

PGOOD

PPVCORE_S0_CPU

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

PP1V2_ENET_REG

PP3V3_S0_FET

PP1V8_S0_REG

1.05V

PP1V5_S0_REG

(44A MAX CURRENT)

TPS7470

PP3V3_S0

PP1V5_S0

PP1V05_S0 V3

V2

V1

RST*

ISL88042

U7870

18

S0PGOOD_RST_LMCPPLLDO_PGOOD

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

SLP_S5_L

SLP_S4_L

SLP_S3_L

09

ALL_SYS_PWRGD

05

SMC_ONOFF_L

RSMRST_PWRGD

SLP_S4_L(P94)

SLP_S3_L(P93)

SLP_S5_L(P95)

U4900

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

99ms DLY

Q3450

PP3V3_S3_FET

P3V3ENET_EN_L

P3V3_S3_WLAN

26

VIN

ENU6200

VOUT

4.5V AUDIO

PP4V5_AUDIO_ANALOG

13

24

07

17

Q7940

P5VS0_EN

PP5V_S0_FET

SMC

U2850

29

MCP_PS_PWRGD

U1000

CPU

U1400

PWRGD

PPBUS_G3H

PPDCIN_G3H_OR_PBUS

(S0)

VPBUS_VSENSE

02

CPUVTTS0_EN

Q5315

02

CPUVTT(1.05V)

TPS51117U7600

EN_PSV VOUT

VIN

LT3470

ENABLE

U6990VOUT

3.425V G3HOT

PBUS_G3H_VSENSE

PP1V05_S0

(8A MAX CURRENT)

PP3V42_G3H_REG 03RN5VD30A-F

SMC PWRGD

U5010

04

RST*

P17(BTN_OUT)

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

PLT_RST*

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

PWRGOOD

RSMRST*

IMVP_VR_ON_R

PM_PWRBTN_L

SMC_RESET_L

25

PM_RSMRST_L

32

10

FSB_CPURST_L

30

CPU_PWRGD

LPC_RESET_L

31

06-1

Power Block DiagramSYNC_MASTER=K69_MLB SYNC_DATE=08/19/2009

3 OF 109

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD


TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM




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TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Top

GROUND

SIGNAL(High Speed)

Bar Code Labels / EEE #’s

POWER

SIGNAL(High Speed)

11

POWER

10

9

8 GROUND

6

5

4

3

2

GROUND

SIGNAL

SIGNAL(High Speed)

SIGNAL(High Speed)

K6 BOARD STACK-UP

Module Parts

BOM Variants

SIGNAL

GROUND

7

Alternate Parts

DEVELOPMENT BOM

BOTTOM

BOM Groups

Programmable Parts

SYNC_MASTER=K24_MLB

BOM Configuration

152S0778152S0693 CYNTEC AS ALTERNATEALL

152S0685152S0796 CYNTEC AS ALTERNATEALL

157S0055157S0058 DELTA AS ALTERNATEALL

152S0874 152S0516 MAGLAYERS AS ALTERNATEALL

152S1024 ALL152S1025 TOKO AS ALTERNATE

337S3769 ALL

ALL516S0790 MOLEX AS ALTERNATE

516-0201 ALL

152S1135 ALL

152S0586152S0847 ALL MAGLAYERS AS ALTERNATE

128S0218128S0093 ALL KEMET AS ALTERNATE

104S0023104S0018 DALE/VISHAY AS ALTERNATEALL

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 CRITICALU5701337S2983 WELLSPRING:BLANK1

IC,ENCORE II,CY7C63803-LQXC CRITICAL IR:PROG341S2384 1 U4800

U5701 CRITICAL WELLSPRING:PROG1341S2616 IC,TP PSOC,K17,K18

CRITICALU4800338S0633 IR:BLANK1

U6100EFI UNLOCKED,K6/K691341T0238 BOOTROM:UNLOCKEDCRITICAL

IC,EFI,LOCKED,K6341S2589 BOOTROM:LOCKEDCRITICAL1 U6100

U6100IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP335S0610 CRITICAL BOOTROM:BLANK1

SMC EXTERNAL,K61 U4900 CRITICAL SMC:PROG341T0240

SMC:BLANK1 U4900IC,SMC,HS8/2117,9X9MM,TLP,HF

IC,LP8545,LED BKLT CTRLR,LLP241353S2896 U9701 CRITICAL

U3900IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN1 CRITICAL343S0493 BCM5764M

PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA337S3761 1 CRITICALU1000 CPU:2.66GHZ

CPU:2.4GHZPDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA337S3680 U10001

CPU:2.26GHZPDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550 U1000337S3769 1

K6_DEBUG:PVT

K6_DEBUG:ENG

LPCPLUS,XDP_CONNK6_DEVEL:PVT

K6_DEVEL:ENG

K6_PROGPARTS

K6_DEBUG:PROD

K6_COMMON

K6_MISC

PCBA,MLB_LDO,BETTER,K6

PCBA,MLB_LDO,BEST,K6

085-1634 K6_DEVEL:PVT

U10001337S3756 CPU:2.53GHZPDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA

MCP89M:A011337S3797 CRITICALIC,MCP89M-A01,31X31MM,BGA1168 U1400

U39901 BCM5764MCRITICAL341S2731 IC,1MBIT,SPI FLASH,K17/18

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12338S0753 1 U4100 CRITICAL

[EEEE_DD23] EEEE:DD23CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM1826-4393

[EEEE_DD24] EEEE:DD24CRITICAL1826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL1337S3866 MCP89M:A02IC,MCP89M-A01,31X31MM,BGA1168 U1400

DEVEL_BOMCRITICALDEVEL1085-1634 K6 MLB_LDO DEVELOPMENT BOM

CRITICAL

639-1120

639-1119

DEVEL_BOM,SMC_DEBUG:YES,XDP

CRITICAL

CRITICAL

CRITICAL

K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23

K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24

COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15

BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG

DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V

K6 MLB_LDO DEVELOPMENT BOM

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN

338S0563

516-0213

516S0706

MOLEX AS ALTERNATE

TOKO AS ALTERNATE

INTEL P7550 CPU AS ALTERNATE

152S0586

337S3704

ALL SSM6P15FE AS ALTERNATE376S0360376S0699

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DRAWING


Schematic / PCB #’s

LAST_MODIFIED=Thu Mar 18 17:53:39 2010

SCHEM,MLB_LDO,K6051-8563 SCH1 CRITICAL

TITLE=MLBABBREV=DRAWING

PCBF,MLB_LDO,K6820-2879 1 CRITICALPCB




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8 7 5 4 2 1NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

Revision History

Revision History

SYNC_MASTER=K24_MLB

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(NEED TO ADD 6 GND TP)

(NEED 3 TP)

KBD BACKLIGHT CONN


(NEED 4 TP)


(NEED 3 TP)

BATT POWER CONN

(NEED TO ADD 4 GND TP)(NEED TO ADD 5 GND TP)


T57 CONN


RIGHT CLUTCH CONN


IPD_FLEX_CONN

(NEED 3 TP)


BIL CONN

SATA HDD/IR/SIL

SATA ODD CONN

SPEAKER FUNC_TEST

LVDS FUNC_TEST


(NEED 2 TP)

Fan ConnectorsDEBUG VOLTAGE


Functional Test Points

KEYBOARD CONN

DC POWER CONN


FSB SIGNALS WITH NOTEST


MIC FUNC_TEST

(NEED 2 TP)

SPI DEBUG CONN

I12

I15

I16

I226

I227

I228

I229

I230

I231

I237

I238

I239

I245

I246

I247

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I250

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I312I313

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FUNC TEST

SYNC_MASTER=K24_MLB

FSB_REQ_LNO_TEST=TRUE

NO_TEST=TRUE FSB_LOCK_L

NO_TEST=TRUE FSB_DSTB_L_PNO_TEST=TRUE FSB_DSTB_L_N

TRUE PM_SLP_S4_LSMC_PM_G2_ENTRUEPP1V5R1V35_S3TRUE

PP4V5_AUDIO_ANALOGTRUE

PP3V3_S0_LCD_FTRUEPP3V3_LCDVDD_SW_FTRUE

PP18V5_S3TRUETRUE PP5V_S0_HDD_FLT

TRUE PPBUS_G3HTRUE PP3V42_G3H

TRUE PP1V5_S0

TRUE PP3V3_S3

TRUE WS_KBD3

TRUE WS_KBD6WS_KBD7TRUE

TRUE PCIE_AP_D2R_N

PCIE_CLK100M_AP_CONN_PTRUE

TRUE USB_CAMERA_CONN_P

USB_BT_CONN_NTRUE

AP_RESET_CONN_LTRUE

TRUE PP3V3_S3

TRUE PP18V5_S3

TRUE Z2_CS_L

TRUE Z2_DEBUG3

TRUE Z2_RESET

TRUE SMBUS_SMC_A_S3_SDA

TRUE PP5V_WLANTRUE PP3V3_ENET

SPI_CLKTRUETRUE SPI_MOSI

TRUE PP5V_S0

TRUE FAN_RT_PWMFAN_RT_TACHTRUE

TRUE WS_KBD2

TRUE SPIROM_USE_MLBTRUE SPI_MISO

TRUE PP5V_SW_ODD

PP5V_WLANTRUE

TRUE WS_KBD1

TRUE PSOC_SCLK

TRUE Z2_CLKINZ2_HOST_INTNTRUE

TRUE Z2_SCLKZ2_MISOTRUEZ2_MOSITRUE

TRUE Z2_BOOST_EN

TRUE PSOC_F_CS_L

WS_KBD11TRUE

TRUE WS_KBD13

TRUE WS_KBD4TRUE WS_KBD5

TRUE PP3V3_S5

TRUE PP5V_S3PP0V9_S5TRUE

PP3V3_S3TRUE

TRUE PP1V8_S0PP3V3_S0TRUE

WS_KBD_ONOFF_LTRUE

PP1V05_S0TRUE

WS_KBD20TRUE

WS_KBD22TRUE

WS_KBD18TRUE

TRUE BI_MIC_LO

TRUE WS_KBD14

TRUE WS_KBD16_NUMWS_KBD15_CAPTRUE

WS_KBD17TRUE

IR_RX_OUTTRUE

TRUE WS_LEFT_OPTION_KBD

WS_KBD21TRUE

TRUE SPKRAMP_R_N_OUT

TRUE SPKRAMP_L_N_OUT

TRUE BI_MIC_HIBI_MIC_SHIELDTRUE

PP5V_SW_ODDTRUE

SATA_HDD_D2R_C_PTRUE

SMC_ODD_DETECTTRUETRUE SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_NTRUE

SATA_ODD_R2D_NTRUE

PP5V_S0_HDD_FLTTRUE

SATA_HDD_R2D_NTRUE

SATA_HDD_D2R_C_NTRUE

PP5V_S3_IR_RTRUE

WS_LEFT_SHIFT_KBDTRUE

TRUE WS_KBD23

WS_KBD19TRUE

TRUE PCIE_WAKE_L

TRUE SPKRAMP_SUB_P_OUTSPKRAMP_SUB_N_OUTTRUE

SPKRAMP_R_P_OUTTRUE

LVDS_IG_A_DATA_PTRUE

SYS_DETECT_LTRUE

SMBUS_SMC_BSA_SCLTRUE

TRUE PP3V3_LCDVDD_SW_F

TRUE LED_RETURN_1

TRUE SMBUS_SMC_A_S3_SDA

WS_CONTROL_KBDTRUE

TRUE LVDS_IG_A_DATA_N

TRUE LVDS_CONN_A_CLK_F_P

USB_T57_PTRUE

TRUE T57_RESET

PP5V_S3_BTCAMERA_FTRUE

TRUE SPKRAMP_L_P_OUT

TRUE SMBUS_SMC_A_S3_SCL

PCIE_AP_D2R_PTRUE

TRUE PPVCORE_S0_CPU

PCIE_AP_R2D_PTRUEPCIE_AP_R2D_NTRUE

PPVCORE_S0_MCPTRUEPP1V2_ENETTRUE

PP5V_S0TRUE

TRUE LVDS_CONN_A_CLK_F_NTRUE LVDS_IG_A_DATA_P

LVDS_IG_A_DATA_NTRUE

LVDS_DDC_CLKTRUE

BKL_VSYNCTRUETRUE PPVOUT_SW_LCDBKLTTRUE PP3V3_S0_LCD_F

TRUE LVDS_IG_A_DATA_P

LVDS_DDC_DATATRUE

TRUE BKL_ISEN2

TRUE Z2_KEY_ACT_L

TRUE PP5V_S3

TRUE T57_PWR_ENTRUE PP3V3_S3

TRUE PICKB_L

TRUE PSOC_MISO

TRUE PSOC_MOSI

TRUE SMBUS_SMC_A_S3_SCL

USB_T57_NTRUE

PPVBAT_G3H_CONNTRUE

SMBUS_SMC_BSA_SDATRUE

SMC_LID_RTRUE

SMC_BIL_BUTTON_LTRUE

SMBUS_SMC_BSA_SDATRUESMBUS_SMC_BSA_SCLTRUE

PP3V42_G3HTRUE

TRUE PCIE_CLK100M_AP_CONN_N

TRUE USB_CAMERA_CONN_N

TRUE USB_BT_CONN_P

TRUE AP_CLKREQ_Q_L

LVDS_IG_A_DATA_NTRUE

SYS_LED_ANODE_RTRUE

SATA_HDD_R2D_PTRUE

TRUE SATA_ODD_R2D_P

TRUE PP3V42_G3H

TRUE BKL_ISEN3LED_RETURN_4TRUELED_RETURN_5TRUE

TRUE LED_RETURN_6

WS_KBD12TRUE

KBDLED_ANODETRUE

SMC_KDBLED_PRESENT_LTRUE

TRUE SPI_CS0_L

WS_KBD10TRUETRUE WS_KBD9TRUE WS_KBD8

TRUE PP3V42_G3H

TRUE PM_SLP_S3_L

TRUE PP18V5_DCIN_FUSE

TRUE ADAPTER_SENSE

FSB_HITM_LNO_TEST=TRUE

FSB_HIT_LNO_TEST=TRUE

NO_TEST=TRUE FSB_DINV_LNO_TEST=TRUE FSB_D_LNO_TEST=TRUE FSB_ADSTB_L

FSB_ADS_LNO_TEST=TRUE

NO_TEST=TRUE FSB_A_L

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9 13 72




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(CPU VCORE PWR)

"S0,S0M" RAILS

(MCP VCORE AFTER SENSE RES)

700 mA max output

"FIREWIRE" RAILS

"S5" RAILS

(BEFORE HIGH SIDE SENSING RES.)

139 mA/ 0 mA

105 mA/241 mA

LVDDR VRef/VTT (0.75V/0.675V) Rails

"ENET" RAILS

(SINCE PE0[3:0] IS NOT USED ON K6)

"S3" RAILSLVDDR (1.5V/1.35V) Rails

4250 mA

(CONNECTS TO MCP BALLS)

& CPU VTT SENSING RES.)

(AFTER HIGH SIDE CPU VCORE

0.9V Rails

(BCM5764M)

"G3H" RAILS

(OR 1.35V)

0 mA

~400mA

(CONNECTS TO MCP BALLS)

(BCM57765)

(CONNECTS TO THE DECAPS)

UNUSED MCP PE0[3:0] AVDD/DVDD

(CONNECTS TO THE DECAPS)

400mA

~100mA

300mA

I1086

Power Aliases

SYNC_MASTER=K24_MLB SYNC_DATE=07/22/2009

=PP3V3_S0_OPA333

=PP3V3_S0_XDP

=PP3V3_S0_MCP

=PP3V3_S0_IMVP

=PP3V3_S0_CPUTHMSNS

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm

PP1V05_S0_MCP_PLL_UF

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mmPP1V2_ENET

MAKE_BASE=TRUE

=PP1V2_ENET_PHY

=PP3V3_ENET_FET_R

=PP3V3_ENET_MCP_RMGT

MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.8VMAKE_BASE=TRUE


PP1V8_S0

=PP0V9_ENET_MCP_RMGT

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_S5_REG

=PP3V3_S5_P0V9S5

=PP3V3_S5_ROM

=PP3V3_S5_LCD

=PP5V_S3_T57

=PP5V_S0_CPU_IMVP

=PPVCORE_S0_MCPGFXFET

=PPVCORE_S0_MCP

=PP5V_S3_WLAN

=PP5V_S3_TPAD

=PP5V_S3_SYSLED

=PP3V3_S3_SMBUS_SMC_A_S3

=PPVCORE_S0_CPU

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_SW_MCP_FSB

=PP1V05_S0_MCP_M2CLK_DLL

=PPLVDDR_S3_MEM_B

=PP1V05_FW_P1V0FWFET

=PP1V05_S0_MCP_PLL_UF_R

=PP1V5_S0_REG

=PP1V05_S0_MCP_DP0_VDD

=PP1V05_S0_FWPWRCTL

=PP1V05_S0_MCP_PLL_IFP

=PPBUS_S5_CPUREGS_ISNS_R

=PP1V05_S0_MCP_PE_AVDD0

=PP1V8_S0_AUDIO

=PP1V2_ENET_PHY_REG

=PP1V05_S0_MCP_PE_DVDD

=PP1V05_S0_MCP_PLL_UF

=PP3V3_S3_PDCISENS

=PPVIN_S0_CPUVTTS0

=PP1V5R1V35_S0_MCPDDRFET

=PPVIN_S0_DDRREG_LDO

=PPVIN_S5_3V3S5

=PPVIN_S3_5VS3

=PPDCIN_S5_CHGR

=PPVP_FW_PHY_CPS_FET

=PP1V2_ENET_REG

=PP1V5R1V35_S3_MCP_MEM

=PP3V42_G3H_REG

=PPLVDDR_S3_MEM_A

=PPBUS_FW_FET

=PPBUS_S5_CPUREGS_ISNS

=PPVIN_S5_CPU_IMVP

=PP1V0_FW_FET_R

=PP3V3_FW_FWPHY

=PPVP_FW_PORT1

=PP3V42_G3H_BMON_ISNS

=PPDDR_S3_REG

=PP3V3_S5_P3V3S0FET

=PP0V9_ENET_FET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PPBUS_S0_LCDBKLT

=PPBUS_G3H

=PP5V_S3_REG

=PP0V9_S5_REG

=PP0V9_ENET_P0V9ENETFET

=PP0V9_S5_MCP_VDD_AUXC

=PP1V0_FW_FWPHY

=PP5V_S3_BTCAMERA

=PP3V3_FW_FET

=PP1V05_S0_MCP_PLL_OR

=PPMCPCORE_S0_REG

=PP5V_S3_MCPDDRFET

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_P3V3FWFET

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_MCP

=PP1V05_S0_MCP_PE_DVDD0

=PP1V05_S0_MCP_PE_DVDD

=PPVTT_S0_DDR_LDO

=PPDDRVTT_S0_MEM_A

=PP1V8_S0_REG

=PPVTT_S3_DDR_BUF

=PP3V3_S3_FET

=PP5V_S0_FET

MIN_NECK_WIDTH=0.3 MMMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEVOLTAGE=12.6V

PPBUS_S5_IMVP_VTT_ISNS

VOLTAGE=1.5VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP1V5R1V35_S3

PPVP_FWMIN_LINE_WIDTH=0.4 mm


MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_FW

VOLTAGE=3.3V


PP1V05_FW


MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

PPDDRVREF_S3

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm

PP1V05_S0_MCP_PE_AVDDMAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 mm


PP0V9_S5MIN_LINE_WIDTH=0.4 mm

=PP3V3_S0_TPAD

=PP18V5_DCIN_CONN

=PP5V_S3_IR

=PP5V_S3_DDRREG


PP3V3_ENET

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_ENET_PHY

=PP3V3_ENET_PWRCTL

=PP5V_S3_AUDIO

=PP3V3_S0_P1V5S0

=PP3V3_S0_DEBUGROM

=PP3V3_S0_DPCONN

=PPSPD_S0_MEM_A

=PP3V3_S0_CPUVTTISNS

=PP3V3_S0_FWLATEVG

=PPDDRVTT_S0_MEM_B

PPDDRVTT_S0

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MM


=PP3V3_S0_PWRCTL

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD

=PP3V3_S0_SMC

=PP3V3_S0_MCPTHMSNS

=PP1V5_S0_SATARDRVR

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_CPU

=PP1V5_S0_MCP_PLL_VLDO

MAKE_BASE=TRUE

PP1V5_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.5V

=PP1V5_S0_MCP_HDA_R

=PP3V3_S0_MCPCOREISNS

=PP1V5_S0_AUDIO_R

=PP3V3_S0_MCP_HDA_R

=PP3V3_S0_ENETPHY

=PP3V3_S0_ODD

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_P1V8S0

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_SMBUS_MCP_0 MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.3 MM

PPBUS_G3HMIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

=PP3V42_G3H_BATT

=PP3V42_G3H_TPAD

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_ONEWIRE

=PPVIN_S0_MCPCORE

=PPVIN_S3_DDRREG

=PPBUS_S5_FWPWRSW

=PP5V_S3_AUDIO_AMP

=PP5V_S3_P5VS0FET

=PP5V_S0_ODD

=PP3V3_S5_MCP_GPIO

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_VMON

=PP3V3_S5_SMBUS_SMC_MGMT

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_LCD=PP5V_S3_RTUSB

PP5V_S3

VOLTAGE=5VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP3V3_S5

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V


MAKE_BASE=TRUE

=PP3V3_S3_VREFMRGN

=PP3V3_S3_WLAN

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_TPAD

=PP3V3_S3_SMS

=PP3V3_S3_CARDREADER

=PP3V3_S3_T57

=PP3V3_ENET_P1V2ENET

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_SMC_0_S0

=PPSPD_S0_MEM_B

=PP3V3_S0_AUDIO_R

=PP3V3_S0_SDCONN

=PP3V3_S0_FWPWRCTL

=PP5V_S0_HDD

=PP5V_S0_KBDLED

=PP5VR3V3_S0_DPCADET

=PP5V_S0_CPUVTTS0

=PP5V_S0_MCPREG

=PP5V_S0_MCPFSBFET

=PP3V3_S0_AUDIO

=PP3V3_S0_FAN_RT

MAKE_BASE=TRUE

PP3V3_S0

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

=PP3V3_S0_FET

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

PPVCORE_S0_MCP

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMAKE_BASE=TRUE


PPVCORE_S0_CPU

MAKE_BASE=TRUE


VOLTAGE=1.25V

=PPVCORE_S0_CPU_REG

=PPCPUVTT_S0_REG

MAKE_BASE=TRUE



VOLTAGE=1.05V

=PP1V05_S0_CPU

=PP1V05_S0_MCP_PE_DVDD1

=PP1V05_S0_MCP_PE_AVDD1



PP0V9_ENETMIN_LINE_WIDTH=0.4 mm

=PP5V_S0_LPCPLUS

=PP5V_S0_FAN_RT

=PP5V_S0_BKL

PP5V_S0


MAKE_BASE=TRUEVOLTAGE=5V

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PPVIN_S5_SMCVREF

=PP3V3_S5_LPCPLUS

=PP3V3_S5_SMC

=PP3V42_G3H_CHGR

PP3V3_G3_RTC

PP3V42_G3H



=PP3V42_G3H_OPA330

PPDCIN_S5_S5MIN_LINE_WIDTH=0.6 MM

VOLTAGE=18.5VMIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

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42

40

41

39 40

58 65

18 19 22

6

22

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUTIN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DISPLAY PORT ALIASES

AUDIO ALIASES

MCPCOREISNS SIGNAL

LEFT OF CPU

BACKLIGHT CONTROLLER ALIASES

5V ODD ALIASES

BELOW CPU

CPU ALIASES

266

UNUSED GPU LANES

BELOW MCP

ABOVE CPU

FAN STANDOFF

PCI-E ALIASES

EMI TALL POGO PINS

FSB MHZ

200133

BSEL

0 0 10 0 0

(RSVD)

100(400)1 1 0

1 0 11 0 0 333

0 1 00 1 1 (166)

USB ALIASES

1 1 1

EMI IO (SHORT) POGO PINS

MCP89 ALIASES

UNUSED USB PORTS

MLB MOUNTING (TO TOPCASE) SCREW HOLES

HEATSINK STANDOFFS

ETHERNET ALIASES

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

DACS ALIASES

LVDS ALIASES

UNUSED CRT & TV-OUT INTERFACE

CHARGER SIGNAL

17 76

17 76

17 76

17 76

17 76

17 76

17 76

17

5%10K

1/16WMF-LF

R0984

402

MF-LF402

10K5%1/16W

R0983R0982

MF-LF1/16W

5%10K

402

R098110K

402

5%1/16WMF-LF

R0980

MF-LF1/16W

5%

402

10K

39 40 57 58

PLACE_NEAR=L9701.1:5MM

402MF-LF

5%

0R0910

1/16W

100K

R0920

1/16WMF-LF5%402

R09110

5%

MF-LF1/16W

402

PLACE_NEAR=U7980.A1:5MM

7

HDA:1.5V

402

0

5% MF-LF1/16W

R0912

402 5% MF-LF

0

1/16W

HDA:3.3V

R0913

0

402 5%1/16W MF-LF

HDA:1.5V

R0914HDA:3.3V

402 1/16W MF-LF

0

5%

R0915

402MF-LF1/16W

10K5%

R0986NO STUFF

18 31

OMIT

3R2P5Z0912

3R2P5Z0909OMIT

OMITZ09113R2P5

OMITZ09083R2P5

STDOFF-4.5OD.98H-1.1-3.48-THZ0901

Z0904STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-THZ0903

STDOFF-4.5OD.98H-1.1-3.48-THZ0905

3R2P5

OMITZ0910

SM

ZS09052.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

2.0DIA-TALL-EMI-MLB-M97-M982.0DIA-TALL-EMI-MLB-M97-M98ZS0904

SM

2.0DIA-TALL-EMI-MLB-M97-M98ZS0907

SM

Z09073R2P5

OMITOMIT

3R2P5Z0906

1.4DIA-SHORT-EMI-MLB-K19-K24ZS0900

SM SM1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0901 ZS09021.4DIA-SHORT-EMI-MLB-K19-K24

SM

1.4DIA-SHORT-EMI-MLB-K19-K24SM

ZS0903 ZS09081.4DIA-SHORT-EMI-MLB-K19-K24

SM SM1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0909

SIGNAL ALIAS

SYNC_MASTER=K24_MLB

ENET_RXD

ENET_RX_CTRL

ENET_RXD_PDMAKE_BASE=TRUE

DP_EXT_HPDMAKE_BASE=TRUE

DP_IG_HPD0

DP_IG_ML0_N

DP_IG_ML0_P

DP_IG_AUX_CH0_P

DP_IG_AUX_CH0_N

=MCP_IFPAB_DDC_CLK

LCD_IG_BKLT_PWM

=MCP_IFPB_TXD_N

=MCP_IFPA_TXD_N

=MCP_IFPA_TXC_N

CRT_IG_HSYNC

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

MCP_TV_DAC_RSET

CRT_IG_R_C_PR

MAKE_BASE=TRUENO_TEST=TRUE

NC_CRT_IG_HSYNC

=MCP_IFPA_TXD_N

=MCP_IFPB_TXC_P

=MCP_IFPAB_DDC_DATA

DP_IG_ML1_N

DP_IG_AUX_CH1_P

DP_IG_AUX_CH1_N

TP_DP_IG_AUX_CH1PMAKE_BASE=TRUE

TP_DP_IG_ML1PMAKE_BASE=TRUE

DP_CA_DET

DP_AUX_CH_C_P

LCD_IG_BKLT_EN

=MCP_IFPB_TXC_N

TP_PEG_CLKREQ_LMAKE_BASE=TRUE

=PP3V3_ENET_FET_R

TP_DP_IG_AUX_CH1NMAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_P

DP_IG_AUX_CH_NMAKE_BASE=TRUE

USB_EXTC_N

TP_MCP_RGB_RED

TP_MCP_RGB_GREEN

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_DAC_RSET

PPBUS_SW_LCDBKLT_PWR

USB_EXTD_P

TP_MCP_RGB_VSYNC

=PP5V_SW_ODD_FET

TP_MCP_RGB_DAC_VREF

CPU_PECI_MCP

MCP_CLK27M_XTALOUT=PEG_R2D_C_P

=PEG_D2R_P

=PEG_R2D_C_N

PEG_CLK100M_P

PEG_CLK100M_N

CRT_IG_VSYNC

USB_WM_NUSB_MINI_P

USB_EXTD_NUSB_WM_P

USB_EXTC_P

PEG_CLKREQ_L

CRT_IG_G_Y_Y

=PEG_D2R_N=MCP_BSEL

=PPBUS_SW_BKL

=PP5V_SW_ODD

=MCP_IFPA_TXD_P

=MCP_IFPA_TXC_P

=MCP_IFPA_TXD_P

=MCP_IFPB_TXD_P

CRT_IG_B_COMP_PB

NC_MCP_CLK27M_XTALINNO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_G_Y_YMAKE_BASE=TRUENO_TEST=TRUE

MAKE_BASE=TRUELVDS_IG_A_CLK_P

LVDS_IG_A_DATA_NMAKE_BASE=TRUE

NC_LVDS_IG_B_CLKPMAKE_BASE=TRUE

NO_TEST=TRUE

LCD_BKLT_PWMMAKE_BASE=TRUE

NC_LVDS_IG_B_DATANNO_TEST=TRUEMAKE_BASE=TRUE

NC_LVDS_IG_A_DATANMAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLKN NO_TEST=TRUEMAKE_BASE=TRUE

LCD_BKLT_ENMAKE_BASE=TRUE

MAKE_BASE=TRUENO_TEST=TRUENC_LVDS_IG_A_DATAP

NC_MCP_TV_DAC_VREFNO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NC_CRT_IG_R_C_PRNO_TEST=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUE

NC_MCP_RGB_RED

MAKE_BASE=TRUE

DP_IG_AUX_CH_P

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_N

DP_EXT_CA_DETMAKE_BASE=TRUE

DP_EXT_ML_PMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUE

NC_MCP_RGB_BLUE

NC_MCP_RGB_GREENMAKE_BASE=TRUE NO_TEST=TRUE

NC_PEG_R2D_C_PNO_TEST=TRUE MAKE_BASE=TRUE

TP_USB_WMPMAKE_BASE=TRUE

NC_MCP_TV_DAC_RSETMAKE_BASE=TRUENO_TEST=TRUE


NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_PEG_R2D_C_NNO_TEST=TRUE


NC_PEG_D2R_P

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

MAKE_BASE=TRUE

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_USB_WMN

MAKE_BASE=TRUE

TP_USB_MINIP

MAKE_BASE=TRUE

TP_USB_EXTDN

TP_USB_EXTCNMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_EXTCP

MAKE_BASE=TRUE

TP_USB_EXTDP

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNCNO_TEST=TRUE

NC_MCP_RGB_DAC_RSETNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUELVDS_IG_A_DATA_P

MAKE_BASE=TRUELVDS_IG_A_CLK_N

CPU_BSELMAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_DAC_VREFMAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_HSYNCMAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PEG_D2R_NNO_TEST=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

VOLTAGE=5VMIN_NECK_WIDTH=0.4 MMMIN_LINE_WIDTH=0.6 MM

PP5V_SW_ODDMAKE_BASE=TRUE

TP_DP_IG_ML1NMAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_ML_N

NC_LVDS_IG_B_DATAPMAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_DDC_CLKMAKE_BASE=TRUE

LVDS_DDC_DATAMAKE_BASE=TRUE

USB_MINI_N TP_USB_MININMAKE_BASE=TRUE

MAKE_BASE=TRUE

PPBUS_SW_BKLMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.375 MMVOLTAGE=12.6V

ENET_MDIO

ENET_RXD

ENET_RXD

MAKE_BASE=TRUEENET_RXCLK_PD ENET_CLK125M_RXCLK

=PP3V3_ENET_FET

ENET_RXD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V


PP3V3_ENET_FET

=MCPCOREISNS_P

=MCPCOREISNS_N

SMC_BC_ACOKMAKE_BASE=TRUE

MCPCOREISNS_NMAKE_BASE=TRUE

MCPCORES0_VO

MCPCOREISNS_PMAKE_BASE=TRUE

MCPCORES0_ISP_R

=CHGR_ACOK

DP_IG_HPD1

=PP3V3R1V5_S0_MCP_HDA

=PP3V3R1V5_S0_AUDIO

VOLTAGE=1.5VMAKE_BASE=TRUE MIN_LINE_WIDTH=0.6mm

MIN_NECK_WIDTH=0.2mm

PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_HDA_R

=PP1V5_S0_AUDIO_R

=PP3V3_S0_AUDIO_R

=PP1V5_S0_MCP_HDA_R

DP_IG_ML1_P

DP_AUX_CH_C_N

DP_IG_ML_N

DP_IG_ML_P


MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.6mm

PP3V3R1V5_S0_AUDIO

ENET_LOW_PWR

MCP_RGMII_VREF

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

9 OF 109

A.13.0

051-8563

8 OF 80

1

2

1

2

1

2

1

2

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

1

1

1

1

1

1

1

1

1

1 11 1

11

1 1 1

1 1 1

69 16

16

16

16

16

16

16

16

16

16

74

74

74

74

16

16

16

16

16

16

68

68

16

16

69 79

68 74

17 75

16

16

16

16

16

70 71

17 75

16

36

16

13

15

15

15

15 74

15 74

74

17 75

17 75

17 75

17 75

17 75

15

74

15

13

70

36

16

16

16

16

74

67 74

6 67 74

70

71

68 74

69 79

69

69 79

6 67 74

67 74

9 72

6

69 79

6 67

6 67

17 75

66

44

44 62

62

16

18 22

51

7

7

7

7

16

68

74

74

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

TEST7

TEST6

DSTBP1*

DINV1*

D31*

D30*

D25*

D11*

D12*

D13*

D14*

DSTBP0*

DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0* D32*

D1*

D2*

D5*

D16*

D20*

D21*

D22*

D23*

D24*

D26*

D27*

D28*

D29*

DSTBN1*

GTLREF

TEST3

TEST4

TEST5

BSEL0

BSEL1

BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3

DATA GRP 2

MISC

DATA GRP 0

DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3*

A4*

A14*

A16*

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*

A21*

A22*

A23*

A24*

A26*

A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5

RSVD6

RSVD7

RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CPU JTAG Support

R1023.1:

R1020.1:R1021.1:R1022.1:

PLACE_NEARs:

PLACE_NEARs:

R1006.1:C1014.1:

R1005.2:

R1000

402MF-LF1/16W

1%54.9

R1002

402MF-LF1/16W

5%68

R1005

U1000.AD26:12.7 mm402MF-LF1/16W1%1K

R1006

U1000.AD26:12.7 mm

402MF-LF1/16W1%2.0K

R1023

U1000.Y1:12.7 mm

54.91/16W

402MF-LF

1%

R1022

U1000.AA1:12.7 mm

402MF-LF1/16W1%27.4

R1021

U1000.U26:12.7 mm

402MF-LF1/16W

1%54.9

R1020

U1000.R26:12.7 mm

27.41/16W

402MF-LF

1%

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

13 61 72

13 72

13 72

13 72

61

12 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

8 72

8 72

8 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

6 13 72

13 72

13 72

13 72

13 72

13 72

13 72

6 13 72

6 13 72

6 13 72

12 72

12 72

12 72

12 72

12 72

12 72

9 12 72

12 24

13 40 61 72

45 79

13 40 72

13 72

12 13 72

13 72

13 72

13 72

13 72

9 12 72

9 12 72

9 12 72

9 12 72

45 79

13 72

13 72

13 72

13 72

13 72

13 72

13 72

13 72

13 72

R1010

1/16W

NO STUFF

0

MF-LF

5%

402R1011NO STUFF

402MF-LF1/16W

5%1K

R1001

402MF-LF1/16W

1%54.9

R109054.9

1/16WMF-LF

1%

402R109154.9

1/16WMF-LF

1%

402

R109354.9

1/16WMF-LF

1%

402

6 13 72

6 13 72

6 13 72

6 13 72

R1094649

1/16WMF-LF

1%

402

R1012NO STUFF

402MF-LF1/16W5%1K

C1014

16VX5R

U1000.AF26:12.7 mm

NO STUFF

10%

402

0.1uF

U1000

FCBGAPENRYN

OMIT

R1092

PLACE_NEAR=J1300.51:12.7 mm1/16WMF-LF

54.9

1%

402

U1000OMIT

PENRYNFCBGA

CPU FSBSYNC_MASTER=T27_MLB SYNC_DATE=08/27/2009

FSB_D_L

CPU_COMPCPU_COMPCPU_COMP

FSB_D_L

CPU_COMP

TP_CPU_RSVD_D3TP_CPU_RSVD_D22TP_CPU_RSVD_D2TP_CPU_RSVD_F6

FSB_A_L

FSB_A_L

FSB_A_L

FSB_ADS_L

CPU_IGNNE_L

CPU_THERMD_N

FSB_A_L

FSB_A_L

FSB_A_LFSB_A_LFSB_A_L

FSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_BPRI_L

FSB_A_LFSB_A_L

FSB_ADSTB_L


FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_ADSTB_L

CPU_FERR_L

CPU_STPCLK_LCPU_INTRCPU_NMICPU_SMI_L

TP_CPU_RSVD_M4TP_CPU_RSVD_N5TP_CPU_RSVD_T2TP_CPU_RSVD_V3TP_CPU_RSVD_B2

FSB_BNR_L

FSB_DEFER_LFSB_DRDY_LFSB_DBSY_L

FSB_BREQ0_L

FSB_CPURST_LFSB_RS_LFSB_RS_LFSB_RS_LFSB_TRDY_L

FSB_HIT_LFSB_HITM_L

XDP_BPM_LXDP_BPM_LXDP_BPM_LXDP_BPM_L

XDP_TCKXDP_TDIXDP_TDOXDP_TMSXDP_TRST_LXDP_DBRESET_L

CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P

FSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_L

FSB_A_L

FSB_A_L

FSB_A_LFSB_A_L

FSB_A_L

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L

FSB_D_LFSB_DSTB_L_N

FSB_D_LFSB_D_L

FSB_D_L

CPU_PSI_LFSB_CPUSLP_LCPU_PWRGDFSB_DPWR_LCPU_DPSLP_LCPU_DPRSTP_L

FSB_DINV_LFSB_DSTB_L_PFSB_DSTB_L_N

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_DINV_LFSB_DSTB_L_PFSB_DSTB_L_NFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_L

CPU_BSELCPU_BSELCPU_BSEL

TP_CPU_TEST5

TP_CPU_TEST3

FSB_DSTB_L_N

FSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_D_LFSB_D_L

FSB_D_LFSB_D_L


FSB_DINV_LFSB_DSTB_L_P


FSB_D_L

FSB_D_LFSB_D_L

FSB_DINV_LFSB_DSTB_L_P

TP_CPU_TEST6TP_CPU_TEST7

CPU_IERR_L

XDP_BPM_L

CPU_PROCHOT_L

XDP_TMS

XDP_TDI

CPU_GTLREF

XDP_TCK

XDP_TRST_L

=PP1V05_S0_CPU

XDP_BPM_L

FSB_CLK_CPU_N

XDP_TDO

CPU_TEST2CPU_TEST1

CPU_TEST4

FSB_D_L

FSB_D_L

10 OF 109

A.13.0

051-8563

9 OF 80

1

2

1

2

1

2

1

21

2

1

2

1

2

1

2

1 2

1

2

1

2

1 2

1 2

1 2

1 2

1

2

2

1

C3

A26

M26

N24

N25

T25

P23

J23

H22

F26

K22

H26

H25

G24

K24

E23

E25

R23

P26

E22 Y22

F24

E26

G25

N22

L23

M24

L22

M23

P25

P22

T24

R24

L25

L26

AD26

C24

AF26

AF1

B22

B23

C21

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

K25

F23

G22

J26

H23

J24

D25

C23

1 2

H4

B3

A6

K5

J4

L5

P4

R1

K3

H2

K2

J3

L1

A21

A22

C7

A24

D21

C20

AB6

AB5

AB3

AA6

AC5

AC1

AC2

AC4

AD1

AD3

AD4

E4

G6

G2

G3

F4

F3

C1

D20

F1

E1

F21

H5

E2

B2

V3

T2

N5

M4

A3

B4

C6

D5

A5

V1

AA3

AB2

AA4

W3

V4

U2

Y4

W5

R3

U5

Y2

M1

L2

P2

G5

W6

U4

Y5

U1

R4

T3

W2

J1

N2

M3

P5

T5

B25

C4

H1

N3

P1

L4

F6

D2

D22

D3

72

72

72

72

72

9 12 72

9 12 72

28 72

9 12 72

9 12 72

7 10 11 12 61

9 12 72

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4




36

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DR


SHEET

PAGE TITLE

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D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1Current numbers from Merom for Santa Rosa EMTS, doc #20905.

(Socket-P KEY)

(CPU CORE POWER)

44 A (SV Design Target)

41 A (SV HFM)

30.4 A (SV LFM)

23 A (LV Design Target)

(CPU IO POWER 1.05V)

4500 mA (before VCC stable)

2500 mA (after VCC stable)

(CPU INTERNAL PLL POWER 1.5V)

130 mA

(BR1#)

61 72

61 72

61 72

61 72

61 72

61 72

MF-LF402

1001%1/16W

PLACE_NEAR=U1000.AE7:25.4 mm

R1101

61 72

61 72

61 72

OMIT

PENRYNFCBGA

U1000

OMIT

PENRYNFCBGA

U1000

1001%1/16WMF-LF402

PLACE_NEAR=U1000.AF7:25.4 mm

R1100

SYNC_DATE=07/20/2009SYNC_MASTER=T27_MLB

CPU Power & Ground

CPU_VID

CPU_VID

CPU_VID

CPU_VID

CPU_VID

CPU_VID

CPU_VID

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

11 OF 109

A.13.0

051-8563

10 OF 80

1

2

AD15

AD17

AD18

C15

A7

A10

A13

A17

B15

B17

B20

C17

C18

D9

D12

D14

D18

E7

E9

E10

E12

E13

E15

E17

E18

E20

F7

F9

F10

F12

F14

F15

F18

F20

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

G21

V6

J6

K6

M6

J21

K21

M21

N21

N6

R21

R6

T21

T6

V21

W21

B26

C26

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AF7

AE7

A9

A12

A15

B14

B18

C9

C10

C12

C13

D10

D15

D17

B12

B10

B7

A18

F17

B9

A20

N23

N26

B1

P3

E19

B19

A23

D16

D11

D4

D1

C25

C22

C2

T4

B8

A4

A8

A11

A14

A16

A19

AF2

B11

B13

B16

B21

B24

C5

C8

C11

C14

C16

C19

D8

D13

D26

E3

E6

E11

E14

E16

E24

F5

F8

F11

F13

F16

F19

F2

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

J2

J5

J22

J25

K1

K4

K23

K26

L3

L21

L24

M2

M5

M22

M25

N1

N4

P6

P21

P24

R2

R5

R22

R25

T1

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

E8

E21

L6

D23

D19

B6

1

2

7 11

7 9 11 12 61

7 10 11

7 10 11




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


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B

C

345678

D

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8 7 5 4 2 1

PLACEMENT_NOTE (C1240-C1243):

1x 330uF, 6x 0.1uF 0402

PLACEMENT_NOTE (C1200-C1219):

4X 330UF. 20X 22UF 0805CPU VCore HF and Bulk Decoupling

VCCA (CPU AVdd) DECOUPLING

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

C126020%

2.0VPOLY-TANTD2T-SM2

330UF

CRITICAL

PLACEMENT_NOTE=Place C1260 between CPU & NB.

20%

X5R-CERM

NO STUFF

C1209CRITICAL

22UF6.3V

603

CPU_CAP:15&CPU_CAP:12

C121922UF

CRITICAL

X5R-CERM6.3V20%

603

CRITICALNO STUFF

6.3V20%

X5R-CERM603

22UFC1208

6.3V

CRITICALCPU_CAP:15&CPU_CAP:12

603X5R-CERM

20%22UFC1218

NO STUFF

603X5R-CERM

20%6.3V

22UF

CRITICALC1207


22UFC1217CRITICAL

6.3V20%

X5R-CERM603

X5R-CERM


CRITICAL

603

20%6.3V

22UFC1206

CRITICAL

603X5R-CERM

22UFC1216

CPU_CAP:15

6.3V20%

22UFC1205

6.3VX5R-CERM603

CRITICALCPU_CAP:15

20%

CRITICAL


6.3V

603

20%

C1215

X5R-CERM

22UF

603

NO STUFFCRITICAL

X5R-CERM

22UFC1204

6.3V20%

6.3V


22UF20%

603X5R-CERM

C1214CRITICAL

CRITICALC1243

D2T-SMPOLY-TANT2.0V20%

Place on secondary side.

470UF-4MOHM

C1213CRITICAL


X5R-CERM6.3V

22UF20%

603

NO STUFF

C120320%

X5R-CERM6.3V

22UF

603

CRITICAL

C1242CRITICAL

POLY-TANT


2.0V

D2T-SM

20%470UF-4MOHM


22UF

X5R-CERM

CRITICAL

6.3V

C1202

603

20%


C1212

6.3V

CRITICAL

603

20%

X5R-CERM

22UF

X5R-CERM

20%

NO STUFFCRITICAL

22UFC1201

603

6.3V

NO STUFFCRITICALC121120%6.3V

603

22UF

X5R-CERM

C1241CRITICAL

POLY-TANT2.0V

D2T-SM

20%470UF-4MOHM


Place inside socket cavity on secondary side.


CRITICALC120022UF6.3V20%

603X5R-CERM


603

C1210CRITICAL

22UF

X5R-CERM6.3V20%

20%2.0VPOLY-TANTD2T-SM


CRITICALNO STUFFC1240470UF-4MOHM

CPU_CAP:15

C122220%

X5R-CERM603

22UF6.3V

CRITICAL


CRITICAL

20%6.3VX5R-CERM603

22UFC1221

NO STUFF

603

20%6.3V

22UF

X5R-CERM

C1220CRITICAL

C126120%10VCERM402

0.1UFC126220%10VCERM402

0.1UFC126320%10VCERM402

0.1UFC126420%10VCERM402

0.1UFC126520%10VCERM402

0.1UFC126620%10VCERM402

0.1UF

BYPASS=U1000.B26::4 mm

10%

CERM16V

402

0.01UFC1251C1250

20%6.3VX5R603

10uF

CPU DecouplingSYNC_DATE=11/23/2009SYNC_MASTER=T27_MLB

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

12 OF 109

A.13.0

051-8563

11 OF 80

32

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3 2

1

2

1

2

1

3 2

1

2

1

2

1

2

1

2

1

3 2

1

2

1

2

1

3 2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

7 10

7 9 10 12 61

7 10

IN

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

NC

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

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2 1


Apple Inc.

PAGE


A

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C

345678

D

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8 7 5 4 2 1

OBSDATA_C1

OBSFN_C0

MCP89-specific pinout

Mini-XDP Connector

ITPCLK#/HOOK5

VCC_OBS_CD

XDP_PRESENT#

Use with 920-0620 adapter board to support CPU, MCP debugging.

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_B1

OBSDATA_D2

OBSDATA_D3

ITPCLK/HOOK4

OBSFN_C1

OBSDATA_C2

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSDATA_B3

OBSFN_D1

PWRGD/HOOK0

OBSDATA_B2

TCK1

TMS

HOOK1

HOOK3

TRSTn

SDA

SCL

OBSFN_D0

RESET#/HOOK6

TDI

TDO

VCC_OBS_AB

NOTE: This is not the standard XDP pinout.

on even-numbered side of J1300

Please avoid any obstructions

DBR#/HOOK7

OBSDATA_C3

OBSDATA_C0

OBSDATA_A1

TCK0

Direction of XDP module

OBSDATA_D1

OBSDATA_D0

OBSFN_B1

OBSDATA_B0

OBSFN_B0

OBSDATA_A2

OBSDATA_A3

HOOK2

998-1571

9 13 72

R13991K

1/16W5%

402MF-LF

XDP

18 42 75

18 42 75

R1315

1/16W1%

402MF-LF

54.9

XDP

C1300

16V10%

402X5R

0.1uF

XDP

C1301

402

XDP

16V10%

X5R

0.1uF

9 72

9 72

9 72

9 13 72

R1303

1/16W5%

402MF-LF

1K

XDP

PLACEMENT_NOTE=Place close to CPU to minimize stub.

9 72

9 72

9 72

9 72

18

18

18

18

18

13 72

13 72

9 72

9 72

9 72

9 72

9 24

18

J1300

CRITICAL

F-ST-SM

LTH-030-01-G-D-NOPEGS

XDP_CONN

eXtended Debug Port (mini-XDP)

SYNC_MASTER=T27_MLB SYNC_DATE=07/28/2009

FSB_CPURST_L

CPU_PWRGD

XDP_TMS

XDP_TDO

XDP_TRST_L

XDP_TDI

XDP_DBRESET_L

XDP_CPURST_L

FSB_CLK_ITP_N

TP_XDP_OBSDATA_D2

TP_XDP_OBSDATA_D0

TP_XDP_OBSDATA_D1

JTAG_MCP_TDI

TP_XDP_OBSDATA_C2

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

TP_XDP_OBSFN_B0

TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2

XDP_PWRGD

TP_XDP_OBSDATA_B3

XDP_OBS20

=PP1V05_S0_CPU

PM_LATRIGGER_L

JTAG_MCP_TCK

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

FSB_CLK_ITP_P

TP_XDP_OBSDATA_D3

JTAG_MCP_TMS

TP_XDP_OBSDATA_C3

=PP3V3_S0_XDP

TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C0

JTAG_MCP_TRST_L

JTAG_MCP_TDO

13 OF 109

A.13.0

051-8563

12 OF 80

1 2

1

2

2

1

2

1

1 2

60

58

52

54

56

50

48

46

44

42

36

40

38

32

34

28

30

26

24

22

18

16

20

14

12

10

8

6

2

4 3

1

5

7

9

11

13

19

15

17

23

21

29

27

25

33

31

37

39

35

43

41

45

49

47

55

53

51

57

59

72

7 9 10 11 61

7

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

CPU_A18*

CPU_D35*

CPU_D37*

CPU_A10*

CPU_A9*

CPU_D48*

CPU_A16*

CPU_D33*

CPU_RS2*

CPU_RS1*

CPU_RS0*

CPU_BSEL2

CPU_BSEL1

CPU_THERMTRIP*

CPU_PECI

CPU_PROCHOT*

CPU_DBSY*

CPU_ADSTB1*

CPU_REQ1*

CPU_REQ4*

CPU_BR0*

CPU_BNR*

CPU_ADS*

CPU_REQ2*

CPU_REQ3*

CPU_REQ0*

CPU_ADSTB0*

CPU_A31*

CPU_A32*

CPU_A30*

CPU_A28*

CPU_A26*

CPU_A27*

CPU_A23*

CPU_A24*

CPU_A25*

CPU_A21*

CPU_A22*

CPU_A19*

CPU_A20*

CPU_A13*

CPU_A14*

CPU_A12*

CPU_A11*

CPU_A8*

CPU_A5*

CPU_A6*

CPU_A7*

CPU_A3*

CPU_A4*

CPU_DSTBN0*

CPU_DBI0*

CPU_DSTBP1*

CPU_DSTBN1*

CPU_DBI1*

CPU_DSTBP2*

CPU_DSTBN2*

CPU_DBI2*

CPU_DSTBP3*

CPU_DSTBN3*

CPU_DBI3*

CPU_BSEL0

CPU_COMP_GND

BCLK_VML_COMP_VDD

CPU_COMP_VCC

BCLK_VML_COMP_GND

CPU_D1*

CPU_D2*

CPU_D3*

CPU_D4*

CPU_D5*

CPU_D6*

CPU_D9*

CPU_D11*

CPU_D12*

CPU_D13*

CPU_D14*

CPU_D15*

CPU_D16*

CPU_D17*

CPU_D18*

CPU_D19*

CPU_D20*

CPU_D21*

CPU_D22*

CPU_D23*

CPU_D24*

CPU_D25*

CPU_D26*

CPU_D27*

CPU_D28*

CPU_D29*

CPU_D30*

CPU_D31*

CPU_D32*

CPU_D34*

CPU_D36*

CPU_D38*

CPU_D39*

CPU_D40*

CPU_D41*

CPU_D42*

CPU_D45*

CPU_D46*

CPU_D47*

CPU_D49*

CPU_D50*

CPU_D51*

CPU_D52*

CPU_D53*

CPU_D54*

CPU_D55*

CPU_D56*

CPU_D57*

CPU_D58*

CPU_D59*

CPU_D60*

CPU_D61*

CPU_D62*

CPU_D63*

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI

CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_D10*

CPU_D8*

CPU_D7*

CPU_A33*

CPU_A34*

CPU_A35*

CPU_D44*

CPU_D43*

CPU_DSTBP0*

CPU_TRDY*

CPU_LOCK*

CPU_HIT*

CPU_DRDY*

CPU_HITM*

CPU_DPRSTP*

CPU_D0*

CPU_DPSLP*

CPU_DPWR*

CPU_STPCLK*

CPU_A15*

CPU_A17*

CPU_A29*

CPU_BPRI*

CPU_DEFER*

CPU_FERR*BCLK_OUT_CPU_P

BCLK_OUT_CPU_N

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

BCLK_OUT_NB_N

BCLK_IN_N

BCLK_IN_P

BCLK_OUT_NB_P

(1 OF 11)

FSB

OUT

IN

IN

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Loop-back clock for delay matching.

8

8

8

9 72

9 12 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

6 9 72

9 72

9 72

9 72

9 72

9 72

9 72

12 72

12 72

9 72

9 72

9 72

9 72

9 72

9 72

9 72

9 72

9 12 72

9 72

9 72

9 72

9 72

9 61 72

8

9 40 61 72

9 40 72

6 9 72

6 9 72

1%1/16WMF-LF402

49.9R1436

49.9

MF-LF402

1%1/16W

R1431

1/16W1%

402MF-LF

49.9R1430

402MF-LF

1%1/16W

49.9R1435

5%62

MF-LF402

1/16W

R14151%

54.9

MF-LF402

1/16W

R1410

1501/16W

NO STUFF

402MF-LF

5%

R1440

OMIT

MCP89M-A01FBGA

U1400

61 72

6 9 72

6 9 72

9 72

9 72

9 72

9 72

6 9 72

MCP CPU InterfaceSYNC_MASTER=T27_MLB SYNC_DATE=11/05/2009

FSB_D_LFSB_D_L

FSB_D_L

FSB_D_L

FSB_D_L

FSB_D_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_D_L

CPU_DPRSTP_LCPU_STPCLK_LFSB_DPWR_LCPU_DPSLP_LFSB_CPUSLP_LPM_DPRSLPVRFSB_CPURST_LCPU_PWRGDCPU_SMI_LCPU_NMICPU_INTRCPU_INIT_LCPU_IGNNE_LCPU_A20M_L

FSB_CLK_MCP_NFSB_CLK_MCP_P

FSB_CLK_ITP_PFSB_CLK_ITP_N

FSB_CLK_CPU_NFSB_CLK_CPU_P

FSB_BPRI_LFSB_DEFER_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_GND

=MCP_BSEL

FSB_DINV_LFSB_DSTB_L_NFSB_DSTB_L_P




FSB_A_LFSB_A_L


FSB_A_L

FSB_A_LFSB_A_L


FSB_A_L

FSB_A_LFSB_A_L

FSB_A_LFSB_A_L


FSB_A_LFSB_A_L

FSB_A_L

FSB_A_LFSB_A_L


FSB_A_LFSB_A_L

FSB_ADSTB_L

FSB_REQ_L

FSB_REQ_LFSB_REQ_L

FSB_ADS_LFSB_BNR_LFSB_BREQ0_L

FSB_REQ_L

FSB_REQ_L

FSB_ADSTB_L

FSB_DBSY_LFSB_DRDY_L

FSB_HITM_LFSB_HIT_L

FSB_TRDY_LFSB_LOCK_L

CPU_PROCHOT_LCPU_PECI_MCP

CPU_FERR_LPM_THRMTRIP_L

=MCP_BSEL=MCP_BSEL

FSB_RS_LFSB_RS_LFSB_RS_L

FSB_A_L

FSB_D_L

FSB_A_LFSB_A_L

FSB_D_L

FSB_D_L

FSB_A_L

=PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_FSB

14 OF 109

A.13.0

051-8563

13 OF 80

1

2

1

2

1

2

1

2

1

2

1

2

1

2

AB35

L31

P32

Y38

T37

C37

Y35

G34

AC31

AC33

AB29

B34

C34

W33

AH34

U28

AE29

AB34

T36

T35

AE30

AE32

AE31

U37

T38

U36

W36

AC35

AE37

AC37

AE36

AB37

AC34

AC38

AB36

AB38

AC36

AF36

Y34

AE38

U33

W34

Y36

W35

W38

U35

T34

W37

U38

U34

K35

L37

T31

T30

P28

K33

K32

N35

C36

D36

A35

A34

AH35

AH37

AH36

AH38

N36

P36

L36

N34

L35

P37

L34

K36

K38

N37

H37

L38

N28

U30

N29

P34

T29

T32

U32

T33

P31

P30

N30

P33

N31

T28

P35

P29

H33

L30

L33

N32

N33

H35

K31

H34

G33

H32

G35

D37

H38

G38

G37

Date post:	25-Jan-2021
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8 7 6 5 4 3 2 1 REV SCHEMATIC,MLB - InformaticaNapoliK18_MLB 07/28/2009 DDR3 SO-DIMM Connector B 26...

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