8. Biasing Transistor...

8. Biasing Transistor Amplifiers

Lecture notes: Sec. 5

Sedra & Smith (6th Ed): Sec. 5.4, 5.6 & 6.3-6.4 Sedra & Smith (5th Ed): Sec. 4.4, 4.6 & 5.3-5.4

ECE 65, Winter2013, F. Najmabadi

Issues in developing a transistor amplifier:

F. Najmabadi, ECE65, Winter 2013, Amplifier Biasing (2/29)

1. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias). o This will lead to different circuit configurations for bias versus signal

2. Compute circuit response to the signal o Focus on fundamental transistor amplifier configurations

3. How to establish a Bias point (bias is the state of the system when there is no signal). o Stable and robust bias point should be resilient to variations in

µnCox (W/L),Vt (or β for BJT) due to temperature and/or manufacturing variability.

o Bias point details impact small signal response (e.g., gain of the amplifier).

BJT biasing with Base Voltage (Fixed Bias)


B

DBBB

BEBBBB

RVVI

VRIV

0

:KVLBE−

=

+=−

* Typically VBB = VCC in order to reduce the need for additional reference voltages.

)(

:KVLCE

0DBBB

CCCCE

CECCCC

VVRRVV

VRIV

−−=

+=−β

B

DBBBC R

VVII 0 −== ββ


Exercise 1: Find RC and RB such that BJT would be in active with VCE = 5V and IC = 25 mA. (VCC = 15 V, Si BJT with β = 100 and VA = ∞).

Ω=+×=+=− −

400 5102551 :KVLCE 3

C

CCECC

RRVRI

V 7.05 and 0 since Activein is BJT 0 =≥=> DCEC VVI

mA 25.0 / == βCB II

k 2.57 7.01025.051 :KVLBE 3

=+×=+=− −

B

BBEBB

RRVRI

Exercise 2: Consider the circuit designed in Exercise 1 (RC = 400 , RB = 57.2 k, VCC = 15 V ). Find the operating point of BJT if β = 200.


mA 25.0 7.0102.5751 :KVLBE 3

=+×=+=−

B

BBEBB

IIVRI

V 7.0 and 0 V, 7.0: Activein is BJT Assume

≥>= CECBE VIV

V 5 400105051 :KVLCE 3

−=+××=+=− −

CE

CECECC

VVVRI

mA 50 == BC II β

BJT in saturation! Note, compared to Exercise 1:

IB is the same.

IC has increased.

VCE had decreased.

Why biasing with base voltage (fixed bias) does not work?


Changes in BJT β changes the bias point drastically. o BJT can end up in saturation or in cut-off easily.

In fixed bias, IB is set through

BJT β then sets IC = β IB (IC changes with β ). o CE circuit then sets VCE .

But, requirements for BJT in active are on IC and VCE and NOT on IB o IC > 0 , VCE > VD0

To make bias point independent of changes in β, the bias circuit should “set” IC and NOT IB !

B

DBBB R

VVI 0 −=

Biasing with Emitter Degeneration


+

+=−

++=−

EB

EDBB

EEBEBBBB

RRIVV

RIVRIV

1

:KVLBE

0 β

Requires a resistor in the emitter circuit!

EB RR )1( :If +<< β

E

DBBEC

EEDBB

RVVII

RIVV

0

0

−

≈≈

≈−

Condition of means that the voltage drop across RB is small and the bias voltage VBB – VD0 appears across RE , setting IE and IC ≈ IE .

EB RR )1( +<< β

Independent of β !

Note that resistor RB is NOT necessary for good biasing but it may exist due to other considerations.

Emitter resistor provides negative feedback!


TBE VVB

EEBEBBBB

eI

RIVRIV

/ ∝

++=

Independent of β ! Negative Feedback:

o If IC ≈ IE ↑ (because β ↑) , VBE ↓ IB ↓ IC ≈ IE ↓

o If IC ≈ IE ↓ (because β ↓) , VBE ↑ IB ↑ IC ≈ IE ↑

β BE -KVL BE junction

BE -KVL BE junction β

Requirements for Biasing with Emitter Degeneration


Requires a resistor in the emitter circuit.

The bias voltage VBB – VD0 should appear across RE to set IE ≈ IC :

1.

o We need to set to ensure

that this condition is always satisfied!

2. VBE ≈ VD0 . In reality, VBE = VD0 ± ∆VBE with ∆VBE ≈ 0.1 V o We need to set or

EEBBBEBB RIRIVV +=−

EBEEBB RRRIRI )1( +<<⇒<< β

)1( min EB RR +<< β

V 1 ≥EE RI

V 0.1 >>EE RI

Emitter Degeneration Bias with a voltage divider


CCBB

B

VRR

RV

RRR

×+

=

=

21

2

21

||

Real Circuit

Voltage Divider


Exercise 3: Find the bias point of the BJT (Si BJT with β = 200 and VA = ∞).

mA 84.2 5107.0)1/(1003.5 2.22

2.22 :KVLBE3

=+++×=

++=−

E

EE

EEBEBB

III

RIVRIβ

V 7.0 and 0 V, 7.0: Activein is BJT Assume

≥>= CECBE VIV

V 0.7 V 10.7 5101084.2101082.2 15

51 :KVLCE

0

333

=>=××++××=

++=−−−

DCE

CE

EECECC

VVV

RIVRI

V 22.215k 34k 9.5

k 9.5

k 03.5k 34||k 9.5||

21

2

21

=×+

=×+

=

===

CCBB

B

VRR

RV

RRR

A 14.1)1/( mA 82.2)1/(

µβββ

=+==+×=

EB

EC

IIII

Notes:

1. We need to solve the complete BE-KVL as we do not know if

2. β >> 1 is a good approximation that reduces the amount of work. Answers using β >> 1 approximation:

)1( EB RR +<< β

V 10.7A 14.2 mA, 2.84

==≈≈

CE

BEC

VIII µ


Step 1: Find RC and RE

k 2.0k 3.0 k 1.0 :Choose

=−==

EC

E

RRR

Exercise 4: Design a BJT bias circuit (emitter degeneration with voltage divider) such that IC = 2.5 mA and VCE = 7.5 V. (VCC = 15 V Si BJT with β ranging from 50 to 200 and VA = ∞).

k 3.0 5.7)(105.2 15

51 :KVLCE3

=+++××=

++=−−

EC

EC

EECECC

RRRR

RIVRI

Free to choose individual values RE & RC (we will see later that amplifier parameters sets the individual values)

Circuit Prototype

Check:

V 1≥EE RI

V 15.210105.2 33 ≥=××= −EE RI


Step 2: Find RB and VBB Using relative error, ε = 10% Use largest RB (Will see later why)

Exercise 4 (Cont’d): Design a BJT bias circuit (emitter degeneration with voltage divider) such that IC = 25 mA and VCE = 5 V. (VCC = 15 V Si BJT with β ranging from 50 to 200 and VA = ∞).

k 5.1 k 5.1)1( 0.1 )1( minmin =→=+≤→+<< BEBEB RRRRR ββ

V 20.3 10 10 2.5 0.7

33

0 =→××+=+≈

++=

BB-

ECDBB

EEBEBBBB

VRIVVRIVRIV

Step 3: Find R1 and R2

213.015

3.20

k 10.5||

21

2

21

2121

==+

=

=+

==

RRR

VV

RRRRRRR

CC

BB

B

k 6.4

k 23.9213.0

k 10.5

2

1

=

==

R

R

Step 4: Find commercial R values:

RC = 2 k RE = 1 k R1 = 24 k R2 = 6.4 k

Emitter-degeneration bias circuits


Basic Arrangement EEBEBBBB RIVRIV ++=

Bias with one power supply

(voltage divider)

EEBEBBBB RIVRIV ++=

Bias with two power supplies

EEBEBBEE RIVRIV ++=

EEEEBEBB VRIVRI −++=0

MOS bias with Gate Voltage (Fixed Bias)


This method is NOT desirable as µnCox (W/L) and Vt are not “well-defined.” Bias point (i.e., ID and VDS) can change drastically due to temperature and/or manufacturing variability. o See S&S Exercise 5.33 (S&S 5th Ed: Exercise 4.19): Changing Vt from 1 to

1.5 V leads to a 75% change in ID.

DDDDDS

tGSoxnD

RIVV

VVL

WCI

−=

−= 2)( 5.0 µ

MOS bias with Source Degeneration (Resistor RS provides negative feedback!)


Negative Feedback:

o If ID ↑ (because µnCox (W/L) ↑ or Vt ↓ ) VGS ↓ ID ↓

o If ID ↓ (because µnCox (W/L) ↓ or Vt ↑ ) VGS ↑ ID ↑

ID Eq. GS KVL

GS KVL ID Eq.

Feedback is most effective if

SGDDSGGS

GSDS

RVIIRVVVIR

/ 0 ≈⇒=+−>>

2)( 5.0 tGSoxnD

DSGGS

VVL

WCI

IRVV

−=

−=

µ

Source-degeneration bias circuits


Basic Arrangement SDGSG RIVV +=

Bias with one power supply

(voltage divider)

Bias with two power supplies

SSSDGS VRIV −+=0

SDGSG RIVV += SDGSSS RIVV +=


Exercise 5: Find the bias point for Vt = 1 V and µnCox (W/L) = 1.0 mA/V2 (Ignore channel-width modulation).

Voltage divider (IG = 0)

V 715)87/()7( =×+=GV

V 1 065

7)105.0(101

7 7 :KVL-GS

5.0

2

234

2

=→=−+

=××++

=+++==

=

−

OVOVOV

OVOV

DStOV

DSGSG

OVoxnD

VVVVV

IRVVIRVV

VL

WCI µ

V 5 V 1015

15 :KVL-DS

=−==−=

+=

SDDS

DDD

DDD

VVVIRV

VIR

mA 5.0/ V 527

V 21

===−=−=

=+=

SSD

GSGS

OVGS

RVIVVV

VV

Exercise (impact of RS): Prove that if Vt = 1.5 V (50% change), ID = 0.455mA (9% change)

Biasing in ICs


Resistors take too much space on the chip. So, biasing with emitter or source degeneration are NOT implemented in ICs.

Recall that the goal of a good bias is to ensure that IC and VCE (or ID and VDS for MOS) do not change. One can force IC (or ID for MOS) to be constant using a current source.

Current source forces IE = I

Current source forces ID = I

BJT response to a current source


1) Current source forces: III EC =≈

3B) VE is set by BE-KVL

EBEBB VVIR 0 ++=

2) IB = IC / β

3A) CCCCC IRVV −=

4) ECCE VVV −=

MOS response to a current source


1) Current source forces: IID =

3B) GSGSGS VVVV −=−=

2) VGS is set by 2)( 5.0 tGSoxnD VV

LWCI −= µ

3A) DDDDD IRVV −=

4) SDDS VVV −=

Current Mirrors (or Current Steering circuits) are used as current sources for biasing ICs


Identical BJTs Qref is always in active since

Identical BJTs and vBE,ref = vBE1

o BJTs will have the same iB and the same iC (ignoring Early effect)

0,,

, 0

DrefBErefCE

refC

VVVi

==

>

βC

CBrefCrefiiiiI 22 :KCL , +=+=

/21

1 refref

C II

iI ≈+

==β

For the current mirror to work, Q1 should be in active:

011 DEECCE VVVV ≥+= Since I1 = const. regardless of

VC1 , this is a current source!

An implementation of a BJT Current Mirror


RVVVII

VVIRV

DEECCref

EEBErefCCref

01

:)Q ( KVL-BE

−+=≈

−+=


Exercise 6: Find the bias point of Q2 (Si BJT with β = 100 and VA = ∞).

mA 4.65

mA 4.65

5 1025

1

3

=≈

=

−+×=

ref

ref

BEref

III

VI

Current Mirror

V 1.165 7.0105.4610100

10100 :KVL-BE2

21

263

2223

−==++×××=

++×=−

EC

E

EBEB

VVV

VVI

A 46.5/mA 4.65

22

122

µβ ≈=≈=≈

CB

EC

IIIII

V 7.0 1.56 V 1.56

165.11065.4105

105 :KVL-CE2

02

2

332

2223

=>==

−××−=

++=−

DCE

CE

CE

ECEC

VVVV

VVI

Assume Q2 in active:

Q2 in active!

Check Q1 in active:

V 7.0 3.835V 3.835 5 1.165)5(

01

11

=>==+−=−−=

DCE

CCE

VVVV

Examples of BJT current mirrors


PNP current Mirror One “reference” BJT feeds many current mirrors

Integer multiple of Iref can be made (See Q3 & Q4)

MOS Current-Steering Circuit


Qref is always in saturation since

OVOVrefOV

GSGSrefGS

trefGSrefGSrefDS

VVVVVV

VVVV

==

==

−>=

1,

1,

,,,

2111

2,

)/(5.0

)/(5.0

OVoxnD

OVrefoxnrefDref

VLWCiI

VLWCiI

µ

µ

==

==

( )( )refref LW

LWII

// 11 =

For the current steering circuit to work, Q1 should be in saturation:

tGSOVDS VVVV −=>1

Identical MOS: Same µCox and Vt

Since I1 = const. regardless of VD1 , this is a current source!

An implementation of a MOS current steering circuit


The above quadratic equation gives VOV . I1 is then found from the MOS iD equation.

SSGSDDDref

OVrefoxnDref

VvRiVVLWCiI

−+=

==

:)Q ( KVL-GS

)/(5.0 2µ

0] [ ] )/(5.0 [

02 =+−−++

=+−−+

tDDSSOVOVrefoxn

tDDSSOVD

VVVVVRLWCVVVVRi

µ

Examples of MOS current steering circuits


One “reference” MOS feeds many current steering circuits.

Any value of Iref can be made (thus, current-steering circuit instead of current-mirror)

( )( )refref LW

LWII

/ / 11 = ( )

( )refref LWLW

II

/ / 22 =

PMOS current steering circuit

An implementation of current steering circuit to bias several transistors in an IC


Exercise: Compute I4/Iref

Date post:	28-Jun-2020
Category:	Documents
Upload:	others
View:	11 times
Download:	1 times

8. Biasing Transistor...

Documents