HT48R30 8-bit OTP Microcontrollers HT48R30 SPECIFICATION Features • 22 bidirectional I/O lines • An interrupt input • An 8-bit programmable Timer/event counter with overflow interrupt • On-chip crystal and RC oscillator • Watch dog timer • 2K × 14 program memory PROM • 96 × 8 data memory RAM • Operating voltage: 2.4V~5.2V • 63 powerful instructions • Halt function to reduce power consump- tion and wake-up feature • Up to 1μs instruction cycle with 4MHz sys- tem clock at VDD=5V • All instructions in 1 or 2 machine cycles • 14-bit table read instruction • Two-level subroutine nesting • Bit manipulation instruction • 1 × 14 option memory PROM General Description The HT48R30 is an 8-bit high performance RISC-like microcontroller specifically designed for multiple I/O product applications. The de- vice is particularly suitable for use in products such as remote controllers, fan/light control- lers, washing machine controllers, scales, toys and various subsystem controllers. A halt fea- ture is included to reduce power consumption. The program and option PROM can be electri- cally programmed. The PROM type program and option memory make the HT48R30 suit- ably use in product development. 1 20th May ’97
Transcript
HT48R308-bit OTP Microcontrollers
HT48R30 SPECIFICATION
Features• 22 bidirectional I/O lines
• An interrupt input
• An 8-bit programmable Timer/eventcounter with overflow interrupt
• On-chip crystal and RC oscillator
• Watch dog timer
• 2K × 14 program memory PROM
• 96 × 8 data memory RAM
• Operating voltage: 2.4V~5.2V
• 63 powerful instructions
• Halt function to reduce power consump-tion and wake-up feature
• Up to 1µs instruction cycle with 4MHz sys-tem clock at VDD=5V
• All instructions in 1 or 2 machine cycles
• 14-bit table read instruction
• Two-level subroutine nesting
• Bit manipulation instruction
• 1 × 14 option memory PROM
General Description
The HT48R30 is an 8-bit high performanceRISC-like microcontroller specifically designedfor multiple I/O product applications. The de-vice is particularly suitable for use in productssuch as remote controllers, fan/light control-lers, washing machine controllers, scales, toysand various subsystem controllers. A halt fea-ture is included to reduce power consumption.
The program and option PROM can be electri-cally programmed. The PROM type programand option memory make the HT48R30 suit-ably use in product development.
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Block Diagram
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Pad Description
Pad No. Pad Name I/O ROM CodeOption Function
127~2919~22
PA0~PA7 I/O Wake-up
Bidirectional 8-bit Input/Output port. Each bit can beconfigured as a wake-up input by a ROM code option.Software instructions determine the CMOS output orschmitt trigger input with a pull-high resistor.
2~523~26
PB0~PB7 I/O —Bidirectional 8-bit Input/Output port. Softwareinstructions determine the CMOS output or schmitttrigger input with a pull-high resistor.
6 VSS — — Negative power supply, GND
7 INT I —External interrupt schmitt trigger input with a pull-high resistor. Edge triggered is activated on a high tolow transition.
8 TMR I — Schmitt trigger input for Timer/Event Counter.
9~14 PC0~PC5 I/O —Bdirectional 6-bit Input/Output port. Softwareinstructions determine the CMOS output or schmitttrigger input with a pull high resistor.
15 RES I — Schmitt trigger reset input. Active low
16 VDD — — Positive power supply
1718
OSC1OSC2
IO
Crystal orRC
OSC1, OSC2 are connected to the RC network orCrystal (determined by ROM code option) for theinternal system clock. In the case of RC operation,OSC2 is the output terminal for 1/4 system clock.
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Pad Position
Pad Assignment
Pad No. Pad Name Pad No. Pad Name
1 PA0 16 VDD
2 PB3 17 OSC1
3 PB2 18 OSC2
4 PB1 19 PA7
5 PB0 20 PA6
6 VSS 21 PA5
7 INT 22 PA4
8 TMR 23 PB7
9 PC0 24 PB6
10 PC1 25 PB5
11 PC2 26 PB4
12 PC3 27 PA3
13 PC4 28 PA2
14 PC5 29 PA1
15 RES
* The IC substrate should be connected to VSS in the PCB layout artwork. * The TMR pad must be bonded to VDD or VSS if the TMR pad is not used.
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Package & Pin Assignment
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Note:
1. For the dice form, the TMR pad must be bonded to VDD or VSS if the TMR pad is not used.
2. The (TMR)VSS and (TMR)INT indicate the TMR pad must be bonded to the VSS and INT pins respectively.
3. For packaging of the HT48R30 microcontroller, the OSC2 pin (RC system oscillator only) had better not be bonded out unless necessary.
*. It is recommended that the user might select the star (*) sign packages first under the reason of inventory.
The system clock for the HT48R30 is derivedfrom either a crystal or an RC oscillator. Thesystem clock is internally divided into four non-overlapping clocks. One instruction cycle con-sists of four system clock cycles.
Instruction fetching and execution are pipe-lined in such a way that a fetch takes an in-struction cycle while decoding and executiontake the next instruction cycle. However, thepipelining scheme causes each instruction toeffectively execute in a cycle. If an instructionchanges the program counter, two cycles arerequired to complete the instruction.
Program Counter - PCThe 11-bit program counter (PC) controls thesequence in which the instructions stored inprogram PROM are executed and its contentsspecify a maximum of 2048 addresses.
After accessing a program memory word tofetch an instruction code, the contents of theprogram counter are incremented by one. Theprogram counter then points to the memoryword containing the next instruction code.
When executing a jump instruction, conditionalskip execution, loading PCL register, subrou-tine call, initial reset, internal interrupt, exter-nal interrupt or return from subroutine, the PCmanipulates the program transfer by loadingthe address corresponding to each instruction.
The conditional skip is activated by instruc-tions. Once the condition is met, the next in-struction, fetched during the currentinstruction execution, is discarded and adummy cycle replaces it to get the proper in-struction. Otherwise proceed with the next in-struction.
The lower byte of the program counter (PCL) isa readable and writable register (06H). Movingdata into the PCL performs a short jump. Thedestination will be within 256 locations.
Once the control transfer takes place, the exe-cution suffers from having an additionaldummy cycle.
Program Memory - PROM
The program memory is used to store the pro-gram instructions which are to be executed. Italso contains data, table, and interrupt entries,and is organized with 2048 × 14 bits, addressedby the program counter and table pointer.
Execution Flow
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Certain locations in the program memory arereserved for special usages:
Location 000H:This area is reserved for program initialization.After chip reset, the program always beginsexecution at location 000H.
Location 004H:This area is reserved for the external interruptservice program. If the INT input pin is acti-vated, the interrupt is enabled and the stack isnot full, the program begins execution at loca-tion 004H.
Location 008H:This area is reserved for the Timer/eventCounter interrupt service program. If a timerinterrupt results from a Timer/event Counteroverflow, and if the interrupt is enabled and thestack is not full, the program begins executionat location 008H.
Table location:Any location in the PROM space can be used aslook-up tables. The instructions “TABRDC [m]”(the current page, 1 page=256 words) and“TABRDL [m]” (the last page) transfer the con-tents of the lower-order byte to the specifieddata memory, and the higher-order byte toTBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the otherbits of the table word are transfered to the
lower portion of TBLH, and the remaining 2bits are read as “0”. The Table Higher-orderbyte register (TBLH) is read only. The tablepointer (TBLP) is a read/write register (07H),which indicates the table location. Before ac-cessing the table, the location must be placed inTBLP. The TBLH is read only and cannot berestored. If the main routine and the ISR (In-terrupt Service Routine) both employ the tableread instruction, the contents of the TBLH inthe main routine are likely to be changed by thetable read instruction used in the ISR. Errors
are thus brought about. Given this, using thetable read instruction in the main routine andthe ISR simultaneously should be avoided.However, if the table read instruction has to beapplied in both the main routine and the ISR,the interrupt(s) is supposed to be disabled priorto the table read instruction. It (They) will notbe enabled until the TBLH has been backup. Alltable related instructions require 2 cycles tocomplete the operation. These areas may func-tion as normal program memory dependingupon the user’s requirements.
Stack Register - STACK
This is a special part of memory which is usedto save the contents of the program counter(PC) only. The stack is organized into 2 levelsand is neither part of the data nor programspace, and is neither readable nor writable. Theactivated level is indexed by the stack pointer(SP) and is neither readable nor writeable. At asubroutine call or interrupt acknowledgement,the contents of the program counter are pushedonto the stack. At the end of a subroutine or aninterrupt routine, signaled by a return instruc-tion (RET or RETI), the program counter isrestored to its previous value from the stack.After a chip reset, the SP will point to the top ofthe stack.
If the stack is full and a non-masked interrupttakes place, the interrupt request flag will berecorded but the acknowledgement will be in-hibited. When the stack pointer is decremented(by RET or RETI), the interrupt will be serv-iced. This feature prevents stack overflow al-lowing the programmer to use the structure
more easily. In a similar case, if the stack is fulland a “CALL” is subsequently executed, stackoverflow occurs and the first entry will be lost(only the most recent two return addresses arestored).
Data Memory - RAM
The data memory is designed with 113 × 8 bits.The data memory is divided into two functionalgroups: special function registers and generalpurpose data memory (96 × 8). Most of them areread/write, but some are read only.
The special function registers include the Indi-rect addressing register (00H), Timer/eventCounter (TMR;0DH), Timer/event Countercontrol register (TMRC;0EH), Programcounter lower-order byte register (PCL;06H),Memory pointer register (MP;01H), Accumula-tor (ACC;05H), Table pointer (TBLP;07H), Ta-ble higher-order byte register (TBLH;08H),Status register (STATUS;0AH), Interrupt con-trol register (INTC;0BH), Watch Dog Timeroption setting register (WDTS;09H), I/O regis-ters (PA;12H, PB;14H, PC;16H) and I/O con-trol registers (PAC;13H, PBC;15H, PCC;17H).The remaining space before the 20H is re-served for future expanded usages and readingthese locations will get “00H”. The general pur-pose data memory, addressed from 20H to7FH, is used for data and control informationunder instruction commands.
All of the data memory areas can handle arith-metic, logic, increment, decrement and rotateoperations directly. Except for some dedicatedbits, each bit in the data memory can be set and
Instruction(s)Table Location
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Notes: *10~*0: Bits of table location
@7~@0: Bits of table pointer
P10∼P8: Bits of current program Counter
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reset by “SET [m].i” and “CLR [m].i”. They arealso indirectly accessable through Memorypointer register (MP;01H).
Indirect Addressing Register
Location 00H is an indirect addressing registerthat is not physically implemented. Anyread/write operation of [00H] accesses datamemory pointed to by MP (01H). Reading loca-tion 00H itself indirectly will return the result00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bitregister. The bit 7 of MP is undefined and readingwill return the result “1”. Any writing operation toMP will only transfer the lower 7-bit data to MP.
AccumulatorThe accumulator closely relates to ALU opera-tions. It is also mapped to location 05H of thedata memory and is the one which can operatewith immediate data. The data movement be-tween two data memories must get through theaccumulator.
Arithmetic and Logic Unit - ALUThis circuit performs 8-bit arithmetic and logicoperations. The ALU provides the followingfunctions:
Arithmetic operations (ADD, ADC, SUB, SBC,DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment & Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a dataoperation but also changes the status register.
Status Register - STATUSThis 8-bit register (0AH) contains the zero flag(Z), carry flag (C), auxiliary carry flag (AC),overflow flag (OV), power down flag (PD), andwatch dog time-out flag (TO). It also records thestatus information and controls the operationsequence.
With the exception of the TO and PD flags,bits in the status register can be altered byinstructions like any other register. Anydata written into the status register will notchange the TO or PD flag. In addition opera-tions related to the status register may givedifferent results from those intended. TheTO flag can be affected only by systempower-up, a WDT time-out or executing the“CLR WDT” or “HALT” instruction. The PDflag can be affected only by executing the“HALT” or “CLR WDT” inctruction or a sys-tem power-up.
The Z, OV, AC and C flags generally reflect thestatuses of the latest operations.
RAM Mapping
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In addition, on entering the interrupt sequenceor executing the subroutine call, the status reg-ister will not be pushed onto the stack automat-ically. If the contents of status are importantand the subroutine can corrupt the status reg-ister, the programmer must take precautions tosave it properly.
Interrupt
The HT48R30 provides an external interruptand internal Timer/event Counter interrupts.The Interrupt Control Register (INTC;0BH)contains the interrupt control bits to set theenable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, allthe other interrupts will be blocked (by clearingthe EMI bit). This scheme may prevent anyfurther interrupt nesting. Other interrupt re-quests may happen during this interval butonly the interrupt request flag is recorded. If acertain interrupt requires servicing within theservice routine, the programmer may set theEMI bit and the corresponding bit of INTC toallow interrupt nesting. If the stack is full, theinterrupt request will not be acknowledged,
even if the related interrupt is enabled, untilthe SP is decremented. If immediate service isdesired, the stack must be prevented from be-coming full.
All these kinds of interrupts have the wake-upcapability. As an interrupt is serviced, a controltransfer occurs by pushing the program counteronto the stack and then branching to subrou-tines at specified location(s) in the programmemory. Only the program counter is pushedonto the stack. If the contents of the register orstatus register (STATUS) are altered by theinterrupt service program which corrupts thedesired control sequence, the programmermust save these contents first.
External interrupts are triggered by a high tolow transition of INT and the related interruptrequest flag (EIF; bit 4 of INTC) will be set.When the interrupt is enabled, the stack is notfull and the external interrupt is active, a sub-routine call to location 04H will occur. The in-terrupt request flag (EIF) and EMI bits will becleared to disable other interrupts.
The internal Timer/event Counter interrupt isinitialized by setting the Timer/event Counter
Labels Bits Function
C 0C is set if the operation results in a carry during an addition operation or if aborrow does not take place during a subtraction operation; otherwise C iscleared. Also it is affected by a rotate through carry instruction.
AC 1AC is set if the operation results in a carry out of the low nibbles in addition orno borrow from the high nibble into the low nibble in subtraction; otherwise ACis cleared.
Z 2Z is set if the result of an arithmetic or logic operation is zero; otherwise Z iscleared.
OV 3OV is set if the operation results in a carry into the highest-order bit but not acarry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD 4PD is cleared by system power-up or executing the “CLR WDT” instruction. PDis set by executing the “HALT” instruction.
TO 5TO is cleared by system power-up or executing the “CLR WDT” or “HALT”instruction. TO is set by a WDT time-out.
− 6 Undefined, read as “0”.
− 7 Undefined, read as “0”.
STATUS Register
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interrupt request flag (TF; bit 5 of INTC),caused by a timer overflow. When the interruptis enabled, the stack is not full and the TF bit isset, a subroutine call to location 08H will occur.The related interrupt request flag (TF) will bereset and the EMI bit cleared to disable furtherinterrupts.
During the execution of an interrupt subroutine,other interrupt acknowledgements are held un-til the “RETI” instruction is executed or the EMIbit and the related interrupt control bit are setto 1 (of course, if the stack is not full). To returnfrom the interrupt subroutine, “RET” or “RETI”may be invoked. RETI will set the EMI bit toenable an interrupt service, but RET will not.
No. Interrupt Source Priority Vector
a External interrupt 1 04H
bTimer/eventCounter overflow 2 08H
Interrupts, occuring in the interval between therising edges of two consecutive T2 pulses, willbe serviced on the latter of the two T2 pulses, ifthe corresponding interrupts are enabled. In
the case of simultaneous requests the prioritiesin the following table apply. These can bemasked by resetting the EMI bit.
The Timer/event Counter interrupt requestflag (TF), External interrupt request flag (EIF),Enable Timer/event Counter bit (ETI), Enableexternal interrupt bit (EEI) and Enable masterinterrupt bit (EMI) constitute an interrupt con-trol register (INTC) which is located at 0BH inthe data memory. EMI, EEI, ETI are used tocontrol the enabling/disabling of interrupts.These bits prevent the requested interruptfrom being serviced. Once the interrupt requestflags (TF, EIF) are set, they will remain in theINTC register until the interrupts are servicedor cleared by a software instruction.
It is suggested that a program does not usethe “CALL subroutine” within the interruptsubroutine. It because interrupts often occurin an unpredictable manner or need to be serv-iced immediately in some applications. If onlyone stack is left and enabling the interrupt isnot well controlled, the original control sequencewill be damaged once the “CALL” operates in theinterrupt subroutine.
Register Bit No. Label Function
INTC(0BH)
0 EMIControls the Master (Global) interrupt(1=enabled; 0=disabled)
1 EEIControls the external interrupt(1=enabled; 0=disabled)
2 ETIControls the Timer/event Counter interrupt(1=enabled; 0=disabled)
Oscillator ConfigurationThere are 2 oscillator circuits in the HT48R30.
Both of them are designed for system clocks,namely the RC oscillator and the Crystal oscil-lator, which are determined by the ROM codeoption. No matter what oscillator type is se-lected, the signal provides the system clock.The HALT mode stops the system oscillatorand resists the external signal to conservepower.
If an RC oscillator is used, an external resistorbetween OSC1 and VDD is required and theresistance must range from 51KΩ to 1MΩ. Thesystem clock, divided by 4, is available onOSC2, which can be used to synchronize exter-nal logic. The RC oscillator provides the mostcost effective solution. However, the frequencyof oscillation may vary with VDD, tempera-tures and the chip itself due to process vari-ations. It is, therefore, not suitable for timingsensitive operations where an accurate oscilla-tor frequency is desired.
If the Crystal oscillator is used, a crystal acrossOSC1 and OSC2 is needed to provide the feed-back and phase shift required for the oscillator,and no other external components are de-manded. Instead of a crystal, the resonator canalso be connected between OSC1 and OSC2 toget a frequency reference, but two external ca-pacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RCoscillator, and no external components are re-quired. Even if the system enters the power downmode, the system clock is stopped, but the WDT
oscillator still works with a period of approxi-mately 78µs. The WDT oscillator can be disabledby ROM code option to conserve power.
Watch Dog Timer - WDT
The clock source of WDT is implemented by andedicated RC oscillator (WDT oscillator) or in-struction clock (system clock divided by 4), de-cided by ROM code option. This timer isdesigned to prevent a software malfunction orsequence from jumping to an unknown locationwith unpredictable results. The Watch DogTimer can be disabled by a ROM code option. Ifthe Watch Dog Timer is disabled, all the execu-tions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillatorwith a period of 78µs normally) is selected, it isfirst divided by 256 (8-stages) to get the nomi-nal time-out period of approximately 20ms.This time-out period may vary with tempera-tures, VDD and process variations. By invokingthe WDT prescaler, longer time-out periods canbe realized. Writing data to WS2, WS1, WS0(bit 2,1,0 of the WDTS) can give different time-
System Oscillator
Watch Dog Timer
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out periods. If WS2, WS1, and WS0 all equal to1, the division ratio is up to 1:128, and themaximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clockmay still come from the instruction clock andoperate in the same manner except that in theHALT state the WDT may stop counting andlose its protecting purpose. In this situation thelogic can only be restarted by external logic.The high nibble and bit 3 of the WDTS arereserved for user’s defined flags, and the pro-grammer may use these flags to indicate somespecified status.
If the device operates in a noisy enviroment,using the on-chip RC oscillator (WDT OSC) isstrongly recommended, since the HALT willstop the system clock.
WS2 WS1 WS0 Division Ratio
0 0 0 1:1
0 0 1 1:2
0 1 0 1:4
0 1 1 1:8
1 0 0 1:16
1 0 1 1:32
1 1 0 1:64
1 1 1 1:128
The overflow of WDT under normal operationwill initialize “chip reset” and set the status bit“TO”. But in the HALT mode, the overflow willinitialize a “warm reset”, and only the PC andSP are reset to zero. To clear the contents ofWDT (including the WDT prescaler ), 3 meth-ods are adopted; external reset (a low level toRES), software instruction(s) and a “HALT” in-struction. The software instruction(s) include“CLR WDT” and the other set − “CLR WDT1”and “CLR WDT2”. Of these two types of instruc-tion, only one can be active depending on theROM code option − “CLR WDT times selectionoption”. If the “CLR WDT” is selected (ie.CLRWDT times equal one), any execution of
the “CLR WDT” instruction will clear the WDT.In the case that “CLR WDT1” and “CLR WDT2”are chosen (ie. CLRWDT times equal two),these two instructions must be executed toclear the WDT; otherwise, the WDT may resetthe chip as a result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the “HALT”instruction and results in the following...
• The system oscillator will be turned offbut the WDT oscillator keeps running (Ifthe WDT oscillator is selected).
• The contents of the on–chip RAM and reg-isters remain unchanged.
• WDT and WDT prescaler will be clearedand recounted again (If the clock of WDTis from the WDT oscillator).
• All of the I/O ports maintain their originalstatus.
• The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by meansof an external reset, an interrupt, an externalfalling edge signal on port A or a WDT overflow.An external reset causes a device initializationand the WDT overflow performs a “warm re-set”. After the TO and PD flags are examined,the reason for chip reset can be determined.The PD flag is cleared by system power-up orexecuting the “CLR WDT” instruction and is setwhen executing the “HALT” instruction. TheTO flag is set if the WDT time-out occurs, andcauses a wake-up that only resets the PC andSP; the others keep their original status.
The port A wake-up and interrupt methods canbe considered as a continuation of normal exe-cution. Each bit in port A can be independentlyselected to wake up the device by the ROM codeoption. Awakening from an I/O port stimulus,the program will resume execution of the nextinstruction. If it is awakening from an inter-rupt, two sequences may happen. If the relatedinterrupt(s) is (are) disabled or the interrupt(s)is enabled but the stack is full, the program willresume execution at the next instruction. If theinterrupt is enabled and the stack is not full,
WDTS Register
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the regular interrupt response takes place. Ifan interrupt request flag is set to “1” beforeentering the HALT mode, the wake-up functionof the related interrupt will be disabled.
Once the wake-up event(s) occurs, it takes 1024tSYS (system clock period) to resume normaloperation. In other words, a dummy period willbe inserted after wake-up. If the wake-up re-sults from an interrupt acknowledgement, theactual interrupt subroutine execution will bedelayed by one or more cycles. If the wake-upresults in the next instruction execution, thiswill be executed immediately after the dummyperiod is finished.
To minimize power consumption, all the I/Opins should be carefully managed before enter-ing the HALT status.
Reset
There are 3 ways in which a reset can occur:
• RES reset during normal operation
• RES reset during HALT
• WDT time-out reset during normal operation
The WDT time-out during HALT is differentfrom other chip reset conditions, since it canperform a “warm reset” that resets only PC andSP, leaving the other circuits keep their state.Some registers remain unchanged during otherreset conditions. Most registers are reset to the“initial condition” when the reset conditions aremet. By examining the PD flag and TO flag, theprogram can distinguish between different“chip resets”.
TO PD RESET Conditions
0 0 RES reset during power-up
u uRES reset during normaloperation
0 1 RES wake-up HALT
1 uWDT time-out during normaloperation
1 1 WDT wake-up HALT
Note: “u” means that “unchange”.
To guarantee that the system oscillator isstarted and stabilized, the SST (System Start-up Timer) provides an extra-delay to delay 1024system clock pulses when system power-up orthe system awakes from the HALT state.
When the system power-up occurs, the SSTdelay is added during the reset period. Butwhen the reset comes from the RES pin, theSST delay is disabled. Any wake-up from HALTwill enable the SST delay.
The chip reset statuses of the functional unitsare as shown.
PC 000H
Interrrupt Disable
Prescaler Clear
WDTClear. After masterreset, WDT beginscounting
Timer/event Counter Off
Input/output Ports Input mode
SPPoint to the top ofstack
Reset Timing Chart
Reset Circuit
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The states of the registers is summarized in thetable.
Note: “∗” means “warm reset”. “u” means “unchanged”. “x” means “unknown”.
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Timer/Event CounterA Timer/event Counter (TMR) is implementedin the HT48R30. The Timer/event Counter con-tains an 8-bit programmable count-up counterand the clock may come from an external sourceor the system clock divided by 4.
Using the internal instruction clock, there isonly one reference time-base. The externalclock input allows the user to count externalevents, measure time intervals or pulse widths,or to generate an accurate time base.
There are 2 registers related to Timer/eventCounter; TMR ([0DH]), TMRC ([0EH]). Twophysical registers are mapped to TMR location;writing TMR makes the starting value put in theTimer/event Counter Preload register and read-ing TMR gets the content of the Timer/eventCounter. The TMRC is a Timer/event Countercontrol register, which defines some options.
The TM0, TM1 bits define the operating mode.The Event count mode is used to count externalevents, which means the clock source comesfrom an external (TMR) pin. The Timer modefunctions as a normal timer with the clocksource coming from the instruction clock. Thepulse width measurement mode can be used tocount the high or low level duration of the ex-ternal signal (TMR). The counting is based onthe instruction clock.
In the Event count or Timer mode, once theTimer/event Counter starts counting, it willcount from the current contents in theTimer/event Counter to FFH. Once overflowoccurs, the counter is reloaded from theTimer/event Counter Preload register and gen-erates the interrupt request flag (TF; bit 5 ofINTC) at the same time.
Timer/Event Counter
Label (TMRC) Bits Function
— 0-2 Unused bits, read as “0”.
TE 3To define the TMR active edge of Timer/event Counter (0=active on low to high; 1=active on high to low)
TON 4To enable/disable timer counting(0=disabled; 1=enabled)
— 5 Unused bits, read as “0”.
TM0TM1
67
To define the operating mode01=Event count mode (External clock)10=Timer mode (Internal clock)11=Pulse width measurement mode00=Unused
TMRC Register
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In the pulse width measurement mode withthe TON and TE bits are equal to one, once theTMR has received a transient from low to high(or high to low if the TE bits is “0”) it will startcounting until the TMR returns to the originallevel and resets the TON. The measured resultwill remain in the Timer/event Counter even ifthe activated transient occurs again. In otherwords, only one cycle measurement can bedone. Until setting the TON, the cycle meas-urement will function again as long as it re-ceives further transient pulse. Note that, inthis operating mode, the Timer/eventCounter starts counting not according to thelogic level but according to the transientedges. In the case of counter overflows, thecounter is reloaded from the Timer/eventCounter Preload register and issues the inter-rupt request just like the other two modes.
To enable the counting operation, the TimerON bit (TON; bit 4 of TMRC) should be set to 1.In the pulse width measurement mode, theTON will be cleared automatically after themeasurement cycle is completed. But in theother two modes the TON can only be reset byinstructions. The overflow of the Timer/eventcounter is one of the wake-up sources. No mat-ter what the operation mode is, writing a 0 toETI can disable the interrupt service.
In the case of Timer/event Counter OFF condi-tion, writing data to the Timer/event Counter
Preload register will also reload that data toTimer/event Counter. But if the Timer/eventCounter is turned on, data written to theTimer/event Counter will only be kept in theTimer/event Counter Preload register. TheTimer/event Counter will still operate untiloverflow occurs.
When the Timer/event Counter (reading TMR)is read, the clock will be blocked to avoid errors.As clock blocking may results in a countingerror, blocking of the clock must be taken intoconsideration by the programmer.
Input/Output PortsThere are 22 bi-directional input/output linesin the HT48R30, labelled from PA to PC, whichare mapped to the data memory of [12H], [14H]and [16H] respectively. All of these I/O portscan be used for input and output operations.For input operation, these ports are non-latch-ing, that is, the inputs must be ready at the T2rising edge of instruction “MOV A,[m]”(m=12H, 14H or 16H). For output operation, allthe data is latched and remains unchangeduntil the output latch is rewritten.
Each I/O line has its own control register (PAC,PBC, PCC) to control the input/output configu-ration. With this control register, CMOS outputor schmitt trigger input with pull-high resistorstructures can be reconfigured dynamically
Input/Output Ports
HT48R30
22 20th May ’97
(i.e., on-the-fly) under software control. To func-tion as an input, the corresponding latch of thecontrol register must write “1”. The pull-highresistance will be exhibited automatically. Theinput source(s) also depend(s) on the controlregister. If the control register bit is “1”, theinput will read the pad state. If the controlregister bit is “0”, the contents of the latcheswill move to the internal bus. The latter ispossible in the “read-modify-write” instruction.For output function, CMOS is the only configu-ration. These control registers are mapped tolocations 13H, 15H and 17H.
After a chip reset, these input/output lines stayat high levels. Each bit of these intput/outputlatches can be set or cleared by “SET [m].i” and“CLR [m].i” (m=12H, 14H or 16H) instructions.
Some instructions first input data and thenfollow the output operations. For example,“SET [m].i”, “CLR [m].i”, “CPL [m]”, “CPLA[m]” read the entire port states into the CPU,execute the defined operations (bit-operation),and then write the results back to the latches orthe accumulator.
Each line of port A has the capability of waking-up the device. The highest two bits of port C arenot physically implemented; on reading them a“0” is returned whereas writing then results in ano-operation. Note that the pull-high optionsare not available for all I/O lines.
ROM Code OptionThe following table shows 7 kinds of ROM code option in the HT48R30. All of the ROM code optionsmust be defined to ensure proper system functioning.
Items Option Description
1 OP[7:0]OP0~OP7 → PA0~PA7Bit=0 Without wake upBit=1 With wake up
2 OP8Bit=0 RC modeBit=1 Crystal mode
3 OP9Bit=0 Two cycle CLRWDTBit=1 One cycle CLRWDT
4 OP10Unused bitThis bit must be set as “0” by default.
5 OP11Unused bitThis bit must be set as “0” by default.
6 OP12Bit=0 RC clock for WDT sourceBit=1 System clock for WDT source
7 OP13Bit=0 Enable WDTBit=1 Disable WDT
HT48R30
23 20th May ’97
PROM Programming & VerificationThe program memory used in the HT48R30 isarranged into a 2K×14 bits program PROM anda 1×14 bits option PROM. The program codeand option code are stored in the programPROM and option PROM. The programming ofPROM canbe summarized in 9 steps as de-scribed below:
• Power on
• Set VPP(RES) to 12.5V
• Set CS(PA5) to low
Let PA3~PA0(AD3~AD0) be the address anddata bus and the PA4(CLK) be the clock input.The data on the AD3~AD0 pins will be clockedinto or out the HT48R30 on the falling edge ofPA4(CLK) for PROM programming and verifi-cation.
The address data contains the code address (11bits) and two option bits. A complete write cyclewill contain 4 CLK cycles. The first cycle, bit0~3 of the address are latched into theHT48R30. The second and third cycles, bit 4~7and bit 8~10 are latched respectively. Thefourth cycle, bit 2 is the TSEL option bit and bit3 is the OSEL option bit. Bit 3 in third cycle andbit 0~1 in the fourth cycle are undefined. If theTSEL is “1” and the OSEL is “0”, the TESTmemory will be read. If the TSEL is “0” and theOSEL is “1”, the option PROM will be accessed.If both the TSEL and OSEL are “0”, the pro-gram PROM will be managed.
The code data is 14 bits wide. A completeread/write cycle contains 4 CLK cycles. In thefirst cycle, bit 0~3 of the code data are accessed.In the second and third, bit 4~7 and bit 8~11are accessed respectively. In the fourth cycle,bit 12~13 are accessed. Bit 14~15 are unde-fined. During code verification, reading will re-turn the result “00”.
Select the TSEL and OSEL to program andverify the program PROM and option PROM.Use the R/W(PA6) to select the programming orverification
The address is incremented by one automat-ically after a code verification cycle. If the un-continued address programming or verificationis accomplished, the automatic addressing in-crement is disabled. For the uncontinued ad-dress programming and verification, the CS pinmust return to high level for a programming orverification cycle, that is, if an uncontinuedaddress is managed, the programming or veri-fication cycle must be interrupted and restart-ed as well.
The related pins of PROM programming andverification are listed in the following table.
PinName Function Description
PA0 AD0 Bit 0 of address/data bus
PA1 AD1 Bit 1 of address/data bus
PA2 AD2 Bit 2 of address/data bus
PA3 AD3 Bit 3 of address/data bus
PA4 CLKSerial clock input foraddress and data
PA5 CS Chip select, active low
PA6 R/W Read/write control input
RES VPPProgramming powersupply
The timing charts of programming and verifica-tion are as shown. There is a LOCK signal forcode protection. If the LOCK is “1”, reading thecode will return the result “1”. However, if theLOCK is “0”, the code protection is disabled andthe code always can be read until the LOCK isprogrammed as “1”.
HT48R30
24 20th May ’97
Successive Verification
HT48R30
25 20th May ’97
Non-successive Verification
HT48R30
26 20th May ’97
Code Programming and Verification
HT48R30
27 20th May ’97
Non-successive Programming and Verification
Code Programming and Verification
HT48R30
28 20th May ’97
Successive Programming and Verification
HT48R30
29 20th May ’97
Instruction Set
Instruction Set Summary
Mnemonic Description InstructionCycle Flag Affected
Add data memory to ACCAdd ACC to data memoryAdd immediate data to ACCAdd data memory to ACC with carryAdd ACC to register with carrySubtract immediate data from ACCSubtract data memory from ACCSubtract data memory from ACC with result indata memorySubtract data memory from ACC with carrySubtract data memory from ACC with carry withresult in data memoryDecimal adjust ACC for addition with result indata memory
AND data memory to ACCOR data memory to ACCExclusive-OR data memory to ACCAND ACC to data memoryOR ACC to data memoryExclusive-OR ACC to data memoryAND immediate data to ACCOR immediate data to ACCExclusive-OR immediate data to ACCComplement data memoryComplement data memory with result in ACC
111
1(1)
1(1)
1(1)
111
1(1)
1
ZZZZZZZZZZZ
Increment &Decrement
INCA [m]INC [m]DECA [m]DEC [m]
Increment data memory with result in ACCIncrement data memoryDecrement data memory with result in ACCDecrement data memory
11(1)
11(1)
ZZZZ
HT48R30
30 20th May ’97
Mnemonic Description InstructionCycle Flag Affected
Rotate
RRA [m]RR [m]RRCA [m]
RRC [m]RLA [m]RL [m]RLCA [m]
RLC [m]
Rotate data memory right with result in ACCRotate data memory rightRotate data memory right through carry withresult in ACCRotate data memory right through carryRotate data memory left with result in ACCRotate data memory leftRotate data memory left through carry with resultin ACCRotate data memory left through carry
11(1)
1
1(1)
11(1)
1
1(1)
NoneNone
CC
NoneNone
CC
Data Move
MOV A,[m]MOV [m],AMOV A,x
Move data memory to ACCMove ACC to data memoryMove immediate data to ACC
11(1)
1
NoneNoneNone
Bit Operation
CLR [m].iSET [m].i
Clear bit of data memorySet bit of data memory
1(1)
1(1)NoneNone
Branch
JMP addrSZ [m]SZA [m]
SZ [m].iSNZ [m].iSIZ [m]SDZ [m]SIZA [m]
SDZA [m]
CALL addrRETRET A,x
RETI
Jump unconditionallySkip if data memory is zeroSkip if data memory is zero with data movementto ACCSkip if bit i of data memory is zeroSkip if bit i of data memory is not zeroSkip if increment data memory is zeroSkip if decrement data memory is zeroSkip if increment data memory is zero with resultin ACCSkip if decrement data memory is zero with resultin ACCSubroutine callReturn from subroutineReturn from subroutine and load immediate datato ACCReturn from interrupt
21(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
222
2
NoneNoneNone
NoneNoneNoneNoneNone
None
NoneNoneNone
None
HT48R30
31 20th May ’97
Mnemonic Description InstructionCycle Flag Affected
Table Read
TABRDC [m]
TABRDL [m]
Read ROM code (current page) to data memoryand TBLHRead ROM code (last page) to data memory andTBLH
No operationClear data memorySet data memoryClear Watchdog timerPre-clear Watchdog timerPre-clear Watchdog timerSwap nibbles of data memorySwap nibbles of data memory with result in ACCEnter power down mode
11(1)
1(1)
111
1(1)
11
NoneNoneNone
TO,PDTO(4),PD(4)
TO(4),PD(4)
NoneNone
TO,PD
Notes: x = 8 bits immediate datam = 7 bits data memory addressA = accumulatori = 0...7 number of bitsaddr = 11 bits program memory address√=Flag(s) is affected−=Flag(s) is not affected(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed one more cycle (4 system clocks).(2): If a skipping next instruction occurs, the execution cycle of instructions will be delayed one more cycle (4 system clocks). Otherwise the original instruction cycle(s) is unchanged.(3): (1) and (2)
(4): The flags may be affected by execution status. If the watchdog timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged.
HT48R30
32 20th May ’97
Instruction Definition
ADC A,[m] Add data memory and carry to the accumulator
Description The contents of the specified data memory, accumulator and the carry flagare added simultaneously, leaving the result in the accumulator.
Operation ACC ← ACC+[m]+C
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
ADCM A,[m] Add the accumulator and carry to data memory
Description The contents of the specified data memory, accumulator and the carry flagare added simultaneously, leaving the result in the specified data memory.
Operation [m] ← ACC+[m]+C
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
ADD A,[m] Add data memory to the accumulator
Description The contents of the specified data memory and the accumulator are added.The result is stored in the accumulator.
Operation ACC ← ACC+[m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
ADD A,x Add immediate data to the accumulator
Description The contents of the accumulator and the specified data are added, leavingthe result in the accumulator.
Operation ACC ← ACC+x
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
HT48R30
33 20th May ’97
ADDM A,[m] Add the accumulator to the data memory
Description The contents of the specified data memory and the accumulator are added.The result is stored in the data memory.
Operation [m] ← ACC+[m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
AND A,[m] Logical AND accumulator with data memory
Description Data in the accumulator and the specified data memory perform a bitwiselogical_AND operation. The result is stored in the accumulator.
Operation ACC ← ACC “AND” [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
AND A,x Logical AND immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logi-cal_AND operation. The result is stored in the accumulator.
Operation ACC ← ACC “AND” x
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
ANDM A,[m] Logical AND data memory with the accumulator
Description Data in the specified data memory and the accumulator perform a bitwiselogical_AND operation. The result is stored in the data memory.
Operation [m] ← ACC “AND” [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
HT48R30
34 20th May ’97
CALL addr Subroutine call
Description The instruction unconditionally calls a subroutine located at the indicatedaddress. The program counter increments once to obtain the address of thenext instruction, and pushes this onto the stack. The indicated address isthen loaded. Program execution continues with the instruction at this ad-dress.
Operation Stack ← PC+1PC ← addr
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
CLR [m] Clear data memory
Description The contents of the specified data memory are cleared to zero.
Operation [m] ← 00H
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
CLR [m].i Clear bit of data memory
Description The bit i of the specified data memory is cleared to zero.
Operation [m].i ← 0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
CLR WDT Clear watch dog timer
Description The WDT and the WDT Prescaler are cleared (re-counting from zero). Thepower down bit (PD) and time-out bit (TO) are cleared.
Operation WDT & WDT Prescaler ← 00HPD & TO ← 0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – 0 0 – – – –
HT48R30
35 20th May ’97
CLR WDT1 Preclear watch dog timer
Description The TD, PD flags, WDT and the WDT Prescaler has cleared (re-countingfrom zero), if the other preclear WDT instruction has been executed. Onlyexecution of this instruction without the other preclear instruction just setsthe indicated flag which implies this instruction has been executed and theTO and PD flags remain unchanged.
Operation WDT & WDT Prescaler ← 00H*PD & TO ← 0*
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – 0* 0* – – – –
CLR WDT2 Preclear watch dog timer
Description The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting fromzero), if the other preclear WDT instruction has been executed. Only execu-tion of this instruction without the other preclear instruction, sets theindicated flag which implies this instruction has been executed and the TOand PD flags remain unchanged.
Operation WDT & WDT Prescaler ← 00H*PD & TO ← 0*
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – 0* 0* – – – –
CPL [m] Complement data memory
Description Each bit of the specified data memory is logically complemented (1’s comple-ment). Bits which previously contained a one are changed to zero andvice-versa.
Operation [m] ← [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
HT48R30
36 20th May ’97
CPLA [m] Complement data memory-place result in the accumulator
Description Each bit of the specified data memory is logically complemented (1’s comple-ment). Bits which previously contained a one are changed to zero andvice-versa. The complemented result is stored in the accumulator and thecontents of the data memory remain unchanged.
Operation ACC ← [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
DAA [m] Decimal-Adjust accumulator for addition
Description The accumulator value is adjusted to the BCD (Binary Code Decimal) code.The accumulator is divided into two nibbles. Each nibble is adjusted to theBCD code and an internal carry (AC1) will be done if the low nibble of theaccumulator is greater than 9. The BCD adjustment is done by adding 6 tothe original value if the original value is greater than 9 or a carry (AC or C)is set; otherwise the original value remains unchanged. The result is storedin the data memory and only the carry flag (C) may be affected.
Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ← (ACC.3~ACC.0)+6, AC1=ACelse [m].3~[m].0) ← (ACC.3~ACC.0), AC1=0andIf ACC.7~ACC.4+AC1 >9 or C=1then [m].7~[m].4 ← ACC.7~ACC.4+6+AC1,C=1else [m].7~[m].4 ← ACC.7~ACC.4+AC1,C=C
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – √
DEC [m] Decrement data memory
Description Data in the specified data memory is decremented by one.
Operation [m] ← [m]–1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
HT48R30
37 20th May ’97
DECA [m] Decrement data memory-place result in the accumulator
Description Data in the specified data memory is decremented by one, leaving the resultin the accumulator. The contents of the data memory remain unchanged.
Operation ACC ← [m]–1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
HALT Enter power down mode
Description This instruction stops program execution and turn off the system clock. Thecontents of the RAM and registers are retained. The WDT and prescaler arecleared. The power down bit (PD) is set and the WDT time-out bit (TO) iscleared.
Operation PC ← PC+1PD ← 1TO ← 0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – 0 1 – – – –
INC [m] Increment data memory
Description Data in the specified data memory is incremented by one.
Operation [m] ← [m]+1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
INCA [m] Increment data memory-place result in the accumulator
Description Data in the specified data memory is incremented by one, leaving the resultin the accumulator. The contents of the data memory remain unchanged.
Operation ACC ← [m]+1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
HT48R30
38 20th May ’97
JMP addr Directly jump
Description Bits 0~10 of the program counter are replaced with the directly-specifiedaddress unconditionally, and control is passed to this destination.
Operation PC ← addr
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
MOV A,[m] Move data memory to the accumulator
Description The contents of the specified data memory are copied to the accumulator.
Operation ACC ← [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
MOV A,x Move immediate data to the accumulator
Description The 8-bit data specified by the code is loaded into the accumulator.
Operation ACC ← x
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
MOV [m],A Move the accumulator to data memory
Description The contents of the accumulator are copied to the specified data memory (oneof the data memory).
Operation [m] ← ACC
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
39 20th May ’97
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation PC ← PC+1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
OR A,[m] Logical OR accumulator with data memory
Description Data in the accumulator and the specified data memory (one of the datamemory) perform a bitwise logical_OR operation. The result is stored in theaccumulator.
Operation ACC ← ACC “OR” [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
OR A,x Logical OR immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logical_ORoperation. The result is stored in the accumulator.
Operation ACC ← ACC “OR” x
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
ORM A,[m] Logical OR data memory with the accumulator
Description Data in the data memory (one of the data memory) and the accumulatorperform a bitwise logical_OR operation. The result is stored in the datamemory.
Operation [m] ← ACC “OR” [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
HT48R30
40 20th May ’97
RET Return from subroutine
Description The program counter is restored from the stack. This is a two cycle instruc-tion.
Operation PC ← Stack
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
RET A,x Return and place immediate data in the accumulator
Description The program counter is restored from the stack and the accumulator loadedwith the specified 8-bit immediate data.
Operation PC ← StackACC ← x
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
RETI Return from interrupt
Description The program counter is restored from the stack, and interrupts are enabledby setting the EMI bit. EMI is the enable master(global) interrupt bit (bit 0;register INTC).
Operation PC ← StackEMI ← 1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
41 20th May ’97
RL [m] Rotate data memory left
Description The contents of the specified data memory are rotated one bit left with bit 7rotated into bit 0.
Operation [m].(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)[m].0 ← [m].7
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
RLA [m] Rotate data memory left-place result in the accumulator
Description Data in the specified data memory is rotated one bit left with bit 7 rotatedinto bit 0, leaving the rotated result in the accumulator. The contents of thedata memory remain unchanged.
Operation ACC.(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)ACC.0 ← [m].7
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
RLC [m] Rotate data memory left through carry
Description The contents of the specified data memory and the carry flag are rotated onebit left. Bit 7 replaces the carry bit; the original carry flag is rotated into thebit 0 position.
Operation [m].(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)[m].0 ← CC ← [m].7
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – √
HT48R30
42 20th May ’97
RLCA [m] Rotate left through carry-place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated one bit left.Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0position. The rotated result is stored in the accumulator but the contents ofthe data memory remain unchanged.
Operation ACC.(i+1) ← [m].i; [m].i:bit i of the data memory (i=0-6)ACC.0 ← CC ← [m].7
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – √
RR [m] Rotate data memory right
Description The contents of the specified data memory are rotated one bit right with bit0 rotated to bit 7.
Operation [m].i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)[m].7 ← [m].0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
RRA [m] Rotate right-place result in the accumulator
Description Data in the specified data memory is rotated one bit right with bit 0 rotatedinto bit 7, leaving the rotated result in the accumulator. The contents of thedata memory remain unchanged.
Operation ACC.(i) ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)ACC.7 ← [m].0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
43 20th May ’97
RRC [m] Rotate data memory right through carry
Description The contents of the specified data memory and the carry flag are togetherrotated one bit right. Bit 0 replaces the carry bit; the original carry flag isrotated into the bit 7 position.
Operation [m].i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)[m].7 ← CC ← [m].0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – √
RRCA [m] Rotate right through carry-place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated one bitright. Bit 0 replaces the carry bit and the original carry flag is rotated intothe bit 7 position. The rotated result is stored in the accumulator. Thecontents of the data memory remain unchanged.
Operation ACC.i ← [m].(i+1); [m].i:bit i of the data memory (i=0-6)ACC.7 ← CC ← [m].0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – √
SBC A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carryflag are subtracted from the accumulator, leaving the result in the accumu-lator.
Operation ACC ← ACC+[m]+C
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
HT48R30
44 20th May ’97
SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carryflag are subtracted from the accumulator, leaving the result in the datamemory.
Operation [m] ← ACC+[m]+C
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
SDZ [m] Skip if decrement data memory is zero
Description The contents of the specified data memory are decremented by one. If theresult is zero, the next instruction is skipped. If the result is zero, thefollowing instruction, fetched during the current instruction execution, isdiscarded and a dummy cycle is replaced to get the proper instruction (2cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]–1)=0, [m] ← ([m]–1)
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SDZA [m] Decrement data memory-place result in ACC, skip if zero
Description The contents of the specified data memory are decremented by one. If theresult is zero, the next instruction is skipped. The result is stored in theaccumulator but the data memory remains unchanged. If the result is zero,the following instruction, fetched during the current instruction execution,is discarded and a dummy cycle is replaced to get the proper instruction (2cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]–1)=0, ACC ← ([m]–1)
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
45 20th May ’97
SET [m] Set data memory
Description Each bit of the specified data memory is set to one.
Operation [m] ← FFH
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SET [m].i Set bit of data memory
Description Bit “i” of the specified data memory is set to one.
Operation [m].i ← 1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SIZ [m] Skip if increment data memory is zero
Description The contents of the specified data memory are incremented by one. If theresult is zero, the following instruction, fetched during the current instruc-tion execution, is discarded and a dummy cycle is replaced to get the properinstruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, [m] ← ([m]+1)
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SIZA [m] Increment data memory-place result in ACC, skip if zero
Description The contents of the specified data memory are incremented by one. If theresult is zero, the next instruction is skipped and the result is stored in theaccumulator. The data memory remains unchanged. If the result is zero, thefollowing instruction, fetched during the current instruction execution, isdiscarded and a dummy cycle is replaced to get the proper instruction (2cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ← ([m]+1)
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
46 20th May ’97
SNZ [m].i Skip if bit “i” of the data memory is not zero
Description If bit “i” of the specified data memory is not zero, the next instruction isskipped. If bit “i” of the data memory is not zero, the following instruction,fetched during the current instruction execution, is discarded and a dummycycle is replaced to get the proper instruction (2 cycles). Otherwise proceedwith the next instruction (1 cycle).
Operation Skip if [m].i≠0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SUB A,[m] Subtract data memory from the accumulator
Description The specified data memory is subtracted from the contents of the accumula-tor, leaving the result in the accumulator.
Operation ACC ← ACC+[m]+1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
SUBM A,[m] Subtract data memory from the accumulator
Description The specified data memory is subtracted from the contents of the accumula-tor, leaving the result in the data memory.
Operation [m] ← ACC+[m]+1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
SUB A,x Subtract immediate data from the accumulator
Description The immediate data specified by the code is subtracted from the contents ofthe accumulator, leaving the result in the accumulator.
Operation ACC ← ACC+x+1
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – √ √ √ √
HT48R30
47 20th May ’97
SWAP [m] Swap nibbles within the data memory
Description The low-order and high-order nibbles of the specified data memory (one ofthe data memories) are interchanged.
Operation [m].3~[m].0 ↔ [m].7~[m].4
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SWAPA [m] Swap data memory-place result in the accumulator
escription The low-order and high-order nibbles of the specified data memory areinterchanged, writing the result to the accumulator. The contents of the datamemory remain unchanged.
Description If the contents of the specified data memory are zero, the following instruc-tion, fetched during the current instruction execution, is discarded and adummy cycle is replaced to get the proper instruction. This is a 2 cycleinstruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
48 20th May ’97
SZA [m] Move data memory to ACC, skip if zero
Description The contents of the specified data memory are copied to the accumulator. Ifthe contents is zero, the following instruction, fetched during the currentinstruction execution, is discarded and a dummy cycle is replaced to get theproper instruction (2 cycles). Otherwise proceed with the next instruction (1cycle).
Operation Skip if [m]=0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
SZ [m].i Skip if bit “i” of the data memory is zero
Description If bit “i” of the specified data memory is zero, the following instruction,fetched during the current instruction execution, is discarded and a dummycycle is replaced to get the proper instruction (2 cycles). Otherwise proceedwith the next instruction (1 cycle).
Operation Skip if [m].i=0
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
TABRDC [m] Move ROM code (current page) to TBLH & data memory
Description The low byte of ROM code (current page) addressed by the table pointer(TBLP) is moved to the specified data memory and the high byte transferedto TBLH directly.
Operation [m] ← ROM code (low byte)TBLH ← ROM code (high byte)
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
HT48R30
49 20th May ’97
TABRDL [m] Move ROM code (last page) to TBLH & data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP)is moved to the specified data memory and the high byte transfered to TBLHdirectly.
Operation [m] ← ROM code (low byte)TBLH ← ROM code (high byte)
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – – – –
XOR A,[m] Logical XOR accumulator with data memory
Description Data in the accumulator and the indicated data memory perform a bitwiselogical Exclusive_OR operation and the result is stored in the accumulator.
Operation ACC ← ACC “XOR” [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
XORM A,[m] Logical XOR data memory with the accumulator
Description Data in the indicated data memory and the accumulator perform a bitwiselogical Exclusive_OR operation. The result is stored in the data memory. Thezero flag is affected.
Operation [m] ← ACC "XOR" [m]
Affected flag(s)TC2 TC1 TO PD OV Z AC C
– – – – – √ – –
XOR A,x Logical XOR immediate data to the accumulator
Description Data in the the accumulator and the specified data perform a bitwise logicalExclusive_OR operation. The result is stored in the accumulator. The zeroflag is affected.
