© 1995
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
mPD780973(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
1997
Document No. U12759EJ1V0PM00 (1st edition)Date Published August 1997 NPrinted in Japan
The information contained in this document is being issued in advance of the production cycle for thedevice. The parameters for the device may change before final production or NEC Corporation, at its owndiscretion, may withdraw the device prior to its production.
DESCRIPTIONmPD780973(A) is a product in the mPD780973 subseries within the 78K/0 series, which incorporates meter controller/
driver, sound generator, LCD controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions
and many other peripheral hardwares.
A flash memory product capable of operating in the same power supply voltage range as the mask ROM product,
mPD78F0974, and other development tools are being developed.
For the details of functional description, refer to the following user’s manual.
mPD780973(A), 78F0974 User’s Manual : to be published soon
78K/0 Series User’s Manual Instructions : U12326E
FEATURES
• On-chip meter controller/driver: PWM output (9-bit resolution): 16
• On-chip sound generator: 1 channel
• On-chip ROM and RAM
• Internal ROM: 24 Kbytes
• Internal high-speed RAM: 768 bytes
• LCD display RAM: 20 ¥ 4 bits
• On-chip EEPROMTM (readable/writable by software): 256 bytes
• Instruction execution time can be varied from high speed (0.24 ms) to low speed (3.81 ms)
• I/O ports: 56 (including segment signal output dual-function pins)
• 8-bit resolution A/D converter: 5 channels
• Serial interface: 2 channels
• Timer: 6 channels
• Supply voltage: VDD = 4.5 to 5.5 V
APPLICATION FIELDAutomotive meter (dashboard) control
2
mPD780973(A)
ORDERING INFORMATION
Part Number Package Quality grade
mPD780973GF(A)-¥¥¥-3B9 80-pin plastic QFP (14 ¥ 20 mm) Special
Remark ¥¥¥ indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published byNEC Corporation to know the specification of quality grade on the devices and its recommended applications.
3
mPD780973(A)
78K/0 SERIES DEVELOPMENT
The products in the 78K/0 series are listed below. The names enclosed in boxes are subseries names.
Note Under planning
100 pins
100 pins
100 pins
For Driving FIPTM
For Driving LCD
For Meter Control
PD780208100 pins78K/0series
PD780228100 pins
PD78044H80 pins
80 pins
PD780308100 pins
For LV
PD78097380 pins
PD78P091464 pins
PD780308Y
PD78064B100 pins
100 pins PD78064 PD78064Y
80 pins
64 pins
64 pins
PD78018F64 pins PD78018FY
PD7801464 pins PD78014Y
PD78000164 pins
PD7800264 pins PD78002Y
PD78083
Adds timer to the PD78054 with enhanced external interface function
Under mass production
Y subseries supports I2C bus.
Under development
ROM-less model of the PD78078
Enhanced serial I/O of the PD78078Y with limited function
Enhanced l/O, FIP C/D of the PD78044F; Total number of display outputs: 53
Enhanced I/O, FIP C/D of the PD78044H; Total number of display outputs: 48
Adds N-ch open drain I/O to the PD78044; Total number of display outputs: 34
Low EMI noise model of the PD78054
Enhanced SIO of the PD78064 with extended ROM and RAM
Controller/driver for driving Automotive meter provided
PWM output, LV digital code decoder, and Hsync counter provided
Low EMI noise model of the PD78064
Subseries for driving LCD with UART provided
Adds UART and D/A to the PD78014 with enhanced I/O
Enhanced A/D of the PD780024
Enhanced serial I/O of the PD78018F, low EMI noise model
Low-voltage model (1.8 V) of the PD78014 with increased choice of ROM and RAM capacities
Adds A/D and 16-bit timer to the PD78002
Adds A/D to the PD78002
Basic subseries for control applications
UART provided, low-voltage (1.8 V) operation42/44 pins
µ
µµ
µ
µ
µ
µ
µµ
µ
µ
µµ
µ
µ
µ
µ
µµ
µµ
µ
µ
For Inverter Control
PD78096464 pins
64 pins
Enhanced A/D of the PD780924
Inverter control circuit and UART provided, low EMI noise model
µ
µ
PD78044F80 pins Basic subseries for driving FIP; Total number of display outputs: 34µ
µ µµ
µ
µ
µ
µ
µ
µ
80 pins Enhanced serial I/O of the PD78054, low EMI noise modelµ
PD78014H64 pins Low EMI noise model of the PD78018Fµµ
For Control
PD78058F PD78058FY
PD78054 PD78054Y
PD780034 PD780034Y
PD780024 PD780024Y
µ
µµ
µ
µ
µµµ
PD780058 PD780058YNoteµµPD780018AYµ
PD78070A PD78070AYµµ
PD78078µ PD78078Yµ
100 pins Low EMI noise model of the PD78078PD78075Bµ PD78075BYµ
µ
µ
PD780924µ
Supporting IEBusTM
PD78098B80 pins
80 pins
Low EMI noise model of PD78098
Adds IEBus controller to the PD78054
µ µPD78098µ µ
4
mPD780973(A)
The major functional differences among the subseries are shown below.
Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O External
Subseries Name Capacity 8-bit 16-bit Watch WDT A/D A/D D/A Expansion
Control mPD78075B 32 K-40 K 4ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART: 1ch) 88 1.8 V Available
mPD78078 48 K-60 K
mPD78070A – 61 2.7 V
mPD780058 24 K-60 K 2ch 2ch 3ch (time-division UART: 1ch) 68 1.8 V
mPD78058F 48 K-60 K 3ch (UART: 1ch) 69 2.7 V
mPD78054 16 K-60 K 2.0 V
mPD780034 8 K-32 K – 8ch – 3ch (UART: 1ch, 51 1.8 V
mPD780024 8ch – time-division 3-wire: 1ch)
mPD78014H 2ch 53
mPD78018F 8 K-60 K
mPD78014 8 K-32 K 2.7 V
mPD780001 8 K – – 1ch 39 –
mPD78002 8 K-16 K 1ch – 53 Available
mPD78083 – 8ch 1ch (UART: 1ch) 33 1.8 V –
Inverter mPD780964 8 K-32 K 3ch Note – 1ch – 8ch – 2ch (UART: 2ch) 47 2.7 V Available
control mPD780924 8ch –
FIP mPD780208 32 K-60 K 2ch 1ch 1ch 1ch 8ch – – 2ch 74 2.7 V –
drive mPD780228 48 K-60 K 3ch – – 1ch 72 4.5 V
mPD78044H 32 K-48 K 2ch 1ch 1ch 68 2.7 V
mPD78044F 16 K-40 K 2ch
LCD mPD780308 48 K-60 K 2ch 1ch 1ch 1ch 8ch – – 3ch (time-division UART: 1ch) 57 2.0 V –
drive mPD78064B 32 K 2ch (UART: 1ch) 2.0 V
mPD78064 16 K-32 K
IEBus mPD78098B 40 K-60 K 2ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART: 1ch) 69 2.7 V Available
supported mPD78098 32 K-60 K
Meter mPD780973 24 K-32 K 3ch 1ch 1ch 1ch 5ch – – 2ch (UART: 1ch) 56 4.5 V –
control
LV mPD78P0914 32 K 6ch – – 1ch 8ch – – 2ch 54 4.5 V Available
Note 10-bit timer: 1 channel
VDD
MIN.Value
5
mPD780973(A)
FUNCTION OVERVIEW
Item Function
Internal ROM 24 Kbytes
Memory High-speed RAM 768 bytes
EEPROM 256 bytes
LCD display RAM 20 ¥ 4 bits
General-purpose registers 8 bits ¥ 32 registers (8 bits ¥ 8 registers ¥ 4 banks)
Instruction cycle 0.24 ms/0.48 ms/0.95 ms/1.91 ms/3.81 ms (at 8.38 MHz operation)
Instruction set • 16-bit operation
• Multiply/divide (8 bits ¥ 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, boolean operation)
I/O ports Total : 56
(Including segment signal output pins) • CMOS input : 5
• CMOS output : 16
• CMOS I/O : 35
A/D converter • 8-bit resolution ¥ 5 channels
• Power fail detector
LCD controller/driver • Segment signal output : Maximum 20
• Common signal output : Maximum 4
• Bias : 1/3
Serial interface • 3-wire serial I/O mode : 1 channel
• UART mode : 1 channel
Timer • 16-bit timer : 1 channel
• 8-bit timer : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
Meter controller/driver PWM output (9-bit resolution): 16
Sound generator 1 channel
Clock output 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.04 MHz, 2.09 MHz, 4.19 MHz, 8.38 MHz
(main system clock: at 8.38 MHz operation)
Vectored- Maskable Internal : 16
interrupt source External : 3
Non-maskable Internal : 1
Software 1
Supply voltage VDD (SMVDD) = 5V±10%
Operation ambient temperature TA = –40 to +85 °C
Package 80-pin plastic QFP (14 ¥ 20 mm)
6
mPD780973(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) .................................................................................................. 7
2. BLOCK DIAGRAM ............................................................................................................................. 9
3. PIN FUNCTIONS ................................................................................................................ .............. 103.1 Port Pins ..................................................................................................................................................... 10
3.2 Non-Port Pins ..............................................................................................................................................11
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................ 12
4. MEMORY SPACE ............................................................................................................................. 15
5. PERIPHERAL HARDWARE FUNCTION FEATURE ....................................................................... 165.1 Ports ............................................................................................................................................................ 16
5.2 Clock Generator ......................................................................................................................................... 17
5.3 Timer/Event Counter .................................................................................................................................. 17
5.4 Clock Output Control Circuit ...................................................................................................................... 20
5.5 A/D Converter ............................................................................................................................................. 21
5.6 Serial Interface ........................................................................................................................................... 22
5.7 LCD Controller/Driver ................................................................................................................................. 23
5.8 Sound Generator ........................................................................................................................................ 24
5.9 Meter Controller/Driver ............................................................................................................................... 24
5.10 EEPROM .................................................................................................................................................... 25
6. INTERRUPT FUNCTIONS ............................................................................................................... 26
7. STANDBY FUNCTIONS ................................................................................................................... 29
8. RESET FUNCTIONS .............................................................................................................. .......... 29
9. INSTRUCTION SET.......................................................................................................................... 30
10. ELECTRICAL SPECIFICATIONS (TARGET VALUE) ..................................................................... 32
11. PACKAGE DRAWING ...................................................................................................................... 42
APPENDIX A. DEVELOPMENT T OOLS .............................................................................................. 43
APPENDIX B. RELATED DOCUMENTS .............................................................................................. 46
7
mPD780973(A)
1. PIN CONFIGURATION (TOP VIEW)
• 80-Pin Plastic QFP (14 ¥ 20 mm)
mPD780973GF(A)-¥¥¥-3B9
Cautions 1. Connect the IC (Internally Connected) pin directly to V SS.
2. Connect the AV SS pin to V SS.
Remark When the mPD780973(A) is used in application fields that require reduction of the noise generated from
inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to
2 VDDs individually and connecting VSS to different ground lines, is recommended.
P90
/S12
P91
/S11
P92
/S10
P93
/S9
P94
/S8
P95
/S7
P96
/S6
P97
/S5
S4
S3
S2
S1
S0
CO
M3
CO
M2
CO
M1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM0
VLCD
SMVSS
SMVDD
P20/SM11
P21/SM12
P22/SM13
P23/SM14
P24/SM21
P25/SM22
P26/SM23
P27/SM24
P30/SM31
P31/SM32
P32/SM33
P33/SM34
P34/SM41
P35/SM42
P36/SM43
P37/SM44
SMVDD
SMVSS
P61/SGO/SGOF
P60/SGOA/PCL
P12
/AN
I2
P11
/AN
I1
P10
/AN
I0
AV
SS
P50
/SC
K
P51
/SO
P52
/SI
VD
D
VS
S
P53
/RxD
P54
/TxD
P40
/TI0
0
P41
/TI0
1
P42
/TI0
2
P43
/TIO
2
P44
/TIO
3
P87/S13
P86/S14
P85/S15
P84/S16
P83/S17
P82/S18
P81/TPO/S19
IC
X1
X2
VSS
VDD
RESET
P07
P06
P05
P04
P03
P02/INTP2
P01/INTP1
P00/INTP0
AVREF
P14/ANI4
P13/ANI3
8
mPD780973(A)
ANI0-ANI4 : Analog Input
AVREF : Analog Reference Voltage
AVSS : Analog Ground
COM0-COM3 : Common Output
IC : Internally Connected
INTP0-INTP2 : Interrupt from Peripherals
P00-P07 : Port0
P10-P14 : Port1
P20-P27 : Port2
P30-P37 : Port3
P40-P44 : Port4
P50-P54 : Port5
P60, P61 : Port6
P81-P87 : Port8
P90-P97 : Port9
PCL : Clock Output
RESET : Reset
RxD : Receive Data
S0-S19 : Segment Output
SCK : Serial Clock
SGO : Sound Generator Output
SGOA : Sound Generator Amplitude Output
SGOF : Sound Generator Frequency Output
SI : Serial Input
SM11-SM14, SM21-SM24, SM31-SM34, SM41-SM44
: Meter Output
SMVDD : Meter Controller Power Supply
SMVSS : Meter Controller Ground
SO : Serial Output
TI00-TI02 : Timer Input
TIO2, TIO3 : Timer Output/Event Counter Input
TPO : Prescaler Output
TxD : Transmit Data
VDD : Power Supply
VLCD : LCD Power Supply
VSS : Ground
X1, X2 : Crystal (Main System Clock)
9
mPD780973(A)
2. BLOCK DIAGRAM
TI00/P40-TI02/P42 16-bit TIMER0
8-bit TIMER1
8-bit TIMER/EVENTCOUNTER2
8-bit TIMER/EVENTCOUNTER3
WATCHDOGTIMER
WATCH TIMER
SERIALINTERFACE
UART
A/DCONVERTER
POWER FAILDETECTOR
INTERRUPTCONTROL
STANDBYCONTROL
CLOCK OUTPUTCONTROL
SOUNDGENERATOROUTPUT
TIO2/P43
TIO3/P44
SCK/P50
SO/P51
SI/P52
RxD/P53
TxD/P54
ANI0/P10-ANI4/P14
AVSS
AVREF
INTP0/P00-INTP2/P02
PCL/SGOA/P60
SGO/SGOF/P61
78K/0CPU CORE
ROM(24 KBytes)
EEPROM(256 Bytes)
RAM(768 Bytes)
VDD VSS IC
PORT0
PORT5
PORT1
PORT2
PORT3
PORT4
PORT6
PORT8
PORT9
LCDCONTROLLER/DRIVER
METERCONTROLLER/DRIVER
SYSTEMCONTROL
P00-P07
P50-P54
P10-P14
P20-P27
P30-P37
P40-P44
P60,P61
P81-P87
P90-P97
S0-S4
S5/P97-S12/P90
S13/P87-S18/P82S19/P81/TPOCOM0-COM3
VLCD
SM11/P20-SM14/P23
SM21/P24-SM24/P27
SM31/P30-SM34/P33
SM41/P34-SM44/P37
SMVDD
SMVSS
X1
X2
RESET
1 0
mPD780973(A)
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name I/O Function After ResetAlternate
Function
P00 to P02 I/O Port 0 Input INTP0 to INTP2
P03 to P07 8-bit input/output port. –
Input/output can be specified bit-wise.
When used an input port, an internal pull-up resistor can be
connected by software.
P10 to P14 Input Port 1 Input ANI0 to ANI4
5-bit input only port.
P20 to P23 Output Port 2 Hi-Z SM11 to SM14
P24 to P27 8-bit output only port. SM21 to SM24
P30 to P33 Output Port 3 Hi-Z SM31 to SM34
P34 to P37 8-bit output only port. SM41 to SM44
P40 to P42 I/O Port 4 Input TI00 to TI02
5-bit input/output port.
P43, P44 Input/output can be specified bit-wise. TIO2, TIO3
P50 I/O Port 5 Input SCK
P51 5-bit input/output port. SO
P52 Input/output can be specified bit-wize. SI
P53 RxD
P54 TxD
P60 I/O Port 6 Input PCL/SGOA
P61 2-bit input/output port. SGO/SGOF
Input/output can be specified bit-wise.
P81 I/O Port 8 Input S19/TPO
P82 to P87 7-bit input/output port. S18 to S13
Input/output can be specified bit-wise.
Input/output port/segment signal output function can be specified
in 2-bit unit by the LCD display control register (LCDC).
P90 to P97 I/O Port 9 Input S12 to S5
8-bit input/output port.
Input/output can be specified bit-wise.
Input/output port/segment signal output function can be specified
in 2-bit unit by the LCD display control register (LCDC).
1 1
mPD780973(A)
3.2 Non-Port Pins
Pin Name I/O Function After ResetAlternate
Function
INTP0 to INTP2 Input External interrupt input by which the effective edge (rising edge, Input P00 to P02
edge, or both rising edge and falling edge) can be specified
SI Input Serial interface serial data input Input P52
SO Output Serial interface serial data output Input P51
SCK I/O Serial interface serial clock input/output Input P50
RxD Input Serial data input for asynchronous serial interface Input P53
TxD Output Serial data output for asynchronous serial interface Input P54
TI00 Input Capture trigger signal input to capture register (CR00) Input P40
TI01 Capture trigger signal input to capture register (CR01) P41
TI02 Capture trigger signal input to capture register (CR02) P42
TIO2 I/O 8-bit timer (TM2) input/output Input P43
TIO3 8-bit timer (TM3) input/output P44
PCL Output Clock output (for trimming of main system clock) Input SGOA/P60
SGOA Output Sound generator signal output Input PCL/P60
SGOF SGO/P61
SGO SGOF/P61
TPO Output 16-bit timer (TM0) prescaler output Input P81/S19
S0 to S4 Output LCD controller/driver segment signal output Output –
S5 to S12 Input P97 to P90
S13 to S18 P87 to P82
S19 P81/TPO
COM0 to COM3 Output LCD controller/driver common signal output Output –
VLCD – LCD drive voltage – –
SM11 to SM14 Output Meter control signal output Hi-Z P20 to P23
SM21 to SM24 P24 to P27
SM31 to SM34 P30 to P33
SM41 to SM44 P34 to P37
ANI0 to ANI4 Input A/D converter analog input Input P10 to P14
AVREF Input A/D converter reference voltage input (shared with analog – –
power supply)
AVSS – A/D converter ground potential. Same potential as VSS. – –
RESET Input System reset input – –
X1 Input Main system clock oscillation crystal connection – –
X2 – – –
SMVDD – Power supply for meter controller/driver – –
SMVSS – Ground potential for meter controller/driver – –
VDD – Positive power supply – –
VSS – Ground potential – –
IC – Internally connected. Connect directly to VSS. – –
1 2
mPD780973(A)
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For
the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin
Pin NameInput/output
I/O Recommended Connection When Not UsedCircuit Type
P00/INTP0 8-A Input/output Independently connect to VSS through resistor.
P01/INTP1
P02/INTP2
P03 to P07
P10/ANI0 to P14/ANI4 9 Input Independently connect to VDD or VSS through resistor.
P20/SM11 to P23/SM14 4 Output
P24/SM21 to P27/SM24
P30/SM31 to P33/SM34
P34/SM41 to P37/SM44
P40/TI00 to P42/TI02 8 Input/output
P43/TIO2
P44/TIO3
P50/SCK
P51/SO 5
P52/SI 8
P53/RxD
P54/TxD 5
P60/SGOA/PCL
P61/SGO/SGOF
P81/S19/TPO 17-A
P82/S18 to P87/S13
P90/S12 to P97/S5
S0-S4 17 Output Leave open.
COM0 to COM3 18
VLCD – –
RESET 2 Input –
SMVDD – – Connect to VDD.
SMVSS Connect to VSS.
AVREF
AVSS
IC Directly connect to VSS.
1 3
mPD780973(A)
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 4
Type 5
Type 8
Type 8-A
Type 9
IN
Schmitt-triggered input with hysteresis characteristic
Push-pull output that can make output high impedance
(both P-ch and N-ch are off)
VDD
N-ch
P-ch
outputdisable
data
OUT
VDD
N-ch
P-ch
outputdisable
data
IN/OUT
inputenable
VDD
N-ch
P-ch
outputdisable
data
IN/OUT
VDD
N-ch
P-ch
outputdisable
data
IN/OUT
pullupenable
VDD
P-ch
N-ch
P-ch
IN +–
Comparator
VREF (Threshold Voltage)
input enable
1 4
mPD780973(A)
Figure 3-1. Pin Input/Output Circuits (2/2)
P-ch
N-chVLC2
P-ch
N-chVLC1
VLC0
SEGdata OUT
P-ch
N-ch
Type 17 Type 17-A
Type 18
P-ch
N-chVLC2
P-ch
N-chVLC1
VLC0
COMdata
OUT
P-ch
N-ch
N-ch
P-ch
pullupenable
data
outputdisable
inputenable
VLC0
VLC1
SEGdata
VLC2
N-ch
P-ch
N-ch
P-ch
VDD
P-ch
VDD
P-ch
N-ch
IN/OUT
P-ch
N-ch
1 5
mPD780973(A)
4. MEMORY SPACE
The memory map of mPD780973(A) is shown in Figure 4-1.
Figure 4-1. Memory Map
FF00H
FFFFH
FEFFH
FEE0HFEDFH
FC00HFBFFH
FA6DHFA6CH
FA59HFA58H
FA00HF9FFH
F900HF8FFH
6000H5FFFH
0000H
5FFFH
1000H0FFFH
0000H
0800H07FFH
0080H007FH
0040H003FH
Data memoryspace
Program memoryspace
Special function register (SFR)256 × 8 bits
General registers32 × 8 bits
Internal high-speed RAM768 × 8 bits
Use prohibited
LCD display RAM20 × 4 bits
Use prohibited
EEPROM256 × 8 bits
Use prohibited
Internal ROM24576 × 8 bits
Program area
CALLF entry area
Program area
CALLT table area
Vector table area
1 6
mPD780973(A)
5. PERIPHERAL HARDWARE FUNCTION FEATURE
5.1 Ports
There are three kinds of I/O port.
• CMOS input (Port 1) : 5
• CMOS output (Port 2, Port 3) : 16
• CMOS input/output (Port 0, Port 4 to Port 6, Port 8, Port 9) : 35
Total : 56
Table 5-1. Functions of Ports
Name Pin Name Function
Port 0 P00-P07 Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Port 1 P10-P14 Dedicated input port
Port 2 P20-P27 Dedicated output port
Port 3 P30-P37 Dedicated output port
Port 4 P40-P44 Input/output port. Input/output specifiable bit-wise.
Port 5 P50-P54 Input/output port. Input/output specifiable bit-wise.
Port 6 P60, P61 Input/output port. Input/output specifiable bit-wise.
Port 8 P81-P87 Input/output port. Input/output specifiable bit-wise.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display control
register (LCDC).
Port 9 P90-P97 Input/output port. Input/output specifiable bit-wise.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display control
register (LCDC).
1 7
mPD780973(A)
5.2 Clock Generator
An on-chip main system clock generator is provided.
The instruction execution time can be changed.
• 0.24 ms/0.48 ms/0.95 ms/1.91 ms/3.81 ms (Main system clock: at 8.38-MHz operation)
Figure 5-1. Clock Generator Block Diagram
5.3 Timer/Event Counter
Six timer/event counter channels are incorporated.
• 16-bit timer : 1 channel
• 8-bit timer : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
Table 5-2. Timer/Event Counter Operations
16-bit Timer 8-bit Timer 8-bit Timer/ Watch Timer Watchdog
TM0 TM1 Event Counter Timer
TM2, TM3
Operating Interval timer — 1 channel 2 channels 1 channel 1 channel
mode External event counter — — 2 channels — —
Function Timer output — — 2 outputs — —
PWM output — — 2 outputs — —
Pulse width measurement 3 inputs — — — —
Square wave output — — 2 outputs — —
Divided output 1 output — — — —
Interrupt request 4 1 2 2 1
X1
X2
Main systemclock oscillator
STOP
fX
fX/2 fX/22 fX/23 fX/24
Prescaler
Prescaler
Clock to peripheralhardware
CPU clock(fCPU)
Standbycontrolcircuit
Selector
1 8
mPD780973(A)
Figure 5-2. 16-bit Timer 0 (TM0) Block Diagram
Figure 5-3. 8-bit Timer 1 (TM1) Block Diagram
fX/8
fX/16
fX/32
fX/64
Selector
TI02/P42
TI01/P41
TI00/P40
Noise rejectioncircuit
Noise rejectioncircuit
Noise rejectioncircuit
Prescaler1, 1/2, 1/4, 1/8
Edgedetector
Edgedetector
Edgedetector
Outputcontrolcircuit
16-bit timer register(TM0)
16-bit capture register 02(CR02)
16-bit capture register 01(CR01)
16-bit capture register 00(CR00)
Internal Bus
INTOVF
INTTM02
INTTM01
INTTM00
TPO/P81/S19
Internal bus
8-bit compare register 1(CR1)
MatchINTTM1
8-bit counter (TM1)
Clear
Internal bus
Selector
fX/23
fX/24
fX/25
fX/27
fX/29
fX/211
1 9
mPD780973(A)
Figure 5-4. 8-bit Timer/Event Counter 2 (TM2) Block Diagram
Figure 5-5. 8-bit Timer/Event Counter 3 (TM3) Block Diagram
Internal bus
8-bit compareregister 2 (CR2)
Match
8-bit counter 2 (TM2)Selector
Internal bus
TIO2/P43fX/23
fX/25
fX/27
fX/28
fX/29
fX/211
OVF
Clear
Output controlcircuit
Output controlcircuit
INTTM2
TIO2/P43
Internal bus
8-bit compareregister 3 (CR3)
Match
8-bit counter 3 (TM3)Selector
Internal bus
TIO3/P44fX/24
fX/26
fX/27
fX/28
fX/210
fX/212
OVF
Clear
Output controlcircuit
Output controlcircuit
INTTM3
TIO3/P44
2 0
mPD780973(A)
Figure 5-6. Watch Timer Block Diagram
Figure 5-7. Watchdog Timer Block Diagram
5.4 Clock Output Control Circuit
Clocks of the following frequency can be output as clock outputs.
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.04 MHz, 2.09 MHz, 4.19 MHz, 8.38 MHz (main system clock: at 8.38
MHz operation)
Figure 5-8. Clock Output Circuit Block Diagram
fX/27
fX/211
Selector PrescalerfW
fW24
fW25
fW26
fW27
fW28
fW29
Selector
Selector
5-bit counter
INTWTI
INTWT
fW212
fX/27 Prescaler
fW213
fW214
fW215
fW216
fW217
fW218
fW220
Selector Controlcircuit
INTWDTmaskableinterrupt request
RESET
INTWDTnon-maskableinterrupt request
fX
fX/2
fX/22
fX/23
fX/24
fX/25
fX/26
fX/27
Selector Clock control circuit Output control circuit PCL/SGOA/P60
2 1
mPD780973(A)
5.5 A/D Converter
Five 8-bit resolution A/D converter channels are incorporated.
This A/D converter has the following two functions.
• A/D conversion with 8-bit resolution
• Power fail detection function
Figure 5-9. A/D Converter Block Diagram
Figure 5-10. Power Fail Detector Block Diagram
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
Selector
Sample & hold circuit
Voltage comparator
Series resistor string
Tapselec-tor
AVREF
AVSS
INTAD
Successive approximationregister (SAR)
Controlcircuit
A/D conversion result register(ADCR1)
Internal bus
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
Mul
tiple
xer
A/D converter Comparator
Power fail comparethreshold value register
(PFT)
Internal bus
Selector INTAD
2 2
mPD780973(A)
5.6 Serial Interface
Two serial interface channels are incorporated.
• Serial interface UART
• Serial interface SIO3
Figure 5-11. Serial Interface UART Block Diagram
Figure 5-12. Serial Interface SIO3 Block Diagram
Internal bus
Receive buffer register(RXB)
Direction control circuit
Direction control circuitTransmit shift register
(TXS)
Transmit control circuitReceive shift register(RXS)
Receive control circuit INTSER
INTSR
Baud rategenerator
fSCKSelector fX/2-fX/28
INTSTRXD/P53
TXD/P54
Internal bus
Serial I/O shift register(SIO)
SI/P52
SO/P51
SCK/P50 Serial clock counter INTCSI
fX/22-fX/24
SelectorSerial clockcontrol circuit
2 3
mPD780973(A)
5.7 LCD Controller/Driver
An LCD controller/driver with the following functions is incorporated.
• Display mode: 1/4 duty (1/3 bias)
• 15 of the segment signal of outputs can be switched to input/output ports in units of 2 (P81/S19 to P87/S13,
P90/S12 to P97/S5).
Table 5-3. Maximum Number of Display Pixels
Bias Method Time Division Common Signal Used Maximum Number of Display Pixels
1/3 4 COM0 to COM3 80 (20 segments ¥ 4 commons)
Figure 5-13. LCD Controller/Driver Block Diagram
Internal bus
Displaydata memory
Segmentdata selector
Portoutput data
Segment driver Common driver
Timing controllerLCDCL
Selector
Prescaler
S0··········S4 S5/P97···········S19/P81 COM0 COM1 COM2 COM3
LCD drive voltagegenerator
fX217
fX216
fX215
fX214
VLCD
2 4
mPD780973(A)
5.8 Sound Generator
The sound generator has the function to sound the buzzer from an external speaker, and the following two signals
are output.
• Basic cycle output signal (with/without amplitude)
A buzzer signal with a variable frequency in a range of 0.5 to 3.8 kHz (at fX = 8.38 MHz) can be output.
By the AND operation between the basic cycle output signal and a 7-bit-resolution PWM signal, the amplitude
can be varied, so that the volume of the buzzer sound can be controlled.
• Amplitude output signal
A PWM signal with a 7-bit resolution for variable amplitude can be independently output.
Figure 5-14 Sound Generator Block Diagram
5.9 Meter Controller/Driver
The meter controller/driver is a function to drive a stepping motor for external meter control or cross coil.
• Can output PWM pulse with a resolution of 9 bits
• Can drive up to four 360° type meters
Figure 5-15 Meter Controller/Driver Block Diagram
Remark n = 1 to 4
fX
fX/2
Selector 5-bit counterBasic cycle PWMgeneration circuit
Amplitude generationcircuit
Internal bus
Selector SGO/SGOF/P61
SGOA/PCL/P60
Internal bus
Compare register
PWM pulsegeneration circuit
fX
fX/2
Selector Output control circuitSMn1 (sin+)
SMn2 (sin–)
2 5
mPD780973(A)
5.10 EEPROM
As data memory, the mPD780973(A) incorporates 256-byte EEPROM (Electrically Erasable PROM) in addition to
internal high-speed RAM (768 bytes). EEPROM is memory which can be read/written by a program. Unlike normal
data memory, data can also be retained during a power failure.
EEPROM is mapped on F900H to F9FFH in the data memory space.
Writing to EEPROM erases the memory contents in EEPROM and automatically performs data write operation.
Write operation is carried out for each byte. The time required for writing is approximately 4.15 ms (main system clock:
at 8.38 MHz operation).
Read/write operation for on-chip EEPROM is the same as for the internal high-speed RAM. The memory contents
can also be read during a write.
Figure 5-16. EEPROM Block Diagram
Internal bus
Data latch
EEPROM(256 × 8 bits)
Addresslatch
EEPROM timer
Read/writecontroller
Write terminationINTWE
Prescaler fX
2 6
mPD780973(A)
6. INTERRUPT FUNCTIONS
There are twenty-one of interrupt functions of three different kinds, as shown below.
• Non-maskable interrupt : 1
• Maskable interrupt : 19
• Software interrupt : 1
Table 6-1. Interrupt Source List
Interrupt Default Interrupt Source Internal/
Type PriorityNote 1 Name Trigger External
Non- — INTWDT Watchdog timer overflow Internal 0004H (A)
maskable (with non-maskable interrupt selected)
Maskable 0 INTWDT Watchdog timer overflow (with interval timer selected) (B)
1 INTAD End of A/D conversion 0006H
2 INTOVF 16-bit timer overflow 0008H
3 INTTM00 TI00 valid edge detection 000AH (C)
4 INTTM01 TI01 valid edge detection 000CH
5 INTTM02 TI02 valid edge detection 000EH
6 INTP0 Pin input edge detection External 0010H (D)
7 INTP1 0012H
8 INTP2 0014H
9 INTCSI End of serial interface SIO3 transfer Internal 0016H (B)
10 INTSER Generation of serial interface UART receive error 0018H
11 INTSR End of serial interface UART reception 001AH
12 INTST End of serial interface UART transmission 001CH
13 INTTM1 Generation of 8-bit timer register and capture 001EH
register (CR1) match signal
14 INTTM2 Generation of 8-bit timer register and capture 0020H
register (CR2) match signal
15 INTTM3 Generation of 8-bit timer register and capture 0022H
register (CR3) match signal
16 INTWE End of EEPROM write 0024H
17 INTWTI Watch timer overflow 0026H
18 INTWT Reference time interval signal from watch timer 0028H
Software — BRK BRK instruction execution — 003EH (E)
Notes 1. The default priority is the priority applicable when two or more maskable interrupt requests are generated
simultaneously. 0 is the highest priority, and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
VectorTable
Address
BasicConfigurationTypeNote 2
2 7
mPD780973(A)
Figure 6-1. Basic Configuration of Interrupt Functions (1/2)
(A) Internal non-maskable interrupt
(B) Internal maskable interrupt
(C) External maskable interrupt (16-bit timer capture input)
Internal bus
Interruptrequest
Prioritycontrolcircuit
Vector tableaddressgenerator
Standby releasesignal
Internal bus
MK IE PR ISP
IFInterruptrequest
Prioritycontrolcircuit
Vector tableaddressgenerator
Standbyreleasesignal
Internal bus
MK IE PR ISP
IFSamplingclock
Prioritycontrolcircuit
Vector tableaddressgenerator
Edgedetector
Interruptrequest
Prescaler mode register (PRM0)
Standbyreleasesignal
2 8
mPD780973(A)
Figure 6-1. Basic Configuration of Interrupt Functions (2/2)
(D) External maskable interrupt (except 16-bit timer capture input)
(E) Software interrupt
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority hung-up flag
Internal bus
External interruptedge enable register
(EGP, EGN)MK IE PR ISP
IFPriority control
circuit
Vector tableaddressgenerator
Edgedetector
Interruptrequest
Standbyreleasesignal
Internal bus
Interruptrequest
Priority controlcircuit
Vector tableaddressgenerator
2 9
mPD780973(A)
7. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current consumption.
• HALT mode : The CPU operating clock is stopped. The average current consumption can be reduced by
intermittent operation in combination with the normal operating mode.
• STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock
is stopped, so that the system operates with ultra-low power dissipation.
Figure 7-1. Standby Functions
8. RESET FUNCTIONS
There are the following two reset methods.
• External reset input by RESET pin.
• Internal reset by watchdog timer runaway time detection.
Main SystemClock Operation
InterruptRequest
STOPInstruction
InterruptRequest
STOP Mode(Main system clockoscillation stopped)
HALT Mode(Clock supply to CPU is stopped,oscillation maintained)
HALTInstruction
3 0
mPD780973(A)
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Note Except r = A
Second operand
Firstoperand
#byte A rNote sfr saddr !addr16 PSW [DE] [HL]
[HL + byte]
[HL + B]
[HL + C]$addr16 1 None
A
r
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV MOV MOV MOV MOV MOV MOV ROR
XCH XCH XCH XCH XCH XCH XCH ROL
ADD ADD ADD ADD ADD RORCADDC ADDC ADDC ADDC ADDC ROLC
SUB SUB SUB SUB SUB
SUBC SUBC SUBC SUBC SUBC
AND AND AND AND AND
OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMPCMP CMP CMP
MOV MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
INC
DEC
B, C
sfr MOV MOV
DBNZ
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
saddr MOV DBNZ INC
DEC
!addr16 MOV
PSW MOVMOV PUSH
POP
[DE]
ROR4
MOV
[HL] MOV
ROL4
[HL + byte]
[HL + B]
[HL + C]
MOV
X
C
MULU
DIVUW
3 1
mPD780973(A)
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Note Only when rp = BC, DE or HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
(4) Call instruction/branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Second operand
First operand
AX
rp
sfrp
saddrp
!addr16
SP
#word
ADDWSUBWCMPW
MOVW
MOVW
MOVW
MOVW
AX
MOVWNote
MOVW
MOVW
MOVW
MOVW
MOVW
rpNote
XCHW
sfrp
MOVW
saddrp
MOVW
!addr16
MOVW
SP
MOVW
None
INCW, DECWPUSH, POP
Second operand
First operandA.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
MOV1
MOV1
MOV1
MOV1
MOV1
BTBF
BTCLR
BTBF
BTCLR
BTBF
BTCLR
BTBF
BTCLR
BTBF
BTCLR
SET1CLR1
SET1CLR1
SET1CLR1
SET1CLR1
SET1CLR1
SET1CLR1
NOT1
MOV1AND1
OR1XOR1
MOV1AND1
OR1XOR1
MOV1AND1
OR1XOR1
MOV1AND1
OR1XOR1
MOV1AND1
OR1XOR1
Second operandFirst operand
AX !addr16 !addr11 [addr5] $addr16
Basic instruction
Compound instruction
BR CALLBR
CALLF CALLT BR, BC, BNCBZ, BNZ
BT, BFBTCLRDBNZ
3 2
mPD780973(A)
10. ELECTRICAL SPECIFICATIONS (TARGET VALUE)
Absolute Maximum Ratings (T A = 25 °C)
Parameter Symbol Test Conditions Ratings Unit
Supply voltage VDD –0.3 to +6.5 V
AVREF –0.3 to VDD+0.3 V
AVSS –0.3 to +0.3 V
SMVDD SMVDD = VDD –0.3 to +6.5 V
SMVSS –0.3 to +0.3 V
Input voltage VI –0.3 to VDD +0.3 V
Output voltage VO1 Except for SM11 to SM14, SM21 to SM24, SM31 to –0.3 to VDD +0.3 V
SM34, SM41 to SM44
VO2 SM11 to SM14, SM21 to SM24, SM31 to SM34, SM41 –0.5 to SMVDD +0.7 V
to SM44
Analog input voltage VAN P10 to P14 Analog input pin AVSS –0.3 to AVREF +0.3 V
Output current high IOH 1 pin –10 mA
P00 to P07, P40 to P44, P50 to P54, P81 to P87, P90 to P97 total –15 mA
P60, P61 total –30 mA
1 pin (SM11/P20 to SM14/P23, SM21/P24 to SM24/P27) –45 mA
SM11/P20 to SM14/P23, SM21/P24 to SM24/P27 total –135 mA
1 pin (SM31/P30 to SM34/P33, SM41/P34 to SM44/P37) –45 mA
SM31/P30 to SM34/P33, SM41/P34 to SM44/P37 total –135 mA
Output current low IOLNote 1 pin Peak value 20 mA
r.m.s. 10 mA
P00 to P07, P40 to P44, P50 to P54, Peak value 50 mA
P81 to P87,P90 to P97 total r.m.s. 20 mA
P60, P61 total r.m.s. 30 mA
1 pin (SM11/P20 to SM14/P23, SM21/P24 to SM24/P27) 45 mA
SM11/P20 to SM14/P23, SM21/P24 to SM24/P27 total 135 mA
1 pin (SM31/P30 to SM34/P33, SM41/P34 to SM44/P37) 45 mA
SM31/P30 to SM34/P33, SM41/P34 to SM44/P37 total 135 mA
Operating ambient TA –40 to +85 °C
temperature
Storage temperature Tstg –65 to +150 °C
Note The root mean square (r.m.s) should be calculated as follows: [r.m.s.] = [peak value] ¥ šduty
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, device reliability
may be impaired. The absolute maximum ratings are values that may physically damage the
product. Be sure to use the product within the ratings.
3 3
mPD780973(A)
Capacitance (T A = 25 °C, VDD = VSS = 0 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input capacitance CIN Except for SM11 to SM14, SM21 to SM24, 15 pF
I/O capacitance CIO SM31 to SM34, SM41 to SM44 15 pF
Output capacitance COUT f = 1 MHz Unmeasured pins returned to 0 V. 15 pF
Output capacitance CSM SM11 to SM14, SM21 to SM24, SM31 to SM34, 30 PF
SM41 to SM44
f = 1 MHz
Unmeasured pins returned to 0 V.
Remark The characteristics of an alternate-function pin and a port pin are the same unless otherwise specified.
Main System Clock Oscillation Circuit Characteristics (T A = –40 to +85 °C, VDD =4.5 to 5.5 V)
Resonator Recommended Circuit Parameter Test Conditions MIN. TYP. MAX. Unit
Ceramic Oscillation frequency VDD = Oscillation voltage 4.0 8.38 MHz
resonator (fX)Note 1 range
Oscillation stabilization After VDD reaches oscillation 4 ms
timeNote 2 voltage range MIN.
Crystal Oscillation frequency VDD = Oscillation voltage 4.0 8.38 MHz
resonator (fX)Note 1 range
Oscillation stabilization After VDD reaches oscillation 10 ms
timeNote 2 voltage range MIN.
External X1 input frequency 4.0 8.38 MHz
clock (fx)Note 1
X1 input high-/low- 55 125 ns
level width (tXH, tXL)
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Caution Wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse
effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as V SS.
• Do not ground wiring to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
X1X2 IC
R1
C2 C1
X1X2 IC
C2 C1
X1X2
µPD74HCU04
3 4
mPD780973(A)
DC Characteristics (T A = –40 to +85 °C, VDD =4.5 to 5.5 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input voltage VIH1 P10 to P14, P51, P54, P60, P61, P81 to P87, P90 to P97 0.7VDD VDD V
high VIH2 P00 to P07, P40 to P44, P50, P52, P53, RESET 0.7VDD VDD V
VIH4 X1, X2 VDD–0.5 VDD V
Input voltage VIL1 P10 to P14, P51, P54, P60, P61, P81 to P87, P90 to P97 0 0.3VDD V
low VIL2 P00 to P07, P40 to P44, P50, P52, P53, RESET 0 0.3VDD V
VIL4 X1, X2 0 0.4 V
Output voltage VOH1 P00 to P07, P40 to P44, P50 to P54, IOH = –1mA VDD–1.0 VDD V
high P60, P61, P81 to P87, P90 to P97
VOH2 SM11 to SM14, SM21 to SM24, IOH = –27 mA (TA = 85 °C) VDD–0.5 VDD–0.07 V
SM31 to SM34, SM41 to SM44 IOH = –30 mA (TA = 25 °C) VDD–0.5 VDD–0.07 V
IOH = –40 mA (TA = –40 °C) VDD–0.5 VDD–0.07 V
VOH3 SGO IOH = –20 mA VDD–0.5 V
Output voltage VOL1 P00 to P07, P40 to P44, P50 to P54, IOL = 1.6 mA 0.4 V
low P60, P61, P81 to P87, P90 to P97
VOL2 SM11 to SM14, SM21 to SM24, IOL = 27 mA (TA = 85 °C) 0.07 0.5 V
SM31 to SM34, SM41 to SM44 IOL = 30 mA (TA = 25 °C) 0.07 0.5 V
IOL = 40 mA (TA = –40 °C) 0.07 0.5 V
VOL3 SGO IOL = 20 mA 0.5 V
Input leakage ILIH1 VIN = VDD Except for X1, X2 3 mA
current high ILIH2 X1, X2 20 mA
Input leakage ILIL1 VIN = 0 V Except for X1, X2 –3 mA
current low ILIL2 X1, X2 –20 mA
Output leakage ILOH VOUT = VDD 3 mA
current high
Output leakage ILOL VOUT = 0 V –3 mA
current low
Software R VIN = 0 V, P00 to P07 10 30 100 kWpull-up resistor
Supply current IDD1 8.38-MHz crystal oscillation operation modeNote 2 15 45 mA
Note 1 4.00-MHz crystal oscillation operation modeNote 2 14.7 44.2 mA
IDD2 8.38-MHz crystal oscillation HALT mode 1.0 2.0 mA
4.00-MHz crystal oscillation HALT mode 0.7 1.2 mA
IDD3 STOP mode 1.0 30 mA
Notes 1. The current flowing in the VDD pin. Not including the current flowing in the A/D converter, port, LCD split
resistor, and on-chip pull-up resistor.
2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)
Remark The characteristics of an alternate-function pin and a port pin are the same unless otherwise specified.
3 5
mPD780973(A)
LCD Controller/Driver Characteristics (T A = –40 to +85 °C, VDD = 4.5 to 5.5 V)
1/3 Bias Method
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 3.0 VDD V
LCD output voltage deviationNote VODC IO = ±5 mA 3.0 V - VLCD - VDD 0 ±0.2 V
(common) VLCD0 = VLCD
LCD output voltage deviationNote VODS IO = ±1 mA VLCD1 = VLCD ¥ 2/3 0 ±0.2 V
(segment) VLCD2 = VLCD ¥ 1/3
LCD split resistor current ILCD 3.0 V - VLCD - VDD 50 260 mA
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment
and common outputs (VLCDn; n=0, 1, 2).
3 6
mPD780973(A)
AC Characteristics
(1) Basic Operation (T A = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Cycle Time TCY Operation on main system clock (fX = 8.38 MHz) 0.238 8 ms
(Min. instruction execution time)
TI input tTIH0, 3/fsamNote ms
high-/low-level width tTIL0
TI input frequency fTI 0 4 MHz
TIO2, TIO3 input tTIH, 100 ns
high-/low-level width tTIL
Interrupt request input tINTH, INTP0 to INTP2 1 ms
high-/low-level width tINTL
RESET low-level width tRSL 10 ms
Note In combination with bits 0 (PRM00) and 1 (PRM01) of prescaler mode register (PRM0), selection of fsam is
possible between fX/8, fX/16, fX/32, and fX/64.
TCY vs. VDD (At main system clock operation)
Operation GuaranteedRange
10.0
5.0
1.0
0.5
0.10 1.0 2.0 3.0 4.0 5.0 6.0
5.54.5
Supply Voltage VDD [V]
Cyc
le T
ime
TC
Y [
s]
µ
3 7
mPD780973(A)
(2) Serial Interface (T A = –40 to +85 °C, VDD = 4.5 to 5.5V)
(a) 3-wire serial I/O mode (SCK ... Internal clock output)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY1 950 ns
SCK high-/low-level width tKH1, tKL1 tKCY1/2–50 ns
SI setup time (to SCK•) tSIK1 100 ns
SI hold time (from SCK•) tKSI1 400 ns
SO output delay time from SCKØ tKSO1 C = 100 pFNote 300 ns
Note C is the load capacitance of SCK and SO output lines.
(b) 3-wire serial I/O mode (SCK ... External clock input)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY2 800 ns
SCK high-/low-level width tKH2, tKL2 400 ns
SI setup time (to SCK•) tSIK2 100 ns
SI hold time (from SCK•) tKSI2 400 ns
SO output delay time from SCKØ tKSO2 C = 100 pFNote 300 ns
SCK rise, fall time tR2, tF2 160 ns
Note C is the load capacitance of SO output line.
(c) UART mode (Dedicated baud rate generator output)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Transfer rate 130.9 kbps
3 8
mPD780973(A)
AC Timing Test Point (Excluding X1 Input)
Clock Timing
TI Timing
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
1/fX
tXHtXL
VDD –0.5 V
0.4 VX1 Input
1/fT1
tTIH0tTIL0
TI00 to TI02
1/fTI
tTIHtTIL
TIO2, TIO3
3 9
mPD780973(A)
Serial Transfer Timing
3-wire serial I/O mode:
tKCYn
tKHntKLn
tR2
tSIKn tKSIn
Input Data
tKSOn
Output Data
SCK
SI
SO
n = 1, 2
tF2
4 0
mPD780973(A)
A/D Converter Characteristics (T A = –40 to +85 °C, AV DD = VDD = 4.5 to 5.5 V, AV SS = VSS =0 V, fX = 8.38 MHz)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Resolution 8 bit
Overall errorNote ±0.6 %
Conversion time tCONV 19.1 ms
Analog input voltage VIAN AVSS AVREF V
Reference voltage AVREF 4.5 VDD V
AVREF–AVSS resistance RAIREF When bit 7 (ADCS1) of the A/D converter 21.4 kWmode register (ADM1) is set to 0.
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
EEPROM Characteristics (T A = –40 to +85 °C, AV DD = VDD = 4.5 to 5.5 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
EEPROM write time tEEWR fX = 5.12 MHz 3.4 ms
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T A = –40 to +85 °C)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 2.0 5.5 V
Data retention supply current IDDDR VDDDR = 2.0 V 0.1 10 mA
disconnected
Release signal set time tSREL 0 ms
Oscillation stabilization wait time tWAIT Release by RESET 217/fX ms
Release by interrupt request Note ms
Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS),
selection of 212/fX and 214/fX to 217/fX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset OperationHALT Mode
Operating ModeSTOP Mode
Data Retention Mode
VDDDR tSREL
STOP Instruction Execution
tWAIT
VDD
RESET
4 1
mPD780973(A)
Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Request Signal)
Interrupt Request Input Timing
RESET Input Timing
HALT Mode
Operating ModeSTOP Mode
Data Retention Mode
VDDDR tSREL
STOP Instruction Execution
tWAIT
VDD
Standby Release Signal(Interruput Request)
tINTL tINTH
INTP0 to INTP2
tRSL
RESET
4 2
mPD780973(A)
11. PACKAGE DRAWING
80 PIN PLASTIC QFP (14 20)
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) ofits true position (T.P.) at maximum material condition.
detail of lead end
M
F
GH I
J
K
M
LN
P
Q R
ITEM MILLIMETERS INCHES
S
P80GF-80-3B9-3
3.0 MAX. 0.119 MAX.
K 1.8±0.2 0.071+0.008–0.009
L 0.8±0.2 0.031+0.009–0.008
P 2.7 0.106
N 0.10 0.004
M 0.15 0.006+0.004–0.003
Q 0.1±0.1 0.004±0.004
A 23.6±0.4 0.929±0.016
B 20.0±0.2 0.795+0.009–0.008
C 14.0±0.2 0.551+0.009–0.008
G
F
0.8
1.0
0.031
0.039
D 17.6±0.4 0.693±0.016
J 0.8 (T.P.) 0.031 (T.P.)
I 0.15 0.006
H 0.35±0.10 0.014+0.004–0.005
+0.10–0.05
6465 40
801
2524
41
A
B
C D S
R 5°±5° 5°±5°
4 3
mPD780973(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the mPD780973(A).
Language Processing Software
RA78K/0Notes 1, 2, 3, 4 78K/0 Series common assembler package
CC78K/0Notes 1, 2, 3, 4 78K/0 Series common C compiler package
DF780974Notes 1, 2, 3, 4, 8 Device file for mPD780973(A), 78F0974
CC78K/0-LNotes 1, 2, 3, 4 78K/0 Series common C compiler library source file
Debugging Tool
IE-78001-R-ANote 8 78K/0 Series common in-circuit emulator
IE-78K0-SL-EMNote 8 78K/0 Series common CPU core board
IE-780974-SL-EM1 Probe board for mPD780973(A), 78F0974 emulation
IE-78000-R-SV3 Interface adapter and a cable for using an EWS as the host machine
IE-70000-98-IF-B Interface adapter for using the PC-9800 series (except the notebook type) as the host machine
IE-70000-98N-IF Interface adapter and a cable for using the notebook type PC-9800 series as the host machine
IE-70000-PC-IF-B Interface adapter for using IBM PC/ATTM as the host machine
EP-80GF-SL Emulation probe for 80-pin plastic QFP (GF-3B9 type)
TGF-080RAP (see Figure A-1) Adapter to be mounted on a target system board for the 80-pin plastic QFP (GF-3B9 type)
Product of Tokyo Eletech Corporation
SM78K0Notes 5, 6, 7 78K/0 Series common system simulator
ID78K0Notes 4, 5, 6, 7 78K/0 Series common integrated debugger
DF780974Notes 1, 2, 5, 6, 7, 8 Device file for mPD780973(A), 78F0974
4 4
mPD780973(A)
Real-time OS
RX78K/0Notes 1, 2, 3, 4 78K/0 series real-time OS
MX78K0Notes 1, 2, 3, 4 78K/0 series OS
Fuzzy Inference Development Support System
FE9000Note 1 /FE9200Note 6 Fuzzy knowledge data creation tool
FT9080Note 1 /FT9085Note 2 Translator
FI78K0Notes 1, 2 Fuzzy inference module
FD78K0Notes 1, 2 Fuzzy inference debugger
Notes 1. PC9800 Series (MS-DOSTM) based
2. IBM PC/AT and compatibles (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 Series 300TM (HP-UXTM) based
4. HP9000 Series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS4800 Series (EWS-
UX/V) based
5. PC-9800 Series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
8. Under development
Remarks 1. For third party development tools, refer to the 78K/0 Series Selection Guide (U11126E)
2. The RA78K/0, CC78K/0, SM78K0, ID78K0, and RX78K/0 are used in combination with the DF780974.
4 5
mPD780973(A)
Drawing for Conversion Adapter (TGF-080RAP)
Figure A-1. TGF-080RAP Drawing (for Reference Only) (unit: mm)
ITEM MILLIMETERS INCHES
b
c
a
d
e
f
g
ITEM MILLIMETERS INCHES
B 14.1 0.555
C 0.8x15=12 0.031x0.591=0.472
A 20.65 0.813
D
H
I 10.0 0.394
23.6 0.929
J 12.4 0.488
E 16.4 0.646
F 18.8 0.740
K 14.8 0.583
L 17.2 0.677
M
Q C 2.0 C 0.079
R 18.65 0.734
13.35 0.526S
N 20.5 0.807
O 27.05
P 0.8 0.031
1.065
W
X
Y
T
U
V
Z
0.8
0.8x23=18.4
0.031
0.031x0.906=0.724
G 21.2 0.835
note: Product by TOKYO ELETECH CORPORATION.
1.325 0.052
19.75 0.778
23.55 0.927
27.05 1.065
10.6 0.417
17.1 0.673
1.125 0.044
14.40 0.567
18.8 0.740
20.65 0.813
9.5 0.374
1.8 0.071
3.55 0.140
5.3 0.209
5.0 0.197
0.9 0.035
0.3 0.012
q 3.5 0.138
r 2.0 0.079
0.25 0.010s
n 7.35 0.289
o 1.2
p 1.85 0.073
0.047
w
t
u
v
7.7
(16.95)
0.303
(0.667)
4- 1.3 4- 0.051
13.6 0.535
1.2 0.047
2.7 0.106
2.4 0.094
h
i
j
k
l
m
g
TGF-080RAP-G0E
D
P
Q
ABC R
ST T
Y
i
de
f
Za
IJKL
k
wv
l
uus
r
qn
p
m o
H G F E M N O X W U b c
V
V
j
t
Protrusion height h
φ
φ φ
φ
φ φφ φφ φ
4 6
mPD780973(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document NameDocument No. Document No.
(English) (Japanese)
mPD780973(A), 78F0974 User’s Manual Planned U12406J
mPD780973(A) Preliminary Product Information This manual U12759J
78K/0 Series User’s Manual Instruction U12326E U12326J
78K/0 Series Instruction Table – U10903J
78K/0 Series Instruction Set – U10904J
mPD780973(A), 78F0974 Special Function Register Table – U12748J
Development Tools Documents (User’s Manual)
Document NameDocument No. Document No.
(English) (Japanese)
RA78K Series Assembler Package Operation EEU-1399 EEU-809
Language EEU-1404 EEU-815
RA78K Series Structured Assembler Preprocessor EEU-1402 EEU-817
RA78K0 Assembler Package Operation U11802E U11802J
Assembly Language U11801E U11801J
Structured Assembly Language U11789E U11789J
CC78K Series C Compiler Operation EEU-1280 EEU-656
Language EEU-1284 EEU-655
CC78K0 C Compiler Operation U11517E U11517J
Language U11518E U11518J
CC78K/0 C Compiler Application Note Programming Know-how EEA-1208 EEU-618
CC78K Series Library Source File – U12322J
IE-78001-R-A Planned Planned
EP-80GF-SL Planned Planned
SM78K0 System Simulator (Windows Based) Reference U10181E U10181J
SM78K Series System Simulator External Parts User Open U10092E U10092J
Interface Specification
ID78K0 Integrated Debugger EWS Based Reference – U11151J
ID78K0 Integrated Debugger Windows Based Guide U11649E U11649J
ID78K0 Integrated Debugger PC Based Reference U11539E U11539J
4 7
mPD780973(A)
Embedded Software Documents (User’s Manual)
Document NameDocument No. Document No.
(English) (Japanese)
78K/0 Series Real Time OS Basic – U11537J
Installation – U11536J
OS for 78K/0 Series MX78K0 Basic U12257E U12257J
Fuzzy Knowledge Data Creation Tool EEU-1438 EEU-829
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator EEU-1444 EEU-862
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-1441 EEU-858
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-1458 EEU-921
Other Documents
Document NameDocument No. Document No.
(English) (Japanese)
IC Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535E C10535J
Quality Grade on NEC Semiconductor Devices IEI-1209 C11531J
Reliable Quality Maintenance on NEC Semiconductor Devices C10983E C10983J
Electrostatic Discharge (ESD) Test – MEM539
Semiconductor Devices Quality Guarantee Guide MEI-1202 C11893J
Microcomputer Product Series Guide – U11416J
Caution The contents of the above related documents are subject to change without notice. The latest
documents should be used for design, etc.
4 8
mPD780973(A)
[MEMO]
4 9
mPD780973(A)
[MEMO]
5 0
mPD780973(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
5 1
mPD780973(A)
NEC Electronics Inc. (U.S.)Santa Clara, CaliforniaTel: 800-366-9782Fax: 800-729-9288
NEC Electronics (Germany) GmbHDuesseldorf, GermanyTel: 0211-65 03 02Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.Milton Keynes, UKTel: 01908-691-133Fax: 01908-670-290
NEC Electronics Italiana s.r.1.Milano, ItalyTel: 02-66 75 41Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.Hong KongTel: 2886-9318Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.Seoul BranchSeoul, KoreaTel: 02-528-0303Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.United Square, Singapore 1130Tel: 253-8311Fax: 250-3583
NEC Electronics Taiwan Ltd.Taipei, TaiwanTel: 02-719-2377Fax: 02-719-5951
NEC do Brasil S.A.Sao Paulo-SP, BrasilTel: 011-889-1680Fax: 011-889-1689
NEC Electronics (Germany) GmbHBenelux OfficeEindhoven, The NetherlandsTel: 040-2445845Fax: 040-2444580
NEC Electronics (France) S.A.Velizy-Villacoublay, FranceTel: 01-30-67 58 00Fax: 01-30-67 58 99
NEC Electronics (France) S.A.Spain OfficeMadrid, SpainTel: 01-504-2787Fax: 01-504-2860
NEC Electronics (Germany) GmbHScandinavia OfficeTaeby, SwedenTel: 08-63 80 820Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NECproduct in your application, please contact the NEC office in your country to obtain a list of authorizedrepresentatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools andcomponents, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also varyfrom country to country.
J96. 8
5 2
mPD780973(A)
The related documents indicated in this publication may include preliminary versions. However, preliminary versions arenot marked as such.
No part of this document may be copied or reproduced in any form or by any means without the prior writtenconsent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear inthis document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual propertyrights of third parties by or arising from use of a device described herein or any other liability arising from useof such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or otherintellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons orproperty arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safetymeasures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on acustomer designated "quality assurance program" for a specific application. The recommended applications ofa device depend on its quality grade, as indicated below. Customers must check the quality grade of each devicebefore using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade,they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.
M4 96.5
This product is manufactured and sold based on the license contract with CP8 Transac Corporation withrespect to the contract for the microcomputers with on-chip EEPROM.This product cannot be used for an IC card (SMART CARD).
EEPROM, FIP, and IEBus are trademarks of NEC Corporation.MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United Statesand/or other countries.IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.SPARCstation is a trademark of SPARK International, Inc.SunOS is a trademark of Sun Microsystems, Inc.NEWS and NEWS-OS are trademarks of Sony Corporation.