VLSI Design, Fall 2020 8. Design of Adders 1 8. Design of Adders Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2020 September 22, 2020 ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 1 / 31 Single-Bit Addition Half Adder S = A ⊕ B C out = A · B A B C out S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Full Adder S = A ⊕ B ⊕ C C out = MAJ (A,B,C ) A B C C out S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 1 / 31 Department of Electrical and Computer Engineering, The University of Texas at Austin J. A. Abraham, September 22, 2020
Transcript
VLSI Design, Fall 20208. Design of Adders 1
8. Design of Adders
Jacob Abraham
Department of Electrical and Computer EngineeringThe University of Texas at Austin
VLSI DesignFall 2020
September 22, 2020
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 1 / 31
Single-Bit Addition
Half AdderS = A⊕BCout = A ·B
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Full Adder
S = A⊕B ⊕ CCout = MAJ(A,B,C)
A B C Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 1 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 2
Full Adder Design I
Brute force implementation from equationsS = A⊕B ⊕ CCout = MAJ(A,B,C)
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 2 / 31
Full Adder Design II
Factor S in terms of Cout
S = A ·B · C + (A+B + C) · Cout
Critical path is usually C to Cout in ripple adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 3 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 3
Layout of Full Adder
Clever layout circumvents usual line of diffusion
Use wide transistors on critical pathEliminate output inverters
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 4 / 31
Full Adder Design III
Complementary Pass Transistor Logic (CPL)
Slightly faster, but more area
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 5 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 4
Ripple Carry Adder
Simplest design: cascade full adders
Critical path goes from Cin to Cout
Design full adder to have fast carry (small delay for carrysignal)
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 6 / 31
Deal with Inversions to Speed Up Carry Path
Critical path passes through majority gate
Built from minority + inverterEliminate inverter and use inverting full adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 7 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 5
Carry Propagate Adders
N-bit adder called CPA
Each sum bit depends on all previous carriesHow do we compute all these carries quickly?
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 8 / 31
Carry Propagate, Generate, Kill (P, G, K)
For a full adder, define what happens to carries
Generate: Cout = 1, independent of C
G = A ·BPropagate: Cout = C
P = A⊕B
Kill: Cout = 0, independent of C
K = A ·B
Generate and Propagate for groups spanning i:j
Gi:j = Gi:k + Pi:k ·Gk−1:j
Pi:j = Pi:k · Pk−1:j
Base Case
Gi:i ≡ Gi = Ai ·Bi, G0:0 = G0 = Cin
Pi:i ≡ Pi = Ai ⊕Bi, P0:0 = P0 = 0
Sum: Si = Pi ⊕Gi−1:0
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 9 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 6
Carry Propagate, Generate, Kill (P, G, K)
For a full adder, define what happens to carries
Generate: Cout = 1, independent of C
G = A ·BPropagate: Cout = C
P = A⊕B
Kill: Cout = 0, independent of C
K = A ·B
Generate and Propagate for groups spanning i:j
Gi:j = Gi:k + Pi:k ·Gk−1:j
Pi:j = Pi:k · Pk−1:j
Base Case
Gi:i ≡ Gi = Ai ·Bi, G0:0 = G0 = Cin
Pi:i ≡ Pi = Ai ⊕Bi, P0:0 = P0 = 0
Sum: Si = Pi ⊕Gi−1:0
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 10 / 31
PG Logic
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 11 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 7
Ripple Carry Adder Revisited in the PG Framework
Gi:0 = Gi + Pi ·Gi−1:0
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 12 / 31
Ripple Carry PG Diagram
tripple = tpg + (N − 1)tAO + txor
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 13 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 8
PG Diagram Notation
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 14 / 31
Carry-Skip Adder
Carry-ripple is slow through all N stages
Carry-skip allows carry to skip over groups of n bits
Decision based on n-bit propagate signal
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 15 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 9
Carry-Skip PG Diagram
For k n-bit groups (N = nk)tskip = tpg + [2(n− 1) + (k − 1)] tAO + txor
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 16 / 31
Carry-Lookahead Adder (CLA)
Carry-lookahead adder computes Gi:0 for many bits in parallel
Uses higher-valency cells with more than two inputs
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 17 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 10
CLA PG Diagram
Higher Valency Cells
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 18 / 31
Carry-Select Adder
Trick for critical paths dependent on late input X
Precompute two possible outputs for X = 0, 1Select proper output when X arrives
Carry-select adder precomputes n-bit sums for both possiblecarries into n-bit group
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 19 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 11
Tree Adders
Tree structures can be used to speed up computations
Look at computing the XOR of 8 bits using 2-input XOR-gates
If lookahead is good for adders, lookahead across lookahead!Recursive lookahead gives O(log N) delay
Many variations on tree adders
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 20 / 31
Brent-Kung Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 21 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 12
Sklansky Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 22 / 31
Kogge-Stone Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 23 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 13
Tree Adder Taxonomy
Ideal N-bit tree adder would have
L = log N logic levelsFanout never exceeding 2No more than one wiring track between levels
Describe adder with 3-D taxonomy (l, f, t)
Logic levels: L+ lFanout: 2f + 1Wiring tracks: 2t
Known tree adders sit on plane defined by l + f + t = L− 1
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 24 / 31
Tree Adder Taxonomy, Cont’d
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 25 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 14
Han-Carlson Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 26 / 31
Brent-Kung Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 27 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 15
Knowles [2,1,1,1] Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 28 / 31
Ladner-Fischer Adder
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 29 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 22, 2020
VLSI Design, Fall 20208. Design of Adders 16
Tree Adder Taxonomy Revisited
ECE Department, University of Texas at Austin Lecture 8. Design of Adders Jacob Abraham, September 22, 2020 30 / 31
![Chapter 11 · 2. COMPARISON OF VLSI ADDERS The most common approach in comparing VLSI adders was to use of a single delay point [1,2]. An example of such comparison (based only on](https://static.documents.pub/doc/80x56/5f44fd1856be9f2faa76e1d7/chapter-11-2-comparison-of-vlsi-adders-the-most-common-approach-in-comparing-vlsi.jpg)
