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INTEL 8086 microprocessor architecture : -

Development of microprocessors

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INTEL 8086 internal architecture

Here

BIU Bus interface unit

EU Execution unit

CS - Code Segment register

DS - Data Segment register

ES - Extra Segment register

SS - Stack Segment register

The BIU handles all transactions of data and addresses on the buses for EU.

The BIU performs all bus operations such as instruction fetching, reading and writing

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operands for memory and calculating the addresses of the memory operands. The

instruction bytes are transferred to the instruction queue.

EU executes instructions from the instruction system byte queue.

Both units operate asynchronously to give the 8086 an overlapping instruction fetch

and execution mechanism which is called as Pipelining. This results in efficient use of the

system bus and system performance.

BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag

register.

Memory

Program, data and stack memories occupy the same memory space. The total addressablememory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the

processor can effectively address only 64 KB of memory. To access memory outside of 64KB the CPU uses special segment registers to specify where the code, stack and data 64 KBsegments are positioned within 1 MB of memory (see the "Registers" section below).

16-bit pointers and data are stored as:address: low-order byteaddress+1: high-order byte

32-bit addresses are stored in " segment: offset" format as:address: low-order byte of segmentaddress+1: high-order byte of segmentaddress+2: low-order byte of offsetaddress+3: high-order byte of offset

Physical memory address pointed by segment : offset pair is calculated as:

address = ( * 16) +

Program memory - program can be located anywhere in memory. Jump and call instructionscan be used for short jumps within currently selected 64 KB code segment, as well as for far

jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction.

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Accumulator register consists of 2 8-bit registers AL and AH, which can be combinedtogether and used as a 16-bit register AX. AL in this case contains the low-order byte of theword, and AH contains the high-order byte. Accumulator can be used for I/O operations andstring manipulation.

Base register consists of 2 8-bit registers BL and BH, which can be combined together andused as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BHcontains the high-order byte. BX register usually contains a data pointer used for based, basedindexed or register indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined together andused as a 16-bit register CX. When combined, CL register contains the low-order byte of theword, and CH contains the high-order byte. Count register can be used as a counter in stringmanipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together andused as a 16-bit register DX. When combined, DL register contains the low-order byte of theword, and DH contains the high-order byte. Data register can be used as a port number in I/Ooperations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usuallyused for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and registerindirect addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and registerindirect addressing, as well as a destination data address in string manipulation instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too smallnegative number to fit into destination operand.Direction Flag (DF) - if set then string manipulation instructions will auto-decrementindex registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.Single-step Flag (TF) - if set then single-step interrupt will occur after the nextinstruction.

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Sign Flag (SF) - set if the most significant bit of the result is set.Zero Flag (ZF) - set if the result is zero.Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in theAL register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of theresult is even.Carry Flag (CF) - set if there was a carry from or borrow to the most significant bitduring last result calculation.

Instruction Set

Instruction set of Intel 8086 processor consists of the following instructions:

Data moving instructions.Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.Logic - AND, OR, exclusive OR, shift/rotate and test.String manipulation - load, store, move, compare and scan for byte/word.Control transfer - conditional, unconditional, call subroutine and return fromsubroutine.Input/Output instructions.Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes

Implied - the data value/data address is implicitly associated with the instruction.

Register - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

Register indirect - instruction specifies a register containing an address, where data islocated. This addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX orBP), the resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SIor DI), the resulting value is a pointer to location where data resides.

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Based Indexed - the contents of a base register (BX or BP) is added to the contents of anindex register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the

contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.

8086 Pin diagram & description

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Reserved locations :

0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset.

FFFF0h - FFFFFh - after RESET the processor always starts program execution atthe FFFF0h address.

Interrupts

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI

instructions or using more complicated method of updating the FLAGS register with the helpof the POPF instruction. When an interrupt occurs, the processor stores FLAGS register intostack, disables further interrupts, fetches from the bus one byte representing interrupt type,and jumps to interrupt processing routine address of which is stored in location 4 * . Interrupt processing routine should return with the IRET instruction.

Integrated 80186 peripherals generate the following hardware interrupts (higher priorityinterrupts are listed first):

Timer 0 - type 8

Timer 1 - type 18Timer 2 - type 19DMA 0 - type 10DMA 1 - type 11INT0 - type 12INT1 - type 13INT2 - type 14INT3 - type 15.

Interrupt types 9, 16 (on 80186), 17, and 20 - 31 are reserved.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTRinterrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine isstored in location 0008h. This interrupt has higher priority then the maskable interrupt.

Software interrupts are non-maskable interrupts. They can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.INT instruction - any one interrupt from available 256 interrupts.INTO instruction - interrupt on overflow. This is a type 4 interrupt.Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. Whenthe CPU processes this interrupt it clears TF flag before calling the interrupt

processing routine.

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Processor exceptions: divide error (type 0), array bounds exception (type 5), unusedopcode (type 6), escape opcode (type 7), and numeric co-processor exception (type16, 80C186 only).

Software interrupt processing is the same as for the hardware interrupts. Software interruptshave the same priority as the NMI interrupt.

I/O ports

65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.

Reserved ports :

00F8h - 00FFhFF00h - FFFFh: 256-byte control block. This is a default block location after RESET.If necessary, the block can be remapped to different place in I/O or memory space.For description of the control block please see "Control registers" in the "Registers"section below.

Registers

Most of the registers contain data/instruction offsets within 64 KB memory segment. There

are four different 64 KB segments for instructions, stack, data and extra data. To specifywhere in 1 MB of processor memory these 4 segments are located the processor uses foursegment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processorinstructions. The processor uses CS segment for all accesses to instructions referenced byinstruction pointer (IP) register. CS register cannot be changed directly. The CS register isautomatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program

stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changeddirectly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with programdata. By default, the processor assumes that all data referenced by general registers (AX, BX,CX, DX) and index register (SI, DI) is located in the data segment. DS register can bechanged directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with

program data. By default, the processor assumes that the DI register references the ESsegment in string manipulation instructions. ES register can be changed directly using POPand LES instructions.

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It is possible to change default segments used by general and index registers by prefixinginstructions with a CS, SS, DS or ES prefix.

All general registers of the 80186 microprocessor can be used for arithmetic and logic

operations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combinedtogether and used as a 16-bit register AX. AL in this case contains the low-order byte of theword, and AH contains the high-order byte. Accumulator can be used for I/O operations andstring manipulation.

Base register consists of 2 8-bit registers BL and BH, which can be combined together andused as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BHcontains the high-order byte. BX register usually contains a data pointer used for based, based

indexed or register indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined together andused as a 16-bit register CX. When combined, CL register contains the low-order byte of theword, and CH contains the high-order byte. Count register can be used as a counter in stringmanipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together andused as a 16-bit register DX. When combined, DL register contains the low-order byte of theword, and DH contains the high-order byte. Data register can be used as a port number in I/O

operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usuallyused for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and registerindirect addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and registerindirect addressing, as well as a destination data address in string manipulation instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 1-bit flags:

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Overflow Flag (OF) - set if the result is too large positive number, or is too smallnegative number to fit into destination operand.Direction Flag (DF) - if set then string manipulation instructions will auto-decrementindex registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.Single-step Flag (TF) - if set then single-step interrupt will occur after the nextinstruction.Sign Flag (SF) - set if the most significant bit of the result is set.Zero Flag (ZF) - set if the result is zero.Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in theAL register.Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of theresult is even.Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit

during last result calculation.

Control registers are used to control 80186 integrated peripherals. These 16-bit registers are part of 256-byte control block that can be mapped into system RAM or I/O space. The control block includes the following registers:

Interrupt control - 20h - 3EhTime 0 control - 50h (counter), 52h (max count A), 54h (max count B), and 56h(control word)Time 1 control - 58h (counter), 5Ah (max count A), 5Ch (max count B), and 5Eh(control word)Time 2 control - 60h (counter), 62h (max count A), and 66h (control word)Chip-select control - A0h (upper memory), A2h (lower memory), A4h (peripheral),A6h and A8h (mid-range memory)DMA descriptors channel 0 - C0h and C2h (source pointer), C4h and C6h(destination pointer), C8h (transfer count) and CAh (control word).DMA descriptors channel 1 - D0h and D2h (source pointer), D4h and D6h(destination pointer), D8h (transfer count) and DAh (control word).Refresh Control Unit registers (80C186 in Enhanced mode only) - E0h - E4hPower-Saving control (80C186 only) - F0hRelocation register - FEh

After reset the control block is mapped at address FF00h in I/O space.

Instruction Set

80186 instruction set consists of the following instructions:

Data moving instructions.Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.Logic - AND, OR, exclusive OR, shift/rotate and test.String manipulation - load, store, move, compare and scan for byte/word.

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Intel 80286 microprocessor architecture

An 8MHz Intel 80286 Microprocessor

Architecture of Intel 80286

Key Features -

16-bit date bus24-bit non-multiplexed bus

Packaged in a 68-pin ceramic pack

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80286 has 2 24 = 16 M Byte of physical memory accessibility

Basic Architecture of 80286

Memory Bank

Memory of 80286 is setup as an odd bank and an even bank, just as it is for the 8086.The even bank is enabled when A 0 is low and the odd bank is enabled when islow. To access an aligned word, both A 0 will be low.

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Memory banks in 80286

Memory Addressing in 80286

1. Real Addressing Mode - It is just like as in 8086. Address is 20 bit with 16 bitsegment and 16 bit offset. When 80286 is hardware reset, it automaticallyenters real address mode.

2. Protected Virtual Addressing Mode (PVAM) - In this we have 1 GByte of

virtual memory and 16 Mbyte of physical memory. The address is 24 bit. Toenter PVAM mode, Processor Status Word (PSW) is loaded by the instructionLPSW.

Load Processor Status Word

PE - Protection EnableMP - Monitor Processor Extension

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automatically fetched from the stack segment. This means the stack segment does not have to be included in the instruction, making for a more compact instruction.

Flags Register

The flags register is a 32-bit register named EFLAGS. The low-order 16 bits of EFLAGS isnamed FLAGS for compatibility with older 8086 and 80286 code. There are three basicgroups of flags, status flags, control flags and the system flags. The flags are as follows:

16 15 0---- ---- ---- ---- ---X CF Carry Flag---- ---- ---- ---- -X-- PF Parity Flag---- ---- ---- ---X ---- AF Auxiliary Carry---- ---- ---- -X-- ---- ZF Zero Flag

---- ---- ---- X--- ---- SF Sign Flag---- ---- ---X ---- ---- TF Trap Flag---- ---- --X- ---- ---- IF Interrupt Flag---- ---- -X-- ---- ---- DF Direction Flag---- ---- X--- ---- ---- OF Overflow Flag---- --XX ---- ---- ---- PL I/O Privilege Level---- -X-- ---- ---- ---- NT Nested Task Flag---X ---- ---- ---- ---- RF Resume Flag--X- ---- ---- ---- ---- v8 Virtual 8086 MODE

The remaining bits are reserved for future Intel use. A flag is considered cleared when it iszero, set when it is 1.

The status flags used by application programmers are CF, PF, AF, ZF, SF, and OF. Theseflags hold the results of various instructions that are then used by later instructions. Whatfollows is a brief description of each flag.

Carry Flag: Set in math instructions to indicate that the high-order bit was eithercarried or borrowed. It is cleared if neither of these conditions occur.Parity Flag: Indicates whether the lower 8-bits of a result contains an even number of

bits set to 1 (flag is set) or an odd set of bits are set to 1 (flag is cleared)Adjust Flag: Set in decimal math instructions to indicate whether the low order 4-bitsof AL where carried, or borrowed. It is cleared if not.Zero Flag:Set to indicate a math instruction resulted in a zero result. It is clearedotherwise. It is also used by string and loop instructions to indicate completion of theinstruction.Sign Flag:Set equal to high-order bit of results of math instruction. If set the result isnegative, positive if cleared.Overflow Flag:Indicates if the number placed in the destination operand overflowed,either too large, or small. If no overflow occurred, the bit is cleared.

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On a read, the microprocessor cheoccurs on the PCHK# pin. A pariuser applies the PCHK signal to a

Interrupts are often used to signal

is same as 80386, except the parit If parity is not used, Intel recomm CACHE MEMORY : The cache

also the instructions of the progracache with each location containi

Control register CR0 is used to co present in the 80386 microproces

The CD ( cache disable ) , NW (and are used to control the 8K byt

If the CD bit is a logic 1, all cachfor debugging software and normcache write-through operation. Astesting. For normal operations CD

Because the cache is new to 8048cycle not present on the 386.

80486 Mem

The 80486 contains the same meincludes a paging unit to allow anto any 4K byte block of linear me80486 memory-management syst

The 80486 paging system can dis pages, while the 80386 could not.

If these are compared with 80386observed ( PWT and PCD ).

The page write through and page

Control Register Zero ( CR 0

cks parity and generates a parity check error, if ity error causes no change in processing unless theinterrupt input.

a parity error in DS-based computer systems. This

bit storage.ends that the DP0 DP3 pins be pulled up to +5v.

emory system stores data used by a program and. The cache is organised as a 4 way set associative

g 16 bytes or 4 doublewords of data. ntrol the cache with two new control bits not

or.

on-cache write through ) bits are new to the 80486e cache.

operations are inhibited. This setting is only usedlly remains cleared. The NW bit is used to inhibitwith CD, cache write through is inhibited only for= 0 and NW = 0.

microprocessor and the cache is filled using burst

ry Management

ory-management system as the 80386. This4K byte block of physical memory to be assignedory. The only difference between 80386 and

m is paging. bled caching for section of translation memory

entries, the addition of two new control bits is

ache disable bits control caching.

For The 80486 Microprocessor

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The PWT controls how the cache functions for a write operation of the external cachememory. It does not control writing to the internal cache. The logic level of this bit isfound on the PWT pin of the 80486 microprocessor. Externally, it can be used todictate the write through policy of the external caching.

The PCD bit controls the on-chip cache. If the PCD = 0, the on-chip cache is enabledfor the current page of memory.

Note that 80386 page table entries place a logic 0 in the PCD bit position, enablingcaching. If PCD = 1, the on-chip cache is disable. Caching is disable regard less ofcondition of KEN#, CD, and NW.

Cache Test Registers

The 80486 cache test registers are TR3, TR4, TR5. Cache data register (TR3) is used to access either the cache fill buffer for a write test

operation or the cache read buffer for a cache read test operation. In order to fill or read a cache line ( 128 bits wide ), TR3 must be written or read four

times. The contents of the set select field in TR5 determine which internal cache line is

written or read through TR3. The 7 bit test field selects one of the 128 different 16 byte wide cache lines. The entry select bits of TR5 select an entry in the set or the 32 bit location in the read buffer.

The control bits in TR5 enable the fill buffer or read buffer operation ( 00 )

Perform a cache write ( 01 ), Perform a cache read ( 10 ) Flush the cache ( 11 ). The cache status register (TR4) hold the cache tag, LRU bits and a valid bit. This

register is loaded with the tag and valid bit before a cache a cache write operation andcontains the tag, valid bit, LRU bits, and 4 valid bits on a cache test read.

Cache is tested each time that the microprocessor is reset if the AHOLD pin is highfor 2 clocks prior to the RESET pin going low. This causes the 486 to completely testitself with a built in self test or BIST.

The BIST uses TR3, TR4, TR5 to completely test the internal cache. Its outcome isreported in register EAX. If EAX is a zero, the microprocessor, the coprocessor andcache have passed the self test.

The value of EAX can be tested after reset to determine if an error is detected. Inmost of the cases we do not directly access the test register unless we wish to performour own tests on the cache or TLB.