802-16 Ofdm Phy Tech Spec

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802.16 OFDM Phy Technical DescriptionREV 1.13 1/7/05 Page 1 of 89

802.16 OFDM Phy

Technical Description

Confidential


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RESTRICTED PROPRIETARY INFORMATION

The information disclosed herein is the exclusive property of SiWorks Inc. and is not tobe disclosed without the written consent of SiWorks Inc. No part of this publication maybe reproduced or transmitted in any form or by any means including electronic storage,reproduction, execution or transmission without the prior consent of SiWorks Inc. The

recipient of this document by its retention and use, agrees to respect the security status ofthe information contained herein.

This document is intended for limited circulation.

The information contained in this document is subject to change without notice andshould not be construed as a commitment by SiWorks Inc. unless such commitment is

expressly given in a covering document.

Copyright SiWorks Inc. (2004)


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Table of Contents1 Purpose........................................................................................................................ 72 Overview..................................................................................................................... 73 Programming Model ................................................................................................. 10

3.1 Transmitter ........................................................................................................ 113.2 Receiver ............................................................................................................ 11

4 Top Level Interface Description............................................................................... 124.1 Port Definitions................................................................................................. 124.2 802.16 SOC System Block Diagram ................................................................ 134.3 Register Description.......................................................................................... 15

5 Reset Logic ............................................................................................................... 186 ARC/PHY Interface................................................................................................. 19

6.1 ARC/PHY Interface and Timing ...................................................................... 196.2 FIFO Control/Status.......................................................................................... 216.3 Miscellaneous (RF,AFE,etc) Control Registers................................................ 236.4 Interrupts ........................................................................................................... 276.5 Frame Timer: .................................................................................................... 336.6 Preamble and AGC Memory Interface ............................................................. 36

7 Transmitter................................................................................................................ 397.1 Overview........................................................................................................... 397.2 Transmitter Control Word and Register Description........................................ 407.3 Transmitter Timing ........................................................................................... 427.4 Transmit Channel Encoder ............................................................................... 43

7.5 IFFT .................................................................................................................. 477.6 Transmit Front End........................................................................................... 497.7 Transmit Test Circuitry..................................................................................... 50

8 Receiver .................................................................................................................... 528.1 Overview........................................................................................................... 528.2 Receiver Control Word & Register Description............................................... 548.3 AFE Rx Interface, Rx FIFO, AGC & Decimation Filters ................................ 588.4 Frequency Correction........................................................................................ 678.5 Timing Recovery, Synchronization & AFC ..................................................... 698.6 FFT.................................................................................................................... 768.7 Timing Correction............................................................................................. 76

8.8 Channel Estimator............................................................................................. 778.9 Channel Decoder............................................................................................... 788.10 Receive Test Circuitry ...................................................................................... 82


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List of Figures

Figure 1: WMAN_PHY System Block Diagram............................................................... 7Figure 3: 802.16 SOC System Block Diagram................................................................. 14Figure 5: PHY Reset Circuitry......................................................................................... 18Figure 7: ARC/PHY Interface Block Diagram................................................................ 19Figure 9: ARC/PHY Write Cycle Timing ..................................................................... 20Figure 11: ARC/PHY Read Cycle Timing ....................................................................... 20Figure 13: rx_en, tx_en & tr_sw timing: TDD Mode....................................................... 25Figure 15: rx_en/tx_en timing: FDD Mode...................................................................... 25Figure 17: rx_en, tx_en & tr_sw control logic.................................................................. 26Figure 19: Transmitter Block Diagram............................................................................ 39Figure 21: Transmit Burst Timing no Offset ................................................................. 42Figure 23: Transmit Burst Timing with Offset .............................................................. 42

Figure 25: Scrambler LFSR.............................................................................................. 43Figure 27: Convolutional Encoder.................................................................................... 44Figure 29: Pilot LFSR ..................................................................................................... 46Figure 31: Frequency Response of 39-tap Halfband Tx Interpolation Filter.................... 49Figure 33: Receiver Block Diagram ................................................................................ 53Figure 35: ADC Interface & Rx FIFO.............................................................................. 58Figure 36: AGC System Level Block Diagram ................................................................ 60Figure 38: AGC Timing.................................................................................................... 61Figure 21: AGC External Timing Diagram ...................................................................... 65Figure 22: Frequency Response of 39-tap Halfband Rx Decimation Filter ..................... 66Figure 24: Freq_Corr Block Diagram............................................................................... 68

Figure 26: SYNC Block Diagram..................................................................................... 70Figure 28: Sequencing of Timing Recovery Operations in SYNC block......................... 71Figure 30: Timing Correction Block Diagram.................................................................. 76Figure 32: Channel Decoder Sub-blocks .......................................................................... 78Figure 34: Demapper Sub-Block ...................................................................................... 78Figure 36: De-Interleaver / De-Puncturer Sub-block........................................................ 79Figure 37: Viterbi Sub-block ............................................................................................ 80Figure 38: Descrambler Sub-block ................................................................................... 81Figure 39: SED Register (SEDR) .................................................................................... 84Figure 52: SED Timing Diagram...................................................................................... 84Figure 41: SED Channel Estimate Magnitude & Phase Timing Diagram........................ 85


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Definitions

CC Convolutional CodingDDS Direct Digital SynthsisFEC Forward Error CorrectionFCH Frame Control HeaderPDU Protocol Data UnitPHY Physical LayerRS Reed- SolomonRS-CC Concatenated Reed-Solomon/Convolutional Coding FEC

Fixed-point numbers are specified as follows:

- An 8-bit signed number with 4 integer bits (including sign) and four binalbits. Eg. 0x77 = 7.875, 0x82 = -7.875.

- An 8-bit unsigned number with 4 integer bits and four binal bits Eg. 0x82 =8.125

- An 8-bit signed integer number Eg. 0x82 = -126 - An 8bit unsigned integer number Eg. 0x82 = 130


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1 PurposeThe purpose of this document is to provide a technical description of the WirelessManOFDM Phy, herein described as the WMAN_PHY.

2 OverviewThe WMAN_PHY implements the Wireless MAN OFDM Phy layer as described in the802.16revD_D3, of the 802.16 specifications. The WMAN_PHY operates inconjunction with an ARC-Tangent processor subsystem which implements the TransmitConvergence Sublayer (TC_Sublayer), performs initial set-up of the Phy and alsoperforms Frame Control Header (FCH) decode of incoming packets. A system levelblock diagram of the WMAN_PHY is shown in Figure 1.

Tx Data

Rx Data

WMAN_PHY AFEARC

ChannelEstimator

Rx ChannelDecoder:

256-ptIFFT

AFC,AGC&

Timing

Tx ChannelEncoder

Control

Status

Dec.Filter

Int.Filter

AFE TxInterface

TxFIFO

RxFIFO

CPInsert

AFE RxInterface

Tx Front End

Rx Front End: Rx_FE

256-ptFFT

Figure 1: WMAN_PHY System Block Diagram


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The WMAN_PHY will support the following features:

Channel Bandwidths: Channel bandwidths ranging from 1.5 to 20 MHz are supported. The bandwidths

are assumed to be selectable upon power up of the chip and will be otherwisefixed during normal operation. An external DDS will be used to generate theappropriate clocks for the WMAN_PHY.

Transmitter:

Channel coding including implementation of the mandatory concatenated Reed-Solomon/Convolution Code (RS-CC) FEC

Support for the modulation and code rates as shown in Table 1. The optional 64-QAM modulation mode is included.

When subchannelization is applied in the uplink, the FEC shall bypass the RSDecoder and use the Overall Coding Rate as the CC Code Rate as indicated inTable 1.

Support for up to 16 subchannels Ability to generate long, short and custom preambles

Modulation Overall CodingRate

RS Code CC Coding Rate

BPSK (12,12,0) 1/2BPSK (12,12,0) 3/4QPSK (32,24,4) 2/3

QPSK (40,36,2) 5/616-QAM (64,48,8) 2/316-QAM (80,72,4) 5/664-QAM 2/3 (108,96,6) 64-QAM (120,108,6) 5/6

Table 1: IEEE 802.16 Modulation Modes

Receiver: Synchronization using long, short and custom preambles Support for a maximum coded data rate of 72.6 Mbps corresponding to 64-QAM

transmission over a 20 MHz channel bandwidth as shown in Table 2


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ChannelBandwidth

(MHz)

Fs/Bw MaxUncoded Data

Rate for

QAM-64(Mbps)

MaxCoded Data

Rate for

QAM-641

(Mbps)

Front End(FECLK)

Clock Rate

2xFs(MHz)1.5 7/6 7.6 5.7 3.53 7/6 15.3 11.5 7

5.5 7/6 27.4 20.6 12.831.75 8/7 8.7 6.6 43.5 8/7 17.5 13.1 87 8/7 34.9 26.2 16

10 8/7 49.9 37.4 22.8614 8/7 69.8 52.4 3220 8/7 96.8 72.6 45.71

Table 2: Max Data Rates for Supported Channel Bandwidths

Analog Front End:

The receiver will interface to dual 10-bit ADCs running at a maximum samplerate of 45.71 MHz (assuming a 20 MHz channel bandwidth)

The transmitter will interface to dual 10-bit DACs running at a nominal samplerate of 45.71 MHz (assuming a 20 MHz channel bandwidth).

1 Assumes R=5/6 for coding rate at Viterbi decoder


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3 Programming ModelThe 802.16 OFDM Phy specification requires support for frame based transmissionwhere a frame 2 consists of a downlink subframe and an uplink subframe. Downlinksubframes consist of a single downlink Protocol Data Unit (PDU) while uplink subframesconsist of contention slots for initial ranging and bandwidth requests followed by one ormultiple uplink PDUs..

A Downlink PDU consists of the following elements:

Preamble Frame Control Header Downlink burst 1,, m

Note that a Downlink subframe consists of a single Downlink PDU

An Uplink PDU consists of the following elements

Preamble Uplink Burst

Note that one or multiple Uplink PDUs can be concatenated together in an UplinkSubframe.

The interface to the Phy has been designed to enable burst based transmission andreception of 802.16 compliant frames. For Subscriber Station operation, frame timing isacquired by the Phy during initial synchronization to the Base Station. For BS operation,frame timing is initialized in the Phy by the external processor. The Phy maintains theframe time and allows the external processor to synchronize itself to the Phy frame timervia programmable interrupts.

In the following sections the interface and partitioning between the MAC and the Phy forthe transmitter and receiver are described.

2 See section 8.3.4.1 of 802.16Revd-D2


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3.1 TransmitterThe Phy assumes that the variable length PDUs from the MAC are transformed into

fixed length FEC blocks before they are input to the Phy. This requires thatconcatenation of short PDUs or segmentation of long PDUs is accomplished externally.In addition, encryption and Cyclic Redundancy Check (CRC) calculations are assumed tobe external to the Phy.

Transmit bursts in Uplink or Downlink format are provided to the Phy by the externalprocessor. A Transmit Control Word (TCW) is associated with each transmit data burstand is applied to the Phy by the external processor in conjunction with the transmit datathrough separate control and data FIFOs. The transmit control word is a multi-elementcontrol signal which describes the format and timing for an associated burst of datacontained in the Tx data FIFO. All elements of the transmit burst from start time,

modulation type and burst size to scrambler seed, midamble type and number of databytes can be specified through the Tx Control Word. In cases where the number of databytes to be transmitted is not equal to an integer number of OFDM symbols, the phy willpad the data with 0xFF as required.

3.2 ReceiverReceive bursts in Uplink or Downlink format are decoded by the Phy and provided to theexternal processor. A Receive Control Word (RCW) is applied to the Phy by the externalprocessor. The RCW is a multi-element control word which is used to control thesynchronization, decoding and descrambling operations of the receiver. The receiver in

the WMAN_Phy has been designed to have extremely low latency allowing functionssuch as Frame Control Header (FCH) decode to be provided by the external processor.

Upon completion of synchronization, AGC and timing/frequency recovery the receiver isprogrammed by the external processor to decode the incoming bursts on a burst by burstbasis. For Subscriber Station operation, the reception of the FCH is performed during theinitial receiver synchronization phase and the receiver must be programmed to receive theproper QPSK rate 1/2 modulation rate. The received FCH is then read and processed bythe external processor. The processor decodes the rate for the next burst from the FCH,generates a new RCW and applies it to the Phy. The available time between FCH beingavailable and the MAC writing the control word for burst #1 is currently 600 phy clock

cycles.

In addition, the external processor must decode the DL and UL MAP and the UCD &DCD messages. The incoming burst profiles are decoded from the messages and thereceiver programmed accordingly.

Receiver Base Station operation is more straightforward as the BS has specified to the SSthe format of the uplink data transmission and when it should occur.


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4 Top Level Interface Description

4.1 Port DefinitionsClock

Port Direction Type Description Domain

arc_clk in std_logic ARC Clock (160 MHz)fe_clk in std_logic Front End Clock

phy_clk in std_logic Phy Clock (100 MHz)reset_n in std_logic Asychronous reset

addr in std_logic_vector(6 downto 0) Register address bus arc_clkbs_sync_in in std_logic Resets the frame timer on the

rising edgecs_n in std_logic Chip select arc_clkdatai in std_logic_vector(31 downto 0) Input data arc_clk

lock_det in std_logic Lock Detect active highlock_det_n in std_logic Lock Detect active low

rd_n in std_logic Read enable arc_clkrf_enable in std_logic RF enable

rx_i in std_logic_vector(9 downto 0) ADC I data fe_clkrx_q in std_logic_vector(9 downto 0) ADC Q data fe_clkwr_n in std_logic Write enable arc_clk

adc_2s_cmp_sel out std_logic Selects 2's complement otherwiseoffset binary

fe_clk

adc_dac_clk_en_n out std_logic Enables fe_clk to be driven to theADCs and DACs

arc_clk

adc_out_en_n out std_logic Enables ADC output fe_clkadc_pd out std_logic Puts ADC in power down fe_clk

agc out std_logic_vector(9downto 0) AGC value fe_clkagc_stb out std_logic Pulses when the AGC value

changesphy_clk

bandgap_pd out std_logic Powers down the bandgapreference

bs_sync_out out std_logic Pulses high for 100 ms each timethe frame timer is reset.

dac_pd out std_logic Puts DAC in power down fe_clkdata_valid out std_logic datao is valid arc_clk

datao out std_logic_vector(31 downto 0) output data arc_clkft_int out std_logic Output from frame timer interrupt 0 arc_clk

int0_n out std_logic Interrupt 0 arc_clkrx_en out std_logic receive enable

sed_clk out std_logic serial interface clock for the symbolerror display

sed_data out std_logic serial interface data for the symbolerror display

sed_fs out std_logic serial interface framesynchronization signal

tr_sw out std_logic transmit switch fe_clktx_en out std_logic transmit enabletx_i out std_logic_vector(9 downto 0) DAC I data fe_clktx_q out std_logic_vector(9 downto 0) DAC Q data fe_clk

vref_pd out std_logic Powers down the voltage reference

Table 3: WMAN_PHY Top Level Interface


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4.2 802.16 SOC System Block DiagramThe WMAN_PHY is designed to be integrated into a complete 802.16 baseband SOC. It

is interfaced to an on-chip ARC micro-controller and on-chip I&Q ADCs and DACs. Asystem level block diagram is shown in Figure 2.


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datai

WMAN_PHY

ARCrd_n

int0_n

wr_n

cs_n

datai(31:0)

PHY_CLK(100 MHz)

ARC_CLK(160 MHz)

data_valid

DO(9:0)OMODEOUTDIS

PDADCPDBGRPDVR

IADC

DO(9:0)

OMODEOUTDIS

PDADCPDBGRPDVR

QADC

PD

D(9:0)

IDAC

PD

D(9:0)

QDAC

datao(31:0)

lock_detlock_det_n

rf_enable

arc_clk

addr(6:0)

rx_i(9:0)

rx_q(9:0)

phy_clk

adc_2s_cmp_sel

adc_pd

fe_clk

adc_out_en_n

dac_pdtx_i(9:0)

agc(9:0)

bandgap_pdvref_pd

tx_q(9:0)

agc_stb

rx_entx_en

tr_sw

AGC(9:0)STROBE

RX_ENTX_EN

LD

LDB

RF_ENABLE

TR_SW

reset_nRESET_PHY_n

SAMP_CLK?

sed_clksed_data

sed_stb_n

SED_CLK?SED_DATA?SED_STROBE_N?

adc_dac_clk_en_n

bs_sync_outft_int

bs_sync_inBS_SYNC_IN BS_SYNC_OUTFT_INT

Figure 2: 802.16 SOC System Block Diagram


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Register Address InitialName (hex) R/W Description Reference Value

(hex)

TDR 20 R/W Transmit DAC Register 00000000RCR0 21 R/W Receive Control Register 0 00000000RCR1 22 R/W Receive Control Register 1 00000000RCR2 23 R/W Receive Control Register 2 00000000RCR3 24 R/W Receive Control Register 3 00000000RCR4 25 R/W Receive Control Register 4 00000000RCR5 26 R/W Receive Control Register 5 00000000RCR6 27 R/W Receive Control Register 6 00000000RSR0 28 R Receive Status Register 0RSR1 29 R Receive Status Register 1RSR2 2A R Receive Status Register 2RSR3 2B R Receive Status Register 3

RSR4 2C R Receive Status Register 4RSR5 2D R Receive Status Register 5RSR6 2E R Receive Status Register 6RSR7 2F R Receive Status Register 7RSR8 30 R Receive Status Register 8RSR9 31 R Receive Status Register 9

P64CR0 32 R/W P64 Coefficient Register 0 00000000P64CR1 33 R/W P64 Coefficient Register 1 00000000P64CR2 34 R/W P64 Coefficient Register 2 00000000P64CR3 35 R/W P64 Coefficient Register 3 00000000P64CR4 36 R/W P64 Coefficient Register 4 00000000P64CR5 37 R/W P64 Coefficient Register 5 00000000P64CR6 38 R/W P64 Coefficient Register 6 00000000P64CR7 39 R/W P64 Coefficient Register 7 00000000

P128CR0 3A R/W P128 Coefficient Register 0 00000000P128CR1 3B R/W P128 Coefficient Register 1 00000000P128CR2 3C R/W P128 Coefficient Register 2 00000000P128CR3 3D R/W P128 Coefficient Register 3 00000000P128CR4 3E R/W P128 Coefficient Register 4 00000000P128CR5 3F R/W P128 Coefficient Register 5 00000000P128CR6 40 R/W P128 Coefficient Register 6 00000000P128CR7 41 R/W P128 Coefficient Register 7 00000000

APCR0 42 R/W AGC Power Compare Register 0 00000000APCR1 43 R/W AGC Power Compare Register 1 00000000APCR2 44 R/W AGC Power Compare Register 2 00000000

APCR3 45 R/W AGC Power Compare Register 3 00000000APCR4 46 R/W AGC Power Compare Register 4 00000000APCR5 47 R/W AGC Power Compare Register 5 00000000AAR0 48 R/W AGC Attenuator Register 0 00000000AAR1 49 R/W AGC Attenuator Register 1 00000000AAR2 4A R/W AGC Attenuator Register 2 00000000AAR3 4B R/W AGC Attenuator Register 3 00000000

Table 5: WMAN_PHY Register Description: 0x20 0x49


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Register Address InitialName (hex) R/W Description Reference Value

(hex)

RACR 4C R/W Receive I&Q Averaging Control Register 00000000RAVGR 4D R Receive I&Q Averaging Register 00000000SEDR 4E R Symbol Error Display Register 00000000

Table 6: WMAN_PHY Register Description: 0x4B 0x4D


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5 Reset LogicA block diagram of the WMAN_PHY reset logic is shown in Figure 3. A single activelow reset signal, reset_n, is provide to the phy. It is assumed that the reset_n signal isasynchronously asserted and synchronously removed based on the arcclk and lasts atleasts one arcclk clock cycle. Inside the PHY Module, reset_n is used to generate twomore reset signals re-timed based on phyclk and feclk to reset the PHY Core and thePHY/AFE interface respectively. The circuit has been designed so that the proper resetswill be generated independently of the power-up state of the flip flops.

fe_reset

phy_clk

fe_clk

phy_reset

arc_reset

CLK

D Qreset_n

arc_clk

CLK

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

D Q

Figure 3: PHY Reset Circuitry


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arc_clk

addr(6:0)

cs_n

wr_n

datao(6:0)

Figure 5: ARC/PHY Write Cycle Timing

arc_clk

addr(6:0)

cs_n

rd_n

datao(6:0)

data_valid

0-? cycles

Figure 6: ARC/PHY Read Cycle Timing

The ARC is clocked at 160 MHz compared with the WMAN_PHY which is clocked at100 MHz. As a result of the two separate clock domains the register interface is requiredto be retimed internally which results in limitations on read/write access. In a read accessthe data_valid signal is used to halt the ARC read cycle until the data is present. Thedata_valid signal can last between ?-? clock cycles depending on the relative timingbetween the two clocks.


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6.2 FIFO Control/Status

The PHY contains four FIFOs; a Tx Data FIFO, a Tx Control FIFO, a Rx Data FIFO andan RX Control FIFO. A brief description of the FIFOs are given below:

Tx Data FIFO: Contains payload data for the Phy transmitter and is written fromthe ARC. This FIFO is of size 127x32 bits or approximately fourOFDM symbols.

Tx Control FIFO: Contains the Transmit control frame which is written from theARC to the Phy. The FIFO is of size 12x32 bits. Each transmitcontrol frame contains three words so the FIFO can contain 4control frames.

Rx Data FIFO: Contains payload data from Phy receiver and is read by the ARC.This FIFO is of size 127x32 bits.Rx Control FIFO: Contains the Rx control frame which is written from the ARC to

the Phy. The FIFO is of size 12x32 bits. Each receive controlframe consists of 3 words so the FIFO can contain 4 controlframes.

The FIFO Control and Status Register are used to set up the FIFOs and are described inTable 7.


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Register Addr Field # of

Name (hex) R/W Name Bits Slice Description

FCR 00 R/W txdfTl 7 6:0 Tx Data FIFO trigger level sets the number of words below whichcauses the Tx Data FIFO watermark interrupt.

FCR 00 R/W txdfRst 1 7 Tx Data FIFO reset resets all status flags, indices, etc. when set to1. Does not clear contents of FIFO

FCR 00 R/W txcfRst 1 8 Tx Control FIFO reset resets all status flags, indices, etc. when setto 1. Does not clear contents of FIFO

FCR 00 R/W rxdfTl 7 15:9 Rx Data FIFO trigger level sets the number of words above whichcauses the Rx Data FIFO interrupt and flag

FCR 00 R/W rxdfRst 1 16 Rx Data FIFO reset resets all status flags, indices, etc. when set to1. Does not clear contents of FIFO

FCR 00 R/W rxcfRst 1 17 Rx Control FIFO reset resets all status flags, indices, etc. Does notclear contents of FIFO

FCR 00 R/W rxdfLpbkEn 1 18 Tx/Rx Data FIFO Loop Back Register when this bit is set to 1,data from the Tx Data Fifo is written to the Rx Data FIFOFCR 00 W txdfOverClr 1 19 Tx Data FIFO overrun clear when this bit is 1, the txdfOverrun flag

is cleared in the FSR. The bit is automatically cleared.FCR 00 W txcfOverClr 1 20 Tx Control FIFO overrun clear when this bit is 1, the txcfOverrun

flag is cleared in the FSR. The bit is automatically cleared.FCR 00 W rxdfUnderClr 1 21 Rx Data FIFO underrun clear when this bit is 1, the rxdfUnderrun

flag is cleared in the FSR. The bit is automatically cleared.FCR 00 W rxcfOverClr 1 22 Rx Control FIFO overrun clear when this bit is 1, the rxcfOverrun

flag is cleared in the FSR. The bit is automatically cleared.

FSR 01 R txdfLevel 7 6:0 Indicates number of words present in Tx Data FIFO

FSR 01 R txcfLevel 4 10:7 Indicates number of words present in Tx Control FIFO

FSR 01 R rxdfLevel 7 17:11 Indicates number of words present in Rx Data FIFO

FSR 01 R rxcfLevel 4 21:18 Indicates number of words present in Rx Control FIFO

FSR 01 R txdfOverrun 1 22 Too many words were written to the Tx Data FIFO - the bit can becleared using txdfOverClr in the FCR.

FSR 01 R txcfOverrun 1 23 Too many words were written to the Tx Control FIFO - the bit can becleared using txcfOverClr in the FCR.

FSR 01 R rxdfUnderrun 1 24 Too many words were read from the Rx Data FIFO - the bit can becleared using rxdfUnderClr in the FCR.

FSR 01 R rxcfOverrun 1 25 Too many words were written to the Rx Control FIFO - the bit can becleared using rxcfOverClr in the FCR.

Table 7: FIFO Register (FCR & FSR) Description


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6.3 Miscellaneous (RF,AFE,etc) Control RegistersThe Miscellaneous Control Register (MCR) contains various control bits for the Analog

Front End (AFE) and external txEn/rxEN operation.Register Addr Field # of


MCR 13 R/W dacPd_n 1 0 DAC power down

MCR 13 R/W 0 DAC powered-down

MCR 13 R/W 1 DAC enabled

MCR 13 R/W *** Inverter required on output of DAC_PD as polarity on DAC isopposite of the above

MCR 13 R/W dac2sCmpSel 1 1 This bits select the numeric format for the DAC output

MCR 13 R/W 0 Offset binary

MCR 13 R/W 1 Twos complementMCR 13 R/W adcPd_n 1 2 ADC power down

MCR 13 R/W 0 ADC powered-down

MCR 13 R/W 1 ADC enabled

MCR 13 R/W adc2sCmpSel 1 3 This bits select the numeric format for the ADC output

MCR 13 R/W 0 Offset binary

MCR 13 R/W 1 Twos complement

MCR 13 R/W adcOutEn_n 1 4 ADC Output EnableMCR 13 R/W 0 Outputs enabledMCR 13 R/W 1 Outputs set to 0MCR 13 R/W overrideEn 1 5 Override Enable turns off the automatic rx_en, tx_en output logic

and causes the state of the rx_en and tx_en signals to follow thestate of the rxEn and txEn bits in this register.

MCR 13 R/W txEn 1 6 If OverrideEn = 1, the tx_en output will follow the state of this bit

MCR 13 R/W rxEn 1 7 If OverrideEn = 1, the rx_en output will follow the state of this bitMCR 13 R/W trSwEn 1 8 If OverrideEn = 1, the tr_sw output will follow the state of this bit

MCR 13 R/W fddSel 1 9 FDD/TDD Mode Select - controls the operation of rx_en and tx_enoutputs as long as en_override = 0.

MCR 13 R/W 0 TDD ModeMCR 13 R/W 1 FDD ModeMCR 13 R/W reserved 1 10 Reserved

MCR 13 R/W bandgapPd_n 1 11 Bandgap reference power down

MCR 13 R/W 0 bandgap reference powered-down

MCR 13 R/W 1 bandgap reference enabled

MCR 13 R/W vrefPd_n 1 12 Voltage reference power down

MCR 13 R/W 0 voltage reference powered-downMCR 13 R/W 1 voltage reference enabled

MCR 13 R/W adcDacClkEn_n 1 13 Enables fe_clk to be driven to the ADCs and DACs.

MCR 13 R/W 0 fe_clk is driven to the ADCs and DACs

MCR 13 R/W 1 fe_clk is not driven to the ADCs and DACs

Table 8: Miscellaneous Control Register (MCR) Description


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rx_en

tx_en

Tx Data from Phy

txStartDelay

txRxDelay

txStopDelay

tx_en

tr_sw

trSwDelay

Figure 7: rx_en, tx_en & tr_sw timing: TDD Mode

A diagram of the timing for rx_en and tx_en is shown in Figure 8 for FDD operation.Note that the timing of rx_en is independent of tx_en in this mode. The delay from tx_engoing high to data output is specified by txStartDelay. During this time zeros aretransmitted. t r. The delay from the end of Transmit Data to tx_en low is specified bytxStopDelay. This allows a programmable number of zeros to be output by thetransmitter before it is shut off. For rx_en, the time, rxStartDelay, from the rising edge ofrx_en going high to the actual frame time that reception of data starts can be set. Thisallows the RF receiver to be turned on prior to the time when the OFDM receiver isactually enabled. It is assumed that the Rx Control Word is placed in the FIFO at leastrxStartDelay before the time at which reception of data actually occurs.

rx_en

tx_en

Tx Data from Phy

txStartDelay

rxStartDelay

txStopDelay

Figure 8: rx_en/tx_en timing: FDD Mode


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The delays are specified in terms of the number of samples (1 OFDM Symbol = 319samples) through a 10-bit register in the DTCR. Note that the delay times are dependenton the channel bandwidth of the modem and should be calculated accordingly. A 10-bitdelay timer range provide up to 38 us delay with 0.037 us resolution at 20 MHz channelbandwidth and 484 us delay with 0.47 us resolution at 1.5 MHz channel bandwidth.

Internal signals, rx_enable and tx_enable are gated by external control logic according tothe diagram in Figure 9 in order to produce the rx_en and tx_en outputs. The internalsignals rx_enable and tx_enable have the same timing and functionality as described inabove for rx_en and tx_en. Three input signals; Lock Detect (Active High) lock_det,Lock Detect (Active Low) lock_det_n and RF Enable rf_enable are used to gate theenable signals. In addition the override logic is also shown.

rx_enable (internal)

tx_enable (internal)

lock_det

rf_enable

tx_en

rx_enld_n

In0

In1Sel

Out

MCR.overridEn

In1

In0Sel

Out

MCR.txEn

MCR.rxEn

tr_sw

In1

In0Sel

Out

tr_sw (internal)

MCR.trSw

Figure 9: rx_en, tx_en & tr_sw control logic


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6.4 InterruptsThe WMAN_PHY generates an active low interrupt, INTB, to the ARC. The PHY

interrupt sources are enabled through the Interrupt Enable Register or IER. The InterruptRegister (IR) provides the status of the interrupt after it has been sampled. The InterruptInformation Register (IIR) provides the status of the interrupt before it has been sampledand can be used to monitor the states of level-sensitive interrupts. The Interrupt ClearRegister (ICR) is used to clear the sampled interrupts.



IER 06 R/W txdfTrigEn 1 0 Setting this bit to 1 enables the Tx Data FIFO Trigger interrupt TxFIFO data has fallen below the trigger threshold

IER 06 R/W txdfUnderrunEn 1 1 Setting this bit to 1 enables the Tx Data FIFO Underrun interruptPhy has attempted to read data but no data was present

IER 06 R/W txcfEmptyEn 1 2 Setting this bit to 1 enables the Tx Control FIFO Empty interrupt

IER 06 R/W rxdfTrigEn 1 3 Setting this bit to 1 enables the Rx Data FIFO Trigger interrupt RxFIFO data has exceeded the trigger threshold

IER 06 R/W rxdfOverrunEn 1 4 Setting this bit to 1 enables the Rx Data FIFO Overrun interrupt Phyhas attempted to write data to FIFO but FIFO was full

IER 06 R/W rxcfEmptyEn 1 5 Setting this bit to 1 enables the Rx Control FIFO Empty interrupt

IER 06 R/W txBurstDoneEn 1 6 Setting this bit to 1 enables the transmit burst done interrupt

IER 06 R/W scramErrorEn 1 7 Setting this bit to 1 enables the tx scrambler underflow error interrupt

IER 06 R/W rxBurstDoneEn 1 8 Setting this bit to 1 enables the receiver burst done interrupt

IER 06 R/W syncDoneEn 1 9 Setting this bit to 1 enables the receiver sync done interrupt

IER 06 R/W pilotUpdateEn 1 10 Setting this bit to 1 enables the receiver pilot update interruptIER 06 R/W rsUpdateEn 1 11 Setting this bit to 1 enables the receiver Reed Solomon error update

interrupt

IER 06 R/W berUpdateEn 1 12 Setting this bit to 1 enables the receiver Viterbi bit error rate updateinterrupt

IER 06 R/W fti0En 1 13 Setting this bit to 1 enables Frame Timer Interrupt 0






IER 06 R/W illegalAccessEn 1 19 Setting this bit to 1 enables the illegal access interrupt

IER 06 R/W ftIntEn 1 20 Setting this bit to 1 enables a pulse to be output on the ft_int pineverytime the conditions programmed in FTINT0 are satisfied.

Table 10: Interrupt Enable Register (IER) Description


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The Interrupt Status Register or ISR provides the status of all interrupts, enabled or not.

Register Addr Field # ofName (hex) R/W Name Bits Slice Description

ISR 08 R txdfTrigInt 1 0 Tx Data FIFO Trigger interrupt interrupt is set to 1 when thenumber of words in the Tx Data FIFO falls below the triggerthreshold. The interrupt register can be cleared by writing a 1 to thislocation in the ICR. The interrupt source is cleared by writingsufficient data to the FIFO so that the trigger threshold is met oralternatively resetting the FIFO

ISR 08 R txdfUnderrunInt 1 1 Tx Data FIFO Underrun interrupt this interrupt is set to 1 when thephy has attempted to read data from the Tx Data FIFO and no datawas present - use ICR to clear

ISR 08 R txcfEmptyInt 1 2 Tx Control FIFO Empty Interrupt this interrupt is set to 1 when theTx Control FIFO is empty. The interrupt register can be cleared bywriting a 1 to this location in the ICR. The interrupt source is clearedby writing data to the FIFO

ISR 08 R rxdfTrigInt 1 3 Rx Data FIFO Trigger interrupt this interrupt is set to 1 when the

number of words in the Rx Data FIFO exceeds the trigger threshold.The interrupt register can be cleared by writing a 1 to this location inthe ICR. The interrupt source can be cleared by reading data fromthe Rx FIFO so that the number of words is below the t riggerthreshold or alternatively by resetting the FIFO

ISR 08 R rxdfOverrunInt 1 4 Rx Data FIFO Overrun interrupt this interrupt is set to 1 when thephy has attempted to write data to the Rx Data FIFO and the FIFOwas full - use ICR to clear

ISR 08 R rxcfEmptyInt 1 5 Rx Control FIFO Empty Interrupt this interrupt is set to 1 when theRx Control FIFO is empty. The interrupt register can be cleared bywriting a bit to this location in the ICR. The interrupt source iscleared by writing data to the FIFO

ISR 08 R txBurstDoneInt 1 6 Transmit Burst Done Interrupt Status this interrupt is set to 1 whena burst from the transmitter has been sent. The sequence numberof the burst (burstSeqNum) is reported back in the Tx StatusRegister (TSR). This interrupt can be cleared by writing a 1 to theICR at this bit location.

ISR 08 R scramErrorInt 1 7 Transmit Scrambler Error Interrupt Status this interrupt is set to 1when a scrambler error has been detected. The sequence numberof the burst with the error (ScramSeqNum) is reported back in the TxStatus Register (TSR). This interrupt can be cleared by writing a 1 tothe ICR at this bit location.

ISR 08 R rxBurstDoneInt 1 8 Recieve Burst Done Interrupt Status this interrupt is set to 1 whena burst has been received by the receiver. The sequence number ofthe burst (burstSeqNum) is reported back in the Rx Status Register(RSR0). This interrupt can be cleared by writing a 1 to the ICR atthis bit location.

ISR 08 R syncDoneInt 1 9 Recieve Sync Done Interrupt Status this interrupt is set to 1 whenthe receiver has completed a synchronizing search and has updatedthe sync status registers. The results of the search can be readfrom RSR1 - RSR4. This interrupt can be cleared by writing a 1 tothe ICR at this bit location.

ISR 08 R pilotUpdateInt 1 10 Recieve Pilot Update Interrupt Status this interrupt is set to 1 whenthe receiver has updated the pilot status registers. The results canbe read from RSR5 and RSR6. This interrupt can be cleared bywriting a 1 to the ICR at this bit location.

ISR 08 R rsUpdateInt 1 11 Recieve Reed Solomon Update Interrupt Status this interrupt is setto 1 when the number of errors corrected by the Reed Solomondecoder has been updated. The results can be read f rom RSR7.This interrupt can be cleared by writing a 1 to the ICR at this bitlocation.


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ISR 08 R berUpdateInt 1 12 Recieve Bit Error Rate Update Interrupt Status this interrupt is setto 1 when the soft bit error rate from the Viterbi decoder is updated.The results can be read from RSR7. This interrupt can be clearedby writing a 1 to the ICR at this bit location.

ISR 08 R fti0Int 1 13 Frame Timer Interrupt 0 Status use ICR to clear






ISR 08 R illegalAccessInt 1 19 Illegal Access Interrupt Status this interrupt is set to 1 when anaccess to an undefined register address is detected or if a writeoperation is performed to a read-only register. This interrupt can becleared by writing a 1 to the ICR at this bit location.

Table 11: Interrupt Register (ISR) Description


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The Interrupt Information Register provides information on level based interrupts at thepoint before the interrupt is sampled and fed to the ISR. This allows level based interruptsources to be monitored directly.



IIR 09 R txdfTrigInf 1 0 State of the signal feeding the Tx Data FIFO Trigger interrupt

IIR 09 R reserved 1 1 Reserved

IIR 09 R txcfEmptyInf 1 2 State of the signal feeding the Tx Control FIFO Empty Interrupt

IIR 09 R rxdfTrigInf 1 3 State of the signal feeding the Rx Data FIFO Trigger interrupt

IIR 09 R reserved 1 4 Reserved

IIR 09 R rxcfEmptyInf 1 5 State of the signal feeding the Rx Control FIFO Empty Interrupt

Table 13: Interrupt Information Register (IIR) Description


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The Interrupt Clear Register allows interrupts and interrupt status flags in the InterruptStatus Register to be cleared. The interrupts are cleared by writing a 1 to the specified bitlocation. The ICR is self-clearing so if a bit is set high it will automatically be clearedafter it has been written.



ICR 0A R txdfTrigClr 1 0 Setting this bit to 1 clears the Tx Data FIFO Trigger interrupt TxFIFO data has fallen below the trigger threshold

ICR 0A R txdfUnderrunClr 1 1 Setting this bit to 1 clears the Tx Data FIFO Underrun interrupt Phyhas attempted to read data but no data was present

ICR 0A R txcfEmptyClr 1 2 Setting this bit to 1 clears the Tx Control FIFO Empty interrupt

ICR 0A R rxdfTrigClr 1 3 Setting this bit to 1 clears the Rx Data FIFO Trigger interrupt RxFIFO data has exceeded the trigger threshold

ICR 0A R rxdfOverrunClr 1 4 Setting this bit to 1 clears the Rx Data FIFO Overrun interrupt Phyhas attempted to write data to FIFO but FIFO was full

ICR 0A R rxcfEmptyClr 1 5 Setting this bit to 1 clears the Rx Control FIFO Empty interrupt

ICR 0A R txBurstDoneClr 1 6 Setting this bit to 1 clears the transmit burst done interrupt

ICR 0A R scramErrorClr 1 7 Setting this bit to 1 clears the tx scrambler underflow error interrupt

ICR 0A R rxBurstDoneClr 1 8 Setting this bit to 1 clears the receiver burst done interrupt

ICR 0A R syncDoneClr 1 9 Setting this bit to 1 clears the receiver sync done interrupt

ICR 0A R pilotUpdateClr 1 10 Setting this bit to 1 clears the receiver pilot update interrupt

ICR 0A R rsUpdateClr 1 11 Setting this bit to 1 clears the receiver Reed Solomon error updateinterrupt

ICR 0A R berUpdateClr 1 12 Setting this bit to 1 clears the receiver Viterbi bit error rate updateinterrupt

ICR 0A R fti0Clr 1 13 Setting this bit to 1 clears Frame Timer Interrupt 0






ICR 0A R illegalAccessClr 1 19 Setting this bit to 1 clears the illegal access interrupt

Table 14: Interrupt Clear Register (ICR) Description


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6.5 Frame Timer:

An OFDM frame timer is provided as a reference time base for the WMAN_Phy. Theperiodicity of the frame timer is specified through three parameters as follows:ftFrameLength the symbol value at which the frame timer will wrapftCpLength the cyclic prefix length used within the OFDM symbolframeFinal the number of samples in the final symbol of the frame

The ftFrameLength symbol field is an 11-bit value which allows the maximum frame sizeof 20 msto be achieved. The number of samples within each OFDM symbol variesaccording to the cyclic prefix length specified in ftCPlength. The number of samplesdepends on the cyclic prefix length. A table showing the correspondence betweenftCpLength and G, the ratio of cylic prefix time to useful time is shown in. .

G ftCpLength1/32 81/16 161/8 321/4 64

Table 15: Cyclic Prefix Lengths

In order to provide precise 2.5 ms to 20 ms frame sizes an additional frameFinal fieldregister is provided. This field specifies the final number of samples in the last partialsymbol of a frame. It is required due to the fact that there is not normally an integer

number of OFDM symbols in the required 2.5 to 20 ms frames due to the varyingchannel bandwidth and cyclic prefix lengths of the target systems. In order to generatethe proper ftFrameLength and frameFinal register values for each combination of channelbandwith, frame size and cyclic prefix length the following formulas and examples areprovided:

n = sampling factorBW = nominal channel bandwidth (Hz)Nfft = FFT size i.e 256ft = frame time (seconds)G = ratio of cyclic prefix time to useful time

Fs = sample frequencySamplesperframe = number of samples per frameSamplespersymbol = number of samples per symbol

fs = floor(BW*n/0.008)*0.008;samplesperframe = fs*ft;samplespersymbol = Nfft + G*Nfft;


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ftFrameLength = floor(samplesperframe/(Nfft + G*Nfft));frameFinal = samplesperframe - ftFrameLength*samplespersymbol;

The following Matlab script shows an example calculation for 1.25 MHz channelbandwidth with G= 1/32 and a 2.5 msec frame time:

n = 144/125;BW = 1.25e6;ft = 2.5e-3;Nfft = 256;G = 1/32;

fs = floor(BW*n/0.008)*0.008;samplesperframe = fs*ft;samplespersymbol = Nfft + G*Nfft;

ftFrameLength = floor(samplesperframe/(Nfft + G*Nfft));frameFinal = samplesperframe - ftFrameLength*samplespersymbol;

ftFrameLengthframeFina l

Result:ftFrameLength =13frameFinal =168

The status of the frame timer can be read through the ftSample and ftSymbol fields in theFrame Timer Status Register.

Six internal interrupts are provided to allow programmable frame-timing based interruptsto the micro controller. The symbol and sample values for each of the frame timerinterrupts are specified through the FTINTR0-5 registers. Operation of these interrupts iscontrolled through the interrupt registers.

The frame timer also has an external interrupt, ft_int. This signal uses the timer valuespecified for frame timer interrupt 0 in order to generate a periodic pulse based externalinterrupt. ft_int is enabled by setting the IER.ftIntEn bit high. . When enabled ft_int willprovide a 160 ns pulse (10 phy_clock cycles @ 100 MHz) whose period is equal to theframe timer duration. Note that ft_int is not enabled, disabled or affected by the frametimer 0 interrupt registers.

The frame timer can either be initialized to start at an arbitrary time (BS Mode) or can beinitialized during the Rx synchronization process (SS Mode). The frame timer can becleared and reset by setting the ftClr bit in theFTCR. The current value of the frame timercan be read in the Frame Timer Status Register.


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It is also possible to synchronize or reset the frame timer using the BS_SYNC_INexternal signal. The rising edge of the BS_SYNC_IN signal is detected and used toprovide the reset to the frame timer. An additional output signal, BS_SYNC_OUT, isalso available which gives a 160 ns (10 phy_clock cycles @ 100 MHz) pulse wheneverthe frame timer is reset, whether through external or internal means.Register Addr Field # of


FTCR 0B R/W ftFrameLength 11 10:0 Symbol value at which the frame timer will wrap

FTCR 0B R/W ftCpLength 8 18:11 cyclic prefix length 8-bit number that specifies the CP length i.e 0,8, 16, 32, 64

FTCR 0B W ftClr 1 19 Clear frame timer by setting this bit high - this bit is self-clearing

FTCR 0B R/W frameFinal 10 28:20 Number of samples in the final symbol of the frame. unsigned

FTSR 0C R ftSample 9 8:0 Current value of the sample field of the frame timer. The maximum

value of the sample field is (255 + ftCpLength) before it wraps tozero.

FTSR 0C R ftSymbol 11 19:9 Current value of the symbol field of the frame timer. The maximumvalue of symbol field is set using ftFrameLength

FTINTR0 0D R/W sampInt0 9 8:0 Sample value at which Frame Timer Interrupt 0 will occur

FTINTR0 0D R/W symInt0 11 19:9 Symbol value at which Frame Timer Interrupt 0 will occur

FTINTR1 0E R/W sampInt1 9 8:0 Sample value at which Frame Timer Interrupt 1 will occur

FTINTR1 0E R/W symInt1 11 19:9 Symbol value at which Frame Timer Interrupt 1 will occur

FTINTR2 0F R/W sampInt2 9 8:0 Sample value at which Frame Timer Interrupt 2 will occur

FTINTR2 0F R/W symInt2 11 19:9 Symbol value at which Frame Timer Interrupt 2 will occur

FTINTR3 10 R/W sampInt3 9 8:0 Sample value at which Frame Timer Interrupt 3 will occur

FTINTR3 10 R/W symInt3 11 19:9 Symbol value at which Frame Timer Interrupt 3 will occur





Table 16: Frame Timer Register (FTR) Description


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An address counter is used to drive the address of the preamble and agc translationmemories. The address counter is reset to 0 by setting the addCntRst bit in the PMCRhigh then low. Subsequent writes will cause the address counter to automaticallyincrement. The data for the memories is written to from the Preamble Memory DataRegister (PMDR).


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PMCR 16 R/W rxMemEn 1 0 Rx Preamble Memory Enable

PMCR 16 R/W 0 Writes to to the receiver preamble memory are inhibited

PMCR 16 R/W 1 Writes to the receiver preamble memory are enabled

PMCR 16 R/W txMemEn 1 1 Tx Preamble Memory Enable

PMCR 16 R/W 0 Writes to to the transmitter preamble memory are inhibited

PMCR 16 R/W 1 Writes to the transmitter preamble memory are enabled

PMCR 16 W addCntRst 1 2 Address Counter Reset

PMCR 16 W Writing a 1 resets the 8-bit memory address counter. This bit clearsitself after the operation completes.

PMCR 16 R/W agcMemEn 1 3 AGC Translation Memory Enable

PMCR 16 R/W 0 Writes to to the AGC translation memory are inhibitedPMCR 16 R/W 1 Writes to the AGC translation memory are enabled

PMDR 17 W wrMemVal 12 21:0 The value written to this address is applied to the selected Rx or Txpreamble memory. The address counter is incremented after theoperation.

PMSR 18 R addrStatus 8 7:0 Address Counter Status Read only value which reflects the valueof the address counter

Table 17: Preamble Memory Control (PMCR) and Data Register (PMDR) Description


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7 Transmitter

7.1 OverviewThe WMANY_Phy transmitter takes uncoded blocks of data and then scrambles, encodesand modulates the data according to the 802.16 specification. The main blocks in thetransmitter are:

Transmit Channel Encoder consisting of:ScramblerEncoder: Reed Solomon Encoder

Serial BufferConvolutional Encoder

Puncturer

InterleaverModulatorIFFTTransmit Front End consisting of:

Tx BufferTx Interpolation FilterTx Test Tone GeneratorTx Analog Front End Interface

A block diagram of the transmitter is shown in Figure 10.

Tx Data

Tx ControlRegisters

WMAN_PHY Transmitter

256-ptIFFT

Tx ChannelEncoder:

Tx Control

Tx StatusRegisters

Int.Filter

AFE TxInterface

TxBuffer

Tx Front End

Scrambler

Encoder

Puncturer

Interleaver

Modulator

TestCircuitry

Figure 10: Transmitter Block Diagram


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7.2 Transmitter Control Word and Register DescriptionWord Field # ofName Word Name Bits Slice Description

tx_cntl0 0 start 11 10:0 Burst start time (symbol number)

rate 3 13:11 Modulation and Code Rate Selection:000 BPSK, R=1/2001 BPSK, R= 010 QPSK, R=1/2011 QPSK, R=

100 QAM 16, R=1/2101 QAM 16, R=3/4110 QAM 64, R=2/3111 QAM 64, R=3/4

length 18 31:14 Number of data bytes to transmit.tx_cntl1 1 seqNum 4 3:0 Control sequence number Tag which can be used to identify a specific

control word

preType 2 5:4 Transmit preamble type:00 No preamble

01 Short preamble (P128)10 Long preamble (P64 + (P128 or Psub))

11 ReservedmidType 2 7:6 Burst midamble type (repetition interval)

00 No midamble01 8 symbol midamble repetition interval

10 16 symbol midamble repetition interval11 32 symbol midamble repetition interval

subChan 5 12:8 Specifies subchannel index0000 16 subchannels with no RS encoding

00001 11111 as per Table 185(D2)scramEn 1 13 Turn on/off scrambling for the burst

0 scrambler off1 scrambler on

scramInit 1 14 Initialize scrambler at start of burst if set to 1scramSeed 15 29:15 Transmit Scrambler Seed

intEn 1 30 Transmit Burst Interrupt Enable0 Interrupt is disabled

1 - Enables an interrupt after the transmit burst has been sent. Note,interrupt must still be enabled at IER

Table 18: Transmit Control Word Description


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TCR0 19 R/W txBsSel 1 0 BS/SS Mode Selection for Transmitter

TCR0 19 R/W 0 Subscriber Station

TCR0 19 R/W 1 - Base Station

TCR0 19 R/W txRst 1 1 Transmitter is held in reset when set to 1

TCR0 19 R/W ifftScale 4 5:2 Selects number of scaling shifts to be performed in the IFFT on thetransmit data. Expected range is from 0 to 8

TCR0 19 R/W ifftScalePre 4 9:6 Selects number of scaling shifts to be performed in the IFFT on thetransmit preamble. Expected range is from 0 to 8.

TCR0 19 R/W ifftScaleSub 4 13:10 Selects number of scaling shifts to be performed in the IFFT on thetransmit subchannel preamble. Expected range is from 0 to 8.

TCR1 1A R/W offsetSample 9 8:0 Selects number of samples to offset the frame timer by.

TCR1 1A R/W offsetSymbol 11 19:9 Selects number of symbols to offset the frame timer by.

TCR1 1A R/W pilotSeed 11 30:20 Pilot seed for initialization at symbol 0.

Table 19: Transmit Control Register (TCR0,1) Description



TSR 1B R BurstSeqNum 4 3:0 Sequence number which caused txBurstDone Interrupt

TSR 1B R ScramSeqNum 4 7:4 Sequence number which caused txScramError Interrupt

Table 20: Transmit Status Register (TSR) Description


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7.3 Transmitter TimingThe timing of a transmit burst is normally dictated by the burst start time field in the Tx

Control Word. The TCW.start field gives the frame timer symbol number at which theburst should be transmitted. A diagram of a transmit burst starting at frame timer symbol0 is shown in Figure 11.

During ranging a subscriber station may be told by the base station to adjust the timing ofits transmit bursts. In order to accommodate ranging the transmit timing offset registers,TCR1.offsetSymbol and TCR1.offsetSample, are provided. These allow all transmitbursts to be offset by a integer number of symbols and samples. A diagram of a transmitburst with TCR1.offsetSymbol =1 and TCR1.offsetSample =90 is shown in Figure 12.

Tx Data from Phy

218 0 1 2 3 4 217Frame Timer

Pre Data

Transmit Control Word issued togenerate preamble at symbol 0TCR1.offsetSymbol = 0TCR1.offsetSample = 0

2.5 ms Frame

Figure 11: Transmit Burst Timing no Offset

Tx Data from Phy

218 0 1 2 3 4 217Frame Timer

Pre Data

Transmit Control Word issued togenerate preamble at symbol 0TCR1.offsetSymbol = 1TCR1.offsetSample = 90

2.5 ms Frame

Figure 12: Transmit Burst Timing with Offset


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7.4 Transmit Channel Encoder7.4.1 Scrambler

The scrambler performs data randomization on each uplink and downlink burst. Thescrambler consists of a 15-bit Linear Feedback Shift Register (LFSR) with feedbackpolynomial 1 + x 14 + x 15 . A diagram of the LFSR is shown in Figure 13. The state of theLFSR is initialized at the start of every allocation. This is accomplished through thescramInit and seed values of the Tx Control Word. In addition, the Scrambler performspadding in cases where the amount of data to be transmitted does not make up a completeOFDM symbol. In theses cases where RS-CC and CC coding is employed, the scramblerwill pad 0xFF to the end of the transmission block allocated with the exception of the lastbyte which is reserved for the 0x00 Viterbi tail byte.

data in

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

data out

Figure 13: Scrambler LFSR

7.4.2 Encoder

The Encoder consists of the following blocks:Reed-Solomon EncoderSerial BufferConvolutional Encoder

Two types of coding are supported: Reed-Solomon + Convolutional Coding RS-CC orConvolutional Coding CC. The type of coding provided for each symbol of transmitdata is determined by the rate and subChan fields of the Tx Control Word. The blocksizes and code rates used for different modulations are shown in Table 21.

tx_cntl0rate

Modulation UncodedBlockSize

CodedBlockSize

OverallCoding

Rate

RS Code CCCodeRate

Comment

0000 BPSK 12 24 1/2 (12,12,0) 1/2 standard compliant0001 BPSK 12 24 3/4 (12,12,0) 3/4 proprietary0010 QPSK 24 48 1/2 (32,24,4) 2/3 standard compliant0011 QPSK 48 48 3/4 (40,36,2) 5/6 standard compliant


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0100 16-QAM 36 96 1/2 (64,48,8) 2/3 standard compliant0101 16-QAM 72 96 3/4 (80,72,4) 5/6 standard compliant0110 64-QAM 96 144 2/3 (108,96,6) 3/4 standard compliant0111 64-QAM 108 144 3/4 (120,108,6) 5/6 standard compliant

Table 21: Block Sizes per Modulation Format

The block descriptions are as follows:

Reed-Solomon Encoder:

The Reed Solomon encoder utilizes an RS(N=255,K=239, T=8) code. The field andgenerator polynomials are as follows:

Code Generator Polynomial: g ( x ) = ( x + 0) ( x + 1) ( x + 2) ( x + 2T-1 ), =02 HEX

Field Generator Polynomial: p ( x ) = x8

+ x4

+ x3

+ x2

+ 1

Note, that the RS encoder is bypassed in subchannelization mode.

Serial Buffer:

A buffer is provided to serialize the bytes provided by the RS Encoder into bits.

Convolutional Encoder:

Each RS block is encoded by a binary convolution encoder with rate, R = , and

constraint rate, K=7, according to the generator polynomials, g0 = 133, g1 = 171. Theconvolutional encoder produces two bits, X & Y as shown in Figure 14.

data in

X

+

+

Y

Figure 14: Convolutional Encoder


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7.4.3 Puncturer and Interleaver

In order to achieve different code rates, data from the convolutional encoder is punctured.The puncture patterns used to provide the different rates are shown in . A 1 indicates the

bit is transmitted and a 0 indicates the bit is removed.

Rate 1/2 2/3 3/4 5/6X 1 10 101 10101Y 1 11 110 11010

Table 22: Puncture Patterns

Interleaving is performed through a two step permutation of a block of encoded inputdata according to formulas defined in the 802.16 specification. The block sizes of theinterleaver depend on the modulation type i.e. BPSK, QPSK, 16-QAM & 64-QAM asshown in Table 23.

Rate 16subchannels

8 subchannel 4 subchannels 2 subchannels 1 subchannel

BPSK 192 96 48 24 12

QPSK 384 192 96 48 24

16-QAM 768 384 192 96 4864-QAM 1152 576 288 144 73

Table 23: Interleaver Block Sizes

The Interleaver block is responsible for insertion of the preamble sequences before thebits are fed to the Modulator. The preamble sequences are specified in the Preamble

Memory Data Register (PMDR) as described in section 6.6. The determination as towhether preamble sequences or regular data are to be transmitted is made through thepreType field in the TCW.

In addition, the Interleaver performs the insertion of Pilot subcarriers into each data burst.A LFSR with polynomial 1 + X 9+X 11 , shown in Figure 15, is used to generate the pilotsequence w k where k represents the OFDM symbol index. In DL mode the index krepresents the symbol index relative to the beginning of the downlink subframe. In ULmode the index k represents the symbol index relative to the beginning of the burst. InInitialization of the LFSR is dependent on whether the phy is in DL or UL mode.

In Dl mode the pilot initilization sequence is 11111111111. In UL mode the pilotinitialization sequence is 10101010101. The pilot initialization sequence is set throughTCR0.pilotSeed.


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TMR2 1E R/W moduPilot 10 9:0 Modulation constellation scale value for pilot - signed

TMR2 1E R/W moduBPSK 10 19:10 Modulation constellation scale value for +1 at BPSK - signed

Table 24: Transmit Modulation Register (TMR0-2) description

The scaling provided in the Transmit Modulation Registers is designed to provide thenormalization, c , required by the 802.16 specification to achieve equal average power forall modulation types. The actual scaling level for each modulation constellation is acombination of the normalization factor, c, and a backoff factor, bkoff used for pre-scaling of the IFFT input to reduce the potential for saturation and ensure the maximuminput value is less than 1. An example showing the setting of the scale value for aparticular modulation constellation is shown below:

moduQAM64 = c * bkoff = (1/sqrt(42)) *0.92 = 0.136054

Typical scale control values for each modulation type are shown in Table 25 for referencepurposes.

Field Name c bkoff Quantized Value

moduQAM64 1/sqrt(42) 0.92 0.142578125moduQAM16 1/sqrt(10) 0.92 0.291015625moduQPSK 1/sqrt(2) 0.92 0.650390625

moduP64 1 0.92 0.919921875moduP128 1/sqrt(2) 0.92 0.650390625moduPSub 1/sqrt(2) 0.92 0.650390625

moduPilot 1 0.92 0.919921875moduBPSK 1 0.92 0.919921875

Table 25: Typical Transmit Modulation Scale Values

7.5 IFFTThe IFFT block is a radix-2 256-point pipelined FFT processor. It performs a 256-pointcomplex Inverse Fast Fourier Transform on the modulated subcarriers provided byModulator. The input and output precision of the IFFT is 10-bits. Note that the IFFTblock is not resource shared with the receiver

Two scaling parameters are provided in the IFFT. They are ifftScale which scales thetransmitted data and ifftScalePre which scales the preamble. Both values areprogrammed through the TCR and are 4-bits with the maximum scale value being limitedto 8. The scale value basically controls a right shift on the decimal point of the IFFToutput and allows the range of the IFFT output to be increased. An example is shown inTable 26 for a signal with input precision. The default scale values weredetermined through simulations of various typical 802.16 transmit bursts with the


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intention of achieving less than ?? saturation/clipping events in ??. The default values forifftScale and ifftScalePre has been set to 6 and 5 respectively.

ScaleValue

InputPrecision

OutputPrecision

0 1.9 1 2 3 4 5 6 7 8

Table 26: IFFT Scaling Example


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7.6 Transmit Front End7.6.1 Tx Buffer

The Tx Buffer is performs Cyclic Prefix insertion on the data output by IFFT in order toform a proper OFDM symbol.. Cyclic prefix lengths of 1/64, 1/32, 1/16 and 1/8 aresupported.

7.6.2 Interpolation Filter

The interpolation filter is a 39-tap halfband filter with approximately 60 dB stopbandattenuation and 0.01 dB ripple. The passband corner lies at 0.42 Fs. The frequencyresponse is shown in Figure 16.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9-180

-160

-140

-120

-100

-80

-60

-40

-20

0

20

Normalized Frequency ( rad/sample)

Magnitude(dB)

Magnitude Response (dB)

Figure 16: Frequency Response of 39-tap Halfband Tx Interpolation Filter

7.6.3 Tx FIFO

The Tx FIFO resolves the asynchronous clock domain boundary between the fixed 100MHz Phy clock (phy_clk) and the variable rate AFE clock (fe_clk). The transmitter hasbeen designed such that the Tx FIFO pulls data as required to meet the ADC clock rate.


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TDR 20 R/W Idac 10 9:0 In-phase DAC value value to placed on the output of the I DACwhen txOutRegsSel = 1

TDR 20 R/W Reserved 6 15:10

TDR 20 R/W Qdac 10 25:16 Quadrature DAC value value to be placed on the output of the QDAC when txOutRegsSel = 1

Table 28: Transmit DAC Register(TDR) Description

Test ToneFrequencySelection

(ttfsel integer)

Test ToneFrequencySelection

(ttfsel(5:0) Hex)

Output Frequency,250 kHz step

Output Frequency500 kHz step

1 0x1 250 kHz 500 kHz2 0x2 500 kHz 1000 kHz3 0x3 750 kHz 1500 kHz4 0x4 1000 kHz 2000 kHz5 0x5 1250 kHz 2500 kHz6 0x6 1500 kHz 3000 kHz7 0x7 1750 kHz 3500 kHz8 0x8 2000 kHz 4000 kHz9 0x9 2250 kHz 4500 kHz

10 0xa 2500 kHz 5000 kHz11 0xb 2750 kHz 5500 kHz12 0xc 3000 kHz 6000 kHz

13 0xd 3250 kHz 6500 kHz14 0xe 3500 kHz 7000 kHz15 0xf 3750 kHz 7500 kHz16 0x10 4000 kHz 8000 kHz17 0x11 4250 kHz 8500 kHz18 0x12 4500 kHz 9000 kHz19 0x13 4750 kHz 9500 kHz20 0x14 5000 kHz 10000 kHz

Table 29: Transmit Test Tone Selection Table


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8 Receiver

8.1 OverviewThe WMANY_Phy receiver takes sampled data from the AFE and then filters,synchronizes, demodulates, decodes and descrambles the data according to the 802.16specification. The main blocks in the transmitter are:

Receive Front EndRx Analog Front End InterfaceAutomatic Gain Control (AGC) Wi-Lan SpecificRx Decimation FilterFrequency CorrectionCP Removal

Synchronization and Automatic Frequency Control (AFC) Wi-Lan SpecificFFTTiming CorrectionChannel Decoder consisting of:

Channel EstimatorDeinterleaverDepuncturerDecoder: Viterbi Decoder

Reed-Solomon DecoderDescrambler

A block diagram of the receiver is shown in Figure 17


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Rx Data

Rx ControlRegisters

WMAN_PHY Receiver

256-ptFFT

Rx ChannelDecoder:

Rx Control

Rx StatusRegisters

DecimationFilter

AFE RxInterface

Rx Front End

Descrambler

Encoder

Depuncturer

Deinterleaver

Chanel Est. Sync &AFC

AGCFrequencyCorr.

TimingCorr.

Figure 17: Receiver Block Diagram


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8.2 Receiver Control Word & Register Description

Word Field # ofName Word Name Bits Slice Description

rx_cntl0 0 seqNum 4 3:0 Control Sequence Number

start 11 14:4 Burst start time (symbol number)rate 3 17:15 Modulation and Code Rate Selection:

000 BPSK, R=1/2001 BPSK, R= 010 QPSK, R=1/2011 QPSK, R=

100 QAM 16, R=1/2101 QAM 16, R=3/4110 QAM 64, R=2/3111 QAM 64, R=3/4

length 11 28:18 Length of burst in symbolspreType 2 30:29 Receive Preamble Type - Long preamble signals a search for long

preamble will occur. Short preamble means a new channel estimate will becalculated, No preamble sends the data straight through

00 No preamble01 Short preamble (P128)

10 Long preamble (P64 + (P128 or Psub))11 Reserved

rx_cntl1 1 subChan 5 4:0 Specifies subchannel index0000 16 subchannels with no RS encoding

00001 11111 as per Table 185(D2)scramEn 1 5 Turn on/off descrambling for the burst

0 descrambler off1 descrambler on

scramInit 1 6 Initialize descrambler at start of burst0 dont initialize

1 - initializescramSeed 15 21:7 Descrambler seed for initialization

midType 2 23:22 Burst midamble type (repetition interval)00 No midamble

01 8 symbol midamble repetition interval10 16 symbol midamble repetition interval11 32 symbol midamble repetition interval

clearTrack 1 24 Clears the timing and frequency tracking loops at the end of the burst.

intEn 1 25 Generate an interrupt at end of burstrx_cntl2 2 searchWin 11 10:0 Length of time in symbols from the start of the search before searchFailed

is asserted. Needed for contention slotsunlockAGC 1 11 AGC is locked during a successful search. This bit will unlock the AGC at

the end of the burstadjustTime 1 12 This bit enables adjustment of the frame timer during synchronization

Table 30: Receive Control Word Description


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RCR0 21 R/W fftScale 4 3:0 Selects number of scaling shifts to be performed in the FFT on thereceive data. Expected range is from 0 to 8.

RCR0 21 R/W fftScalePre 4 7:4 Selects number of scaling shifts to be performed in the FFT on thereceive preamble . Expected range is from 0 to 8.

RCR0 21 R/W chnInterpEn 1 8 Enables interpolation between even carriers in the channelestimation

RCR0 21 R/W 0 = disableRCR0 21 R/W 1 = enableRCR0 21 R/W feedFwdEn 1 9 Enables feed forward correction where the average phase of the

pilot subcarriers is used to adjust the phase on the other subcarriers.RCR0 21 R/W 0 = disableRCR0 21 R/W 1 = enableRCR0 21 R/W rxRst 1 10 Holds receiver in reset when set to 1

RCR1 22 R/W demapScale 6 5:0 Demapper soft bit scaling factor - unsigned value which isused for prescaling the soft bits.

RCR1 22 R/W demapK64 10 15:6 Demapper slicing point for QAM64 - signedRCR1 22 R/W demapK16 10 25:16 Demapper slicing point for QAM16 - signed

RCR2 23 R/W syncThresh 6 5:0 Specifies the percentage of power that the matched filter has toachieve in order to signal a synchronization hit unsigned

RCR2 23 R/W syncMinPwr 15 20:6 Specifies the minimum power that the matched filter has to achievein order to signal a synchronization hit - unsigned

RCR2 23 R/W guard 8 28:21 Guard time inside of the cyclic prefix - unsigned. Guard isthe number of samples of the CP which is included in the OFDMsymbol sent to the FFT

RCR3 24 R/W timeEn 1 0 Enables timing correctionRCR3 24 R/W 0 = disableRCR3 24 R/W 1 = enableRCR3 24 R/W timeLoopA 8 8:1 Loop filter A coefficient - signed

RCR3 24 R/W timeLoopB 8 16:9 Loop filter B coefficient - signedRCR3 24 R/W timeFactor 12 28:17 Frequency offset (freqency domain) to timing offset conversion

factor signed

Table 31: Receive Control Registers (RCR0-3) Description


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Register Addr Field # of Name (hex) R/W Name Bits Slice Description

RCR4 25 R/W freqEn 1 0 Enables frequency tracking correctionRCR4 25 R/W 0 = disabledRCR4 25 R/W 1 = enabledRCR4 25 R/W P64FreqEn 1 1 Enables preamble 64 to be used for frequency offset estimation.

Can be used simultaneously with P128FreqEn.RCR4 25 R/W 0 = disabledRCR4 25 R/W 1 = enabledRCR4 25 R/W P128FreqEn 1 2 Enables preamble 128 to be used for frequency offset estimation.

Can be used simultaneously with P64FreqEn.RCR4 25 R/W 0 = disabledRCR4 25 R/W 1 = enabledRCR4 25 R/W freqFactor 8 10:3 Pilot offset (time domain) to frequency offset conversion factor -

signedRCR4 25 R/W pilotAmplitude 10 20:11 Expected amplitude of pilot carriers that is used for the pilot error

calculation - signed

RCR5 26 R/W agcLockTime 9 8:0 Value of the sync counter at which AGC is locked during a longpreamble search - unsigned

RCR5 26 R/W agcDelay 6 14:9 Number of samples between AGC updates - unsignedRCR5 26 R/W agcVal 8 22:15 AGC value to apply to AGC output - unsignedRCR5 26 R/W agcOverrideEn 1 23 Overrides internally generated AGC output value and outputs

agcVal aboveRCR5 26 R/W agc6BitSel 1 24 Selects 6-bit mode for AGC operation, otherwise 8-bit mode. The

attenuation is incremented in 1 dB steps for 6-bit mode and 1/2 dBsteps for 8-bit mode. The most significant bit of the AGC value isnot used in 6-bit mode so the range is reduced.

RCR5 26 R/W agcAvgSel 2 26:25 Sets the number of samples to average final agc value.RCR5 26 R/W 00 = no averagingRCR5 26 R/W 01 = average 2 samplesRCR5 26 R/W 10 = average 4 samplesRCR5 26 R/W 11 = reservedRCR5 26 R/W agcTableTestEn 1 27 Enables test mode where agc outputs attenuation table value.RCR5 26 R/W 0 = disabledRCR5 26 R/W 1 = enabled

RCR6 27 R/W agcOffset 8 7:0 AGC attenuation offset to apply after AGC lock - signed.

Table 32: Receive Control Registers (RCR4-6) Description


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8.3 AFE Rx Interface, Rx FIFO, AGC & Decimation Filters8.3.1 AFE Rx Interface & Rx FIFO

The AFE Rx interface provides the interface between the 10-bit I&Q data from theADCs and the AGC, Rx FIFO and Decimation filters. The control signals for theADCs i.e. adc_2s_cmp_sel, adc_out_en_n, adc_pd, bandgap_pd & vref_pd are setthrough the MCR. The 10-bit in-phase and quadrature data, rx_I and rx_q, is fed directlyto the Rx FIFO where it is resynchronized to the phy_clk domain. Afterresynchronization the I&Q data is sent directly to the AGC and then the decimationfilters.

DO(9:0)OMODEOUTDIS

PDADCPDBGRPDVR

IADC

DO(9:0)

OMODEOUTDIS

PDADCPDBGRPDVR

QADC

rx_i(9:0)

rx_q(9:0)

adc_pdadc_out_en_n

bandgap_pd

vref_pd

adc_2s_cmp_selMCR

Decimation

Filter

AGC

fe_clk

Rx FIFO

Figure 18: ADC Interface & Rx FIFO

The Rx FIFO resynchronizes the I&Q data from the variable fe_clk clock domain to the100 MHz phy_clk clock domain.


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8.3.2 AGC

8.3.2.1 Overview

Relevant Control WordsRx_cntl0 unlockAGC AGC is locked during a successful search. This bit will unlock the AGC at

the end of the burst Note, this function actually provided by the SYNCcircuit

Relevant Control RegistersRCR agcLockTime Value of the sync counter at which AGC is locked during a long preamble

search - unsignedagcDelay Number of samples between AGC updates - unsignedagcVal AGC value to apply to AGC output - unsignedagcOverrideEn Overrides internally generated AGC output value and outputs agcVal aboveagc6BitSel Selects 6-bit mode for AGC operation, otherwise 8-bit mode. The

attenuation is incremented in 1 dB steps for 6-bit mode and 1/2 dB stepsfor 8-bit mode. The msb and lsb of the AGC value are not used in 6-bitmode so the range is reduced.

agcAvgSel Sets the number of samples to average final agc value00 no averaging10 average2 samples10 average 4 samples11 reserved

agcTableTestEn Enables test mode where agc outputs attenuation table value.agcOffset AGC attenuation offset to apply after AGC lock - signed.

Relevant Status RegistersRSR attenuation Value of sync attenuation output

The AGC is implemented as a table based look up table and is designed to lock in on theoptimum gain during the long preamble sequence of the OFDM transmission. A systemlevel block diagram of the AGC is shown in Figure 19.

The AGC generates an internal 8/6-bit output, currentAtten which selects an attenuationlevel for the I&Q input signals before the ADCs. The AGC output represents a range of0 to 127 dB attenuation in dB steps in 8-bit mode and a range of 0 to 64 dB in 1 dBsteps in 6-bit mode. Note that in 6-bit mode, the msb and lsb of the 8-bit AGC outputword are set to 0 and should not be used. If the AGC value is less than zero, then it is setto zero. If the internal AGC value is greater than 2 ^AGC_BITS -1 then the AGC value is setto 2 ^AGC_BITS -1.

The internal 8-bit agc value is used to address an 256x10-bit agc translation RAM. ThisRAM is used to translate the monotonic 8-bt agc value to a programmable 10-bit outputfield. Each 8-bit AGC value is used address an individual memory location whose 10-bitvalue is then read and place in a register to provide a 10-bit agc output. The use of a 10-bit programmable output field allows the agc circuit to interface to different chipsetswhich may have their gains distributed over several chips. Note that the agc translationRAM is loaded through the preamble memory interface using the PMDR and PMCRregisters.


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DO(9:0)

IADC

QADC

rx_i(9:0)

rx_q(9:0)

ADCcontrolMCR

AGC

fe_clk

Rx FIFO

DO(9:0)Attenuator+ Filter

Attenuator+ Filter

RCR5agcVal(7:0)

agcOverrideEnagc6bitSel

agc(9:0)

agc_stb

agcDelay

rx_i

rx_q

SOC

currentAtten (7:0) AGCTranslation

Memory

Figure 19: AGC System Level Block Diagram

Operation of the AGC is as follows:

AGC is unlocked at reset and at the end of a rx burst when an Rx control wordcommand has the unlock bit set.

AGC is locked agcLockTime samples after the first successful synchronization(P64_Hit) to to a the P64 preamble. The maximum value of agcLockTime is 128with the typical value being 64 samples.

While the AGC is unlocked the average power, P 32, over 32 fe_clk samples iscompared to the 10 attenuation compare values. The index of the maximumcompare value of which the P 32 is greater is used to adjust the AGC value from alist of 11 values of attenuation.

Each AGC iteration requires agcDelay fe_clk clock cycles. This consists of 32fixed cycles for performing the average power calculation and an additionalnumber of cycles to account for additional delays in the system. . The additionaldelay is used to account for the following:

o Attenuator setting time, att_timeo ADC pipeline delay, adc_delayo Internal pipeline delays, int_delay

The total number of fe_clk clock cycles available for AGC updates (agc_cycles)is dictated by the shortest possible OFDM symbol and is:

agc_cycles = 2((G)*256 + *(64 + agcLockTime ) + 19


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Note that G is the cyclic prefix ratio and the 19 additional clock cycles in theequation is due to the delay through the decimation filter as the SYNC blockwhich controls the AGC circuit resides after the decimation filter. For a worstcase situation where agcLockTime = 64 and G= 1/32, agc_cycles = 291.

The total number of agc iterations, agc_iter, is dependent on agcDelay and on agc_cycleswhich is the total number of cycles available as follows:

agc_iter = round(agc_cycles/agcDelay);

A reference calculation is given below for the current ASIC implementation under thewrost case scenario i.e. minimum cyclic prefix ratio:

att_time = 4 clock cycles // Attenuator + Filter delayadc_delay = 7 clock cycles // Delay due to ADC pipelineint_delay = 5 clock cycles // Delay due to Rx FIFO

agcDelay = 32 + 4 + 7 + 5 = 48

agc_iter = round(291/48) = 6

Therefore in the worst case a maximum of 6 agc iterations are possible.

A symbol timing diagram is provided in Figure 20 which shows the approximate timingof the AGC estimation during the short preamble. In this case agcLockTime was set to64.

P 64 P64 P64 P64 P128CP Data 0CP P128 CP

AGC Locked

AGC Unlocked

P64_Hit agcLockTime

Figure 20: AGC TimingIt is also possible to apply an offset to the output of the AGC. The agcOffset register inRCR6 is an 8-bit signed offset which is applied to the output of the AGC after it has beenlocked. The agc output is calculated as follows:

CurrentAtten = agc_int + agc_offset

Note that the agc output saturation to zero or 2 ^AGC_BITS -1 occurs after the offset is added.


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Finally, it is also possible to provide an extra agc iteration which is the average of the last0, 2 or 4 AGC outputs . This is controlled through the agcAvgSel bit in RCR5. Forinstance if in normal operation (agcAvgSel =0) the agc operates with 7 iterations, inaveraging mode with agcAvgSel =1 (2 samples averaged) an 8 th iteration is producedwhose value is the average of the last 2 outputs. This potentially provides a means of

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802-16 Ofdm Phy Tech Spec

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