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8051 MicrocontrollerCourse Outcomes

C501.1:The student will get basic knowledge of memory structure, SFR format, working of timer, counter, UART, interrupt in 8051 and ARM 7 microcontroller.

C501.2:The student will be able to understand the working of different instruction sets in 8051, ARM7 and interfacing of peripheral devices such as ADC, DAC, 7segment Display, LCD, Stepper motor, DC motor, relay to 8051 and ARM7 microcontroller.

C501.3: The student will be able to apply knowledge of instruction set for writing code for arithmetic operations, data transfer operation, timer, counter, UART, interrupt and programming peripheral devices.

C501.4:The student will be able to analyze and select suitable instructions and special function register of 8051 and ARM7 microcontroller for writing efficient code.

C501.5:The student will be able to design small embedded system around microcontroller for various applications

Advantages of microprocessor

Designer can decide on amount RAM,ROM,I/O ports needed to fit task at hand

Advantages of Microcontroller

Less space requirementsLow power consumptionThree criteria in Choosing a Microcontroller

8051 Basic Component4K bytes internal ROM 128 bytes internal RAMFour 8-bit I/O ports (P0 - P3).Two 16-bit timers/countersOne serial interfaceData Bus : 8bitAddress Bus : 16 bit

Other 8051 featursonly 1 On chip oscillator (external crystal)6 interrupt sources (2 external , 3 internal, Reset)64K external code (program) memory(only read)PSEN64K external data memory(can be read and write) by RD,WRCode memory is selectable by EA (internal or external)We may have External memory as data and code

12345678910111213141516171819204039383736353433323130292827262524232221P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST(RXD)P3.0(TXD)P3.1(T0)P3.4(T1)P3.5XTAL2XTAL1GND(INT0)P3.2(INT1)P3.3(RD)P3.7(WR)P3.6VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8) 8051

P1P2P0P34 I/O portEach of 8 bit wideI/O port

RSTVcc10 uF8.2 K9

C230pFC130pFXTAL2XTAL1GNDUsing a TTL oscillatorXTAL2 is unconnected.

Using a quartz crystal oscillatorWe can observe the frequency on the XTAL2 pin.NCEXTERNALOSCILLATORSIGNALXTAL2XTAL1GND

Minimum connection for 8051 based systemCPU timing And Machine cycle

Oscillator Formed by crystal, capacitor and on-chip inverter generates a pulse train at frequency of crystal

Pulse time: clock frequency established smallest interval of time within uc.

State : basic time interval for discrete operation of uc such as fetching an opcode, decoding an opcode, executing an opcode

Machine cycle: smallest interval of time to accomplish any simple instruction or part of complex instruction

1 MC= 6 State

1 State= 2 oscillator pulses

1MC= 12 clock periodTime required to execute instruction =C X 12 Crystal frequencyInstructionMachine cycleADD A, R01MOV A, #23H2LJMP3XTAL = 11.0592 MHz machine cycle = 1 / 921.6 kHz = 1.085 s11.0592 MHz / 12 = 921.6 kHz;Registers of 8051ABR0R1R3R4R2R5R7R6DPHDPLPCDPTRPCSome 8051 16-bit RegisterSome 8-bit Registers of the 8051Program Status Word (PSW) Register

Program Status Word (PSW) Register

RS1RS0Register Bank0 000111021138051 Memory Organization00H7FHRAM=128 byteRange=00 to 127Range=00H to 7FH7F=1271F=31Register Bank and Stack1FH32 ByteBit addressable read/ write memory20H2FH16 ByteRead/ Write storageScratch pad30H80 Byte128 ByteR0R1R2R3R4R5R6R7Register Bank 000H1FH8 ByteRegister Bank 107HRegister Bank 308H8 ByteRegister Bank and StackRegister Bank 28 Byte8 Byte0FH17H10H18H32 ByteR0R1R2R3R4R5R6R7Register Bank 007 H06 H05 H04 H03 H02 H01 H00 HR0R1R2R3R4R5R6R7Register Bank 10F H0E H0D H0C H0B H0A H09 H08 HR0R1R2R3R4R5R6R7Register Bank 217 H16 H15 H14 H13 H12 H11 H10 HR0R1R2R3R4R5R6R7Register Bank 31F H1E H1D H1C H1B H1A H19 H18 HADDRESSREGADDRESSREGADDRESSREGADDRESSREG

RS1RS0Register Bank0 00011102113How to switch register bank? Default register bank= Register Bank 0MOV A,R0H ; move data from R0 into reg. AMOV A, 00H; move data from memory location 00h(R0) into reg. A Que. To move data from reg. R0 of register bank 2

SETB PSW.4CLR PSW.3MOV A, R0H

RS1PSW.4RS0PSW.3Register Bank0 00011102113MOV A,10H Stack in 8051

Stack is a section of RAM used by CPU to store information temporary This information could be data or an address

The register used to access stack is called SP(stack pointer) register.

Default value in SP reg. is 07H i.e RAM location 08H is the first location used for stack by 8051

Register Bank 1= Default Stack memory

Location 08H to 1FH in 8051 RAM can be used for stack.

If in given program we need more than 24 bytes ( 08h to 1Fh)of stack, we can change SP to point RAM location 30 7FH using instruction

MOV SP,#RAM address

80868051SP=16 bitSP=8 bit00H7FH1FH20H2FHRegister Bank and StackBit addressable read/ write memoryRead/ Write storageScratch pad30H80868051SP 16 bit reg.SP 8 bit reg.SP decremented by 2SP incremented by 1SP=SP-2SP=SP+1Syntax: PUSH registerEx. PUSH AXSyntax: PUSH addressEx. PUSH 680868051SP 16 bit reg.SP 8 bit reg.SP incremented by 2SP decremented by 1SP=SP+2SP=SP-1Syntax: POP registerEx. POP AXSyntax: POP addressEx. POP 6PUSHPOPDifference between operation of PUSH and POP instruction?PUSH: storing the CPU register in the stackPOP: Pulling the contents off the stack back into a CPU register Register Bank 1= Default Stack memory

SP=07HR0R1R2R3R4R5R6R70F H0E H0D H0C H0B H0A H09 H08 H07HADDRESSREGHow to store data to Stack memory?

MOV R6, #25H; R6=25H MOV R1, #12H; R1= 12HMOV R4, #0FEH; R4=0FEHPUSH 6PUSH 1PUSH 4

DATASPDefault position of stack pointerSPSPSP12HFEH25HRegister Bank 1= Default Stack memorySP=07HHow to restore data from Stack memory?

MOV R6, #25H; R6=25H MOV R1, #12H; R1= 12HMOV R4, #0FEH; R4=0FEHPUSH 6PUSH 1PUSH 4POP 5; POP 3; POP 2;

Current statusR0R1R2R3R4R5R6R70F H0E H0D H0C H0B H0A H09 H08 H07HADDRESSREGDATASPSPSPSP12HFEH25H R5=0FEH R3=12HR2=25H

Bit addressable read/ write memory16 byteRange= 20H to 2FH

16 x 8 = 128 bits

Byte addressableBit addressableRegister=8 bitByte has address Register=8 bitBit has addressAccess registers in bytesAccess registers in bitsEx. SPEx. I/O port reg.

Bit addressable read/ write memoryMOV A, #03H; copy byte 03h to reg. AMOV 26H,A; copy data byte from reg. A to memory location 26H

16 byte00000011SETB 32H

1CLR 32H0P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.087H86H85H84H83H82H81H80HP0ADDRESSMOV P0, #0FFH BYTE addressable instruction

SETB P0.0 BIT addressable instructionRead/ Write storageScratch pad

Use for read and write storage

General purpose storing of data

If we need more registers we simply use RAM locations 30-7FH Extra 128 byte on chip RAM in 8052

8052 is advanced version of 8051Another 128 bytes of on chip RAM with address 80-FFH are designated as special function register(SFR) / upper RAM

80518052128 byte of RAM256 byte of RAM

Two different physical memories, but they have same addresses

SFR Special Function RegisterBit addressable registers8051 microcontrollers, has only 21 SRF registersRest of locations are intentionally left unoccupied in order to enable the manufacturers to further develop microcontrollers keeping them compatible with the previous versions. ROM in 8051

4K bytes on chip ROMUse to store user codeROM=code memorySize of PC=16 bit Therefore maximum size of on chip ROM can be 0000 to FFFFFH i.e 64 Kbytes4 K bytes of ROM memory has addresses from 0000H to 0FFFH.

Tristate Buffer

Tristate buffer has single input, single output and enable control pin.

By activating the enable, data at input is transferred to output.

When receiver current requirements exceeds the drivers capability, we must use buffer/drivers.

Increase the fan out capacity of microcontroller

When connecting IC chip to microcontroller, we need to find out how many input pins of IC chips can be driven by single output pin of microcontroller.

Internal structure of ports of 8051

Since all ports of 8051 are bidirectional, they all have following 3 components in their structure1.D latch2.Output driver3.Input buffer

Internal structure of ports of 8051

Since all ports of 8051 are bidirectional, they all have following 3 components in their structure1.D latch2.Output driver3.Input buffer

PORT 1P1Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to the pin by the external device then it read fine. But when '0' is written to the pin by the external device then the external source must sink current due to internal pull-up. If the external device is not able to sink the current the pin voltage may rise, leading to a possible wrong reading.

How to write data to port pin?000110

How to write data to port pin?111001

How to read port pin?111001MOV P1, #0FFH; to configured port as input port, we must write 1(logic high) to that portsMOV A, P1Active1MOV A, P1

How to read latch?11MOV P1, #0FFH; to configured port as input port, we must write 1(logic high) to that ports

ANL P1, A; P1 = A AND P1ActiveANL P1, A;P1 = A AND P1

PORT 0P0Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing for accessing external memory.

control =1 , the port is used for address/data interfacing. control =0, the port can be used as a normal bidirectional I/O port.

Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance pin can be pulled up or low by an external source. When the port is used as an output port, a '1' written to the latch again turns 'off' both the output MOSFETs and causes the output pin to float. An external pull-up is required to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower MOSFET. Hence the output becomes zero.

When the control is '1', address/data bus controls the output driver MOSFETs. If the address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'. Hence for normal address/data interfacing (for external memory access) no pull-up resistors are requiredDCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCData/AddressControlP0.x100011Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required. Port 0 = Data/Address linesDCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCData/AddressControlP0.x111100Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required. Port 0 = Data/Address linesDCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCData/AddressControlP0.x00FloatingHence the output pin floats. This high impedance pin can be pulled up or low by an external source. Hence pull up register required11100 Port 0 = I/O port

PORT 2P2Port-2 is used for higher external address byte or a normal input/output port. The I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to internal pull-up there is limited current driving capability. DCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCData/AddressControlP2.x011100 Port 2 = I/O portPull upregister1DCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCData/AddressControlP2.x111100 Port 2 = Address linesPull upregister11DCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCData/AddressControlP2.x11 Port 2 = Address linesPull upregister00

PORT 3P3Each pin of Port-3 can be individually programmed for I/O operation or for alternate function. The alternate function can be activated only if the corresponding latch has been written to '1'. To use the port as input port, '1' should be written to the latch. This port also has internal pull-up and limited current driving capability. DCLKQQWrite LatchInternal CPU BusRead PinRead LatchVCCP2.xPort 3 = I/O / Address linesPull upregisterAlternate output FunctionAlternate input FunctionThe alternate function can be activated only if the corresponding latch has been written to '1'.TXD, RD, WR RXD, INT0, INT1,T0, T1 111Timer in 8051The 8051 has two timers/countersTimer- to generate a time delayCounter-to count events happening outside the microcontrollerTimer 0 and timer 1 are 16 bit

Timer 0Timer 1Every timer needs a clock pulse to tickTH0TL000H00HTH0TL000H01HTH0TL000H01HTH0TL000H02HTH0TL000H02HTH0TL000H03HXTALoscillatorTimer operating frequency 12Timer frequency= Crystal frequency / 12

Crystal frequency= 11.0592 MHz

Then timer frequency= 1.085 usTMOD is a 8-bit registerUse to set the various timer operation modesM1M0ModeOperating mode00013-bit timer mode8-bit timer/counter THx with TLx as 5-bit prescaler01116-bit timer mode16-bit timer/counter THx and TLx are cascaded; there is no prescaler1028-bit auto reload8-bit auto reload timer/counter; THx holds a value which is to be reloaded TLx each time it overfolws113Split timer modeTMOD: timer/Counter mode control registerGATEC/TM1M0GATEC/TM1M0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Timer 1Timer 0BitOperating modeC/TC/T = 1, counterC/T =0, timerGATEGATE=0, TRX=1, timer onGATE=1, INTX=1, TRX=1, timer on

GATEC/TM1M0GATEC/TM1M0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0TMOD: timer/Counter mode control registerTF1TR1TF0TR0IE1IT1IE0IT0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0TF1Timer 1 overflow flagTR1Timer 1 run control bitTF0Timer 0 overflow flagTR0Timer 0 run control bitIE1interruptIT1interruptIE0interruptIT0interruptTCON: Timer/ Counter control register GATEC/TM1M0GATEC/TM1M0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0TMODTF1TR1TF0TR0IE1IT1IE0IT0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0TCONTMOD reg. is not bit addressableEx. MOV TMOD, #02H

TCON reg. is bit addressable Ex. SETB TR1

THx and TLx can be use like general purpose registerEx. MOV TH0, #05H Mode 116 bit timer0000h to FFFFhAfter the timer is started, it start to count up. It count up until it reaches its limit of FFFFH. When timer rolls over from FFFFH to 0000H , it sets high a flag bit called TF(timer flag)

TH0TL000H00HTH0TL000H01HTH0TL000H01HTH0TL000H02HTH0TL000H02HTH0TL000H03HXTALoscillatorTimer operating frequency 12Timer frequency= Crystal frequency / 12Crystal frequency= 11.0592 MHzThen timer frequency= 921.6 KHzi.e each timer clock has period of (1/921.6 KHz)=1.085us1.085 us1.085 us x 21.085 us x 3No. of Count Delay

1 count = 1.085 us Calculate a values of THx and TLx for generation of 5 ms delay ?THxTLxFFFFTHxTLxEE00Timer generated Delay = ( 65536 - NNNN ) x 1.085 us NNNN = 65536 - (Timer generated Delay / 1.085 us)XXXX= (NNNN)H If timer is 16 bit, what will be the maximum delay the timer can generate ?TH0TL0FFFFTH0TL00000The number of counts for rollover is FFFF-0000= FFFF(65535 decimal)One extra clock needed when timer roll over from FFFF to 0 and rises TF flag.

Maximum delay= (65535+1) x 1.085 us =71.1 ms Timer generated Delay = ( FFFF - xxxx + 1 ) x 1.085 us Calculate a values of THx and TLx for generation of 1 sec delay ?THxTLxFFFFTHxTLx4BFD1 sec= 20 x 50 ms

NNNN=65536 - (50 ms/ 1.085 us)=19453=(4BFD)h

NNNN = 65536 - (Timer generated Delay / 1.085 us)XXXX= (NNNN)H X 20Generation of square wave ?TF = 1 / TDelayDelayFind the value of THx and TLx for generation a frequency 100 KHz ?

Square wave Frequency = 100 KHzSquare wave Time period = 10 usDelay = (10 us / 2) = 5 us

NNNN = 65536 - (Timer generated Delay / 1.085 us)XXXX= (NNNN)H= 65536-(5 us / 1.085 us)= 65531=(FFFB)h

TH0TL0FFFFTH0TL0FFFBIn order to repeat the process the register THx and TLx must be reloaded with orignal values,

TFx must be reset to 0Minimum frequency that 8051 can generate ?TF = 1 / TDelayDelayMinimum frequency means maximum time period

Maximum time period = 71 ms

Therefore minimum frequency = 1 / (2 x 71 ms) = 7 Hz

TH0TL0FFFFTH0TL00000Maximum frequency that 8051 can generate ?TF = 1 / TDelayDelayMinimum frequency means maximum time period

minimum time period = 1.085 us

Therefore maximum frequency = 1/(2 x 1.085 us) = 461 KHz

TH0TL0FFFFTH0TL0FFFBMode 013 bit timer0000h to 1FFFhAfter the timer is started, it start to count up. It count up until it reaches its limit of 1FFFH. When timer rolls over from 1FFFH to 0000H , it sets high a flag bit called TF(timer flag)Mode 0 is exactly like mode1 except that it is a 13 bit timer instead of 16 bit.

Mode 08 bit timer, auto reload mode00h to FFhAfter the timer is started, it start to count up. It count up until it reaches its limit of FFH. When timer rolls over from FFH to 00H , it sets high a flag bit called TF(timer flag)When TLx reg. roll from FFh to 00h and TFx set to 1, TL reloaded automatically by original value kept by THx register.

05h05hTHxTLxTFx06h07hFFh00h05h010Calculate a maximum delay that can generate in mode 2 ?THxFFTHx00Timer generated Delay = ( 256 - NN ) x 1.085 us NN = 256 - (Timer generated Delay / 1.085 us)XX= (NN)H

Max delay= 256 x 1.085 us= 0.277 ms

Minimum freq= 1/ (2 x 256 x 1.085 us) = 1.8 KHzMode 3Split timer mode(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.TH0 is an 8-bit timer only controlled by Timer 1 control bits.(Timer 1) Timer/Counter 1 stopped.Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters.Timer 1=offTimer 0=onTH0TL08 bit timer8 bit timerTR1TR0TF1TF0

Counter

Every thing is same as that of timer, the only difference is clock source.

GATEC/TM1M0GATEC/TM1M011TMOD Counter 0 Counter 1External clock pulseIn the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle.

Mode 1

Mode 2

MOV TMOD, #01HTimer 0, mode 1, 16 bit modeagain1: MOV TL0, #00H TL0=00hMOV TH0, #0EEH TH0=EEhMOV P1, #0FFHTurn on LedACALL DELAYCall delayMOV P1, #00HTurn off LedACALL DELAYCall delaySJMP again1Short jump to L1DELAY: SETB TR0Turn on timer 0again: JNB TF0 againMonitor TF0 flag until it rolls overCLR TR0Stop timerCLR TF0Clear overflow flagRETReturn from subroutineGATEC/TM1M0GATEC/TM1M000000001TMODMain codeSub-routineLED blinkingGATEC/TM1M0GATEC/TM1M000000001TF1TR1TF0TR0IE1IT1IE0IT0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0TMODTCONMOV TMOD, #01HTimer 0, mode 1, 16 bit modeMOV TL0, #0F2H MOV TH0, #0FFH

Serial communication in 8051TransmitterReceiver00101101TransmitterReceiver00101101Serial transferParallel transfer

Asynchronous serial communicationIn asynchronous method, each data is placed between start and stop bits, this is called framingThe start bit is always 0 (low) and stop bit is 1(high)LSB is sent out firstWhen there is no transfer, signal is 1 (high), which referred to as mask Data transfer rate

Bps: bit per secondBaud rate: number of signal changes per second

In case of 8051 bps=baud rateRS232 is the most widely used I/O interfacing standard to allow compatibility among data communication equipment.

RS232Microcontroller (TTL)Logic 0Logic 1Logic 0Logic 13v to 25v-3v to -25v0 to 0.8 v2v to 5v

MAX232 IC: voltage converter used to convert RS232 signals to TTL voltage levels that will be acceptable to 8051 and vice versa.CPUmicrocontrollerRS232MAX232TXD (P3.1)RXD (P3.0)RXDTXDTo allow data transfer between PC and 8051 without any error, we must make sure that baud rate of 8051 matches baud rate of PCs COM port.110150300600120024004800960019200Some of the baud rate supported by PCBaud rate in 8051 is programmable with the help of timer 1In mode 2 (8 bit auto reload mode)

SBUF register

Is 8 bit registerByte of data to be transferred via TXD line, it must be placed in SBUF register.Similarly SBUF holds the byte of data when it received by the 8051s RXD lineThe moment data is written into SBUF, it is framed with start bit and stop bit and transferred serially via TXD pin

SBUF

SCON registerSM0 - Serial port mode bit 0 is used for serial port mode selection. SM1 - Serial port mode bit 1. SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit. When set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It should be cleared in mode 0.

Mode 0

serial data are transmitted and received through the RXD pin, while the TXD pin output clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the least significant bit (LSB bit) is sent/received first.

RECEIVETRANSMITMode 1

In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1). The START bit is only used to initiate data receive, while the STOP bit is automatically written to the RB8 bit of the SCON register.

RECEIVETRANSMITRelation between crystal frequency and baud rate

XTALoscillator921.6KHzTimer operating frequency 12 3228,800 HzTo timer 1 to set baud rate11.0592 MHzTH1=256 -28,800Baud rateHMode 2

In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit (always 1). On transmit, the 9th data bit is actually the TB8 bit of the SCON register. This bit usually has a function of parity bit. On receive, the 9th data bit goes into the RB8 bit of the same register (SCON).The baud rate is either 1/32 or 1/64 the oscillator frequency.

RECEIVETRANSMITMode 3

Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is variable.

SCON registerREN - Reception Enable bit enables serial reception when set. When cleared, serial reception is disabled.

TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of transmitting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit. RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.

SCON registerTI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent. It's a signal to the processor that the line is available for a new byte transmitted. It must be cleared from within the software.

RI - Receive Interrupt flag is automatically set upon one byte receive. it signals that byte is received and should be read quickly prior to being replaced by a new data. This bit is also cleared from within the software.

Interrupts in 80518051 microcontrollerPollingInterruptDevice 1Device 1Device 1Device 2Device 2Switch pressed: LED onSwitch released: LED off

ROM memory locations 00 to 30H locations are for Interrupt vector tableBest way to write a code is:

ORG 00HLJMP MAINORG 30HMAIN: ..ENDInterruptDevice 1AddressMain code0400h0401h0403h0404h0406hL1:SETB P1.3ACALL DelayCLR P1.3ACALL DelaySJMP L1P1.3INT08051 microcontrollerSquare waveP1.4AddressInterrupt0000hReset0001h0002h0003hINT00004h0005h0006h0007h0008h0009h000Ah000BhTF0000Ch000Dh000Eh000Fh0010h0011h0012h0013hINT10014hAddressRAMStack memory0007h000008h000009h00AddressInterrupt service routine (ISR)0003h0004hCPL P1.4RETILED0304AddressRAMStack memory0007h000008h000009h000304PC=0403hInterrupt vector tableInterruptDevice 1AddressMain code0400h0401h0403h0404h0406hL1:SETB P1.3ACALL DelayCLR P1.3ACALL DelaySJMP L1P1.3INT08051 microcontrollerSquare waveP1.4AddressInterrupt0000hReset0001h0002h0003hINT00004h0005h0006h0007h0008h0009h000Ah000BhTF0000Ch000Dh000Eh000Fh0010h0011h0012h0013hINT10014hAddressRAMStack memory0007h000008h000009h00AddressInterrupt service routine (ISR)0003h0004hCPL P1.4RETILED0304AddressRAMStack memory0007h000008h000009h000304PC=0403hROMSteps in executing an interrupt

It finishes the instruction it is executing and saves the address of next instruction (PC) on stack

it jumps to fixed location in memory called interrupt vector table that holds the address of interrupt service routine.

Microcontroller gets the address of ISR from interrupt vector table and jumps to it. It start to execute ISR until it reaches the last instruction of subroutine, which is RETI.

Upon execution of RETI instruction, the microcontroller returns to place where it was interrupted. First it gets program counter (PC) address from stack by popping the top two bytes of stack in to PC. Then it starts to execute from address.

IE (Interrupt enable ) register:

There are two types of activation for external hardware interrupt

1.Level triggered2.Edge triggered

INT0 and INT1 pins are normally high

Level triggered is default mode upon reset of 8051

INT0INT111INT0INT100Level triggeredInterruptINT0 and INT1 pins are normally high

Level triggered is default mode upon reset of 8051,

to make them edge triggered interrupts, we must programs bits of TCON register

INT0INT111INT0INT1Edge triggeredInterruptTF1TR1TF0TR0IE1IT1IE0IT0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0TCONTimerInterruptIT0 = 0, INT0 level triggered interruptIT0 = 1, INT0 edge triggered interrupt

IT1 = 0, INT1 level triggered interruptIT1 = 1, INT1 edge triggered interrupt

IE0 and IE1 are use to keep track of edge triggered interrupt, are used internally by 8051 to indicate whether or not an interrupt is in use.

Upon edge triggered pulse on INT0 and INT1, 8051 set IEx bit in TCON reg.Only execution of RETI instruction at the end of ISR will clear IEx

Addressing mode

CPU can access data in various ways. The data could be in register/ memory/ immediate value

These various ways of accessing data are called addressing modes

ImmediateRegisterDirectRegister indirectindexedImmediate addressing mode

In this mode, source operand is constant. Operand comes immediately after opcode.

MOV A, #25HA