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Prepared bySHIHABUDEEN H

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8086 includes few features, which enhancemultiprocessing capability (it can be used with mathcoprocessors like 8087, I/O processor 8089 etc.

Operates on +5v supply and single phase (single line)

clock frequency.(Clock is generated by separateperipheral chip 8284).

8086 comes with different versions. 8086 runs at 5MHz, 8086-2 runs at 8 MHz, 8086-1 runs at 10 MHz

It comes in 40-pin configuration with HMOStechnology having around 20,000 transistors in itscircuitry.

It has multiplexed address and data bus like 8085 dueto which the pin count is reduced considerably

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Some of the pins serve particular function inminimum mode(single processor mode) andothers function in maximummode(multiprocessor mode)

Control signals are mainly 3 groups

1. signals having common functions in

minimum mode and maximum mode2. signals having special functions in minimum mode

3. signals having special functions in maximum mode

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AD15

AD0:-these are time multiplexedaddress/data bus A19A16/S6-S3these are time multiplexed

address/status lines.S6is always low.S5

denotes the status of interrupt enable flag.S4& S3denotes which segment register is usedfor memory access. Address bits are separatedfrom status bits by ALE signal

S4 S3 segment

0 0 Data/Extra

0 1 Stack

1 0 Code/None

1 1 Data

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7 :- Bus high enable signal indicate thetransfer of data over higher order data bus

:- when low it indicates the peripherals that

the processor is performing a memory or I/Oread operation

READY:- is an acknowledgement fromperipherals that they have completed the data

transfer INTR :-interrupt request from peripherals . if a

request is pending ,the processor entersinterrupt acknowledgement cycle

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:- the input is examined by aWAITinstruction .when it is low , the execution willcontinue , but the processor remains in an idle

state NMI:- Non Maskable Interrupt . This is an edge

triggered interrupt and cannot be maskedusing software

RESET:- the processor terminates its activity &the execution start from FFFF0H

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CLK: - clock input for the system timing

VCC:- + 5V power supply

GND:- Ground for internal circuit

MN/:- the logic level at this pin decideswhether the processor has to operate either insingle or multiprocessor mode

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M/:the state of this line indicates whetherthe CPU is having a memory or I/O operation

:- a read strobe for interrupt

acknowledgement cycles . when it is low , theprocessor has accepted the interrupt

/:-Data Transmit /Receive :- it denotes thedirection of data flow through the transceivers

:- when low it indicates the peripherals thatthe processor is performing a memory or I/Owrite operation

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ALE:- Address latch Enable . Denotes theavailability of valid address on multiplexedbus

HOLD,HLDA:- Hold& hold acknowledge:-when hold is high , another master isrequesting the bus access. After receivingHOLD request , the processor issues hold

acknowledge signal on HLDA pin

:-Data enable. Indicates the availability ofvalid data over address/data line

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2 , 1, 0 status lines.Reflects the types ofoperation

: this O/P indicates the other system busmaster will be prevented from gaining the systembus , while lock is low

2 0 Operation

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory1 1 1 Passive

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QS0,QS1:- Queue status . Indicates the status of

prefetch queue

0 1 :-Request/Grant . These pinsare used in other local masters , to force theprocessor to release the local bus at the end ofcurrent bus cycle

QS

1

QS0

Indication

0 0 No operation

0 1 First byte of Opcode

1 0 Queue is empty

1 1 Subsequent byte of Opcode

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8086 processor has a 16-bit data bus multiplexedwith the 16 lower address lines

The processor loads on the address bus (AD0to

AD7, AD8to AD15and A16to A19) the address to beused, and sets the ALE. Thus the address signalsA0to A15are latched on the 74LS373.

On the next clock the processor resets the ALE and

the AD0to AD7and AD8 to AD15lines are used tocarry data (D0to D7 and D8to D15). The enables the buffers of the 74LS245, while the /specifies the direction (read/write)

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The 74LS373 and the 74LS245 are used todemultiplex the AD0to AD7and AD8 to AD15lines. They also provide the necessary bufferingfor the A0to A7, A8to A15, D0to D7 and D8to

D15 lines.

The rest of the address lines (A16to A19) as wellas control lines (, , and M/) need to be

buffered using the 74LS244 octal buffer.

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During the first clocking period (T1), the address is sent to the

address and address/data connections, and the ALE, /andM/signals are also output

During T2the , are asserted, and data appear on the bus

In T4all bus signals are deactivated in preparation for the next buscycle, and the signal returns to logic 1.

ADDRESS/DATA

WR

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During the first clocking period (T1), the address is sent to the addressand address/data connections, and the ALE, /and M/signals

are also outputDuring T2the , are assertedIn T3the READY signal is sampled and if low, T3becomes a wait state,to allow time to the memory to access dataThe bus is sampled at the end of T3Finally, the signal is deactivated

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8086 support 1MB of external memory .thismemory space is organized as bytes of datastored at consecutive addresses over the range

00000H to FFFFFH 8086 can access any two consecutive bytes as

word of data

Lower addressed data is taken as LSB byte andHigher addressed data as MSB byte of word

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D15-D8 D7-D0

CS CS

BHE A0A1---A19

UPPER BANK LOWER BANK

ODDEVEN

Memory is organized as even and odd banks , each of 512KB,byte data with even address is transferred on D7to D0andbyte data with odd addresses transferred on D15to D8lines

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Instruction stream is fetched from the memoryas words .then there are 3 possibilities

1: Both may be data 2: both the bytes may be Opcode

3: one of the byte may be Data while the othermaybe Opcode

All the 3 possibilities are taken care of by thedecoder circuit , which further derives thesignals those acts as input to the timing and

control unit The timing and control unit derives all signals

required for the execution of instruction

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7 0 memory address

FFFFFH

FFFFEH

00002H

00001H

00000H

8 bits

Memory address space

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The locations from FFFF0H to FFFFF H arereserved for operations including jump toinitialization programme and I/O processor

initialization The locations 00000H to 003FFH are reserved

for interrupt vector table

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8086 can address up to 64 KB I/O byte registers or32 k word I/O registers

Address of an I/O device must not be greater than16 bits, 216=64 KB I/O devices can be accessed by

CPU

I/O address appear on address lines A0 to A15A16 to A19 are at logic 0 levelduring I/Ooperations

DX register is user as 16 bit I/O address pointer. I/O ports are addressed in the same manner as

memory locations

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In a minimum mode 8086 system, the

microprocessor 8086 is operated in minimummode by strapping its MN/MXpin to logic 1.

In this mode, all the control signals are given outby the microprocessor chip itself. There is asingle microprocessor in the minimum modesystem. The remaining components in thesystem are latches, transceivers, clock generator,

memory and I/O devices. Some type of chip selection logic may be

required for selecting memory or I/O devices,depending upon the address map of the system.

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Latches are generally buffered output D-typeflip-flops like 74LS373 or 8282. They are used forseparating the valid address from the

multiplexed address/data signals and arecontrolled by the ALE signal generated by 8086.

Transceivers are the bidirectional buffers andsome times they are called as data amplifiers.

They are required to separate the valid datafrom the time multiplexed address/data signals.

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CLK

READY

RESET

8284A

CLOCK

GENERATOR

WAIT STATE

GENERATOR

MN/

M/

INTA

R

WR

DT/ R

EN

ALE

HE

AD0-AD15

A16-A19

8286

TRANCEIVER

RAM 21422716

PROM

PERIPHERAL

DATAADDR/DATA

ADDR

8282

LATCH

CONTROL

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They are controlled by two signals namely, DENand DT/ R.

The DT/ Rsignal indicates the direction of data,

i.e. from or to the processor. The system containsmemory for the monitor and users programstorage.

Usually, EPROM are used for monitor storage,while RAM for users program storage. A systemmay contain I/O devices.

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The clock generator generates the clock from thecrystal oscillator and then shapes it and dividesto make it more precise so that it can be used as

an accurate timing reference for the system. The clock generator also synchronizes some

external signal with the system clock. It has 20address lines and 16 data lines, the 8086 CPU

requires three octal address latches and two octaldata buffers for the complete address and dataseparation.

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The working of the minimum mode configurationsystem can be better described in terms of the timingdiagrams rather than qualitatively describing theoperations.

The opcode fetch and read cycles are similar. Hencethe timing diagram can be categorized in two parts,the first is the timing diagram for read cycle and thesecond is the timing diagram for write cycle.

The read cycle begins in T1with the assertion ofaddress latch enable (ALE) signal and alsoM/ signal. During the negative going edge of thissignal, the valid address is latched on the local bus.

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The BHEand0signals address low, high or bothbytes. From T1to T4, the M/signal indicates amemory or I/O operation.

At T2, the address is removed from the local bus and

is sent to the output. The bus is then tristated. Theread (RD) control signal is also activated in T2. The read (RD) signal causes the address device to

enable its data bus drivers. After RDgoes low, thevalid data is available on the data bus.

The addressed device will drive the READY linehigh. When the processor returns the read signal tohigh level, the addressed device will again tristateits bus drivers.

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A write cycle also begins with the assertion of ALEand the emission of the address. The M/ signalis again asserted to indicate a memory or I/Ooperation. In T2, after sending the address in T1,the processor sends the data to be written to theaddressed location.

The data remains on the bus until middle ofT4state. The becomes active at the beginning ofT2(unlike is somewhat delayed in T2 to Provide

time for floating). The and0signals are used to select the

proper byte or bytes of memory or I/O word to beread or write.

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M/ Transfer Type

0 0 1 I / O read

0 1 0 I/O write1 0 1 Memory read

1 1 0 Memory write

Data transfer table

The M/ , andsignals indicate the

type of data transfer as specified in table below

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The HOLD pin is checked at leading edge of eachclock pulse. If it is received active by the processorbefore T4of the previous cycle or during T1state ofthe current cycle, the CPU activates HLDA in the

next clock cycle and for succeeding bus cycles, thebus will be given to another requesting master.

The control of the bus is not regained by theprocessor until the requesting master does not

drop the HOLD pin low. When the request isdropped by the requesting master, the HLDA isdropped by the processor at the trailing edge ofthe next clock

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In the maximum mode, the 8086 is operated bystrapping the MN/pin to ground.

In this mode, the processor derives the statussignal

2

, 1,

0

. Another chip called buscontroller derives the control signal using thisstatus information .

In the maximum mode, there may be more

than one microprocessor in the systemconfiguration.

The components in the system are same as inthe minimum mode system.

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CLK

READY

RESET

8284A

CLOCK

GENERATOR

WAIT STATE

GENERATOR

MN/

AD0-AD15

A16-A19

DATA

BUFFERS

RAM 21422716

PROM

PERIPHERAL

DATA

ADDR/DATA

ADDR

8282

LATCH

8288

BUS

CONTROLER CONTROL

/

CLK

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The basic function of the bus controller chipIC8288, is to derive control signals likeR ndWR( for memory and I/O devices),DT/

R

,EN,ALEetc. using the information by theprocessor on the status lines.

The bus controller chip has input lines 2 , 1, 0 andCLK. These inputs to 8288 are driven by CPU.

It derives the outputs DT/ R,EN,ALE, ,, , .The, and CEN pins are specially useful formultiprocessor systems.

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and are generally grounded. CENpin is usually tied to +5V. The significance ofthe MCE/PDENoutput depends upon thestatus of the pin.

If is grounded, it acts as master cascadeenable to control cascade 8259A, else it acts asperipheral data enable used in the multiple busconfigurations.

pin used to issue two interruptacknowledge pulses to the interrupt controlleror to an interrupting device.

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, are I/O read command and I/Owrite command signals respectively . These signalsenable an I/O interface to read or write the datafrom or to the address port.

The , are memory read commandand memory write command signals respectivelyand may be used as memory read or write signals.

All these command signals instructs the memory

to accept or send data from or to the bus. For both of these write command signals, the

advanced signals namely are available.

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They also serve the same purpose, but areactivated one clock cycle earlier than the signals respectively.

The maximum mode system timing diagramsare divided in two portions as read (input) andwrite (output) timing diagrams.

The address/data and address/status timings

are similar to the minimum mode.

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ALE is asserted in T1, just like minimum mode.

Here the only difference between in timingdiagram between minimum mode and

maximum mode is the status signals used andthe available control and advanced commandsignals.

2 , 1, 0

are set at the beginning of buscycle.8288 bus controller will output a pulse ason the ALE and apply a required signal to itsDT/ Rpin during T1

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In T2, 8288 will set EN=1 thus enablingtransceivers, and for an input it will activateor . These signals are activated

until T4. For an output, the oris activated from T2to T4and oris activated from T3to T4. The statusbit S0to S2remains active until T3and become

passive during T3and T4. If reader input is not activated before T3, wait

state will be inserted between T3and T4

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The request/grant response sequence containsa series of three pulses. The request/grant pinsare checked at each rising pulse of clock input.

When a request is detected and if the conditionfor HOLD request are satisfied, the processorissues a grant pulse over the pinimmediately during T4(current) or T1(next)state.

When the requesting master receives this pulse,it accepts the control of the bus, it sends arelease pulse to the processor using pin

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8088P

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Both are 40 pin DIP

8086 is having 16 bit data bus and 20 bitaddress bus

8088 is having 8 bit data bus and 20 bit addressbus

Pin no 34 is /S7 for 8086 but for 8088 it is

0

(status pin)

8086 :- 6 byte instruction prefetch queue

8088 :- 4 byte instruction prefetch queue

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8086 :- M/control signal

8088 :- /IOcontrol signal

8086 draws a maximum supply current of 360mA , For 8088 it is 340 mA

Both requires +5v power supply

Temperature range 320FH to 1800FH

Execution time is more in 8088 as compared to8086

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8088 can execute the complete instruction set of8086

Address lines A8to A15are not multiplexed in8088

In 8088 ,BIU will fetch a from memory if atleast one byte is free in the queue , but in 8086

at least 2 bytes should be free for nextinstruction fetch