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Signal Description of 8086 Microprocessor

The 8086 Microprocessor is a 16-bit CPU available in 3 clock rates, i.e. 5, 8 and 10M!,

packa"ed in a #0 pin C$%&'P or plastic packa"e. The 8086 Microprocessor operates in sin"leprocessor or ()ltiprocessor con*i")rations to achieve hi"h per*or(ance. The pin

con*i")ration is as sho+n in *i"1. o(e o* the pins serve a partic)lar *)nction in (ini()(

(ode sin"le processor (ode and others *)nction in (a/i()( (ode ()ltiprocessor (ode

con*i")ration.

The 8086 si"nals can be cate"ori!ed in three "ro)ps. The *irst are the si"nals havin" co((on

*)nctions in (ini()( as +ell as (a/i()( (ode, the second are the si"nals +hich have

special *)nctions in (ini()( (ode and third are the si"nals havin" special *)nctions *or

(a/i()( (ode

The *ollo+in" si"nal description are co((on *or both the (ini()( and (a/i()( (odes.

AD15-AD0:

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These are the ti(e ()ltiple/ed (e(or '2 address and data lines. ddress re(ains on the

lines d)rin" T1 state, +hile the data is available on the data b)s d)rin" T4, T3, T and T#.

ere T1, T4, T3, T# and T are the clock states o* a (achine ccle. T is a+ait state. These

lines are active hi"h and *loat to a tristate d)rin" interr)pt ackno+led"e and local b)s hold

ackno+led"e ccles.

A19/S6, A18/S5, A17/S4, A16/S3:

These are the ti(e ()ltiple/ed address and stat)s lines. &)rin" T1, these are the (ost

si"ni*icant address lines or (e(or operations. &)rin" '2 operations, these lines are lo+.

&)rin" (e(or or '2 operations, stat)s in*or(ation is available on those lines *or T4, T3,

T and T# .The stat)s o* the interr)pt enable *la" bitdisplaed on 5 is )pdated at the

be"innin" o* each clock ccle. The # and 3 co(binedl indicate +hich se"(ent re"ister is

presentl bein" )sed *or (e(or accesses as sho+n in Table 1.1.

These lines *loat to tri-state o** tristated d)rin" the local b)s hold ackno+led"e. The stat)s

line 6 is al+as lo+lo"ical. The address bits are separated *ro( the stat)s bits )sin"latches controlled b the $ si"nal.

The b)s hi"h enable si"nal is )sed to

indicate the trans*er o* data over the hi"her order &15-&8 data b)s as sho+n in Table 1.4. 't

"oes lo+ *or the data trans*ers over &15-&8 and is )sed to derive chip selects o* odd address

(e(or bank or peripherals. is lo+ d)rin" T1 *or read, +rite and interr)ptackno+led"e ccles, +hen- ever a bte is to be trans*erred on the hi"her bte o* the data b)s.

The stat)s in*or(ation is available d)rin" T4, T3 and T#. The si"nal is active lo+ and is

tristated d)rin" 7hold7. 't is lo+ d)rin" T1 *or the *irst p)lse o* the interr)pt ackno+led"e

ccle.

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Table 1.4

%ead si"nal, +hen lo+, indicates the peripherals that the processor is

per*or(in" a (e(or or '2 read operation. is active lo+ and sho+s the state *or T4,

T3, T o* an read ccle. The si"nal re(ains tristated d)rin" the 7hold ackno+led"e7.

!AD":

This is the ackno+led"e(ent *ro( the slo+ devices or (e(or that the have co(pleted the

data trans*er. The si"nal (ade available b the devices is snchroni!ed b the 848# clock

"enerator to provide read inp)t to the 8086. The si"nal is active hi"h.

#$%-lnterr&pt e'&est:

This is a level tri""ered inp)t. This is sa(pled d)rin" the last clock ccle o* each instr)ction

to deter(ine the availabilit o* the re)est. '* an interr)pt re)est is pendin", the processor

enters the interr)pt ackno+led"e ccle. This can be internall (asked b resettin" the

interr)pt enable *la". This si"nal is active hi"h and internall snchroni!ed.

%!S%:

This inp)t is e/a(ined b a 7'T7 instr)ction. '* the T$T inp)t "oes lo+, e/ec)tion +ill

contin)e, else, the processor re(ains in an idle state. The inp)t is snchroni!ed internall

d)rin" each clock ccle on leadin" ed"e o* clock.

$M#-$on-(as)a*le #nterr&pt:

This is an ed"e-tri""ered inp)t +hich ca)ses a Tpe4 interrr)pt. The 9M' is not (askable

internall b so*t+are. transition *ro( lo+ to hi"h initiates the interr)pt response at the end

o* the c)rrent instr)ction. This inp)t is internall snchroni!ed.

!S!%:

This inp)t ca)ses the processor to ter(inate the c)rrent activit and start e/ec)tion *ro(

::::0. The si"nal is active hi"h and ()st be active *or at least *o)r clock ccles. 't restartse/ec)tion +hen the %$$T ret)rns lo+. %$$T is also internall snchroni!ed.

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+-+loc) #np&t:

The clock inp)t provides the basic ti(in" *or processor operation and b)s control activit. 'ts

an as((etric s)are +ave +ith 33; d)t ccle. The ran"e o* *re)enc *or di**erent 8086

versions is *ro( 5M! to 10M!.

.++ :

9& "ro)nd *or the internal

circ)it.

M$/M :

The lo"ic level at this pin decides +hether the processor is to operate in either (ini()(

sin"le processor or (a/i()( ()ltiprocessor (ode. The *ollo+in" pin *)nctions are *or

the (ini()( (ode operation o* 8086.

M/# -Me(or/#:

This is a stat)s line lo"icall e)ivalent to 4 in (a/i()( (ode. hen it is lo+, it indicates

the CPU is havin" an '2 operation, and +hen it is hi"h, it indicates that the CPU is havin" a

(e(or operation. This line beco(es active in the previo)s T# and re(ains active till *inal

T# o* the c)rrent ccle. 't is tristated d)rin" local b)s ?hold ackno+led"e?.

-#nterr&pt Ac)no2lege:

This si"nal is )sed as a read strobe *or interr)pt ackno+led"e ccles. 'n other +ords, +hen it"oes lo+, it (eans that the processor has accepted the interr)pt. 't is active lo+ d)rin" T4, T3

and T o* each interr)pt ackno+led"e ccle.

A!-Aress latc !na*le:

This o)tp)t si"nal indicates the availabilit o* the valid address on the addressdata lines, and

is connected to latch enable inp)t o* latches. This si"nal is active hi"h and is never tristated.

-Data %rans(it/eceie:

This o)tp)t is )sed to decide the direction o* data *lo+ thro)"h the transreceivers

bidirectional b)**ers. hen the processor sends o)t data, this si"nal is hi"h and +hen the

processor is receivin" data, this si"nal is lo+. o"icall, this is e)ivalent to 1 in (a/i()(

(ode. 'ts ti(in" is the sa(e as M'2. This is tristated d)rin" 7hold ackno+led"e7.

This si"nal indicates the availabilit o* valid data over the addressdata lines. 't is )sed to

enable the transreceivers bidirectional b)**ers to separate the data *ro( the ()ltiple/ed

addressdata si"nal. 't is active *ro( the (iddle o*T4 )ntil the (iddle o* T# &$9 is tristatedd)rin" 7hold ackno+led"e7 ccle.

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M#$#MM MD! 8086 S"S%!M A$D %#M#$S

'n a (ini()( (ode 8086 sste(, the (icroprocessor 8086 is operated in (ini()(

(ode b strappin" its M9M@A pin to lo"ic1.

'n this (ode, all the control si"nals are "iven o)t b the (icroprocessor chip itsel*.

There is a sin"le (icroprocessor in the (ini()( (ode sste(.

The re(ainin" co(ponents in the sste( are latches, transreceivers, clock "enerator,

(e(or and '2 devices.

o(e tpe o* chip selection lo"ic (a be re)ired *or selectin" (e(or or '2

devices, dependin" )pon the address (ap o* the sste(.

The latches are "enerall b)**ered o)tp)t &-tpe *lip-*lops, like, B#3B3 or 8484.

The are )sed *or separatin" the valid address *ro( the ()ltiple/ed addressdata

si"nals and are controlled b the $ si"nal "enerated b 8086.

Transreceivers are the bidirectional b)**ers and so(e ti(es the are called as data

a(pli*iers.

The are re)ired to separate the valid data *ro( the ti(e ()ltiple/ed addressdata

si"nal. The are controlled b t+o si"nals, na(el, &$9A and &T%A.

The &$9A si"nal indicates that the valid data is available on the data b)s, +hile

&T% indicates the direction o* data, i.e. *ro( or to the processor.

The sste( contains (e(or *or the (onitor and )sers pro"ra( stora"e.

Us)all, $P%2M are )sed *or (onitor stora"e, +hile %Ms *or )sers pro"ra(

stora"e. sste( (a contain '2 devices *or co(()nication +ith the processor as+ell as so(e special p)rpose '2 devices.

The clock "enerator "enerates the clock *ro( the crstal oscillator and then shapes it

and divides to (ake it (ore precise so that it can be )sed as an acc)rate ti(in"

re*erence *or the sste(.

The clock "enerator also snchroni!es so(e e/ternal si"nals +ith the sste( clock.

The "eneral sste( or"ani!ation is sho+n in :i". 1.1.

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ince it has 40 address lines and 16 data lines, the 8086 CPU re)ires three octal

address latches and t+o octal data b)**ers *or the co(plete address and data

separation.

The +orkin" o* the (ini()( (ode con*i")ration sste( can be better described in

ter(s o* the ti(in" dia"ra(s rather than )alitativel describin" the operations.

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8086 T'M'9> &'>%M

The opcode *etch and read ccles are si(ilar. ence the ti(in" dia"ra( can be

cate"ori!ed in t+o parts, the *irst is the ti(in" dia"ra( *or read ccle and the second

is the ti(in" dia"ra( *or +rite ccle.

%$& C$ T'M'9> &'>%M

:i" 1.4 sho+s the read ccle ti(in" dia"ra(. The read ccle be"ins in T1 +ith the assertion

o* the address latch enable $ si"nal and also M'2A si"nal.

&)rin" the ne"ative "oin" ed"e o* this si"nal, the valid address is latched on the local b)s.

The D$A and 0 si"nals address lo+, hi"h or both btes.

:ro( Tl to T#, the M'2A si"nal indicates a (e(or or '2 operation.

t T4 the address is re(oved *ro( the local b)s and is sent to the o)tp)t. The b)s is then

tristated. The read %&A control si"nal is also activated in T4 .

The read %& si"nal ca)ses the addressed device to enable its data b)s drivers. *ter %&A

"oes lo+, the valid data is available on the data b)s.

The addressed device +ill drive the %$& line hi"h, +hen the processor ret)rns the read

si"nal to hi"h level, the addressed device +ill a"ain tristate its b)s drivers.

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%'T$ C$ T'M'9> &'>%M

:i" 1.3 sho+s the +rite ccle ti(in" dia"ra(. +rite ccle also be"ins +ith the

assertion o* $ and the e(ission o* the address.

The M'2A si"nal is a"ain asserted to indicate a (e(or or '2 operation.

'n T4 a*ter sendin" the address in Tl the processor sends the data to be +ritten to the

addressed location.

The data re(ains on the b)s )ntil (iddle o* T# state. The %A beco(es active at the

be"innin" o*T4 )nlike %&A is so(e+hat delaed in T4 to provide ti(e *or *loatin".

The D$A and 0 si"nals are )sed to select the proper bte or btes o* (e(or or

'2 +ord to be read or +ritten.

The M'2A, %&A and %A si"nals indicate the tpes o* data trans*er as speci*ied in

Table

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D esponse Se'&ence

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The 2& pin is checked at the end o* the each b)s ccle. '* it is received active b the

processor be*ore T# o* the previo)s ccle or d)rin" T1 state o* the c)rrent ccle, the CPU

activities & in the ne/t clock ccle and *or the s)cceedin" b)s ccles, the b)s +ill be"iven to another re)estin" (aster The control control o* the b)s is not re"ained b the

processor )ntil the re)estin" (aster does not drop the 2& pin lo+. hen the re)est is

dropped b the re)estin" (aster, the & is dropped b the processor at the trailin" ed"e

o* the ne/t clock as sho+n in *i" 1.#.

MA#MM MD! 8086 S"S%!M A$D %#M#$S

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'n the (a/i()( (ode, the 8086 is operated b strappin" the M9M@A pin to "ro)nd. 'n this

(ode, the processor derives the stat)s si"nals 4A, 1A and 0A. nother chip called b)s

controller derives the control si"nals )sin" this stat)s in*or(ation. 'n the (a/i()( (ode,

there (a be (ore than one (icroprocessor in the sste( con*i")ration. The other

co(ponents in the sste( are the sa(e as in the (ini()( (ode sste(. The "eneral sste(

or"ani!ation is as sho+n in the *i"1.1

The basic *)nctions o* the b)s controller chip 'C8488, is to derive control si"nals like %&A

and %A *or (e(or and '2 devices, &$9A, &T%A, $, etc. )sin" the in*or(ation

(ade available b the processor on the stat)s lines. The b)s controller chip has inp)t lines

4A, 1A and 0A and CE. These inp)ts to 8488 are driven b the CPU. 't derives the

o)tp)ts $, &$9A, &T%A, MTCA, MCA, '2%CA, '2CA and '2CA. The $9A,

'2D and C$9 pins are speciall )se*)l *or ()ltiprocessor sste(s. $9A and '2D are

"enerall "ro)nded. C$9 pin is )s)all tied to

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:i" 1.1 Ma/i()( Mode 8086 ste(

The (a/i()( (ode sste( ti(in" dia"ra(s are also divided in t+o portions as read inp)t

and +rite o)tp)t ti(in" dia"ra(s. The addressdata and addressstat)s ti(in"s are si(ilar to

the (ini()( (ode. $ is asserted in T1, H)st like (ini()( (ode. The onl di**erence lies

in the stat)s si"nals )sed and the available control and advanced co((and si"nals. The *i".

1.4 sho+s the (a/i()( (ode ti(in"s *or the read operation +hile the *i". 1.3 sho+s the

sa(e *or the +rite operation.

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:i". 1.4 Me(or %ead Ti(in" in Ma/i()( Mode

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Ti(in"s *or %IA>TA :i". 1.3 Me(or rite Ti(in" in Ma/i()( Mode

:i"1.#. %IA>TA Ti(in"s in Ma/i()( Mode

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