8411

UNIVERSITY OF ÇUKUROVA INSTITUTE OF NATURAL AND APPLIED SCIENCE

PhD THESIS

Ahmet TEKE UNIFIED POWER QUALITY CONDITIONER: DESIGN, SIMULATION AND EXPERIMENTAL ANALYSIS

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

ADANA, 2011

ÇUKUROVA UNIVERSITY INSTITUTE OF NATURAL AND APPLIED SCIENCES

Ahmet TEKE

PhD THESIS DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING We certify that the thesis titled above was reviewed and approved for the award of degree of the Doctor of Philosophy by the board of jury on 25/05/2011. ……………….................... ………………………….. ……................................ Prof. Dr. Mehmet TÜMAY Prof. Dr. Tankut YALÇINÖZ Assoc. Prof. Dr. Đlyas EKER SUPERVISOR MEMBER MEMBER ……………….................... ………………………….. Assoc. Prof. Dr. Ulus ÇEVĐK Assist. Prof. Dr. K. Çağatay BAYINDIR MEMBER MEMBER This PhD Thesis is written at the Department of Electrical and Electronics Engineering of Institute of Natural and Applied Sciences of Çukurova University.

Registration Number:

Prof. Dr. Đlhami YEĞĐNGĐL Director Institute of Natural and Applied Sciences

This thesis was supported by the Scientific Research Project Unit of Çukurova University for my thesis (Project Number: MMF2009D3). Note: The usage of the presented specific declarations, tables, figures and photographs either in

this thesis or in any other reference without citation is subject to "The law of Arts and Intellectual Products" number of 5846 of Turkish Republic.

UNIFIED POWER QUALITY CONDITIONER: DESIGN, SIMULATION AND EXPERIMENTAL ANALYSIS

I

ABSTRACT

PhD THESIS

Ahmet TEKE

ÇUKUROVA UNIVERSITY

INSTITUTE OF NATURAL AND APPLIED SCIENCES DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Supervisor:Prof. Dr. Mehmet TÜMAY Year: 2011, Pages: 204 Jury :Prof. Dr. Mehmet TÜMAY Prof. Dr. Tankut YALÇINÖZ Assoc. Prof. Dr. Đlyas EKER Assoc. Prof. Dr. Ulus ÇEVĐK Asst. Prof. Dr. K. Çağatay BAYINDIR

Power quality (PQ) problem can be defined as the deviations of the voltage

and/or current from the nominal sine wave. PQ problems generally concern with voltage sags/swells and harmonic currents. Custom Power (CP) devices that mitigate these power quality problems have gained more attention in the recent decades. Unified Power Quality Conditioner (UPQC) is one of the CP devices and it mitigates both load current and supply voltage problems, simultaneously.

In this study, UPQC and a new topology of UPQC namely OPEN UPQC are designed, modeled and setup experimentally to mitigate voltage sag/swells and harmonic currents. UPQC consists of Dynamic Voltage Restorer (DVR) and Active Power Filter (APF). An improved voltage compensation controller and new sag/swell detection method based on Enhanced Phase Locked Loop (E-PLL) are presented for DVR. Traditional Instantaneous Reactive Power Theory (IRPT) is optimized for APF control algorithm to compensate harmonic load current under unbalanced and distorted supply voltages. Digital Signal Processor based 6 kVA, 230Vline-lineUPQC and OPEN UPQC prototypes have been developed for laboratory tests. UPQC and OPEN UPQC with proposed controller algorithms effectively compensates the sag/swell in supply voltage by keeping the load voltage amplitude at 0.9-1 per unit and eliminates the load current harmonics by keeping supply current at 5%<THD (Total Harmonic Distortion), simultaneously.

This experimental study was conducted in Power Quality Laboratory at Electrical and Electronics Engineering Department, Çukurova University, Adana, Turkey. Key Words: Unified Power Quality Conditioner, OPEN UPQC, Custom Power, Active

Power Filter, Dynamic Voltage Restorer.

UNIFIED POWER QUALITY CONDITIONER: DESIGN, SIMULATION AND EXPERIMENTAL ANALYSIS

II

ÖZ

DOKTORA TEZĐ

Ahmet TEKE

ÇUKUROVA ÜNĐVERSĐTESĐ FEN BĐLĐMLERĐ ENSTĐTÜSÜ

ELEKTRĐK ELEKTRONĐK MÜHENDĐSLĐĞĐ ANABĐLĐM DALI Danışman : Prof. Dr. Mehmet TÜMAY Yıl: 2011, Sayfa: 204 Jüri : Prof. Dr. Mehmet TÜMAY Prof. Dr. Tankut YALÇINÖZ Doç. Dr. Đlyas EKER

Doç. Dr. Ulus ÇEVĐK Yrd. Doç. Dr. K. Çağatay BAYINDIR

Güç kalitesi problemi gerilim ve/veya akımın nominal sinüs dalga formundan

sapması olarak tanımlanabilir. Güç kalitesi problemleri genellikle gerilim düşümleri/yükselmeleri ve harmonikli akımlar ile ilgilidir. Güç kalitesi problemlerine çözüm getiren Özel Güç Donanımları son yıllarda büyük bir önem kazanmıştır. Birleştirilmiş Güç Kalitesi Düzenleyici (BGKD) bu donanımlardan biridir ve hem akım hem de gerilim kalitesi problemlerini eş zamanlı olarak azaltır.

Bu çalışmada, gerilim düşümü/yükselimi ve akım harmoniklerini azaltmak amacıyla BGKD ve yeni bir BGKD topolojisi olan Açık BGKD tasarlanmış, modellenmiş ve deneysel olarak kurulmuştur. BGKD, Dinamik Gerilim Đyileştiricisi (DGĐ) ve Aktif Güç Filtresinden (AGF) oluşmaktadır. DGĐ için Gelişmiş-Faz Kilitlemeli Döngü yöntemi tabanlı bir gerilim kompanzasyon yöntemi ve gerilim düşümü/yükselmesini tespit etmek amacıyla yeni bir hata tespit yöntemi sunulmuştur. AGF kontrolcüsünde, Anlık Reaktif Güç Teorisi dengesiz ve harmonikli besleme gerilimlerinde en iyi çalışacak şekilde iyileştirilmiştir. Laboratuvar testleri için Sayısal Sinyal Đşlemci tabanlı 6 kVA, 230Vfaz-faz BGKD ve Açık BGKD prototipleri geliştirilmiştir. Amaçlanan BGKD ve Açık BGKD, kaynak geriliminde meydana gelen gerilim düşümü/yükselimini dengeler ve hassas yük gerilimini 0.9-1 birim değerde ve ayrıca harmonikli yük akımlarını yok ederek kaynak akımını (Toplam Harmonik Bozulma, THB), THB<%5değerinde eşzamanlı olarak tutar.

Bu deneysel çalışma Çukurova Üniversitesi Elektrik Elektronik Mühendisliği Bölümü Güç Kalitesi Laboratuvarında gerçekleştirilmiştir, Adana, Türkiye. Anahtar Kelimeler: Birleştirilmiş Güç Kalitesi Düzenleyicisi, Açık BGKD, Özel

Güç, Aktif Güç Filtresi, Dinamik Gerilim Đyileştiricisi.

BĐRLEŞTĐRĐLMĐŞ GÜÇ KALĐTESĐ DÜZENLEYĐCĐ: TASARIM, SĐMÜLASYON VE DENEYSEL ANALĐZ

III

ACKNOWLEDGEMENTS

It is a pleasure to thank my supervisor Prof. Dr. Mehmet TÜMAY who made

this thesis possible for his esteemed guidance, encouragement, friendship and

support during my studies.

I am grateful to Prof. Dr. Süleyman GÜNGÖR for his encouragement and

good wishes for my work. I also thank to my co-supervisor Assist. Prof. Dr. K.

Çağatay BAYINDIR for his valuable comments on my study. I am especially

indebted to my thesis committee members, Prof. Dr. Tankut YALÇINÖZ, Assoc.

Prof. Dr. Đlyas EKER and Assoc. Prof. Dr. Ulus ÇEVĐK. I also wish to thank Assist.

Prof. Dr. M. Emin MERAL, Ph.D. M. Uğraş CUMA, Rsch. Asst. Lütfü

SARIBULUT, Rsch. Asst. Adnan TAN, Rsch. Asst. Murat FURAT, Rsch. Asst.

Tahsin KÖROĞLU and Ph.D. Alper TERCĐYANLI for their technical helps and

useful suggestions during the study. I am also grateful to the members of the

Electrical and Electronics Engineering Department, Çukurova University.

I would like to thank and acknowledge the financial supported by Electrical,

Electronics and Informatics Research Group of Scientific and Technological

Research Council of Turkey (Project Number: 106E188) for our research project.

This thesis is a part of the research project entitled as “Modeling and Implementation

of Custom Power Park (106E188)”. This project also supports two other Ph.D.

studies namely “Voltage Quality Enhancement with Custom Power Park” and

“Digital Signal Processor based Implementation of Custom Power Device

Controllers”.

I would like also to thank and acknowledge the financial supported by

Scientific Research Project Unit of Çukurova University for my thesis (Project

Number: MMF2009D3).

Finally, I also wish to express my deepest gratitude to my parents and

extended family for their endless support, encouragement and patience.

IV

CONTENTS PAGE

ABSTRACT………………………………………………………………………… I

ÖZ………………………………………………………………………………….. II

ACKNOWLEDGEMENTS……………………………………………………… III

CONTENTS………………………………………………………………………. IV

LIST OF TABLES…………………………………………………………………. X

LIST OF FIGURES……………………………………………………………….XII

LIST OF SYMBOLS…………………………………………………………. XVIII

LIST OF ABBREVATIONS………………………………………………………XX

1. INTRODUCTION……………………………………………………………….. 1

1.1. Background and Research Motivation………………………………………...1

1.2. Objectives and Organization of Thesis………………………………………..3

1.3. Contributions of Thesis………………………………………………………. 5

2. ELECTRIC POWER QUALITY………………………………………………... 7

2.1. Power Quality Terminology………………………………………………….. 7

2.2. Classification of Power Quality Problems and Their Impacts………………...8

2.2.1. Current Harmonic Distortion…………………………………………..10

2.2.2. Voltage Sags……………………………………………………………11

2.2.3. Voltage Swells………………………………………………………… 12

2.3. Power Quality Standards……………………………………………………. 12

2.3.1. Standards Related with Voltage Characteristics………………………. 13

2.3.1.1. IEEE Standards………………………………………………...13

2.3.1.2. IEC Electromagnetic Compatibility Standards………………...13

2.3.1.3. The European Voltage Characteristics Standard……………….14

2.3.2. Standards Related with Current Harmonics…………………………... 15

2.3.2.1. IEEE Standards………………………………………………...16

2.3.2.2. The International Electrotechnical Commission……………… 17

2.3.2.3. Energy Networks Association Engineering

Recommendation G5/4………………………………………... 18

2.4. Custom Power Devices to Mitigate Power Quality Problems……………….19

V

2.4.1. Custom Power Devices………………………………………………...20

2.4.2. Comparisons of Power Quality Mitigation Devices…………………...23

2.4.3. Cost Range of Custom Power Devices……………………………….. 27

2.5. Summary……………………………………………………………………..28

3. LITERATURE REVIEWS OF CUSTOM POWER DEVICES………………... 29

3.1. Literature Review of Active Power Filter……………………………………29

3.1.1. Power Circuit Topologies of APF……………………………………...30

3.1.2. Control Techniques of APF…………………………………………… 34

3.1.3. Active Power Filter in Service…………………………………………36

3.2. Literature Review of Dynamic Voltage Restorer…………………………… 37

3.2.1. Power Circuit Topologies of DVR……………………………………. 38

3.2.2. Control Techniques of DVR…………………………………………... 42

3.2.3. Field Applications of DVR……………………………………………. 45

3.3. Literature Review of Unified Power Quality Conditioner………………….. 46

3.3.1. Power Circuit Topologies of UPQC…………………………………... 48

3.3.2. Control Techniques of UPQC Topologies…………………………….. 50

3.3.3. UPQC in Service and Future Trends………………………………….. 53

3.4. Summary……………………………………………………………………..53

4. CONTROL STRATEGY OF UPQC AND OPEN UPQC……………………… 55

4.1. Control Algorithms for APF………………………………………………… 55

4.1.1. Proposed APF Controller………………………………………………56

4.1.2. Reference Current Generation………………………………………… 58

4.1.3. Hysteresis Current Controller………………………………………….59

4.2. Control Algorithms for DVR………………………………………………...60

4.2.1. Proposed Reference Voltage Generation……………………………… 61

4.2.2. PWM Gate Signal Generation………………………………………… 65

4.2.3. Proposed Sag/Swell Detection………………………………………... 66

4.3. Summary……………………………………………………………………..69

5. DESIGN OF UNIFIED POWER QUALITY CONDITIONER………………...71

5.1. Power Circuit Design of Proposed APF…………………………………….. 71

5.1.1. Design of DC Link Capacitor………………………………………….73

VI

5.1.2. Design of Inverter Circuit……………………………………………...74

5.1.3. Design of Filter Units…………………………………………………. 75

5.2. Components of Proposed APF……………………………………………….77

5.2.1. Voltage and Current Measurements……………………………………78

5.2.2. Signal Conditioner/Interface Board……………………………………79

5.2.3. Firing and Fault Protection Board……………………………………..79

5.2.4. IGBT Driver Circuit…………………………………………………...81

5.2.5. Three-Phase Bridge IGBT Inverter with DC Link Capacitor………….81

5.2.6. Smoothing Inductor and Choke Reactors……………………………...82

5.2.7. Three-Phase Bridge Rectifier with a Resistive Load…………………. 83

5.3. Power Circuit Design of Proposed DVR…………………………………….84

5.3.1. Design of DC Supply…………………………………………………..86

5.3.2. Design of Inverter Circuit…………………………………………….. 86

5.3.3. Design of LC Filter…………………………………………………….87

5.3.4. Design of Series Injection Transformer………………………………. 89

5.4. Components of Proposed DVR……………………………………………... 90

5.4.1. Disturbance (Sag/Swell) Generator…………………………………… 91

5.4.2. Voltage Transducers……………………………………………………93

5.4.3. Signal Conditioner/Interface Board……………………………………93

5.4.4. H-Bridge PWM Inverters……………………………………………... 94

5.4.5. Passive LC Output Filter……………………………………………… 95

5.4.6. Injection Transformer…………………………………………………. 96

5.5. Practical Recommendations for Experimental Study……………………….. 97

5.6. Summary……………………………………………………………………..99

6. SIMULATION STUDY OF UPQC TOPOLOGIES…………………………...101

6.1. Controller of Proposed APF………………………………………………...102

6.2. Controller of Proposed DVR………………………………………………. 103

6.3. Simulation Verification of Proposed UPQC……………………………….. 104

6.3.1. Simulation Results for Standby Operation of DVR…………………. 106

6.3.2. Simulation Results for Reference Current Extraction……………….. 107

VII

6.3.3. Simulation Results for Voltage Sag Compensation and Current Harmonic

Elimination with Proposed UPQC…………………………………... 107

6.3.3.1. Case Study 1: No Voltage Sag, Current Harmonic

Elimination…………………………………………………... 108

6.3.3.2. Case Study 2: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination…………………………………………………... 112

6.3.3.3. Case Study 3: 20% Double Phase Voltage Sag, Current Harmonic

Elimination…………………………………………………... 117

6.4. Simulation Verification of Proposed OPEN UPQC……………………….. 122

6.4.1. Case Study 4: No Voltage Sag, Current Harmonic Elimination…….. 124

6.4.2. Case Study 5: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination…………………………………………………………...127

6.4.3. Case Study 6: 20% Double Phase Voltage Sag, Current Harmonic

Elimination…………………………………………………………...132

6.5. Summary……………………………………………………………………137

7. EXPERIMENTAL VERIFICATION OF UPQC TOPOLOGIES………...……139

7.1. Experimental Results for Standby Operation of DVR…………………….. 140

7.2. Experimental Results for Reference Current Extraction…………………....141

7.3. Experimental Results for Voltage Sag Compensation and

Current Harmonic Elimination with Proposed UPQC……………………. 143

7.3.1. Case Study 1: No Voltage Sag, Current Harmonic Elimination……...143

7.3.2. Case Study 2: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination…………………………………………………………...146


Elimination…………………………………………………………...150

7.4. Experimental Results for Voltage Sag Compensation and

Current Harmonic Elimination with Proposed OPEN UPQC…………….. 154

7.4.1. Case Study 4: No Voltage Sag, Current Harmonic Elimination……..155

7.4.2. Case Study 5: 25% Single-Phase Voltage Sag,

Current Harmonic Elimination………………………………………158

VIII


Elimination………………………………………………………….. 162

7.5. Summary……………………………………………………………………166

8. CONCLUSIONS AND FUTURE WORK……………………………………. 169

REFERENCES………………………………………………………………….. 173

BIOGRAPHICAL INFORMATION……………………………………………. 199

APPENDIX A: Most Common Power Quality Problems……………………….. 200

APPENDIX B: Fundamentals of Instantaneous Reactive Power Theory……….. 202

IX

X

LIST OF TABLES PAGE

Table 2.1. Financial loss per voltage sag for some types of industries ................... 12

Table 2.2. IEEE-519 current harmonic distortion limits ......................................... 17

Table 2.3. Custom power device application matrix............................................... 27

Table 5.1. The filter design parameters of DVR ..................................................... 88

Table 5.2. The ratings and components of disturbance generator........................... 92

Table 6.1. Data of the simulated UPQC system ................................................... 101

Table 6.2. THD contents of load and supply currents of Phase_A for Case 1 ...... 111


Table 6.4. THD contents of supply and filtered currents of Phase_A for Case 3 . 120




Table 7.1. Data of the experimental UPQC system .............................................. 139







Table A.1. Most common PQ problems ................................................................ 200

XI

XII

LIST OF FIGURES PAGE

Figure 2.1. Basic disturbances: (a) Causes at customer side, (b) Causes at utility

side and (c) Affected equipment ......................................................... 9

Figure 2.2. Percentage occurrences of PQ disturbances in equipment

interruptions ........................................................................................ 9

Figure 2.3. Most common types of power quality problems .............................. 10

Figure 2.4. Single line diagrams of a real system with/without CP devices ....... 21

Figure 2.5. Circuit diagram of a shunt APF ........................................................ 21

Figure 2.6. Circuit diagram of a DVR ................................................................ 22

Figure 2.7. Circuit diagram of (a) UPQC and (b) OPEN UPQC ........................ 23

Figure 2.8. The topologies of DVR and STS ...................................................... 24

Figure 2.9. The topology of UPS ........................................................................ 24

Figure 3.1. Basic representation of APF ............................................................. 30

Figure 3.2. Various power circuit topologies of APF: (a) Three-phase 3/4 wire

based, (b) Three-phase with uncontrolled rectifier and(c) Cascaded

multilevel inverter based .................................................................. 31

Figure 3.3. Control unit of APF with a specified power circuit topology .......... 34

Figure 3.4. Basic representation of DVR ............................................................ 37

Figure 3.5. Various power circuit topologies of DVR ........................................ 39

Figure 3.6. Control unit of a DVR with a specified power circuit topology ...... 43

Figure 3.7. Basic representation of UPQC.......................................................... 47

Figure 3.8. Various power circuit topologies: (a) Left shunt-UPQC, (b) Right

shunt-UPQC, (c) OPEN UPQC, (d) Interline UPQC and

(e) Multilevel UPQC ........................................................................ 48

Figure 3.9. Control unit of UPQC with a specified power circuit topology ....... 51

Figure 4.1. The control system of traditional APF .............................................. 56

Figure 4.2. Proposed APF controller................................................................... 57

Figure 4.3. Voltage and current waveforms of hysteresis band controller .......... 59

Figure 4.4. Structure of series inverter control ................................................... 60

Figure 4.5. Reference signal generation for the series controller ....................... 61

XIII

Figure 4.6. Supply voltage and its extracted components .................................. 65

Figure 4.7. Generation of PWM gate signals ...................................................... 66

Figure 4.8. Structures of conventional and proposed sag detection methods ..... 67

Figure 4.9. The depth values of sag with conventional and proposed methods . 68

Figure 5.1. Power diagram of the (a) Proposed UPQC and (b) OPEN UPQC ... 71

Figure 5.2. Power circuit and control system of APF ......................................... 72

Figure 5.3. The single-phase equivalent circuit of APF...................................... 72

Figure 5.4. Experimental block diagram of APF ................................................ 78

Figure 5.5. The current transformers and voltage transducers ............................ 78

Figure 5.6. Picture of signal conditioning board of APF .................................... 79

Figure 5.7. Picture of firing and fault protection board ...................................... 80

Figure 5.8. APF control board ............................................................................ 80

Figure 5.9. IGBT driver cards for one of H-bridge inverters .............................. 81

Figure 5.10. APF inverter with DC link capacitors .............................................. 82

Figure 5.11. Choke reactors (on the top) and interface reactors (on the bottom) . 83

Figure 5.12. Harmonic polluting load ................................................................... 84

Figure 5.13. DVR system connected with energy storage .................................... 85

Figure 5.14. The single-phase equivalent circuit of DVR .................................... 85

Figure 5.15. Experimental block diagram of DVR ............................................... 91

Figure 5.16. View of disturbance generator system .............................................. 92

Figure 5.17. LEM LV25-400 voltage transducer cards ........................................ 93

Figure 5.18. Picture of signal conditioner/interface board ................................... 94

Figure 5.19. Three base VSI with IBGT modules and IGBT driver boards ......... 95

Figure 5.20. Passive LC filters for three-phases of DVR ..................................... 96

Figure 5.21. Single-phase injection transformers ................................................. 97

Figure 6.1. Simulation model of proposed APF control system ...................... 102

Figure 6.2a. PSCAD/EMTDC model of DVR control system: Reference signal

generation ...................................................................................... 103

Figure 6.2b. PSCAD/EMTDC model of DVR control system: Sag/swell

detection ......................................................................................... 104

Figure 6.3. PSCAD/EMTDC model of UPQC ................................................. 105

XIV

Figure 6.4. Sag detection signals for H-bridge inverters of supply voltages .... 106

Figure 6.5. The load current and generated reference currents ......................... 107

Figure 6.6. The waveforms of supply and load voltages for Case 1 ................. 109

Figure 6.7. RMS trends of supply and load voltages ........................................ 109

Figure 6.8. Waveforms of supply voltages and supply currents during Case 1 110

Figure 6.9. Waveforms of Phase_A supply/injected/load voltages;

supply/injected/load currents during Case 1................................... 111



Figure 6.12. Waveforms of supply voltages and currents during Case 2 ............ 114



Figure 6.14. Three-phase voltage and current waveforms at starting of

single-phase 25% voltage sag for Case 2 ....................................... 116

Figure 6.15. Three-phase voltage and current waveforms at ending of




Figure 6.18. The waveforms of supply voltages and currents during Case 3 ..... 119



Figure 6.20. Three-phase voltage and current waveforms at starting of double

phase 20% voltage sag for Case 3 .................................................. 121

Figure 6.21. Three-phase voltage and current waveforms at ending of double


Figure 6.22. PSCAD/EMTDC model of OPEN UPQC ...................................... 123






XV



















Figure 7.1. PWM signals for H-bridge inverters of Phase_A and Phase_B ..... 141

Figure 7.2. Reference currents using traditional and improved IRPT methods 142

Figure 7.3. Experimental diagram of UPQC system with measurement points 143








supply/filter/load currents during Case 2 ....................................... 148



XVI











Figure 7.17. Experimental diagram of OPEN UPQC with measurement points 155





















XVII

XVIII

LIST OF SYMBOLS CDC : DC link capacitor

Cf : Filter capacitance

e(t) : The error signal

Ed : Nominal DC supply voltage

F : Farad

fo : Cutoff frequency

fr : Fundamental frequency

fs : Switching frequency

h : Harmonic order

H : Henry

IaRef : Active filter reference current

Ic : Capacitor current

Ih : hth harmonic current

Iinj : Injected current

IL : Load current

ILH : Maximum demand load current (at fundamental frequency) at PCC

Io : Load current

Is : Supply current

ISC : Maximum short circuit current at point of common coupling

K : Filter factor

k : Modulation index

Lf : Filter inductance

M : Mega

Mag(t) : Amplitude

ms : Milliseconds

p : Instantaneous real power

q : Instantaneous imaginary power

s : Seconds

Tr_A : Injection transformer for phase_A

u(t) : Input signal to the PLL

XIX

Un : Nominal voltage

Va : Phase_A voltage

Vb : Phase_B voltage

Vc : Phase_C voltage

Vd : D component of voltage

VDC : DC link voltage

Verror : Ideal reference voltage value for the PLL

Vinj : Injected voltage

VL : Load voltage

Vo : Nominal load voltage

Voav :Total harmonic of the load Vo

Vp : Voltage phasor

Vpeak : Peak value of voltage

Vphase : Phase voltage

Vq : q component of voltage

Vrms : RMS value of voltage

Vs : Supply voltage

wo : Angular frequency

x(t) : Per unit sinusoidal voltage output of the PLL

y(t) : Output of the PLL

α : Alpha component

β : Beta component

θ(t) : Phase angle of the tracked signal

µ : Micro

Ω : Ohm

XX

LIST OF ABBREVIATIONS

AC : Alternating Current

APF : Active Power Filter

ASD : Adjustable Speed Drive

CP : Custom Power

DC : Direct Current

DSP : Digital Signal Processor

DSTATCOM : Distribution Static Compensator

DVR : Dynamic Voltage Restorer

EMC : Electromagnetic Compatibility

EMI : Electromagnetic Interference

ET AL : And Others

FFT : Fast Fourier Transform

FPGA : Field Programmable Gate Array

GTO : Gate Turn-Off Thyristor

IEC : International Electrotechnical Commission

IEEE : Institute of Electrical and Electronics Engineers

IGBT : Insulated Gate Bipolar Transistor

IHD : Individual Harmonic Distortion

IRPT : Instantaneous Reactive Power Theory

KVA : Kilovolt Ampere

MC-UPQC : Multiconverter Unified Power Quality Conditioner

MVA : Megavolt Ampere

OPEN UPQC : OPEN Unified Power Quality Conditioner

PCC : Point of Common Coupling

PFC : Power Factor Correction

PI : Proportional Integral

PLC : Programmable Logic Controller

PLL : Phase Lock Loop

PQ : Power Quality

XXI

PSCAD/EMTDC : Power System Computer Aided Design/Electromagnetic

Transient DC Program

PU : Per Unit

PWM : Pulse Width Modulation

RMS : Root Mean Square

SARFIx : System Average RMS Frequency Index

SPWM : Sinusoidal Pulse Width Modulation

STS : Static Transfer Switch

TDD : Total Demand Distortion

THD : Total Harmonic Distortion

UPQC : Unified Power Quality Conditioner

UPS : Uninterruptible Power Supply

VSI : Voltage Source Inverter

1. INTRODUCTION Ahmet TEKE

1

1. INTRODUCTION

1.1.Background and Research Motivation

Power quality is defined as the concept of powering and grounding electronic

equipment in a manner that is suitable to the operation of that equipment and

compatible with the premise wiring system and other connected equipment in

Institute of Electrical and Electronics Engineers (IEEE) Standard 1159-1995 (IEEE

Std 519, 1995). International Electrotechnical Commission (IEC) defined power

quality as set of parameters defining the properties of power quality as delivered to

the user in normal operating conditions in terms of continuity of supply and

characteristics of voltage (frequency, magnitude, waveform and symmetry) (Meral,

2009).

There are two classes of power quality problems: phenomena due to low

quality of current drawn by the load caused by nonlinear loads and voltage

disturbances that cause faults in the power system (Sannino et al., 2003). The most

significant and critical power quality problems are voltage sags, voltage swells and

current harmonics. These problems may cause tripping of sensitive electronic

equipment with disastrous consequences in industrial plants where tripping of critical

equipment can bear the stoppage of the whole production with high costs associated

(Chen, 2005).

Custom Power devices also called as power quality compensator employ

power electronic or static controllers in medium or low voltage distribution systems

for the purpose of supplying a level of power quality that is needed by electric power

customers that are sensitive to root mean square (RMS) voltage variations and

voltage transients. CP devices include static switches, power converters, injection

transformers, master control modules and/or energy storage modules that have the

ability to perform current interruption and voltage regulation functions in a

distribution system to improve power quality (Sabin et al., 2003). CP devices are

generally used for voltage regulation, active filtering, load balancing or power factor

correction (Ghosh, 2002).


2

Active Power Filter is a shunt connected compensating device. The main

purpose of this device is to protect supply currents from current harmonics in the

load side (downstream). This is accomplished by rapid shunt current injection to

compensate for the harmonics in the load current. Dynamic Voltage Restorer is a

series connected compensating device that protects sensitive loads from sag/swell

disturbances in the supply side (upstream). This is performed by rapid series voltage

injection to compensate for the drop/rise in the supply voltage.

In recent years, Unified Power Quality Conditioner which offers customers

high quality of power has become an increased concern of engineers. UPQC is a

combination of a shunt (APF) and a series compensator (DVR) connected together

via a common direct current (DC) link capacitor. These devices compensate the

power quality disturbances such as current harmonics and voltage sag/swell to

protect sensitive process loads as well as improve service reliability. However, these

devices do not allow local distributors to guarantee different quality demand levels to

the final customers, because they improve power quality for all the supplied end

users. The installation investments are also quite high relative to the power quality

level obtained.

A solution that has similar performances and advantages, but also makes cost

reduction possible, is OPEN UPQC. This new solution, analyzed in (Morris et al.,

2009) as a simulation study, starts from UPQC configuration and removes the

common DC connection. Therefore, the control strategy is different than the

traditional combined series and shunt converters. Above all, OPEN UPQC can

stabilize load voltage, keep load voltage and supply current sinusoidal and balanced

as well.

The combination of APF and DVR concept being relatively new is still being

researched. It is considered that this will be a universal solution to all power quality

issues because of its voltage and current compensating capability (Jayanti, 2008). In

order to achieve the mitigation of PQ disturbances, new circuit topologies for UPQC

and new control techniques to detect and extract the PQ disturbances should be

examined.


3

1.2. Objectives and Organization of Thesis

The main objectives of this thesis are as follows.

1- To describe the power quality definitions, types of the PQ problems,

main sources of the PQ problems, negative influences of the PQ problems, PQ

standards, solutions to PQ problems and Custom Power concept.

2- To present literature survey of APF, DVR and UPQC with their control

algorithms and power circuit topologies.

3- To find/develop control methods for reference current extraction for APF,

To describe the modeling of APF,

To evaluate the performance of the APF with simulation studies,

To describe the experimental setup of APF,

To evaluate the performance of APF with experimental analysis.

4- To find/develop control methods for reference voltage generation and

sag/swell detection for DVR,

To describe the modeling of DVR,

To evaluate the performance of the DVR with simulation studies,

To describe the experimental setup of DVR,

To evaluate the performance of DVR with experimental analysis.

5- To describe the modeling of UPQC,

To evaluate the performance of the UPQC with simulation studies,

To describe the experimental setup of UPQC,

To evaluate the performance of UPQC (6 kVA, 220 Vl-l) with experimental

analysis.

6- To describe the modeling of OPEN UPQC,

To evaluate the performance of the OPEN UPQC with simulation studies,

To describe the experimental setup of OPEN UPQC,

To evaluate the performance of OPEN UPQC (6 kVA, 220 Vl-l) with

experimental analysis.

7- To present specific and practical recommendations on software and

hardware of the laboratory prototype implementations.


4

A small scale, simple and low cost UPQC and OPEN UPQC circuits are

designed, simulated and experimentally implemented. The power circuits of UPQC

topologies consist of DVR and APF and the control circuit employs new algorithms.

The results of the proposed UPQC and OPEN UPQC systems meet the international

standards for power quality.

After an introductory section where the background and research motivation

of the study are introduced, the structure of this thesis is as follows:

Chapter 2, power quality terms and definitions, types of the power quality

problems, overview of sources of the power quality problems, negative impacts of

the power quality problems and power quality standards are described. The

overviews of Custom Power devices namely Active Power Filter, Dynamic Voltage

Restorer and Unified Power Quality Conditioner are presented.

Chapter 3, after wide literature survey, the control algorithms and power

circuit configurations of each CP device are classified. The advantages and

disadvantages of both the controller methods and circuit topologies are clearly

emphasized.

Chapter 4, the controller algorithms of APF and DVR are presented. The

drawbacks associated with the conventional control technique are presented. The

reference current extraction algorithm of APF is based Instantaneous Reactive Power

Theory. The drawback associated with the conventional IRPT technique is presented

and the modified IRPT method is proposed. DVR with a new compensation method

and a new sag/swell detection method is presented. Both the reference voltage

extraction and sag detection algorithms are based Enhanced Phase Locked Loop and

nonlinear adaptive filter.

Chapter 5, the power circuit design procedure of APF and DVR are

presented. The power circuit of DVR is optimized to perform minimum power

injection and reduce the inverter losses. The designed APF protection board protects

the overall system by preventing the firing pulses going to Insulated Gate Bipolar

Transistor (IGBT) drivers. The laboratory design procedures of 6 kVA, 220 Vl-l

UPQC topologies are presented.


5

Chapter 6, modeling and simulation of UPQC and OPEN UPQC that are the

combination of APF and DVR are presented. Several case studies are performed to

show the validity of proposed UPQC and OPEN UPQC. APF is always on line and

eliminates the load current harmonics keeping the supply current almost sinusoidal.

DVR becomes online when a voltage sag is detected otherwise it is in off state.

Chapter 7, several laboratory tests are performed to show the performance of

proposed UPQC topologies experimentally. The capabilities of UPQC and OPEN

UPQC are deeply analyzed during steady state, transients and faults. The results of

experimental case studies are discussed. The advantages and disadvantages of UPQC

topologies are presented.

Chapter 8, the conclusions, contributions of the thesis and author’s

recommendations for future work are explained.

Finally, all the references used in the thesis, biographical information of the

author and sections of the Appendix are presented.

1.3. Contributions of Thesis

The main differences and important contributions of this thesis can be

summarized as follows:

(i) OPEN UPQC is investigated as experimentally in UPQC literature for the

first time. OPEN UPQC is a relatively new device and not much work has yet been

reported on its theoretical, design procedure and experimental analysis. The

publications made as a result of this thesis will contribute to scientific literature. This

thesis will also contribute to the concept finding solutions to the electric power

quality problems and this will also pioneer the using of related devices in the world.

(ii) APF control algorithm is optimized for harmonic compensation of load

current under unbalanced supply voltages. The disadvantage of IRPT theory under

unbalanced supply voltages is eliminated by creating virtual alpha and beta

components. The number of voltage measurement points has been reduced using this

control approach.


6

(iii) An algorithm for unbalanced voltage sag detection is presented. A passive

filter with a low cut-off frequency is not used in the sag detection. The proposed

method can detect the single-phase voltage sags correctly. The extraction and tracking

of disturbances are fast and accurate when compared with the traditional detection

methods. Each phase of DVR is controlled independently thus minimum voltage

injection is obtained during unbalanced faults. During the standby operation of DVR,

two lower IGBTs in each phase remain turned on while the two upper IGBTs remain

turned off.

(iv) A reference voltage generation method is presented which is used in a

voltage compensation of DVR. Most of the methods in literature have drawbacks to

generate compensation signals experimentally when the supply voltage is distorted

and unbalanced. With this approach, “distortions in the supply line are perfectly

filtered” and a purely sinusoidal reference voltage is obtained.

(v) The wide literature survey for APF, DVR and UPQC has been

accomplished and 6 kVA DSP based laboratory prototypes of UPQC and OPEN

UPQC have been constructed.

(vi) Practical recommendations and suggestions for experimental study are

presented.

2. ELECTRIC POWER QUALITY Ahmet TEKE

7

2. ELECTRIC POWER QUALITY

Power quality has gained more importance in the power industry since the

last two decades 1980s (Dugan et al., 2003). Everybody does not agree with the use

of the term power quality, but they do agree that it has become a very important

aspect of power delivery especially in the second half of the 1990s. There is a lot of

disagreement about what power quality actually incorporates. Various sources use the

term power quality with different meanings. Other sources use similar but slightly

different terminology like quality of power supply or voltage quality (Bollen, 2001).

2.1. Power Quality Terminology

The term power quality has gained some official status already within the

IEEE, e.g., through the name of Standards Coordinating Committee 22: “Power

Quality”. But the international standards setting organization in electrical engineering

(IEC) does not yet use the term PQ in any of its standard documents. Instead it uses

the term “Electromagnetic Compatibility”, which is not the same as power quality

but there is a strong overlap between the two terms. Below, a number of different

terms will be discussed (Bollen, 2001). The definition of power quality given in the

IEEE dictionary originates in IEEE Std. 1100: Power quality is the concept of

powering and grounding sensitive equipment in a matter that is suitable to the

operation of that equipment. However, the following definition is given in IEC

61000-1-1: Electromagnetic compatibility is the ability of an equipment or system to

function satisfactorily in its electromagnetic environment without introducing

intolerable electromagnetic disturbances to anything in that environment. The most

common terms about PQ are explained below with their definitions (Bollen, 2001).

Current quality is concerned with deviations of the current from the ideal. The

ideal current is a single-frequency sine wave of constant frequency and magnitude.

An additional requirement is that this sine wave is in phase with the supply voltage.

Thus where voltage quality has to do with what the utility delivers to the consumer,

current quality is concerned with what the consumer takes from the utility. Voltage


8

and current are strongly related and if either voltage or current deviates from the

ideal it is hard for the other to be ideal. Voltage quality is concerned with deviations

of the voltage from the ideal. The ideal voltage is a single-frequency sine wave of

constant frequency and constant magnitude. The term voltage quality can be

interpreted as the quality of the product delivered by the utility to the customers.

Power quality problem is defined as any power problem manifested in voltage,

current or frequency deviations that result in failure or misoperation of customer

equipment.

The power supply system can only control the quality of the voltage, it has no

control over the currents that particular loads might draw. Therefore, the standards in

the power quality area are devoted to maintaining the supply voltage within certain

limits. Any significant deviation in the waveform magnitude, frequency or purity is a

potential power quality problem. Of course, there is always a close relationship

between voltage and current in any practical power system. Although the generators

may provide a near-perfect sine-wave voltage, the current passing through the

impedance of the system can cause a variety of disturbances to the voltage (Dugan et

al., 2003). Power quality is often considered as a combination of voltage and current

quality. In most of the cases, it is considered that the network operator is responsible

for voltage quality at the point of connection while the customer’s load often

influences the current quality at the point of connection(Bhattacharyya et al., 2007),

(Meral, 2009).

2.2. Classification of Power Quality Problems and Their Impacts

The power quality is seriously disturbed due to the widely use of nonlinear

loads and various faults in power system. Moreover, the controlling equipment and

electronic devices based on computer technology demand higher levels of power

quality. This kind of devices are sensitive to small changes of power quality, a short-

time change on PQ can cause great economical losses. Because of the two reasons

mentioned above, no matter for the power business, equipment manufacturers or for

electric power customers, power quality problems had become an issue of increasing


9

interest. Under the situation of the deregulation of power industry and competitive

market, as the main character of goods, power quality will affect the price of power

directly in near future (Zhao et al., 2004). The most common power quality problems

are given in Table A.1 in Appendix A (Almeida, 2003).

A number of national and local surveys helped to quantify the statistical

aspects of this problem. The most common disturbances and the most commonly

affected equipments are illustrated in Figure 2.1 (Emanuel, 1997). One report shows

that power outages and interruptions cost the U.S. economy between $104 billion

and $164 billion a year due to equipment damage, materials loss, idled labor and lost

production or sales and another $15 billion to $24 billion a year is lost due to power

quality phenomena (Liu et al., 2006).

Figure 2.1. Basic disturbances: (a) Causes at customer side, (b) Causes at utility side

and (c) Affected equipment

Another survey result is given in Figure 2.2. It is concluded that the voltage

sag/swell and harmonics are most common power problems encountered in the

industrial processes (Seng, 2002).

Figure 2.2. Percentage occurrences of PQ disturbances in equipment interruptions


10

This thesis takes into account the most common power quality problems such

as voltage sags/swells and current harmonics as shown in Figure 2.3. Together they

account for high percentage of the power quality disturbances affecting most

commercial and industrial customers (Chen, 2005). The more detailed descriptions of

power quality problems were explained in (Meral, 2009).

Figure 2.3. Most common types of power quality problems

2.2.1. Current Harmonic Distortion

The harmonic voltage and current distortion are strongly linked with each

other because harmonic voltage distortion is mainly due to non-sinusoidal load

currents. Current harmonic distortion requires over-rating of series components like

transformers and cables. As the series resistance increases with frequency, a distorted

current will cause more losses than a sinusoidal current of the same rms value

(Bollen, 2001). Types of equipment that generate current harmonics are single-phase

loads, switched mode power supplies, electronic fluorescent lighting ballasts, small

Uninterruptible Power Supply (UPS) units and variable speed drives (Meral, 2009).


11

The problems caused by current harmonics (Chapman, 2001a) are

overloading of neutrals, overheating of transformers, nuisance tripping of circuit

breakers, over-stressing of power factor correction capacitors and skin effect. The

annual added cost due to harmonics in military electric power installations is $716.3

million for the year 2001 (Liu et al., 2006).

2.2.2. Voltage Sags

Voltage sag is defined as a decrease to between 0.1 and 0.9 per unit (pu) in

rms voltage at the power frequency for durations from 0.5 cycle to 1 min. Voltage

sags are generally related with system faults but can also be caused by energization

of heavy loads or starting of large motors and overloaded wiring. The term sag

describes a short-duration voltage decrease. Although the term has not been formally

defined, it has been increasingly accepted and used by utilities, manufacturers and

end users. IEC definition for this phenomenon is “dip”. The two terms are considered

interchangeable, with sag being the preferred synonym in the U.S. power quality

community. Terminology used to describe the magnitude of a voltage sag is often

confusing. A “15 percent sag” can refer to a sag which results in a voltage of 0.85 or

0.15pu. The preferred terminology would be one that leaves no doubt as to the

resulting voltage level: “a sag to 0.85 pu” or “a sag whose magnitude was 15

percent”. When not specified otherwise, a 15 percent sag will be considered an event

during which the rms voltage decreased by 15 percent to 0.85pu. The nominal or

base, voltage level should also be specified (Dugan et al., 2003).

Voltage sag problems in industrial equipment include (Eberhard et al., 2007)

relays opening due to the dip affecting the relay’s coil voltage, undervoltage sensors

on the AC mains operating unnecessarily, incorrect reports from sensors, such as air

flow sensors or water pressure sensors, circuit breakers or fuses operating, either due

to the increase in current on non-dipped phases or (more often) due to a large

increase in current immediately after the dip or a small section of highly-sensitive

electronics that responds incorrectly to the sag. Typical financial losses per voltage

sag for some types of industries are given in Table 2.1 (Chapman, 2001b).


12

Table 2.1. Financial loss per voltage sag for some types of industries Industry Typical financial loss per event Semiconductor production € 3.800.000 Financial trading € 6.000.000 per hour Computer centre € 750.000 Telecommunications € 30.000 per minute Steel works € 350.000 Glass industry € 250.000

2.2.3. Voltage Swells

A voltage swell can be defined as an increase to between 1.1 and 1.8 pu in

rms voltage or current at the power frequency for durations from 0.5 cycle to 1 min.

The voltage swells are usually associated with system fault conditions, but they are

not as common as voltage sags. One way that a swell can occur is from the

temporary voltage rise on the unfaulted phases during a single line to ground fault.

(Dugan et al., 2003). Swells can also be caused by switching off a large load or

energizing a large capacitor bank, insulation breakdown, sudden load reduction and

open neutral connection. Voltage swells can negatively affect the performance of

sensitive electronic equipment, cause data errors, produce equipment shutdowns,

may cause equipment damage and reduce equipment life. It causes nuisance tripping

and degradation of electrical contacts. It also causes most of the problems as voltage

sag which explained above (Bangor, 2009).

2.3. Power Quality Standards

Standards are needed to achieve coordination between the characteristics of

the power supply system and the requirements of the end use equipment. This is the

role of power quality standards. The methods have been established for measuring

these phenomena and in some cases defining limits for satisfactory performance of

both the power system and connected equipment. In the international community,

both IEEE and IEC have created a group of standards that addresses these issues

from a variety of perspectives (McGranaghan et al., 2002).


13

2.3.1. Standards Related with Voltage Characteristics

The most common international standards setting limits on voltage quality are

described below.

2.3.1.1. IEEE Standards

Short duration voltage variations include variations in the fundamental

frequency voltage that last less than one minute according to IEEE Standard 1159

and IEC definitions. These variations are best characterized by plots of the rms

voltage versus time but it is often sufficient to describe them by a voltage magnitude

and a duration that the voltage is outside of specified thresholds (McGranaghan,

2005). Voltage variations can be a momentary low voltage (voltage sag), high voltage

(voltage swell) or loss of voltage (interruption). IEEE Standard 1159 specifies

durations for instantaneous, momentary and temporary disturbances.

In IEEE, standards work under way to define indices for characterizing

voltage sag performance is being coordinated by IEEE P1564. The most common

index used is System Average RMS Frequency Index (SARFIx). This index

represents the average number of voltage sags experienced by an end user each year

with a specified characteristic. The SARFI index and other alternatives for describing

voltage sag performance are being formalized in the IEEE Standard 1564 Working

Group (McGranaghan, 2005).

2.3.1.2. IEC Electromagnetic Compatibility Standards

A comprehensive framework of standards on electromagnetic compatibility is

under development within the IEC. Electromagnetic compatibility (EMC) is defined

as: the ability of a device, equipment or system to function satisfactorily in its

electromagnetic environment without introducing intolerable electromagnetic

disturbances to anything in that environment. There are two aspects to EMC: A piece

of equipment should be able to operate normally in its environment and it should not


14

pollute the environment too much. In EMC terms: immunity and emission. There are

standards for both aspects (Bollen, 2001). Immunity standards define the minimum

level of electromagnetic disturbance that a piece of equipment shall be able to

withstand. The basic immunity standard IEC-61000-4-1 gives four classes of

equipment performance: (i) Normal performance within the specification limits, (ii)

Temporary degradation or loss of function which is self-recoverable, (iii) Temporary

degradation or loss of function which requires operator intervention or system reset

and (iv) Degradation or loss of function which is not recoverable due to damage of

equipment, components or software or loss of data.

The maximum amount of electromagnetic disturbance that a piece of

equipment is allowed to produce is defined in emission standards. Within the existing

IEC standards, emission limits exist for current harmonics IEC 61000-3-2 and

61000-3-6 and for voltage fluctuations IEC 61000-3-3, 61000-3-5 and 61000-3-7.

Most power quality phenomena are not due to equipment emission but due to

operational actions or faults in the power system. As the EMC standards only apply

to equipment, there are no "emission limits" for the power system (Bollen, 2001).

2.3.1.3. The European Voltage Characteristics Standard

EN 50160 dealing with requirements concerning the supplier’s side

characterizes voltage parameters of electrical energy in public distribution systems.

On the user’s side, it is the quality of power available to the user’s equipment that is

important. Correct equipment operation requires the level of electromagnetic

influence on equipment to be maintained below certain limits. Equipment is

influenced by disturbances on the supply and by other equipment in the installation,

as well as itself influencing the supply. These problems are summarized in the EN

61000 series of EMC standards, in which limits of conducted disturbances are

characterized.

European standard 50160 gives the main characteristics of the voltage at the

customer's supply terminals in public low-voltage and medium-voltage networks

under normal operating conditions. Some disturbances are just mentioned below, for


15

others a wide range of typical values are given and for some disturbances actual

voltage characteristics are given (Bollen, 2001). Standard EN 50160 gives limits for

some variations. For each of these variations the value is given which shall not be

exceeded for 95% of the time. The measurement should be performed with a certain

averaging window. The length of this window is 10 minutes for most variations, thus

very short time scales are not considered in the standard.

The following limits for the low-voltage supply are given in the document

(Bollen, 2001):

Voltage magnitude: 95% of the 10-minute averages during one week shall

be within ±10% of the nominal voltage of 230 V

Harmonic distortion: For harmonic voltage components up to order 25,

values are given which shall not be exceeded during 95% of the 10-minute averages

obtained in one week. The total harmonic distortion shall not exceed 8% during 95%

of the week.

Standard EN 50160 does not give any voltage characteristics for events. For

completeness a list of events mentioned in EN 50160 is reproduced below (Bollen,

2001), (Meral, 2009):

Voltage magnitude steps: These normally do not exceed ±5% of the

nominal voltage, but changes up to ±10% can occur a number of times per day.

Voltage sags: Frequency of occurrence is between a few tens and one

thousand events per year. Duration is mostly less than 1 second and voltage drops

rarely below 40%. At some places sags due to load switching occur very frequently.

Voltage swells: They occur under certain circumstances. Over voltages due

to short-circuit faults elsewhere in the system will generally not exceed 1.5 kV rms in

a 230V system.

2.3.2. Standards Related with Current Harmonics

The most common international standards setting limits on harmonics are

described in the following subsections.


16

2.3.2.1. IEEE Standards

The current harmonic limits given in IEEE Std.519-1995 as requirements that

must be guaranteed by the end user is shown in Table 2.2. For the current harmonic

limits, Total Demand Distortion (TDD) calculation is used. TDD shown in (2.1) shall

be less or equal than proper values prescribed in Table 2.2. The term TDD is very

much like Total Harmonic Distortion (THD) as given in (2.2). The only difference is

the dominator. THD calculation compares the momentary measured harmonics with

the momentary measured fundamental component. TDD calculation compares the

momentary (but steady-state) measured harmonics with the maximum demand

current, which is not a momentary number at all. The difference between TDD and

THD is important because it prevents a user from being unfairly penalized for

harmonics during periods of light load (only the harmonic polluting loads are

running). During periods of light load it can appear that harmonic levels have

increased in terms of percent (THD calculation) even though the actual current

harmonics in amperes (TDD calculation) stayed the same (Blooming et al., 2007),

(Meral, 2009).

maxh2h

h 2

n

IRMS harmonic current

TDDI Max demand load current (15 or 30min)== =∑

(2.1)

2 2rms 1

Current

1

X X RMS sum of all harmonic currentTHD

X RMS fundamental current

−= =

(2.2)

Individual Harmonic Distortion (IHD) at a particular harmonic frequency is

the ratio of the rms of the harmonic under consideration to the rms value of the

fundamental as stated in (2.3).

Harmonic frequencyIHD .100

Fundamental frequency= (2.3)


17

As the problems caused by harmonics become recognized around the world,

standards setting bodies are creating electrical standards that define legal limits for

the level of current harmonics and voltages (Ingram, 1998). The Institute of

Electrical and Electronic Engineers has drafted a Recommended Practice (IEEE Std.

519, 1995) that provides limits for harmonic distortion. IEEE Std. 519 limits the

current harmonics that can be drawn from the power system.

Table 2.2. IEEE-519 current harmonic distortion limits Maximum current harmonic distortion in percent of ILH Individual harmonic order (Odd harmonics) ISC/ILH <11 11≤h<17 17≤h<23 23≤h<35 35≤h TDD <20* 20<50 50<100 100<1000>1000

4.0 7.0 10.0 12.0 15.0

2.0 3.5 4.5 5.5 7.0

1.5 2.5 4.0 5.0 6.0

0.6 1.0 1.5 2.0 2.5

0.3 0.5 0.7 1.0 1.4

5.0 8.0 12.0 15.0 20.0

Even harmonics are limited to 25% of the odd harmonic limits above Current distortions that results in a DC offset, e.g., half-wave converters, are not allowed * All power generation equipment is limited to these values of current distortions, regardless of actual ISC/ILH.

These limits are proportional to the short circuit current ratio and each

consumer must limit the current that they draw accordingly as shown in Table 2.2.

The aim of the standard is to ensure that voltage harmonic distortion is kept low by

limiting the current harmonics drawn by end users.

2.3.2.2. The International Electrotechnical Commission

IEC has a standard, IEC 61000-3-2, that defines current harmonic limits for

devices with a current rating less than or equal to 16A (Ingram, 1998). This has been

ratified as a Harmonized European Standard, EN 61000-3-2 and as a British Standard

(BS EN 61000-3-2, 1995). Unlike its predecessor (IEC 555-2, 1982), no distinction

is made between domestic and professional equipment, rack mounted and three-

phase equipment is specifically mentioned in BS EN 61000-3-2.


18

For future, new standards and/or technical reports are currently being drafted

(Routimo, 2008). For example, limits for interharmonics (IEC 61000-3-9) and

emission limits for frequency range 2-9 kHz (IEC 61000-3-10) will apply to

equipment with input current lower than 16 A. In addition, IEC 61000-3-14 will

assess emission limits for the connection of disturbing installations to low voltage

power systems. The limits specified in IEC for low-voltage systems allow a THD of

8% and include limits for individual harmonic components, which decrease with

frequency.

2.3.2.3. Energy Networks Association Engineering Recommendation G5/4

The intention of the Energy Networks Association Recommendation G5/4,

first published in 2001, was to try to ensure that the levels of harmonics in the Public

Electricity Supply do not constitute a problem for other users of that supply. This is a

primary function of EMC Management and Regulation and it forms part of the

Distribution Code which is a statutory requirement placed on the UK Electricity

Supply Industry. In addition, under EU legislation the supply industry has a duty to

meet BS EN 50160, voltage characteristics of electricity supplied by public

distribution systems, which includes magnitudes of harmonic voltage distortion

among other parameters. To facilitate the connection of non-linear equipment, G5/4-

1 specifies current harmonic emission limits with the intention of limiting the overall

voltage distortion to no more than the network planning levels specified in ER G5/4-

1, which in turn are set to achieve compatibility (Ena, 2006).

G5/4-1 identifies consumers by their point of common coupling (PCC) to the

supply and applies limits at that point. G5/4-1 therefore applies to every consumer

connected to the Public Electricity Supply, including domestic, commercial, shop and

office consumers and industrial users.

It forms part of the consumer’s agreement to connect and it is the

responsibility of the individual consumer to ensure that the appropriate procedures to

agree connection of new loads are followed. It is also very important that the

consumer understands the responsibilities placed on him by the supply utilities to


19

avoid the possibility of having to implement costly remedial measures in the event of

a problem. It is important to understand that G5/4-1 is effectively an “Installation

Standard” and applies to the total harmonic generating equipment installed by a

consumer. It is not a product or equipment standard and no single items of equipment

can be said to comply.

2.4. Custom Power Devices to Mitigate Power Quality Problems

The mitigation device and point of connection is chosen according to its

economic feasibility and reliability that is required. Innovative solutions employing

power electronics are often applied when rapid response is essential for suppressing

or counteracting the disturbances, while conventional devices are well suited for

steady-state or general regulation (Arora et al., 1998). There are two general

approaches to mitigate the PQ problems. One, named as load conditioning, is to

ensure that the process equipment is less sensitive to disturbances, allowing it to ride

through the disturbances. The other is to install a line conditioning device that

suppresses or counteracts the disturbances (Rudnick et al., 2003). Commercially

available mitigation devices tend to protect against a group of PQ disturbances.

Mitigation devices vary in size and can be installed at all voltage levels of a power

system (high, medium and low voltages).

Custom Power is a concept based on the use of power electronic controllers

in the distribution system to supply value-added, reliable and high quality power to

its customers. CP devices or controllers include APFs and DVRs that have the ability

to perform harmonic mitigation and voltage compensation functions in a distribution

system to improve reliability and/or power quality (Sabin et al., 2003). For simple

load applications, selection of the proper mitigation device is fairly straightforward.

However, in large systems with many loads all aspects of the power system must be

considered carefully. Also, when dealing with large systems it is necessary to know

the different sensitive load requirements. Consideration must also be given to the

potential interaction between mitigation devices, connected loads and the power

system (Arora, 1998).


20

2.4.1. Custom Power Devices

Harmonic current flowing through the impedance of power system results in

harmonic voltage drop at the load bus and along the feeder. Faults on transmission or

distribution system can cause voltage sag at the load bus and along the feeder as

shown in Figure 2.4. Custom power devices are a special category of power

conditioning equipment, used to protect the entire facility from such voltage

disturbances (Ghosh, 2002). Custom power devices have to work within parts of a

cycle, thanks to the advancements in power electronics technology, such that the load

bus will not be affected by the supply disturbance.

CP solutions can be categorized as network reconfiguring type or

compensating type (Ghosh, 2002). The network reconfiguring devices are usually

called switchgear and they include current limiting, circuit breaking and current

transferring devices. Network reconfiguring types are Static Current Limiter, Static

Circuit Breaker and Static Transfer Switch (STS). The compensating devices

compensate a load, correct its power factor, unbalance or improve the quality of

supplied voltage. Compensating types are Active Power Filter (also called as

Distribution Static Compensator), Dynamic Voltage Restorer and Unified Power

Quality Conditioner.


21

Figure 2.4. Single line diagrams of a real system with/without CP devices

The basic circuit diagram of APF is shown in Figure 2.5. APF is shunt

connected device that can eliminate the nonlinear load harmonics and can

compensate load reactive current.

Figure 2.5. Circuit diagram of a shunt APF


22

Dynamic Voltage Restorer is a series compensating device and the basic

diagram of a DVR is shown in Figure 2.6. It is used for protecting a sensitive load

that is connected downstream from sag/swell. It can also regulate the bus voltage at

the load terminal.

Figure 2.6. Circuit diagram of a DVR

UPQC consists of two voltage source inverters. It can simultaneously perform

the tasks of APF and DVR. The basic circuit diagrams of UPQC and OPEN UPQC

are shown in Figure 2.7. UPQC and OPEN UPQC protect the loads against voltage

sag, swell, voltage unbalance, harmonics and poor power factor.

UPQC is a combination of a shunt (Active Power Filter) and a series

compensator (Dynamic Voltage Restorer) connected together via a common DC link

capacitor. OPEN UPQC (a new topology of UPQC) consists of DVR and APF

supplied from separate DC link sources. OPEN UPQC allows local distributors to

supply different grades of power to the final customers.


23

Figure 2.7. Circuit diagram of (a) UPQC and (b) OPEN UPQC

2.4.2. Comparisons of Power Quality Mitigation Devices

Power quality problems can be mitigated using traditional and power

electronics based devices. DVR, STS and UPS are most common types of voltage

sag mitigation devices. DVR is usually designed to mitigate voltage dips with

magnitude lower than 50% (Bongiorno et al., 2003). STS can limit the duration of

interruptions and voltage sags/swells to less than one half-cycle in most cases, by

transferring the load from the affected line to a back-up feeder. This high speed of

response is obtained by using two static switches, constituted each by two

antiparallel thyristors, to perform the transfer of the load. The topologies of DVR and

STS are shown in Figure 2.8.


24

Figure 2.8. The topologies of DVR and STS

DVR is not suitable to compensate for interruptions of the supply voltage and

the range of sags that it can mitigate depends on the size of the energy storage.

However, STS cannot mitigate sags that affect both feeders (Benachaiba et al., 2008).

DVR costs less compared to the UPS systems. UPSs have typically been designed

for the correction of different types of voltage disturbances fall into the category of

voltage sags.

Taking the UPS as an example, this has two major implications

(Ramachandaramurthy et al., 2004). First, the energy that a UPS is required to store

is based upon the long duration of a typical voltage outage or blackout, not relatively

short duration voltage sag as shown in Figure 2.9. Secondly, UPS systems are

typically designed for small loads, such as a computer mainframe or low power

safety critical systems. At high power levels, the cost of a UPS system can be

prohibitive as the UPS would need to be able to withstand not only the load current,

but also the full load voltage.

Figure 2.9. The topology of UPS


25

In terms of minimum apparent power injection or size of the coupling

transformer, the performance of a DVR is found to be superior to a Distribution

Static Synchronous Compensator (DSTATCOM). DVR is also smaller in size and

costs less compared to the DSTATCOM. The amount of apparent power injection

required by a DSTATCOM to correct a given voltage sag is much higher than that of

a DVR. The main reason of that is a DVR corrects the voltage sag only on the

downstream side (Haque, 2001).

Tap changing transformer is another solution where it only takes care of a

limited range of voltage sag. The tap-changing transformer is: slow in response,

exhibits contact erosion, needs routine maintenance of its parts, has an uneconomical

size and requires frequent replacement of transformer oil (Singh et al., 2004).

Compared to the other devices, DVR is clearly considered to be one of the best

economic solutions for its size and capabilities (Benachaiba et al., 2008).

When a Static Synchronous Compensator is employed at the distribution level

or at the load end for power factor improvement, active harmonic filtering, dynamic

load balancing, flicker mitigation and voltage regulation alone it is called as

DSTATCOM. DSTATCOM is a fast-compensating reactive power source that’s

applied on the transmission or distribution system to reduce voltage variations such

as sags, surges and flicker, along with instability caused by rapidly varying reactive

power demand. DSTATCOM can also help provide quick recovery for the

transmission system after contingency events such as loss of part of the system or

individual equipment. DSTATCOM is well suited to a major goal of the smart grid:

Integration of renewable energy sources, such as wind, concentrated solar and tidal

power generation. It allows these renewable energy sources to meet utility

interconnection requirements, as well as the power factor, voltage output and low-

voltage ride-through requirements of various worldwide grid codes. When it is used

to do harmonic filtering and reactive power compensation, it is called as Active

Power Filter (Ara et al., 2003), (S&C, 2010).

The use of isolation and harmonic reduction transformers, passive filters and

active solutions are main methods for harmonic mitigation (Chapman, 2001a).

Passive filters are used to provide a low impedance path for current harmonics so


26

that they flow in the filter and not the supply. Passive filters are suited only to

particular harmonics, the isolating transformer being useful only for triple-N

harmonics and passive filters only for their designed harmonic frequency. In some

installations the harmonic content is less predictable. In many IT installations, for

example, the equipment mix and location is constantly changing so that the harmonic

culture is also constantly changing. A convenient solution is the active filter or active

conditioner.

Power Factor Correction (PFC) techniques include both passive and active

solutions for eliminating harmonic distortion and improving power factor. The

passive approach uses inductors, transformers, capacitors and other passive

components to reduce harmonics and phase shift. The passive approach is heavier

and less compact than the active approach, which is finding greater favor due to new

technical developments in circuitry, superior performance and reduced component

costs. Specially corrected transformers are effective only for certain harmonic

frequencies and most passive filters, once installed and tuned, are difficult to upgrade

and may generate harmful system resonance. As for active PFC techniques, they

must be applied to each individual power supply or load in the system, which

complicates architecture and results in high system cost.

Unlike traditional PFC techniques, APF supplies only the harmonic and

reactive power required to cancel the reactive currents generated by nonlinear loads.

In this case, only a small portion of the energy is processed, resulting in greater

overall energy efficiency and increased power processing capability (Brooks, 2004).

APF utilizes harmonic or current injection to achieve PFC. APF determines the

harmonic distortion on the line and injects specific currents to cancel the reactive

loads. This technique has been used for years in high-power, three-phase systems, but

high costs and complicated high-speed circuitry made it impractical for low-level

power systems. However, new techniques that utilize simpler circuitry are making

active power filtering more attractive and advantageous for low power, single-phase

systems. APF is connected in parallel to the front end or AC input of the system and

corrects all loads directly from the AC line. This type of APF provides excellent

harmonic filtering that complies with international harmonic regulations.


27

2.4.3. Cost Range of Custom Power Devices

An overview of events that can be mitigated by the custom power devices

mentioned in this thesis is provided in Table 2.3. Each of these technologies has

found its way into several applications, either as demonstration projects or as cost-

effective and viable solutions to distinct types of PQ problems (Perry et al., 2003).

Table 2.3. Custom power device application matrix

APF STS DVR

Backup Energy Supply Device

Voltage Sag 2 14

Voltage Swell

Momentary Interruption

Capacitor Switching Transient

Voltage Regulation

Flicker

Harmonics 3

Reactive Power Compensation

Cost Range (US$) 120 to 175 per kVAR

500 to 1000 per A

150 to 250 per kVA

750 to 1500 per kVA

1 Generally corrects up to 100% of nominal for “load-induced” sag to 65% to 70% of

nominal. Corrects up to 90% of nominal for “load-induced” sag to 55% to 60%. This

technology is not a typical solution for power-system “fault-induced” voltage sags. 2 Generally corrects up to between 90% and 100% for a sag to 20% of nominal. 3 One model corrects to the 25th harmonic, one model corrects to the 17th. 4 One device corrects for voltage sags and momentary interruptions. Others typically

correct for voltage sags down to 50%.


28

2.5. Summary

Some types of the power quality problems are voltage sag/swell, interruption,

voltage fluctuation, voltage unbalance, current harmonic, current unbalance and

current unbalance. Among them, voltage sags/swells and current harmonics are the

most common power quality problems. Some PQ reports indicate that poor PQ can

cause large financial losses to different types of industries. The limits of PQ

problems are generally set by IEEE and IEC standards.

Custom Power is a concept based on the use of power electronic controllers

in the distribution system to supply value-added, reliable and high quality power to

its customers by eliminating PQ problems. CP devices or controllers, include APFs

and DVRs that have the ability to perform harmonic mitigation and voltage

compensation functions in a distribution system to improve reliability and/or power

quality (Sabin et al., 2003). UPQC and OPEN UPQC topologies consist of two

voltage source inverters and it can simultaneously perform the tasks of APF and

DVR with different circuit topologies. UPQC do not allow local distributors to

guarantee different quality demand levels to the final customers, because they

improve power quality for all the supplied end users. The installation investments are

also quite high relative to the power quality level obtained. A solution that has

similar performances and advantages, but also makes cost reduction possible, is

OPEN UPQC.

The next chapter presents the wide literature survey on Active Power Filter,

Dynamic Voltage Restorer and Unified Power Quality Conditioner.

3. LITERATURE REVIEWS OF CUSTOM POWER DEVICES Ahmet TEKE

29

3. LITERATURE REVIEWS OF CUSTOM POWER DEVICES

The related survey studies are presented under the following heads.

3.1. Literature Review of Active Power Filter

Power electronics based devices/equipments are a major key component of

today’s modern power processing, at the transmission as well as the distribution level

because of the numerous advantages offered by them. These devices, equipments,

nonlinear load including saturated transformers, arc furnaces and semiconductor

switches and so on, draw non-sinusoidal currents from the utility. Therefore a typical

power distribution system has to deal with harmonics and reactive power support

(Khadkikar et al., 2009a), (Teke et al., 2010b).

The presence of harmonics and reactive power in the grid is harmful, because

it will cause additional power losses and malfunctions of the grid components (Luo

et al., 2009). Conventionally, passive filters composed of tuned L-C components

have been widely used to suppress harmonics because of their low initial cost and

high efficiency. However, passive filters have many disadvantages, such as large

size, mistuning, instability and resonance with load and utility impedances (Shuai et

al., 2009). Active Power Filters have now become an alternative solution for

controlling current harmonics in supply networks at the low to medium voltage

distribution level or for reactive power and/or voltage control at high voltage

distribution level (Habrouk et al., 2000). APF such as shunt APFs, series APFs,

hybrid APFs, UPQC and other combinations have made it possible to mitigate some

of the major power quality problems (Khadkikar et al., 2009b).

The main circuit of APF is shown in Figure 3.1. APF system can be divided

into two sections as: The control unit and the power circuit. Control unit consists of

reference signal generation, gate signal generation, capacitor voltage balance control

and voltage/current measurement. Power circuit of APF is generally comprised of

energy storage unit, DC/AC converter, harmonic filter and system protection.


30

Figure 3.1. Basic representation of APF

The findings of the comprehensive literature survey summarize the available

studies related with the control unit and the power circuit of APF.

3.1.1. Power Circuit Topologies of APF

APFs are basically categorized into four types, namely, two-wire (single-

phase) (Fujita, 2009), three-phase three wire (Shuai et al., 2009), three-phase three-

wire with Zig-Zag transformer (Jou et al., 2008) and three-phase four wire

(Vodyakho et al., 2009a) configurations to meet the requirements of the three types

of nonlinear loads on supply systems (Singh et al., 1999). Basic topologies of APF

are shown in Figure 3.2.


31

Figure 3.2. Various power circuit topologies of APF: (a) Three-phase 3/4 wire based,

(b) Three-phase with uncontrolled rectifier and (c) Cascaded multilevel inverter based


32

APFs are used in low power (<100 kVA), medium power (100 kVA-10 MVA)

and high power (>10 MVA) applications (Habrouk et al., 2000). For low power

applications, APFs can be applied for single-phase and three-phase systems. For

single-phase systems, APFs generally mitigate the current harmonics. For three-

phase systems, APFs generally provide acceptable solution for unbalanced load

currents and mitigate the current harmonics. For medium power applications, the

main aim is to eliminate or reduce the current harmonics. Because of economic

considerations, reactive power compensation using active filters at the high voltage

distribution level is not generally regarded as viable (Habrouk et al., 2000). For high

power applications, the harmonic pollution in high-power ranges is not such a major

problem as in lower-power systems. One of the few applications of active filters in

high power systems is the installation of parallel combination of several active filters

because the control and co-ordination requirements of these filters are complicated.

The power circuit of APF generally consists of DC energy storage unit, DC/AC

converter and passive filter.

DC capacitor serves two main purposes: (1) it maintains a DC voltage with a

small ripple in steady state and (2) it serves as an energy storage element to supply

the real power difference between load and supply during the transient period (Jain et

al., 2003). DC link voltage should be higher than maximum peak of the supply

voltage. DC link voltage can be controlled using proportional-integral-derivative

controller (Rahim et al., 2005), PI controller (Singh et al., 2007) and fuzzy logic

(Brahim et al., 2010). In (Shuai et al., 2009), DC link is fed from separate voltage

supply to stabilize DC-side voltage within a certain range. Switched capacitor APF

that brings new dimension to APF as it reduces components and ratings (particularly

capacitor) while performing at low switching frequency is evaluated in (Radzi et al.,

2009). DC link, instead of a capacitor, is used as a battery pack, which is charged

from a photovoltaic array in (Flores et al., 2009). DC link is fed from renewable

energy sources in (Singh et al., 2011).

The converter types of APF can be either Current Source Inverter (Terciyanli

et al., 2011) or Voltage Source Inverter (VSI) (Singh et al., 1999) bridge structure.

VSI structures with Insulated Gate Bipolar Transistor (IGBTs) or Gate Turn Off


33

Thyristor (GTO) have become more dominant, since it is lighter, cheaper and

expandable to multilevel and multi step versions, to enhance the performance with

lower switching frequencies. IGBTs are generally used up to 1 MVA rating, GTO

thyristors are generally used higher than 1 MVA rating (Singh et al., 1999).

Power circuit configuration of APFs can be parallel active filter (Uyyuru et

al., 2009), series active filter (Senturk et al., 2009) and combination of series and

parallel filters (Singh et al., 1999), (Habrouk et al., 2000). The purpose of parallel

active filters is to cancel the load current harmonics fed to the supply. It can also

perform the reactive power compensation and balancing of three-phase currents. The

series active filter produces a PWM voltage waveform which is added/subtracted

to/from the supply voltage to maintain a purely sinusoidal voltage waveform across

the load. However, series active filters are less common industrially than their rivals,

parallel active filters. Combinations of several types of filter can achieve greater

benefits for some applications. The examined combinations are combination of both

parallel and series active filters, combination of series active and parallel passive

filters, combination of parallel active and passive filters (Luo et al., 2010) and active

filter in series with parallel passive filters (Salmeron et al., 2010). Seven-level APF

configuration is also examined in (Massoud et al., 2004), (Xiao et al., 2009).

Multilevel three-leg center-split VSIs are more preferable in medium and large

capacity applications due to lower initial cost and fewer switching devices that need

to be controlled (Dai et al., 2008). The series stacked multilevel converter topology,

which allows standard three-phase inverters to be connected with their DC busses in

series is chosen in (Henning et al., 2008). This converter has both regenerated energy

generation and active power filtering capabilities.

An inductance for output filtering of VSI is used to eliminate the harmonic at

different frequencies. The different combinations of L and C filters to attenuate the

switching ripple currents are examined in (Routimo et al., 2007). A rectifier

employing phase control with extra low inductance characteristic or load which high-

frequency input current, may affect APF and causing it to malfunction or shutdown.

While APF is being applied to this type of load, a reactor (3%~5%) is recommended

to install at the input side of the load to reduce the rising rate of load input current


34

(Enersine, 2010). LC passive filter is used in (Shuai et al., 2009) for harmonic

elimination and reactive power compensation. LCL filter is used in (Vodyakho et al.,

2009) that gives advantages in costs and dynamic performance since smaller

inductors can be used compared to L-filter in order to achieve the necessary damping

of the switching harmonics.

3.1.2. Control Techniques of APF

Active power filters are generally designed to compensate current harmonic,

reactive power, voltage harmonic and to balance the supply current and supply

voltage. Control strategy is based on the overall system control, extraction of

reference signal, capacitor voltage balance control and generation of gating signals as

shown in Figure 3.3.

Figure 3.3. Control unit of APF with a specified power circuit topology

The general control techniques to overcome these PQ disturbances are open

loop control system and closed loop control system. The closed loop control systems

can be further subdivided into other techniques as constant capacitor voltage


35

technique, constant inductor current technique, optimization techniques and linear

voltage control technique (Habrouk et al., 2000).

Classification according to current/voltage reference estimation techniques

can be made as time domain control and frequency domain control that are processed

by the open loop or closed loop control techniques (Habrouk et al., 2000). Control

strategy in the frequency domain is based on the Fourier analysis of the distorted

voltage or current signals to extract compensating current/voltage reference (Singh et

al., 1999). Frequency domain approaches are suitable for both single and three-phase

systems. The frequency domain algorithms are sine multiplication technique

(Habrouk et al., 2000), conventional Fourier and Fast Fourier Transform (FFT)

algorithms (Fathi et al., 2006) and modified Fourier series techniques (Salam et al.,

2006). Control methods of APF’s in the time domain are based on instantaneous

derivation of compensating commands in the form of either voltage or current signals

from distorted and harmonic polluted voltage or current signals (Singh et al., 1999).

Time domain approaches are mainly used for three-phase systems. The time domain

algorithms are Dq method (Fathi et al., 2006), synchronous flux detection algorithm

(Li et al., 2006), fictitious power compensation algorithm (Silva et al., 2008),

constant active power algorithm, constant (unity) power factor algorithm (Flores et

al., 2009), IRPT (p-q) (Mauricio et al., 2009) and neural network (Brahim et al.,

2010). A component that has a frequency between the two frequencies is called an

interharmonic. A method for real-time detection and extraction of interharmonic

components in a power signal with potentially time-varying characteristics is

presented in (Mojiri et al., 2010).

The measurements of load voltage, load current, injected current and

capacitor voltage are required for reactive current extraction (Mauricio et al., 2009).

However, the measurements of load current, injected current and capacitor voltage is

enough for only current harmonic extraction in (Karimi et al., 2003). In (Azevedo et

al., 2008), there is no need to measure the load current or power to calculate the

reference currents.

The switching signals for the solid state devices of APF are generated using

PWM (Massoud et al., 2004), space vector modulation (Zhang et al., 2007), fuzzy


36

logic based control techniques (Qu et al., 2007), sliding-mode (Matas et al., 2008),

hysteresis (Vodyakho et al., 2010), multiresonant controller (Pucci et al., 2009) or

deadbeat controller (Fujita, 2009). The capacitor voltage balance control is

performed using PI controller (Jiang, 2001), artificial neural network based adaptive

PI controller (Bhattacharya et al., 2008), space vector modulation (Zhang et al.,

2008) and fuzzy controller (Kumar et al., 2009) methods.

The digital controllers used in APF for real time applications are combination

of DSP and Field Programmable Gate Array (FPGA) (Fujita, 2009), processor board

(Firlit, 2005), FPGA (Shu et al., 2008) and DSP (Kedjar et al., 2009).

3.1.3. Active Power Filter in Service

Applications of shunt active filters are expanding, not only into industry and

electric power utilities but also into office buildings, hospitals, water supply utilities

and rolling stock (Akagi, 1996), (Akagi, 2000), (Bae et al., 2006). The field

applications of APF are:

Shunt APF of 440V 200-kVA and a shunt active filter of 210V 75-kVA,

designed by Toyo Electric-Manufacturing Company, have been installed for

harmonic compensation at water supply facilities in Takatsuki-City, Japan.

300-kVA Shunt APF manufactured by Meidensha Corporation has been

installed to compensate for harmonic currents generated by eight adjustable speed

drives.

1.5-MW inverter and APF system for the injection of regenerated energy

in a Spoornet Traction Substation (one of South-Africa’s largest railway companies).

21-MVA APF using 4.5-kV 1.5-kA injection-enhanced gate transistors

manufactured by Toshiba-Mitsubishi-Electric Industrial Systems Corporation.

48-MVA APF manufactured by Central Japan Railway Company.

The alternative solution to APF for reactive power compensation can be

capacitor banks and thyristor controlled reactors. The alternative solution to APF for

harmonic mitigation is passive filters. However, APF provides better power quality

than its alternative solutions and it has fast response and fewer transients.


37

3.2. Literature Review of Dynamic Voltage Restorer

Dynamic Voltage Restorer (also known as Static Series Compensator (Lee et

al., 2004), (Awad et al., 2004), (Awad et al., 2005)) maintains the load voltage at a

desired magnitude and phase by compensating the voltage sag/swell, voltage

unbalance and voltage harmonics presented at the point of common coupling

(Ramachandaramurthy et al., 2004), (Mahesh et al., 2008), (Jowder, 2009), (Teke et

al., 2010a). In order to mitigate voltage disturbances, DVR injects voltages of

suitable magnitude and phase in series with the line as shown in Figure 3.4. During

standby operation, DVR neither absorbs nor delivers real power. However, when

voltage sag/swell occurs in the system, DVR delivers/absorbs real power transiently

to/from DC link. Many loads facilitated in industrial plants such as adjustable speed

drives and process control equipments are able to detect voltage faults as minimal as

a few milliseconds. Due to the sensitivity of the loads, DVR is required to response

in a very high speed (Chan et al., 2006).

Figure 3.4. Basic representation of DVR

The alternative solution to DVR can be UPS, switched autotransformer or D-

STATCOM (Haque, 2001), (Banaei et al., 2006), (Kumar et al., 2007). DVR costs

less compared to the UPS systems. UPSs have typically been designed for the


38

correction of different types of voltage disturbances, which may not necessary, fall

into the category of voltage sags. Taking the UPS as an example, this has two major

implications (Ramachandaramurthy et al., 2004). First, the energy that a UPS is

required to store is based upon the long duration of a typical voltage outage or

blackout, not relatively short duration voltage sag. Secondly, UPS systems are

typically designed for small loads, such as a computer mainframe or low power

safety critical systems. DVR is smaller in size and costs less compared to the

DSTATCOM. The amount of apparent power injection required by a DSTATCOM to

compensate a given voltage sag is much higher than that of DVR. The main reason of

that is DVR corrects the voltage sag only on the downstream side (Haque, 2001).

Another solution may be using an autotransformer where it only takes care of a

limited range of voltage sag. The autotransformer has poor controllability, slow

response time for mechanical switching units and needs routine maintenance of its

parts. DVR system consists of power circuit and the control unit. The findings of the

comprehensive literature review summarize the available studies related with the

control unit and the power circuit of DVR and applications of DVR.

3.2.1. Power Circuit Topologies of DVR

DVR can be used for medium voltage (Li et al., 2007b), (Meyer et al., 2008),

(Toodeji et al., 2009) and low voltage applications (Muni et al., 2004). DVR is

generally designed as 3-phase 3-wire (Saleh et al., 2008) but there are also 1-phase

(Kasuni et al., 2006) and 3-phase 4-wire (Wang et al., 2004) studies for DVR.

Available topologies for DVR are transformerless (Li et al., 2002), multilevel (Loh et

al., 2004), four-leg DVR (Naidu et al., 2007), H bridge (Jimichi et al., 2008b) and

interline (Moradlou, et al., 2011). Power circuit of DVR generally consists of DC

link, DC/AC converter, LC filter and injection transformer as shown in Figure 3.5.


39

Figure 3.5. Various power circuit topologies of DVR


40

DC link (energy storage unit) supplies required power for compensation of

load voltage during voltage sag/swell or harmonics. For most DVR applications, the

energy source can be an electrolytic capacitor bank. The selection of the optimum

topology and DVR ratings is related with the distribution of the remaining voltage,

the outage cost and investment cost. The topology of storage systems with auxiliary

supply is applied to increase the performance when the grid of DVR is weak. In this

type, variable DC link voltage (Ho et al., 2008) or constant DC link voltage

(Ramasamy et al., 2007) topologies are applied (Figures 3.5a, 3.5c). In the topology

of storage systems with grid itself, the remaining voltage on supply side (Saleh et al.,

2008) or load side (Jimichi et al., 2008a) is used to supply necessary power to the

system if DVR is connected to the strong grid (Figures 3.5b, 3.5d). Flywheel energy

storage system utilizes a single AC/AC power converter for the grid interface as

opposed to a more conventional AC/DC/AC converter, leading to higher power

density and increased system reliability (Perez et al., 2006), (Zhu et al., 2008), (Wang

et al., 2009). Therefore, a new inter-phase AC-AC topology is presented in (Sree et

al., 2000), (Sasitharan et al., 2009) which needs no storage device. In (Sridhar et al.,

2007), voltage control using a Distributed Generation supported DVR is presented.

When the DC link is fed from the rectifier, the rectifier can be controlled using

hysteresis (Jianfeng et al., 2002) or PI controllers (Sridhar et al., 2007), (Zhu et al.,

2008).

The inverter circuits convert DC power to AC power. The types of inverter

are voltage source (fed) inverter and current source (fed) inverter (Dixon et al.,1997),

(Graovac et al., 2001), (Nielsen et al., 2004). Current source inverter is easy to limit

over current conditions but the value of output voltage varies widely with changes in

load (Figure 3.5d). In the voltage source inverter, the values of output voltage

variations are relatively low due to capacitor but it is difficult to limit current because

of capacitor (Figures 3.5a, 3.5b, 3.5c). Some types of this inverter are: Cyclo

converter based (Sree et al., 2000), 6-bridge (Nguyen et al., 2004), H bridge (Jimichi

et al., 2008b) and Multilevel inverter (Loh et al., 2004), (Sanchez et al., 2009). VSIs

have its drawbacks, such as a rather slow control of converters (LC filter) output

voltage and current protection problems. DC bus voltage oscillations can be observed


41

that make the control of series filter output voltage more difficult. Such problems can

be overcome using current-source converters (Graovac et al., 2001).

The filter unit eliminates the dominant harmonics produced by inverter

circuit. Filter unit consists of inductor (L) and capacitor (C). The design procedure

for LC filter is given in (Dahono et al., 1995). The effect of harmonics generated by

the inverter can be minimized using the inverter side (Newman et al., 2005) or line

side filtering (Choi et al., 2000a). Inverter side filtering scheme has the advantage of

being closer to the harmonic source thus high order current harmonics are prevented

to penetrate into the series injection transformer but this scheme has the

disadvantages of causing voltage drop and phase angle shift in the fundamental

component of the inverter output (Figures 3.5a, 3.5b, 3.5d). In line side filtering

scheme, current harmonics penetrate into the series injection transformer but the

voltage drops and phase shift problems do not disturb the system (Figure 3.5c).

DVR is most of time in standby mode and conduction losses will account for

the bulk of converter losses during the operation (Daehler et al., 2000). The voltage

rating of the transformer depends on the grid voltage level and the depth of voltage

sag which will be compensated. The rated current multiplied by the injection voltage

level gives the VA rating of each phase (Wang et al., 2006). Its main tasks are:

connects DVR to the distribution network via the high voltage windings and

transforms and couples the injected compensating voltages generated by the voltage

source converters to the incoming supply voltage (Benachaiba et al., 2008).

In (Loh et al., 2004) and (Sanchez et al., 2009), DVR is implemented using a

multilevel inverter topology allowing the direct connection of DVR to the

distribution network without using a bulky and costly injection transformer. In (Li et

al., 2002), the use of the transformer is eliminated applying the voltage boosting

functions and a dynamic energy replenishing charging circuit.

In standby mode, the injection transformer works like a secondary shorted

current transformer using bypass switches delivering utility power directly to the

load. Alternatively, during standby operation of DVR, two upper IGBTs in each

phase of the inverter remain turned off while the two lower IGBTs remain turned on.

A short circuit across the secondary (inverter side) windings of the series transformer


42

through L filter is obtained eliminating the use of bypass switches (Jimichi et al.,

2008b). Differential current protection of the transformer or short circuit current on

the customer load side is only two examples of many protection functions possibility

(Benachaiba et al., 2008). The protection of a DVR against voltage surges and short

circuit conditions to prevent its malfunction or destruction is discussed in (Raithmayr

et al., 1998), (Silva et al., 2004).

3.2.2. Control Techniques of DVR

The main considerations for the control system of a DVR include sag/swell

detection, voltage reference generation for transient/steady state control of the

injected voltage, voltage injection strategies and methods for generating of gating

signals as shown in Figure 3.6. Supply voltage data is generally used to generate

reference voltage signal and sag detection signal in most of DVR studies (Silva et al.,

2005), (Jimichi et al., 2008a), (Cheng et al., 2009).

Use of 2 2+d qV V or Vd in a vector controller is the simplest type of sag/swell

detection, which will return the state of supply at any instant in time and hence,

detect whether or not sag has occurred (Fitzer et al., 2004), (Cheng et al., 2009). To

separate the positive and negative sequence components, low pass filters are used

after the d-q transformation in the literature. For effective removal, the cut-off

frequency of the low pass filter must be reduced but has the side effect of reducing

the controller response time (Jung et al., 2002). Other methods in use are neural

networks (Santoso et al., 1996), (Chung et al., 2007), tracking the positive sequence

of the supply voltage (Fitzer et al., 2001), kalman filtering (Dash et al., 2004),

applying the Fourier transform (Amaris et al., 2008) and applying the wavelet

transform (Parsons et al., 1999). Further information about conventional sag

detection method is presented in (Mokhtari et al., 2000). In (Jung et al., 2002), a new

control method for DVR system is proposed by detecting the negative and positive

sequence components using differential controllers and digital filters.


43

Figure 3.6. Control unit of a DVR with a specified power circuit topology

There is also single-phase sag detection methods used in DVR. Soft phase

locked loop (Hangzhou et al., 2008), mathematical morphology theory based low-

pass filter (Zhou et al., 2008) and instantaneous value comparison method (Bae et al.,

2007) are the commonly used methods for single-phase sag detection.

Voltage reference generation is achieved using dq (Jung et al., 2002),

(Bongiorno et al., 2003), (Nielsen et al., 2004), (Yin et al., 2005), pqr (Kim et al.,

2004), artificial neural network (Jurado, 2004), sliding mode (Ruilin et al., 2005),

fuzzy logic (Bayindir et al., 2007) and software Phase Locked Loop (PLL)

(Ramasamy, 2007). Most of DVR controllers are using open-loop feed forward

control in order to meet the fast compensation requirement. However, the presence of

the switching harmonic LC filter would introduce voltage oscillations in transients.

These oscillations increase damping response time of the system (Otaduiet al., 2002).


44

The saturation of the series injection transformer and the voltage drop across

the inductor in steady-state operation are other factors that affect the performance of

DVR in open-loop control (Choi et al., 2002). The load voltage may not be

compensated to the desired value in open-loop feed forward control. The problems

stated above shows that closed-loop control can reduce the damping oscillations

coursed by the switching harmonic LC filter and the load voltage can track closer to

the reference load voltage under varying load condition. Multi-loop control and

closed-loop state variable control are closed-loop control strategies of DVR

(Vilathgamuwa et al., 2002), (Joos et al., 2004). The performance of these control

strategies are investigated with its dynamic and damping performance. These control

schemes can reduce the damping oscillations, but cannot catch up with the fast

dynamic response. Other control strategy is boundary controller (Chan et al., 2006).

The characteristic of load determines the required control strategy to inject

compensation voltage. DVR should ensure the unchanged load voltage with

minimum energy dissipation for injection. The methods for injection of missing

voltage can be divided into four groups (Chung et al., 2003), (Won et al., 2003),

(Chung et al., 2007), (Ezoji et al., 2009a), (Nielsen et al., 2001): Pre-sag

compensation method (Ramachandaramurthy et al., 2002), in-phase voltage injection

method (Margo et al., 2007), phase advance method (Choi et al., 2000b),

(Vilathgamuwa et al., 2003) and voltage tolerance method with minimum energy

injection (Li et al., 2007a).

In pre-sag compensation, the supply voltage is continuously tracked and the

load voltage is compensated. On the other hand, in in-phase compensation, DVR

voltage is always in phase with the measured supply voltage regardless of the load

current and presag voltage. In phase advance method, decreasing the power angle

between the remaining voltage and the load current minimizes real power consumed

by DVR. In voltage tolerance method with minimum energy injection method, the

phase angle and magnitude of corrected load voltage within the area of load voltage

tolerance are changed. The small voltage drop and phase angle jump on load can be

tolerated by load itself and the size of the energy storage is minimized.


45

Fuzzy logic control of DVR for voltage injection is reported in (Jurado et al.,

2003), (Bayindir et al., 2007) in the literature using dq synchronous reference frame.

The control of DVR can be implemented using DSP (Fernandes et al., 2009), FPGA

or combination of them with passive circuits.

The generated reference signal is used to produce gate switching signals of

the inverter. The main modulation techniques used in DVR are space vector PWM

modulation (Duane et al., 1999), deadbeat control (Ghosh et al., 2004a), PWM

(Jimichi et al., 2008b) and hysteresis (Ezoji et al., 2009b). The hysteresis control has

the advantages of quick controllability, easy implementation and variable switching

frequency (Ezoji et al., 2009b). PWM has a great impact on its transient performance

and higher operating frequency capability (Jimichi et al., 2008b). PWM method is

widely used for gate signal generation in custom power applications. The deadbeat

controller has very fast transient response (Ghosh et al., 2004a). The space vector

PWM technique can generate output voltages and/or currents with less harmonic

distortion (Duane et al., 1999).

3.2.3. Field Applications of DVR

DVR have been installed in the Semiconductor, Plastic Extrusion, Food

Processing and Paper Mill factories. Some of DVR applications in service are

summarized as follows (Buxton, 1998), (McHattie, 1998).

i) Orian Rug Company: The first DVR to enter service was installed by

Westinghouse at the Orian Rugs Co. Plant in the USA. This is a highly automated

facility with two main processes. The plant is served by a single 12.47-kV feeder

from a 20-MVA substation transformer four miles away. A 2-MVA DVR, with 660 kJ

of energy storage was installed to this plant.

ii) Florida Power Corporation: 2-MVA DVR at Econlockhatchee was installed

as part of Florida Power Corporation’s new Power Quality Program.

iii) Bonlac Foods, Australia: The Bonlac load is approximately 5.25-MVA and

the facility is served by a 22-kV feeder from Powercor’s Kyabram substation 11

miles away. A 2-MVA DVR was installed to this plant.


46

iv) Caledonian Paper: Scottish Power serves Caledonian Paper via a 132-kV

transmission line which is stepped and the total plant load is 47-MVA. 4-MVA DVR,

with 8MJ of energy storage was installed to this plant.

v) PureWave DVR installations have produced exceptional results for both

power suppliers and energy users. Here are but a few examples:

Semiconductor Manufacturer: A pair of 6-MVA PureWave DVRs protects a

microprocessor manufacturing facility in the southwest U.S. Operating at 12.47-kV,

DVRs serve a 35-MVA load.

Plastic Extrusion Manufacturer: A rug manufacturer in the U.S. uses a

PureWave DVR to protect the yarn extrusion process from sags. A 2-MVA DVR

installed on the 12.47-kV system corrected over 40 sags in its first year of full

operation and over 100 sags the second year.

Food Processing Plant: Interruptions at a powdered milk manufacturing plant

in Australia not only resulted in costly cleanups, but also mandated regulatory

inspections. The dairy processor realized savings of over $1 million annually with

the installation of a PureWave DVR on its 22-kV system, protecting a 6-MVA load.

Paper Mill: An 8-MVA machine load required PureWave DVR protection at a

paper mill in Scotland. A 4-MVA DVR placed on the mill’s 11-kV distribution

system provides sag correction, resulting in increased production by enabling the

machine to run at full speed.

3.3. Literature Review of Unified Power Quality Conditioner

Power quality issues are becoming more and more significant in these days

because of the increasing number of power electronic devices that behave as

nonlinear loads. A wide diversity of solutions to power quality problems is available

for both the distribution network operator and the end user (Singh et al., 1999). The

power processing at supply, load and for reactive and harmonic compensation by

means of power electronic devices is becoming more prevalent due to the vast

advantages offered by them. The shunt APF is usually connected across the loads to

compensate for all current related problems such as the reactive power


47

compensation, power factor improvement, current harmonic compensation and load

unbalance compensation, whereas the series active power filter is connected in a

series with a line through series transformer. It acts as controlled voltage supply and

can compensate all voltage related problems, such as voltage harmonics, voltage sag,

voltage swell, flicker, etc (Khadkikar et al., 2008). UPQC is a Custom Power device

and consists of combined series active power filter that compensates voltage

harmonics, voltage unbalance, voltage flicker, voltage sag/swell and shunt active

power filter that compensates current harmonics, current unbalance and reactive

current as shown in Figure 3.7 (Mekri et al., 2008), (Teke et al., 2011).

Figure 3.7. Basic representation of UPQC

UPQC is also known as the universal power quality conditioning system,

universal active power line conditioner and universal active filter (Aredes et al.,

1998), (Jacobina et al., 2007). UPQC system can be divided into two sections: The

control unit and the power circuit. Control unit includes disturbance detection,

reference signal generation, gate signal generation and voltage/current

measurements. Power circuit consists of two voltage source converters, standby and

system protection system, harmonic filters and injection transformers.

The findings of the comprehensive literature survey summarize the available

studies related with control unit and power circuit of UPQC.


48

3.3.1. Power Circuit Topologies of UPQC

UPQC is a combination of a shunt (Active Power Filter) and a series

compensator (Dynamic Voltage Restorer) connected together via a common DC link

capacitor, which facilitates the sharing of the active power. Each compensator

consists of IGBT inverters, which can be operated in current or voltage controlled

mode. Depending upon the location of the shunt compensator with respect to series

compensator, UPQC model can be named as right shunt-UPQC or left shunt-UPQC.

Typically the active power generated in one unit is consumed in the other unit

maintaining the energy balance overall characteristics of the right shunt-UPQC are

superior to those of the left shunt-UPQC (Ghosh et al., 2002). Basic topologies of

UPQC are shown in Figure 3.8.

Figure 3.8. Various power circuit topologies: (a) Left shunt-UPQC, (b) Right shunt-

UPQC, (c)OPEN UPQC, (d) Interline UPQC and(e) Multilevel UPQC


49

UPQC can be used for medium voltage and low voltage applications. In case

of low power applications, it is not convenient to install a UPQC, since DVR spends

most of its time in standby mode (Mastromauro et al., 2007). UPQC is generally

designed as 3-phase 3-wire (3P3W) systems (Xinming et al., 2009). 3-phase 4-wire

(3P4W) system is also realized from (3P3W) system where the neutral of series

transformer used in series part UPQC is considered as the fourth wire for 3P4W

system (Khadkikar et al., 2009a). There are also single-phase UPQC systems (Nasiri

et al., 2003). Various topologies such as multilevel topology (Tolbert et al., 2000),

single-phase UPQC with two half-bridge converters (Nasiri et al., 2003), H bridge

topology (Ghosh et al., 2004b), (Munoz et al., 2009) and single-phase UPQC with

three legs (Nasiri et al., 2003) are the examined for UPQC applications. A new

topology consists of the DC/DC converter and the supercapacitor is presented in

(Han et al., 2007). The series and parallel units do not have a common DC link in

(Brenna et al., 2009). Advanced renewable generation based distributed power

generation system is developed in (Chakraborty et al., 2009). UPQC is connected

between two independent feeders to regulate the bus voltage of one of the feeders

while regulating the voltage across a sensitive load in the other feeder in (Jindal et

al., 2007). A new configuration, named multiconverter unified power quality

conditioner (MC-UPQC), for simultaneous compensation of voltage and current in

adjacent feeders has been proposed in (Mohammadi et al., 2009). Compared to a

conventional UPQC, MC-UPQC topology is capable of fully protecting critical and

sensitive loads against distortions, sags/swell and interruption in two-feeder systems.

The protection of a UPQC against voltage surges and short circuit conditions

to prevent its malfunction or destruction is discussed in (Chae et al., 2001), (Axente

et al., 2008), (Axente et al., 2010b). The power circuit of UPQC generally consists of

common energy storage unit, DC/AC converter, LC filter and injection transformer.

DC link (energy storage unit) supplies required power for compensation of

load voltage during voltage sag/swell or current harmonics. UPQC generally consists

of two voltage source inverters (series and shunt) using IGBT which operate from a

common DC link storage capacitor (Hosseini et al., 2009). DC link (DC-DC

converter) connected to the battery energy storage system is used in (Davari et al.,


50

2009). Voltage interruption can also be eliminated by the use of a UPQC with

distributed generation (George, 2007). Split capacitor topology is used in (Aredes et

al., 1998). Photovoltaic generation as well as the functions of a unified power quality

conditioner is presented in (Cavalcanti et al., 2006).

VSIs are preferred for both shunt and series sides (Hosseini et al., 2009). The

series converters are generally composed of 6 bridge VSI (Leon et al., 2009) and

rarely composed of three single-phase H bridge VSIs (Ghosh et al., 2004b). Shunt

converters are generally composed of 6 bridge VSIs for three-phase (Forghani et al.,

2007). There are also some studies using 6 bridge inverters for series converter

(Xinming et al., 2009) and three single-phase H bridge inverters for shunt converter

(Ghosh et al., 2004b). Current source inverters are preferred for both shunt and series

sides in (Vadirajacharya et al., 2008).

The effect of harmonics generated by the inverter can be minimized using

inverter side and line side filtering (Choi et al., 2000a), (Newman et al., 2005).

Inverter side LC filtering is generally preferred for both series sides (Basu et al.,

2008) and inverter side L filtering is generally preferred for shunt side (Laxmi et al.,

2006). Inverter side C filtering is preferred for shunt side in (Jindal et al., 2007).

UPQC incorporating an LCL filter is presented in (Axente et al., 2007).

Series converter of UPQC is most of time in standby mode and conduction

losses will account for the bulk of converter losses during the operation (Daehler et

al., 2000). In this mode, the series injection transformer works like a secondary

shorted current transformer using bypass switches delivering utility power directly to

the load. UPQC without injection transformer has been designed and reported in (Tey

et al., 2002). A novel configuration of UPQC which can be connected to the

distribution system without series injection transformers is presented in (Han et al.,

2006).

3.3.2. Control Techniques of UPQC Topologies

The control unit is the most important part of UPQC system. Rapid detection

of disturbance signal with high accuracy, fast processing of the reference signal and


51

high dynamic response of the controller are the prime requirements for desired

compensation (Rezaeipour et al., 2008). The main considerations for the control

system of a UPQC include (Figure 3.9):

Series inverter control: Sag/swell detection, voltage reference generation,

voltage injection strategies and methods for generating of gating signals.

Shunt inverter control: Current reference generation, methods for

generating of gating signals and capacitor voltage control.

Figure 3.9. Control unit of UPQC with a specified power circuit topology

Monitoring of 2q

2d VV + or Vd in a vector controller is the simplest type of

sag/swell detection (Fitzer et al., 2004), (Cheng et al., 2009). The sag/swell detection

methods for series inverter side are root mean square method, FFT method (Kisck et

al., 2007), Synchronous frame (dq) detection method (Elnady et al., 2001), Peak

Sequence Analysis method (Srisongkram et al., 2009) and analogical method of

perturbation detection for voltage (Khoor et al., 2005).

To generate reference signals for shunt converter, IRPT is generally preferred

for reference current calculation (Fujita et al., 1998). An extended method based on

IRPT in a rotating reference frame is used to suppress the harmonics and to correct

the power factor. Adaptive detection technique is evaluated in (Karimi et al., 2003)


52

that minimizes the affects of noise or parameter variations. Besides, sinusoidal

template vector algorithm (Djeghloud et al., 2008), DC link voltage, neuron based

(Kinhal et al., 2011) and PI controller method (Basu et al., 2008) and fuzzy control

(Singh et al., 1998) are used. Dq transform (Zhu et al., 2003), vector template

generation method (Khadkikar et al., 2006), adaptive detection (Rong et al., 2009),

using peak detector and averaging method (Esfandiari et al., 2004), using band pass

filter and positive sequence calculation (Haque et al., 2002) and finite impulse

response filter (Chen et al., 2000) are used to generate reference signals for series

converter unit. Least squares algorithm (Kamwa et al., 1992), wavelet transform

(Elnady et al., 2001), neural network (Tey et al., 2002), positive sequence component

method (Jaime et al., 2002), linear quadratic regulator (Tey et al., 2004), unit vector

template generation method (Khadkikar et al., 2006), multi variable regulator based

with kalman filters (Kwan et al., 2005), artificial intelligence method (George, 2007),

pole shift control (Jindal et al., 2005) and abc-dq transform method (Lee et al., 2010)

are employed to generate reference signals for both series and shunt converter

simultaneously.

The overall power balance of UPQC is maintained through DC-link capacitor

(Jayanti et al., 2009). DC voltage control can be fulfilled by the traditional DC

voltage feedback or PI control (Basu et al., 2008), composite control (Xinming et al.,

2009). UPQC implemented in (Chen et al., 2004) uses a control circuit without

reference calculation. The control of UPQC can be implemented using DSP (Axente

et al., 2010a), FPGA or combination of them with passive circuits.

The outputs of controller process are the control signals used in generation of

switching signals of the inverter. To generate gating signals for only shunt converter,

hysteresis controller (Basu et al., 2008) and predictive current regulation current

controller (Newman et al., 2002) are employed. Sinusoidal PWM (SPWM) (Basu et

al., 2008) and hysteresis controller (Khadkikar et al., 2004) methods are employed to

generate gating signals for only series converter. Space vector PWM in (Li et al.,

2004), fuzzy hysteresis in (Mekri et al., 2008) and SPWM strategy in (Moreno et al.,

2008) are preferred for both series and shunt side inverter signal generation,

respectively.


53

3.3.3. UPQC in Service and Future Trends

Digital controller based UPQC has been developed for a laboratory prototype

in some of the studies (Kolhatkar et al., 2007), (Khadkikar et al., 2008), (Basu et al.,

2008), (Axente et al., 2010a). As a large scale structure, a 250kVA UPQC is

developed at Centre for the Development of Advanced Computing, Trivandrum,

India and is under field trial at the centre (Kumar et al., 2006). Hykon Group

Company installs IGBT based UPQC in the range of 10kVA to 250kVA connected to

a low voltage level (Juha, 2009).

Most of the proposed or practiced control strategies for power quality

conditioners have been reviewed with regard to performance and implementation.

The research reveals that there has been a significant increase in interest of UPQC

and associated control methods. This can be attributed to the availability of suitable

power-switching devices at affordable price as well as new generation of fast

computing devices (microcontroller, DSP, FPGA) at low cost (Rezaeipour et al.,

2008). However, deregulation of electricity market may contribute to rising

penetration level of distributed generation from renewable energy sources (e.g. wind,

solar, biomass, etc.) in the near future. This can lead to an increase in the number of

UPQC studies based on distributed generation (Malabika et al., 2007).

3.4. Summary

Widespread applications of power electronic based devices/equipments in

industry have increased the importance and application of power quality studies.

Decrease in the cost of power electronic devices and improvement in the efficiency

of both power converters and energy storage components have increased the

applicability of new technological solutions such as Custom Power devices. CP

devices including DVR, APF and UPQC are showing tremendous development.

These devices have become very popular in recent years in both low voltage and

medium voltage applications. The comprehensive reviews of articles concerning CP

devices are presented to show the advantages and disadvantages of each possible


54

configuration and control techniques. The literature survey reveals that new control

algorithms and topologies for CP devices have been developed to minimize the

power losses, increase the system flexibility and efficiency. These reviews will help

the researchers to select the optimum control strategy and power circuit configuration

for their CP applications.

The next chapter discusses the traditional and proposed control strategies for

UPQC and OPEN UPQC in detail.

4. CONTROL STRATEGIES OF UPQC AND OPEN UPQC Ahmet TEKE

55

4. CONTROL STRATEGIES OF UPQC AND OPEN UPQC

The control systems of UPQC and OPEN UPQC consist of APF and DVR

controllers. APF controller measures the load voltages, capacitor voltage, load

currents and injected currents. The controller algorithm of APF processes the

measured values and generates the required compensation signals. These signals are

then compared in hysteresis controller and the required gate signals are generated.

DVR controller measures the supply voltages to generate the required compensation

and sag/swell detection signals. These signals are then compared in PWM controller

and the required gate signals are generated.

4.1. Control Algorithms for APF

In this thesis, a simple and effective control algorithm is proposed for

reference current generation. The algorithm for reference current generation is based

on the Instantaneous Reactive Power Theory and it presents some interesting features

(Afonso et al., 2000), namely:

It is inherently a three-phase system theory,

It is based in instantaneous values, allowing excellent dynamic response,

Its calculations are relatively simple (it only includes algebraic expressions

that can be implemented using standard processors),

It allows two control strategies: constant instantaneous supply power and

sinusoidal supply current.

The control system of the traditional APF is shown in Figure 4.1. Three-phase

load voltages, DC capacitor voltage, load currents and injected currents are the input

for the control system. The capacitor voltage is controlled using PI controller. The

outputs of the control system are the reference currents (Ia, Ib and Ic). This obtained

error signals are compared with hysteresis controller and required gate signals for

IGBT switches are generated.


56

Figure 4.1. The control system of traditional APF

4.1.1. Proposed APF Controller

The fundamentals of IRPT are explained in Appendix B. The most important

disadvantage of IRPT theory is that voltage harmonics in supply voltages (so load

voltages) result in increased THD content. This can cause the incorrect calculation of

reference current. To overcome this problem, only one load voltage measurement is

performed. With the use of the measured value, 90° phase shifted virtual voltage is

generated as shown in Figure 4.2 (Cuma, 2010). The generation of this virtual

voltage depends on the detection of zero crossing of phase-to-phases voltage of A

and B phases. With the zero crossing detection, frequency compensation is made on

virtual voltage. The unbalances between measured load voltages are eliminated using

this control approach.

abV Vα = (4.1)

abV V 90β = − ° (4.2)

A PI controller is used to compensate DC link capacitor voltage if APF is in

compensation state. The instantaneous active power is calculated by using the

transformed values and they are applied to a 100 Hz digital low pass filter.


57

The filtered active power value is summed by the output of the voltage

controller to be used in reverse transformation. With a similar way, the reactive

power value is calculated and a reverse transformation is made by using the active

and reactive power values.

Figure 4.2. Proposed APF controller

The basic principle of the compensator will be considered, concerning the α

axis instantaneous current on the load side (Akagi et al., 1984). The instantaneous

active and reactive currents are divided into the following two kinds of instantaneous

currents, respectively:

~ ~

2 2 2 2 2 2 2 2

V VV Vp p q q

V V V V V V V Vi β βα αα

α β α β α β α β

− −− −+ + +

+ + + +=

(4.3)

where p and p are the DC and AC components of the instantaneous real power and

q and %q are the DC and AC components of the instantaneous imaginary power.

The first term of the right-hand side of (4.3) is the instantaneous value of the

conventional fundamental reactive current. The third term is the instantaneous value

of the conventional fundamental reactive current. The second term is the

instantaneous value of the current harmonics which represents the AC component of

the instantaneous real power. The fourth term is the instantaneous value of the


58

current harmonic which represents the AC component of the instantaneous imaginary

power. Accordingly, the sum of the second and fourth terms is the instantaneous

value of the conventional current harmonics. Note that the second and fourth terms

include a conventional negative sequence component. Equation (4.3) leads to the

following essential conclusions (Akagi et al., 1984).

1) The instantaneous reactive power compensator eliminates both the third

and fourth terms. For this reason, the displacement factor is unity not only in steady

states but also in transient states.

2) The current harmonics represented by the fourth term can be eliminated by

the compensator comprising switching devices without energy storage components.

To sum up, from (A.7) in Appendix B, in order to compensate current

harmonics, instantaneous compensating currents (icα and icβ) on α and β coordinates

are calculated by using p and %q as given below:

~1

CP

~CP

V VI p

I V Vq

α βα

β β α

− − = − −

(4.4)

4.1.2. Reference Current Generation

The feedback method used to control self-supporting DC bus is very

important. The method consists of controlling the capacitor voltage to a reference

value. To achieve this, a PI control may be chosen for the error between the reference

value and the capacitor voltage value at the end of each period. The result is the

value of the compensator lost power. This value modifies the power term, which

appear in the compensation current expressions. This term is multiplied with a

constant and added as an error to the filtered value of the instantaneous real power

(Herrera et al., 2008). In order to obtain the reference compensation currents the

error signal is calculated using (4.2).


59

err ref fii i −= (4.5)

4.1.3. Hysteresis Current Controller

The basic of the hysteresis current control is based on an error signal between

an injection current (Iinj) and a reference current of APF (Iref) which produces proper

control signals. The hysteresis band current controller decides the switching pattern

of APF (Ezoji, 2009a). The conventional hysteresis band current control scheme used

for the control of APF is shown in Figure 4.3. There are bands above and under the

reference current. When the error reaches to the upper limit, the current is forced to

decrease. When the error reaches to the lower limit, the current is forced to increase.

Figure 4.3. Voltage and current waveforms of hysteresis band controller

The switching logic is formulated as follows:

• If Iinj< (Iref − hb) upper switch is OFF and lower switch is ON.

• If Iinj> (Iref + hb) upper switch is ON and lower switch is OFF as shown in

Figure 4.3.


60

Some significant advantages of hysteresis controllers over other types of

controllers designed with linear or nonlinear control techniques for APF applications

are as follows (Tilli et al., 1998):

Switching behavior of the power inverter can be directly taken into

account at the design level,

Robustness to load parameters’ variation can be proved,

Almost static response is achieved (the dynamics are obviously bounded

by the DC-link voltage and by the actual switching frequency),

Simple hardware implementation, based on logical devices, is possible

according to Boolean nature of controller input/output variables.

4.2. Control Algorithms for DVR

The control system of DVR performs voltage measurements, sag/swell

detection, reference voltage extraction and gate signal generation. Simple and

effective control algorithms are proposed for both sag detection and reference

voltage generation in this thesis. The algorithms are based on the nonlinear adaptive

filter presented in (Karimi et al., 2002). This filter can be used as a PLL. The filter

has also the abilities of peak detection and signal decomposition. Its performance is

immune to noise and external distortions, accuracy and speed of its response are

controllable and its structural simplicity provides major advantage for its

implementation within embedded controllers.

DVR control includes the reference voltage generation and sag/swell

detection computations as shown in Figure 4.4.


61

Figure 4.4. Structure of series inverter control 4.2.1. Proposed Reference Voltage Generation

The reference voltage computation of series inverter control, which is based

on (4.6-4.23) is shown in Figure 4.5. For series inverter, A(t) corresponds to supply

voltage VS and E(t) corresponds to VPLL_S.

Figure 4.5. Reference signal generation for the series controller

The required compensation signal Verr_S is obtained from (VPLL_S-VS). C(t)

corresponds to Vamp_S and this signal is used to detect voltage sags/swells. The

measurements of supply voltages are required for control strategy of DVR. The

control signals of DVR controller are derived from the following equations.


62

B(t) can be expressed as a continuous time,

B(t) A(t) -E(t) B(t)E(t)dt= ∫

(4.6)

B(t) and E(t) located at right hand side of (4.6) are assumed as a constant due

the value at the instant t is equal to that of the instance (t-1). Hence, the final

statement of (4.6) is given in (4.7).

B(t) A(t) -E(t 1) B(t -1)E(t -1)dt= − ∫ (4.7)

Considering that B(t-1) and E(t-1) are constant, then;

2B(t) A(t) -B(t 1)E (t 1) dt= − − ∫ (4.8)

If the constants are assumed as;

22B(t -1)E (t -1) k= (4.9)

Then, the last statement of B(t) can be written as;

2B(t) A(t)-k t= (4.10)

θ(t) can be expressed as;

(t) (B(t)cos (t) ) dtθ θ π= +∫ (4.11)

Substituting B(t) and A(t)=Asinωt into θ(t), also assuming cosθ(t) is constant,

then;


63

2( ) cos ( ) (( sin t )t t A k t dt dtθ θ ω π= − +∫ ∫ (4.12)

The last statement of θ(t) is given in (4.13).

22kA(t) cos (t)( cos t t ) t2

θ θ ω πω

= − − + (4.13)

E(t) can be expressed as;

E(t) sin (t)θ= (4.14)

Substituting θ(t) into the E(t), E(t) can be written as;

22kAE(t) sin(cos (t)( cos t t ) t)2

θ ω πω

= − − + (4.15)

C(t) can be expressed as;

C(t) B(t)E(t) dt= ∫ (4.16)

In (4.16), E(t) is assumed as a constant due the value at the instant t is equal

to that of the instance (t-1). Hence, the last statement of (4.16) is given in the

following.

C(t) B(t) E(t 1)dt= −∫ (4.17)

Considering that E(t-1)=k3 is a constant, then;

3C(t) k B(t) dt= ∫ (4.18)


64

Substituting B(t) into the C(t), C(t) can be expressed as;

3 2C(t) k (Asin t k t) dtω= − ∫ (4.19)

The last statement of C(t) can be written as follows.

23 2 3k A k kC(t) cos t t

2ω

ω= − −

(4.20)

D(t) can be expressed as;

D(t) C(t)E(t)=

(4.21)

D(t) C(t)sin (t)θ= (4.22)

The last statement of D(t) can be written as follows.

3

C(t)D(t) C(t)sin( t)k

π= + (4.23)

The difference of A(t) and (4.15) give the required magnitude and phase angle

of series compensating voltage to perform the desired operation. The supply voltage

and its extracted components such as difference of input and synchronized

fundamental component B(t), the amplitude C(t), synchronized fundamental

component D(t) and PLL signal E(t)are shown in Figure 4.6 when a 0.3 pu voltage

sag occurs at 1.5s <t< 2.1s.

E-PLL extracts and directly provides the following pieces of information

from the input (Karimi et al., 2002), (Karimi et al., 2003):

Fundamental sinusoidal component of the input; this signal is synchronous

with the input and is smooth and noise-free,


65

Amplitude of the fundamental component of the input,

Phase angle of the fundamental component of the input; this phase can be

adjusted to be its constant phase or total phase.

Figure 4.6. Supply voltage and its extracted components

4.2.2. PWM Gate Signal Generation

The voltage compensation signal Verror is compared with a fixed frequency

carrier wave to generate the firing pulses as PWM signals as shown in Figure 4.7. In

this way, the voltage in the same phase with supply side generated by DVR voltage


66

source inverter is injected to the load side.

Figure 4.7. Generation of PWM gate signals

4.2.3. Proposed Sag/Swell Detection

Proposed sag/swell detection method is compared with the conventional

method using d-q transformation to show the superiority of proposed detection

method. In the conventional method, the phase voltages VA, VB and VC are

transformed to d-q plane as given in (4.24). With the use of (4.25), the sag/swell

depth (Sconv) is obtained (Teke et al., 2009).

Ad

Bq

C

2 2 Vcos cos( ) cos( )V 2 3 3 V3V 2 2sin sin( ) sin( ) V3 3

π πθ θ θ

π πθ θ θ

− +=

− +

(4.24)

2 2

conv qdS 1 V V= − + (4.25)

The block diagram of the d-q transformation based sag/swell detection

method is shown in Figure 4.8a. The most important disadvantage of this method is

that it uses three-phase voltage measurements for the detection. The method is unable

to detect the voltage sag lower than a definite depth. As an instance, a single-phase to


67

ground fault resulting in 20% of voltage sag cannot be determined by this method if

the voltage sag detection limit is selected to be 10%. D-q method uses the average of

the three-phase voltage and perceives the single-phase voltage sag as an average

value of 6.67% that is lower than sag detection limit (10%) (Meral, 2009), (Cuma,

2010).

Another restriction of this method is the use of low pass filter tuned at 50 Hz.

This filter reduces the response speed of the detection scheme. To overcome the

disadvantages of the d-q sag detection method, C(t) signal depicted in Figure 4.5 is

used in this thesis. With the proposed fault detection method, the controller is able to

detect balanced and unbalanced voltage sags/swells without an error. C(t) gives the

amplitude of the tracked signal A(t). For example, if the amplitude of the measured

Phase_A supply voltage is 220 Vrms, C(t) signal is obtained as continuous 1 pu. If the

amplitude falls to the 176 Vrms, the amplitude of the C(t) signal falls to 0.8 pu. The

voltage sag/swell detection method based on E-PLL method is presented in Figure

4.8b.

By subtracting the C(t) signal from the ideal voltage magnitude (1 pu), the

voltage sag/swell depth (Sprop) can be detected as given in (4.26). The comparison of

this value with the limit value of 10% (0.1 pu) gives information whether a fault

occurred or not (Meral, 2009), (Cuma, 2010).


68

Figure 4.8. Structures of conventional and proposed sag detection methods

propS 1 C(t)= − (4.26)

As an example, a single-phase voltage sag initiates at 1.5s with a duration of

0.5s. The conventional method cannot detect the single-phase sag because the error

signal is not correctly calculated as shown in Figure 4.9. The proposed method can

detect the sag depth with an exact certainty and enables the control system to

generate the required gating signals.


69

Figure 4.9. The depth values of sag with conventional and proposed methods

When the supply voltage is within the nominal operation values, DVR is in

OFF-mode (standby). During standby operation of DVR, two lower IGBTs of each

phase H-bridge inverter remain turned on while the two upper IGBTs remain turned

off, thus forming a short circuit across the secondary (inverter side) windings of the

series transformer through LF (Jimichi et al., 2008a). Thus, there is no need to use of

bypass switches. When the supply voltage deviates from its nominal operation value,

DVR comes into ON-mode. In this mode, by using an independent sag detection

method for each phase, each H-bridge inverter is controlled independently. With this

method, minimum energy is injected and switching losses are reduced.

4.3. Summary

The control of UPQC and OPEN UPQC systems consist of APF and DVR

controller. APF controller generates the reference current signal measuring the load

voltage, load current, injected current and capacitor voltage. Proposed APF controller

is derived from IRPT method. The negative effect of traditional IRPT when the

supply voltage is unbalanced and distorted is eliminated using virtual alpha and beta

components. APF controller board protects the overall system by closing the firing


70

pulses going to IGBT drivers. APF also regulates the DC link voltage. Hysteresis

control technique is used to generate the gate switching pulses of APF. DVR

controller generates the reference voltage and sag detection signals measuring the

supply voltages. DVR controller is based E-PLL and the reference voltage signal and

sag detection signal are extracted simultaneously. DVR controller uses independent

sag detection method for each phase and thus each H-bridge inverter is controlled

independently. Sinusoidal PWM control technique is used to generate the gate

switching pulses of DVR.

The main mathematical and numerical features of the control algorithms are

presented. The improvements on APF and DVR controllers are validated with

simulation cases in PSCAD/EMTDC.

The next chapter presents the design of UPQC and OPEN UPQC power

circuits consisting of both shunt (APF) and series (DVR) compensators in detail.

5. DESIGN OF UNIFIED POWER QUALITY CONDITIONER Ahmet TEKE

71

5. DESIGN OF UNIFIED POWER QUALITY CONDITIONER

The power circuits of the proposed UPQC topologies namely UPQC and

OPEN UPQC in a three-phase network are shown in Figure 5.1. The shunt unit

(APF) is designed to minimize load current harmonics from 23.5% to <5% at the

supply side. The series unit (DVR) is designed to inject30% of the network power

supplied from a storage system.

Figure 5.1. Power diagram of (a) Proposed UPQC and (b) OPEN UPQC

5.1. Power Circuit Design of Proposed APF

The components of APF power circuit are DC energy storage unit (DC

capacitor), three-phase inverter circuit, smoothing inductor and choke reactor as

shown in Figure 5.2.


72

Figure 5.2. Power circuit and control system of APF

The single-phase equivalent circuit of APF is shown in Figure5.3. The load

current drives harmonic polluting current (Ih), APF injects the required compensation

current (Iinj) and supply current draws a sinusoidal current (Is).

Figure 5.3. The single-phase equivalent circuit of APF


73

5.1.1. Design of DC Link Capacitor

DC capacitor (energy storage unit) supplies required power for harmonic

compensation of load current during operation. The capacitor size need to be selected

to cover the desired di/dt capability required to compensate current harmonics in any

condition (Vodyakho et al., 2009a). In voltage source active filters, DC voltage of the

energy storage capacitor must be greater than the maximum line voltage. For proper

operation of active filter, at any instant the voltage of the DC capacitor voltage

should be 1.5 times of the line maximum voltage (Emadi, 2004).

Design of the DC side capacitor is based on the principle of instantaneous

power flow on the DC and AC side of the converter. The fluctuation due to the load-

change cannot be taken as a method for capacitor design. However, unlike the

voltage ripple caused by the load unbalance that the ripple must be suppressed by

enlarging the capacitor value, the voltage control section will regulate this fluctuation

caused by the load change. The magnitude of the voltage fluctuation depends on the

closed loop response and can be made small by suitable design of the control

parameters. According to the above analysis, the selection of capacitor value CDC is

governed by reducing the worst case voltage ripple (at 2ω) caused by the unbalanced

load and it can be found from (5.1), (Emadi, 2004):

fLratedDC

DC,p p(max)

I

3wVC π

−

=

(5.1)

where VDC,p-p(max) is the peak to peak voltage ripple, IfLrated is the filter current, w is the

angular frequency.

Theoretically, the capacitor voltage and capacitance of the capacitor value can

be also determined using the findings of (Rathle, 2005). The capacitor value is then

selected by considering the commercial capacitor values.


74

L_LDC

a

1.15 V 2V

m>

(5.2)

aafL

c

mC I2w V

=∆

(5.3)

VDC= The capacitor voltage

VL_L= The peak line to line AC input voltage

ma= The modulation index

C= DC capacitor value

IafL= The output current of APF

∆Vc= The ripple voltage value in % of the capacitor voltage

w= Switching frequency

DC capacitor value is calculated as1900 µF using (5.3) when ma=1,

∆Vc=2.5% of VDC, IafL=6A and w=62831 rad/s. The capacitor is selected as 2200 µF.

5.1.2. Design of Inverter Circuit

The inverter circuit converts DC power to AC power. Three-phase IGBT with

anti-paralleling diodes having turn-off capability are used in the inverter circuits. A

voltage source inverter is energized by a capacitor at the input. The inverter is then

connected in parallel to the distribution line through three smoothing inductors as

shown in Figure 5.2. The proper voltage level for DC capacitor and the power

switching devices with low internal impedance should be selected for the

experimental studies because the active power filter is always on line.

The three-phase PWM voltage source inverter will be used in this thesis.

PWM switched inverters provide better performance to control asymmetries and

especially over currents during unbalanced faults. The current control is achieved by

modulating the output voltage waveform within the inverter. The main advantage of

PWM inverter is including fast switching speed of the power switches. PWM


75

technique offers simplicity and good response. Besides, high switching frequencies

can be used to improve on the efficiency of the converter, without incurring

significant switching losses (Lara et al., 2002).

5.1.3. Design of Filter Units

The shunt APF filter system contains the smoothing-coupling inductors and

chokes (line) reactors filters. The smoothing and coupling inductors establish a link

between the filter and system. The active power filter delivers its current to the

system through the inductor. For controllability of APF, this inductor should not be

large (Emadi, 2004).

Peak ripple current is chosen to be the criterion for designing the inductor.

For calculating the ripple current, no-load condition is considered and the effect

inductor resistance is assumed to be negligible. Under this condition, the inverter

reference voltage is equal to the supply voltage. Thus the required smoothing

inductance given by (Chaoui et al., 2008):

DCsh

s f (p p)max

V

6f IL

−∆=

(5.4)

where ∆If(p-p)max=% of peak compensation current, VDC is the DC side voltage, fs is

the switching frequency.

The design of the smoothing and coupling inductor can also be performed

with the constraint that for a given switching frequency the minimum slope of the

inductor current is smaller than the slope of the triangular waveform that defines the

switching frequency. In this way, the intersection between the current error signal and

the triangular waveform will always exist. The slope of the triangular waveform is

defined by (Luis et al., 1995):


76

4 fλ ξ= (5.5)

where ξ is the amplitude of the triangular waveform, which has to be equal to the

maximum permitted amount of ripple current and f is the frequency of the triangular

waveform (i.e. the inverter switching frequency). The maximum slope of the inductor

current is equal to:

an dciL

f

V V 2d

dt L

+= (5.6)

Since the slope of the inductor current has to be smaller than the slope of the

triangular waveform and the ripple current is known, the value of smoothing-

coupling inductor is calculated using (5.5) and (5.6).

an dcsh

V V 2L

4 fξ+

= (5.7)

The smoothing inductance is calculated as 10 mH using (5.4) when

VDC=375VDC, ∆If(p-p)max=0.6A and f=10 kHz. To improve the smoothing inductance

performance considering the filter market, the inductance is selected as 19 mH (multi

output: 15mH+4mH).

The typical diode DC capacitor front-end configuration of loads draws pulsed

currents from the utility lines, which may lead to high harmonic distortion of the line

currents and poor load power factor. To alleviate this problem, drive manufacturers

typically recommend the use of 3-5% choke (line) reactors (Hoevenaars, 1999).

ch LX (3 5%)Z= − (5.8)

To calculate the actual inductance value, (5.9) should be used.


77

(5.9)

where Lch is inductance in Henrys, Xch is inductive reactance or impedance in ohms

and f is the frequency.

The choke reactor is calculated as 5.73 mH using (5.8) and (5.9) when

ZL=45 Ω and Xch is 4% of ZL. To improve the smoothing inductance performance

considering the filter market, the inductance is selected as 6 mH.

5.2. Components of Proposed APF

The experimental setup of DSP based APF is presented in Figure 5.4. The

current harmonics are generated using resistive load supplied from three-phase diode

rectifier. This rectifier is equipped with choke reactors which makes the line current

more sinusoidal. Three-phase three leg IGBT inverter is used as the voltage source

converter. This inverter is fed from a DC link capacitor. The output of the VSI is

connected to the line via smoothing inductors that convert the voltage output of

inverter to current.

A signal conditioning board is designed to measure load voltages, DC link

capacitor voltage, the filter currents and load currents. The current transformers are

used to measure the filter and load currents. The voltage transducers are used to

measure load voltages and DC link capacitor voltage (Cuma, 2010). DSP kit is used

as the controller of APF. DSP is directly connected on the signal conditioning board.

The outputs of the DSP are applied to a protection and firing board. This board is

responsible to protect the overall system by closing the firing pulses going to IGBT

drivers. The board senses the voltage and current levels on the system and makes

analog protection by the use of logic. The firing section is used as a buffer between

the outputs of DSP kit and IGBT drivers.

/(2 )ch chL X f= Π


78

Figure 5.4. Experimental block diagram of APF

5.2.1. Voltage and Current Measurements

CTF-5A current transformers are used to measure the filter and load currents.

Their secondaries are connected to six connectors on the left bottom of the signal

conditioning board. LV25-P voltage transducers are used to measure the load

voltages and capacitor voltage as shown in Figure 5.5.

Figure 5.5. The current transformers and voltage transducers


79

5.2.2. Signal Conditioner/Interface Board

Signal conditioning board measures the load voltages, DC link voltage, load

currents and filter currents as shown in Figure 5.6. The details of the circuit diagrams

for signal conditioning board are comprehensively presented in (Cuma, 2010).

Figure 5.6. Picture of signal conditioning board of APF

5.2.3. Firing and Fault Protection Board

Protection and firing board is used to drive the IGBT drivers while making

protection functions at the same time as shown in Figure 5.7. The outputs of signal

conditioning board are limited to 3VDC as the ADC inputs of DSP are 3V compatible.

Voltage level greater than 3VDC means that the measured signal is out of limits. An

adjustable voltage compare level is used to control APF voltage and currents. Any

voltage above the compare level stops the firing signals going to the drivers. This is

achieved by comparing the compare voltage level with measurement outputs.


80

Figure 5.7. Picture of firing and fault protection board

TMS320F28335, signal conditioning board, protection and firing board forms

the complete control board as shown in Figure 5.8.

Figure 5.8. APF control board


81

5.2.4. IGBT Driver Circuit

Three Semikron SKHI 22B H4 IGBT drivers are used to drive three

Semikron SKM75GB123D dual IGBT modules. The driver circuit (SKHI 22-2)

amplifies the amplitudes of buffer card at 0-5 V to (-7V)-(15V). IGBT driver card for

one of H-bridge inverters is shown in Figure 5.9.

Figure 5.9. IGBT driver cards for one of H-bridge inverters

5.2.5. Three-Phase Bridge IGBT Inverter with DC Link Capacitor

Three Semikron SKM75GB123D IGBT modules are used to construct the

three wire IGBT inverter as shown in Figure 5.10. DC link capacitors are connected

to the IGBT inverter via busbars. This bank is formed by two series and two parallel

connections of four 450V, 2200µF DC capacitors. By this way, DC voltage rating of

the filter is adjusted to 900VDC while maintaining 2200 µF of capacitor value. Four

1600VDC 0.22 µF snubber capacitors are also added to the inverter to suppress

overshoots.


82

Figure 5.10. APF inverter with DC link capacitors

5.2.6. Smoothing Inductor and Choke Reactors

The smoothing inductors and choke inductors are shown in Figure 5.11. The

values of smoothing inductances for phases A, B and C are 19.41 mH, 20.04 mH and

19.49 mH, respectively. The values of choke reactors for phases A, B and C are 6.14

mH, 6.07 mH and 6.21 mH, respectively.


83

Figure 5.11. Choke reactors (on the top) and interface reactors (on the bottom)

5.2.7. Three-Phase Bridge Rectifier with a Resistive Load

The single-phase load used for the experiment is shown in Figure 5.12. The

load has two 90Ω/6500 W resistors in series and supplied from SKD62/16 three-

phase rectifier.


84

Figure 5.12. Harmonic polluting load

5.3. Power Circuit Design of Proposed DVR

The components of DVR power circuit are DC energy storage unit, inverter

circuit, LC harmonic filter and injection transformer as shown in Figure 5.13.

DCInputs

Fuse

3 phasesupply

DCoutputs

Heatsink


85

Figure 5.13. DVR system connected with energy storage

The single-phase equivalent circuit of DVR is given in Figure 5.14. The

voltage sag occurs on supply voltage (Vs), DVR senses the voltage sag and injects the

missing voltage to the system in series (Vinj) and the load voltage is not affected by

the voltage sag (VL).

Figure 5.14. The single-phase equivalent circuit of DVR


86

5.3.1. Design of DC Supply

A storage system with auxiliary supply is used in DVR for UPQC and DC

capacitor is used in DVR for OPEN UPQC. The design procedure for DC capacitor

was mentioned in Section 5.1.1. DC supply (energy storage unit) provides required

power for compensation of load voltage during voltage sag/swell. The reactive power

exchanged between DVR and the distribution system is internally generated by DVR

without any AC passive reactive components. Real power exchanged at the AC

terminals of DVR must be provided at DC terminal of DVR (Woodley et al., 1999).

Thus, DC link voltage is almost kept constant with this topology during voltage sag.

DC link voltage level is related with sag level to be compensated and the

turns ratio of injection transformer (Teke, 2005).

DC an sl(pu)V a 2V V=

(5.10)

where Van is the single-phase phase to ground rms voltage, Vsl(pu) is the sag level to be

compensated and a is the turns ratio.

DC link voltage is calculated as 270VDC when Van=127Vrms, Vsl(pu)=0.3 pu

and a=5 using (5.10).

5.3.2. Design of Inverter Circuit

IGBTs are used in the inverter circuits to convert DC power to AC power. A

voltage source inverter is energized by a constant DC voltage supply of low

impedance at the input. The output voltage is independent of load current. The

inverters are then connected in series to the distribution line through single-phase

injection transformers. IGBT is a unidirectional conducting device and hence in most

of the applications an anti-parallel diode has to be used (Meral, 2009). When IGBTs


87

are used as switching components in an inverter or converter, freewheeling diodes are

needed to sustain the current from the inductive load such as a motor or transformer.

PWM switched inverters provide superior performance to control

asymmetries and especially over currents during unbalanced faults. Three single-

phase PWM VSIs are used in this thesis. Use of single-phase H-bridge PWM

inverters in DVR power circuit makes possible the injection of positive, negative and

zero sequence voltages. The voltage control is achieved by modulating the output

voltage waveform within the inverter. The main advantage of PWM inverter is

including fast switching speed of the power switches. PWM technique offers

simplicity and good response. Besides, high switching frequencies can be used to

improve on the efficiency of the converter, without incurring significant switching

losses (Lara et al., 2002).

5.3.3. Design of LC Filter

LC filter suppresses the dominant harmonics produced by inverter circuit.

Inverter side filtering is preferred for harmonic elimination in this thesis. This

scheme has the advantageous of being closer to the harmonic source and low voltage

side thus it prevents the current harmonics to penetrate into the series injection

transformers (Choi et al., 2002).

The design procedure of the LC filter can be divided into four steps by

considering the assumptions of (Dahono et al., 1995), (Teke, 2005).

(i) Based on the DC supply voltage Ed and nominal load voltage Vo, the

modulation index k is calculated.

d

o

E

Vk 2= (5.11)

(ii) The result is used to calculate filter factor K by using (5.12).


88

2/16542

14404

5-

5

64

4

15-

Π

+=

kkkk

K

(5.12)

(iii) Equation (5.13) calculates the optimum value of the filter inductance.

2/12

2

,

41

Π+

Ι=

oav

d

s

r

avo

d

so

o

fV

EK

f

f

V

EK

f

VL (5.13)

Io is the load current, fs is the switching frequency, fr is the fundamental output

frequency and Vo,av is the total harmonic of the load voltage.

(iv) Equation (5.14) calculates the optimum value of the filter capacitance.

avosf

d

fVfL

EKC

,2

= (5.14)

L and C values are calculated following the design procedure of (Dahono et

al., 1995) in this thesis. The values of filter design parameters shown in Table 5.1.

The nominal modulation index is calculated using (5.11) and it results in k=1.

d

o

E

Vk 2=

Table 5.1. The filter design parameters of DVR Vo Ed Io fr fs Vo,av

190 Vrms 270 VDC 9.09 Arms 50 Hz 10 kHz 0.1%

The result is then used to calculate the factor K by using (5.12).


89

2/16542

14404

5

5

64

4

15

Π

+=

kkkk

K → 00716.0=K

The optimum values of the inductance and capacitance of the filter can be

calculated by using (5.13) and (5.14).

2/1

,

2

2

,

41

Π+

Ι=

avo

d

s

r

avo

d

so

of

V

EK

f

f

V

EK

f

VL → fL 9.2 mH=

avosf

d

fVfL

EKC

,2

= → fC 20 Fµ=

From the view of costs and weight, the capacitor is the much cheaper device

than the inductor. To improve the filter performance considering the filter market, the

capacitor is selected as 18 µF and the filter inductor is selected as 10 mH in the

thesis.

5.3.4. Design of Series Injection Transformer

The transformers reduce the voltage requirement of the inverters and provide

isolation between the inverters. This can prevent DC storage capacitor from being

shorted through switches in different inverters (Ghosh, 2002). The electrical

parameters of series injection transformer should be selected correctly to ensure the

maximum reliability and effectiveness. In normal bypass mode, full load currents

pass through these semiconductor switches. The flowing current will increase during

sags because of injected power for compensation so the switches and protection

devices should handle the total current. Injection transformer rated at 1 kVA (5:1 turns

ratio, primary/secondary) are used in this thesis.


90

5.4. Components of Proposed DVR

The hardware components of DSP controlled three-phase DVR and typical

output waveforms are given in Figure 5.15. DVR prototype system consists of an

eZdsp F2812 DSP board, H-bridge IGBT inverter, LC filter circuit, DC supply,

injection transformer and measurement devices. Three voltage transducer circuits

(LEM LV25-400) are used to measure the supply voltages. Signal conditioning board

is responsible for input and output signal conditioning for DSP controller. The

produced signals have 0-3.3 Vpeak value. These signals are amplified to 0-5 V and

connected to IGBT driver circuit (SKHI 22B). The driver circuit changes the

amplitudes of the (0-5 V) signals to (-7 Vpeak)-(15 Vpeak). The amplified signals are

given to Gate-Emitter of each IGBT (SKM75GB123D) which is now suitable to

trigger an IBGT. Four IGBTs (two legs) are required to obtain an H bridge inverter.

Two IGBT modules are used for each leg and one driver circuit is required for each

leg. The procedure is the same for other two phases.

A constant DC power supply (270VDC) is employed as energy storage for

UPQC. DC link capacitor (2200 µF) is used as energy storage for OPEN UPQC.

Three single-phase H-bridge PWM inverters consisting of IGBT switches are used in

the voltage source converter circuit. The inverter side filtering is preferred in this

thesis. Voltage sag/swell generator is feeding the load through the series injection

transformers of DVR. Each inverter output is filtered out by an LC filter to eliminate

the higher order harmonics generated by the inverter itself. The filtered output of the

IGBT inverters are connected to the primary side of the injection transformers thus

enabling the injection of the missing voltage to the load.


91

Figure 5.15. Experimental block diagram of DVR

The experimental photographs are taken within the project “Modeling and

Implementation of Custom Power Park” which is supported by Scientific and

Technological Research Council of Turkey with project number of 106E188.

5.4.1. Disturbance (Sag/Swell) Generator

A disturbance generator is designed and implemented to create voltage sag at

any instant of with amplitudes ranging from 0-220Vl-l. The designed disturbance

generator system consists of variable voltage sources, thyristors pairs, thyristors

drivers, protection devices and time relays as shown in Figure 5.16. The ratings of

components on disturbance generator are given in Table 5.2. During normal

operating conditions, the load is supplied from Supply-1. This supply is fixed at 220

Vl-l. When a disturbance is desired, the system is supplied from Supply-2 arranged as

desired voltage level (0-220Vl-l) and time interval.


92

Table 5.2. The ratings and components of disturbance generator Component Ratings Voltage supplies 18.75 kVA, 25 A, 3x380 V input,

3x(0-380) V variable output Thyristor modules Semikron 1200 V, 40 A Thyristor drivers Semikron 12 V Timer relays 220 V, single-phase AC time relays

Figure 5.16. View of disturbance generator system

Supply 1: 220 Vrms Supply 2: 0 - 220 Vrms

Sag /swellgenerator

Thyristor

pairs

Thyristor

driver

Timer


5.4.2. Voltage Transducers

The three-phase set of voltages are measured from the

three LEM LV25-400 transducer cards. The card is adjusted to read

convert it into 1.5 Vpeak

Figure 5.17. LEM LV25

5.4.3. Signal Conditioner/Interface Board

The voltage measurement is achieved using transducers

boards. The supply voltages are measured using voltage transducers. The transducers

convert 220 Vrms value to 1.5 V

used to add 1.5 VDC

this way, the analog input signals are increased to the 0

inputs, processes them using the internal algorithm and produces square wave output

signals having 0-3.3 V amplitudes.

5 V low and high levels which are required value for the input of IGBT driver.

0.6 V diode voltage drop is used to increase the output voltage level to 3

permissible by the IGBT driver cards.

UNIFIED POWER QUALITY CONDITIONER Ahmet TEKE

93

.2. Voltage Transducers

phase set of voltages are measured from the supply

400 transducer cards. The card is adjusted to read

peak. Transducer card used in the thesis is shown in Figure 5.17

. LEM LV25-400 voltage transducer cards

Signal Conditioner/Interface Board

The voltage measurement is achieved using transducers

voltages are measured using voltage transducers. The transducers

value to 1.5 Vpeak sinusoidal signals. The signal conditioning card is

offset to the transducer outputs and bufferin

this way, the analog input signals are increased to the 0-3Vpk level


3.3 V amplitudes. DSP outputs must be amplified from 0

5 V low and high levels which are required value for the input of IGBT driver.

6 V diode voltage drop is used to increase the output voltage level to 3

permissible by the IGBT driver cards.

UNIFIED POWER QUALITY CONDITIONER Ahmet TEKE

supply side by using

400 transducer cards. The card is adjusted to read 220 Vrms and

is shown in Figure 5.17.

The voltage measurement is achieved using transducers circuit and offset

voltages are measured using voltage transducers. The transducers

The signal conditioning card is

offset to the transducer outputs and buffering DSP outputs. By

level. DSP takes the


DSP outputs must be amplified from 0-3.3 V to 0-

5 V low and high levels which are required value for the input of IGBT driver. The

6 V diode voltage drop is used to increase the output voltage level to 3.9 V that is


94

The circuit diagram of input section of signal conditioning card is shown in

Figure 5.18. The output of each voltage transducer is connected to the input section

of signal conditioning card as can been seen from the left side in Figure 5.18. Voltage

transducers output a current proportional to voltage applied to its primary.

Figure 5.18. Picture of signal conditioner/interface board

5.4.4. H-Bridge PWM Inverters

The circuit diagram of a single-phase H bridge inverter is given in Figure

5.19. Semikron SKM75GB123D IGBT modules are used to construct the H bridge

inverters. Each IGBT module consists of two IGBTs connected in top bottom

configuration. The inverters are fed from a 270VDC supply and give190 VAC output at

maximum modulation index. These voltages are filtered and injected to the lines

through injection transformers. The three-phase H-bridge inverters used in the thesis

are shown in Figure 5.19. Each of the IGBT drivers drives two IGBTs on the same

leg of the inverter as shown in Figure 5.19.


95

Figure 5.19. Three base VSI with IBGT modules and IGBT driver boards

5.4.5. Passive LC Output Filter

Lf= 10mH and Cf= 18µF are chosen. The nominal values of inductor and

capacitor are 11A/350 V and 6A/400V, respectively. The designed LC filter is shown

in Figure 5.20.

IGBT module

Heat sink

IGBT driver Fan

DC link

Gate signals


96

Figure 5.20. PassiveLC filters for three-phases of DVR

5.4.6. Injection Transformer

The output of the LC filter is given to the load using a transformer rated at

440:88 Vrms (turns ratio 5:1). 1 kVA single-phase injection transformers are shown in

Figure 5.21.

Inductor of LC filter

Capacitor of LC filter


97

Figure 5.21. Single-phase injection transformers

5.5. Practical Recommendations for Experimental Study

The following recommendations and suggestions can save time and money

during experimental studies.

i. Floating point DSP should be used in the experimental study because it has

the following advantages (Cuma, 2010):

Many algorithms used in control applications see a performance boost

from native floating-point. These algorithms such as square root, division, sine,

cosine, FFT have a floating point nature.

Coding is simplified as one can easily use float data type and use it in

control algorithms.

The scaling and saturation burden seen in fixed point is removed.

The floating point unit of F28335 follows the IEEE 754 format for

single precision floating point math.

Injection transformer

Primary Secondary

Phase_A

Phase_B

Phase_C

_


98

ii. DSP cables should be shielded to reduce their sensitivity to EMI caused

by opening and closing the power switches.

iii. IGBT snubber circuits should be used to prevent the creation of large

over-voltage due to di/dt.

iv. The length of the cable between DC link capacitor and IGBT inverter

should be minimum to reduce the creation of large over-voltage due to di/dt. If

available a laminated busbur should be used.

v. Low noise and high precision operational amplifier should be used in

measurement, signal conditioning and protection boards.

vi. The supplies of measurement signal conditioning and protection boards

should be fed from an isolation transformer.

vii. Shielded twisted pair cable should be used to eliminate inductive and

capacitive coupling.

viii. Accurate and fast measurements of voltage and current are key point for

correct operation and control. Measurement devices (current transformers, current

transducers and voltage transducer) with high accuracy, fast response time and low

power consumption should be used in the experimental studies.

ix. Intelligent power modules that integrate power devices, drivers and

protection circuitry in an ultra compact package provide compact, high precise, low

noise and high performance solution. They satisfy user needs for higher frequency

operation to provide a noiseless inverter.

x. DC power supply of DVR should generate output voltage with low noise,

low ripple, excellent load and line regulation. It should present advanced protection

capabilities.

xi. Circuit protection devices such as circuit breakers, fuses and residual

current protection switch should be properly selected to automatically limit or cut off

the flow of electricity when a ground fault, overload or short circuit occur in the

wiring system. Very fast current limiting fuses should be used to limit both the

magnitude and duration of current flow under short circuit conditions.

xii. Grounding is very important. Improper grounding can be the source of

errors, noise and a lot of trouble.


99

5.6. Summary

This section contains step-by-step design procedures for UPQC and OPEN

UPQC consisting of both shunt (APF) and series (DVR) compensators. The

important criterion for design process is to satisfy the standard limits for PQ. The

power circuit of APF consists of inverter circuit, DC capacitor and passive filters.

The design procedures and rating selections of APF components are mathematically

analyzed. The power circuit of DVR consists of inverter circuit, DC energy storage,

passive filter and injection transformer. The design procedures and rating selections

of DVR components are mathematically analyzed. Practical recommendations and

suggestions for experimental study are presented in order to minimize the time and

financial losses.

The next chapter presents the extensive simulation cases to test the

performance of proposed both proposed UPQC and OPEN UPQC using

PSCAD/EMTDC.


100

6. SIMULATION STUDY OF UPQC TOPOLOGIES Ahmet TEKE

101

6. SIMULATION STUDY OF UPQC TOPOLOGIES

In this section, the reference current/voltage extraction capabilities of

APF/DVR under unbalanced and distorted supply conditions are presented using

PSCAD/EMTDC program. Several case studies are presented to test the overall

performance of both proposed UPQC and OPEN UPQC. The control algorithms are

the same for both proposed UPQC and OPEN UPQC. UPQC uses common DC link

for APF and DVR. OPEN UPQC uses two separate energy storage devices for APF

and DVR. The data of simulation parameters are summarized in Table 6.1.

Table 6.1. Data of the simulated UPQC system SYSTEM Supply voltage Phase_A: 126.26Vrms, 2.39%THD

Phase_B: 131.96Vrms, 2.56%THD Phase_C: 125.49Vrms, 2.72%THD

System frequency 50 Hz ACTIVE POWER FILTER Smoothing inductor Phase_A: 19.41 mH, Phase_B: 20.04 mH,

Phase_C: 19.49 mH Choke reactor Phase_A: 6.14 mH, Phase_B: 6.07 mH,

Phase_C: 6.21 mH DC link capacitor and voltage 2200µF, 375VDC Sampling time 25 µs DYNAMIC VOLTAGE RESTORER Switching frequency 10 kHz Inverter filter Capacitance: 18 µF, 400 V

Phase_A: 8.42 mH, Phase_B: 8.28 mH, Phase_C: 8.1 mH

Transformer Primary/Secondary: 440/88Vrms, 1 kVA DC supply 270 VDC Sampling time 20 µs RESISTIVE LOAD Three-phase resistive load R=90Ω/6500 W, Two resistors in series


102

6.1. Controller of Proposed APF

The simulation model of APF control system is shown in Figure 6.1. The

control system is consisting of reference current generation, hysteresis current

control and firing pulse generation blocks. The details and operating principles of

proposed APF control system are mentioned in Section 4.2.2.

Figure 6.1. Simulation model of proposed APF control system

Voltage /current measurements

and Alpha-Beta transform

VrAIrA

IrB

IrC

Vaph

Iaph

Ibta

B

+D +

F

+

B+

D +

F

+

*0. 8165 *

-0 . 4082*

-0 . 4082*0

*0. 7071 *

-0 . 7071

Pinst

* Iaph

Vaph

* Ibta

Vbta

B+

F +

*Iaph

Ibta

B-

F +

Vbta

*

Vaph

QinstB-

F + Qinstdc

Vcappi

B

+

F -

q _in st

p_inst Calculation of

−

p ~p − q ~q

*

*

B+

F -

G -

Vaph

Pinst

Vbta

Qinst

*

*

B+

F +

G +

Pinst

Qinst

Vbta

Vaph

N

D

N/D

N

D

N/D

a2pb2

a2pb2Vaph

*

Vaph B

+

F +

*Vbta

Vbta

a 2pb 2GR

*Vbta

*Vaph

* GR

IcRef

IbRef

IaRef

* GR

* GR

B+

D +

B

+D +

*0. 8165

D +

*0

*- 0 . 4082

*0. 7071*

- 0 . 4082 *

- 0 . 7071

0. 0

0. 0Calculation of

reference signals

e-sT

*

1

Vbta

D+

F -

err_A

IaRef

err _A

G1

G4

Ifa

D+

F -

err _BIbRef

err_B

G3

G6

Ifb

D+

F -

err _CIcRef

err _ C

G5

G2

Ifc Gate signal generation


103

6.2. Controller of Proposed DVR

PSCAD/EMTDC models of DVR control system for reference signal

generation and sag/swell detection are shown in Figures 6.2a and 6.2b.

Figure 6.2a. PSCAD/EMTDC model of DVR control system: Reference signal

generation

1 2 3 4

1 2 3 4

1 2 3 4

eA

eB

eC

Pa

Pb

Pc

Comparator

Vapu+-

* K 2 ++

++

Sin

*

*yA

Pi

A

Pi *100

Sin

1sT

1sT

tetaA

Vbpu+-

* ++

++

Sin

*

* yB

Pi*-0 . 5

B

Pi *100

Sin

1sT

1sT

Vcpu +-* +

+

++

Sin

*

* yC

Pi* -0.5

C

Pi *100

Sin

1sT

1 sT

tetaB

tetaC

+-xA yA eA

+-xByBeB

+-xCyCeC

K 1

K2K1

K 2K 1

K3

K3

K 3

K4

K4

K 4

Error calculation for Phase_A

Error calculation for Phase_B

Error calculation for Phase_C

PWM signal generation



E- PLL: Amplitude and phase angle extraction for Phase_A

E-PLL: Amplitude and phase angle extraction for Phase_B

E-PLL: Amplitude and phase angle extraction for Phase_C

*-0. 5

Comparator

Comparator


104

Figure 6.2b. PSCAD/EMTDC model of DVR control system: Sag/swell detection

6.3. Simulation Verification of Proposed UPQC

In this section, the reference current/voltage extraction capabilities of

APF/DVR under distorted supply conditions and the minimum energy injection

capability of proposed DVR are presented. Three case studies are presented to test

the overall performance of proposed UPQC. PSCAD/EMTDC diagram of proposed

UPQC system is shown in Figure 6.3.


105

Controller of DVR

0.00607 [H]

0.00614 [H]

0.00621 [H]

4 5 [o hm ]

D D

D D

D D

IrA

IrB

IrC

VrB

VrC

V cap

1 3 5

4 6 2

G1 G3 G5

G4 G6 G2

0.01941[H]

Ifa

Ifb

Ifc

0.02[H]

0.01949 [H]

Va

Vb Vc

2200 [uF]

VrA

R=0R=0R=0

R=0R=0R=0

R=0R=0R=0

Vap

R=0V f

fr

R=0V f

frVbp

R=0V f

frVcp

VdvrA

VdvrB

VdvrC

8 .2 8 [mH ]

8 .4 2 [mH ]

18 [uF]

18 [uF]

8 .1 [mH ]

#1#2

#1#2

#1#2

g2 g4

g3

1

g1

4

23

g6 g8

g7

1

g5

4

23

g10 g12

g11

1

g9

4

23

Controller of APF

R=0R=0R=0

R=0R=0R=0

R=0R=0R=0

Vaa

R=0V f

fr

R=0V f

frVba

R=0V f

frVca

BRK_Ap

BRK_Bp

BRK_Cp

BRK_Aa

BRK_Ba

BRK_Ca

18 [uF]

DYNAMIC VOLTAGE

RESTORER

ACTIVE POWER FILTER

SUPPLY_1

SUPPLY_2

6 BRIDGE

RECTIFIER

CHOKE

REACTOR

SMOOTHING

INDUCTOR DC

CAPACITOR

LC FILTER

INJECTION

TRANSFORMER

H BRIDGE

INVERTER

3 PHASE

INVERTER

HARMONIC

COMPONENTS

Figure 6.3. PSCAD/EMTDC model of UPQC


106

6.3.1. Simulation Results for Standby Operation of DVR

During standby operation of DVR, two lower IGBTs of each phase H-bridge

inverter remain turned on while the two upper IGBTs remain turned off. Each H-

bridge inverter is controlled independently by using an independent sag detection

method for each phase as mentioned in Section 4.2.3. With this method, minimum

energy is injected and switching losses are minimized. The sag detection signals of

each phase of H-bridge inverters are shown in Figure 6.4. In this case, single-phase

25% voltage sag is occurred on phase_A of supply voltage at 0.8 s, so the amplitude

of phase_B and phase_C of supply voltage are at their nominal value. The inverter of

phase_A is in operating mode because the sag detection signal enables the gate signal

generation. But, the inverters of phase_B and phase_C are in stand-by mode.

Figure 6.4. Sag detection signals for H-bridge inverters of supply voltages


107

6.3.2. Simulation Results for Reference Current Extraction

The waveforms of load current, reference current using traditional IRPT

theory and reference current using improved IRPT theory are shown in Figure 6.5

when the supply voltage is unbalanced and harmonic distorted as stated in Table 6.1.

Figure 6.5. The load current and generated reference currents

Traditional IRPT theory fails to generate the required compensation signal

when the load voltage is distorted and unbalanced. This disadvantage can be

eliminated using improved IRPT theory in which the load voltage is filtered using all

pass filter and the alpha-beta components are virtually generated as explained in

Section 4.1.2.

6.3.3. Simulation Results for Voltage Sag Compensation and Current Harmonic

Elimination with Proposed UPQC

In this section, PSCAD/EMTDC simulation results are presented to show the

performance of UPQC for sag mitigation and current harmonic elimination. There


108

are four possible types of faults that can occur in a typical power distribution system.

The probabilities of prevalence of the various types of faults are as follows

(Kirawanich et al., 2003):

1- Single line-to-ground faults: 70%

2- Line-to-line faults: 15%

3- Double line-to-ground faults: 10%

4- Three-phase faults: 5%

The case studies are performed taking the findings of (Kirawanich et al.,

2003) into consideration. Three cases are comprehensively analyzed: Case 1) No

voltage sag and current harmonic elimination, Case 2) 25% single-phase voltage sag

and current harmonic elimination, Case 3) 20% double phase voltage sag and current

harmonic elimination.

6.3.3.1. Case Study1: No Voltage Sag, Current Harmonic Elimination

At stand-by operation (no-fault condition), DVR injects no voltage to the

system (DVR is in OFF-mode). The supply voltages and load voltages are in phase

with each other (blue: phase_A, green: phase_B, red: phase_C). The waveform of

load voltage contains more harmonic component than the supply voltage because

current harmonic causes a voltage drop on a series transformer as shown in Figure

6.6 (VlA=VsA-VinjA).


109

Figure 6.6. The waveforms of supply and load voltages for Case 1

RMS trends of supply and load voltages are shown in Figure 6.7. The trends

are identical to each other.

Figure 6.7. RMS trends of supply and load voltages


110

APF is on line and eliminates the load current harmonics as shown in Figure

6.8. At stand-by operation (no-fault condition), average load voltage THD is 2.22%

and supply current THD is 4.09%.

Figure 6.8. Waveforms of supply voltages and supply currents during Case 1

The load voltage is identical to supply voltage as shown in the Figure 6.9.

The voltage waveforms indicate the supply (VsA), injected (Vinj) and load (VlA)

voltages of Phase_A, respectively. The current waveforms indicate the supply (IsA),

injected (IinjA) and load (IlA) currents of Phase_A, respectively. DC link capacitor

voltage is almost kept constant during voltage sag.


111


supply/injected/load currents during Case 1

The instantaneous THD contents of supply and filtered currents for Phase_A

are presented in Table 6.2. The amplitudes of low order harmonics (5th, 7th, 11thand

13th) are high in load current. APF injects the required compensation current to the

system and the amplitudes of low order harmonics are minimized in the supply

current.

Table 6.2. THD contents of load and supply currents of Phase_A for Case 1

THD content of Phase_A load current

THD content of Phase_A supply current

Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.01

1 100 18 0.11

2 0.04 19 0.86

2 0.1 19 0.34

3 1.57 20 0.01

3 1.19 20 0.08

4 0.08 21 0.03

4 0.22 21 0.08

5 22.19 22 0.01

5 3.47 22 0.06

6 0.02 23 0.97

6 0.32 23 0.29

7 8.1 24 0.01

7 1.12 24 0.08

8 0.02 25 0.52

8 0.13 25 0.24


112

9 0.52 26 0.01

9 0.12 26 0.11

10 0.02 27 0.07

10 0.19 27 0.17

11 5.46 28 0.01

11 0.73 28 0.11

12 0.02 29 0.47

12 0.19 29 0.22

13 2.62 30 0.01

13 0.55 30 0.06

14 0.01 31 0.41

14 0.07 31 0.07

15 0.05

15 0.01

16 0.01 THD(%)=24.54

16 0.05 THD(%)=4.09

17 1.7

17 0.76

6.3.3.2. Case Study2: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination

DVR comes into ON-mode and injects missing voltage to the system during

the voltage sag. 25% single-phase voltage sag occurs on phase_A of supply voltage

but the phase_A of load voltage is not affected by voltage sag with the help of DVR.

The supply voltages and load voltages are in phase with each other as shown in

Figure 6.10.



113

RMS trends of supply and load voltages are shown in Figure 6.11. RMS value

of phase_A load voltage is maintained constant at its nominal value during voltage

sag.


The waveform results for 25% sag on phase_A of supply voltage for 3s

duration are shown in Figure 6.12. The phase_A load current so its load voltage is

not affected during the voltage sag as shown in Figure 6.12. The waveform of load

voltage is identical with load current waveforms because the load is purely resistive.

The phase_A load current is not affected when the voltage sag occurs on Phase_A.


114

Figure 6.12. Waveforms of supply voltages and currents during Case 2

DVR injects the missing voltage to the system in series and APF injects the

compensation current to the system in shunt as shown in Figure 6.13.




115

THD contents of supply and filtered currents for Phase_A are presented in

Table 6.3. The amplitudes of characteristic harmonics (5th, 7th, 11thand 13th) are high

in load current. APF injects the required compensation current to the system and the

amplitudes of characteristic harmonics are minimized in the supply current.




Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.2

1 100 18 0.04

2 1.02 19 0.83

2 1.63 19 0.19

3 1.27 20 0.02

3 2.53 20 0.05

4 2.1 21 0.12

4 1.47 21 0.16

5 22.68 22 0.07

5 2.7 22 0.08

6 0.24 23 1.01

6 0.57 23 0.11

7 7.69 24 0.13

7 1.61 24 0.04

8 0.21 25 0.48

8 0.23 25 0.21

9 0.46 26 0.02

9 0.59 26 0.05

10 0.51 27 0.09

10 0.26 27 0.09

11 5.51 28 0.13

11 1.03 28 0.04

12 0.31 29 0.5

12 0.04 29 0.07

13 2.5 30 0.14

13 0.76 30 0.09

14 0.09 31 0.38

14 0.19 31 0.09

15 0.15

15 0.19

16 0.26 THD(%) 24.94

16 0.1 THD(%) 4.93

17 1.66

17 0.68 At the starting of sag, the load voltage can be affected due to instantaneous

reduction of the voltage reference, the capacitor voltage and delay originated from

sag detection time. The waveforms of supply voltages and load currents are shown in

Figure 6.14. When the sag occurs, only the related H-bridge inverter of DVR starts to

operate. The voltage sag occurs only on phase_A of supply voltage. The phase_A of

load current (so its voltage) does not affected by voltage sag.


116

Figure 6.14. Three-phase voltage and current waveforms at starting of single-

phase25% voltage sag for Case 2

At the ending of sag, the load voltage can be affected due to instantaneous

reduction of the voltage reference and delay originated from sag detection time. As

shown in the Figure 6.15, DVR comes into standby operation whenever the sag ends.

THD of the load voltages is always kept below the IEEE voltage harmonic limits

(IEEE Std 519, 1995).


117

Figure 6.15. Three-phase voltage and current waveforms at ending of single-phase 25% voltage sag for Case 2

6.3.3.3. Case Study3: 20% Double Phase Voltage Sag, Current Harmonic

Elimination

DVR is in ON-mode and injects the missing voltage to the system during the

voltage sag as shown in Figure 6.16. The supply voltage and load voltage are in

phase with each other. 20% voltage sag occurs on phase_A and phase_B of supply

voltage but the phase_A and phase_B of load voltage are not affected by voltage sag

with the help of DVR.


RMS trends of supply and load voltages are shown in Figure 6.17. RMS

values of phase_A and phase_B load voltages are maintained constant at its nominal

value during voltage sag.


118


The waveform results for 20% double phase sag on phase_A and phase_B of

supply voltage for 3 s duration are shown in Figure 6.18. Phase_A and phase_B load

currents so their load voltages are not affected by voltage sag. The load voltage

waveform is identical with load current waveforms because the load is purely

resistive. Phase_A and Phase_B load currents are not affected when a voltage sag

occurs on Phase_A and Phase_B of supply voltage.


119

Figure 6.18. The waveforms of supply voltages and currents during Case 3


filter current to the system in shunt as shown in Figure 6.19. DC link capacitor



120

Figure 6.19. Waveforms of Phase_A supply/injected/load voltages; supply/injected/load currents during Case 3


Table 6.4.

Table 6.4. THD contents of supply and filtered currents of Phase_A for Case 3



Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.2

1 100 18 0.1

2 0.64 19 0.88

2 0.95 19 0.42

3 1.08 20 0.14

3 1.44 20 0.1

4 1.02 21 0.13

4 0.55 21 0.12

5 22.8 22 0.23

5 2.37 22 0.13

6 0.82 23 1.03

6 1.1 23 0.11

7 7.69 24 0.08

7 1.12 24 0.06

8 0.73 25 0.48

8 0.24 25 0.13

9 0.36 26 0.1

9 0.11 26 0.03

10 0.54 27 0.14

10 0.2 27 0.05

11 5.59 28 0.19

11 1.11 28 0.13

12 0.6 29 0.55

12 0.21 29 0.02

13 2.53 30 0.09

13 0.84 30 0.09

14 0.4 31 0.41

14 0.15 31 0.05

15 0.15

15 0.07

16 0.38 THD(%)=24.77

16 0.05 THD(%)=3.75

17 1.74

17 0.6 At the starting of sag, the load voltage is affected due to instantaneous


shown in Figure 6.20, when the sag occurs, only the related H-bridge inverters of

DVR start to operate. As also shown in the current waveforms, the sag occurs on

phase_ A and phase_B. The phase_ A and phase_B load currents so their voltages are

not affected by sag.


121

Figure 6.20. Three-phase voltage and current waveforms at starting of double phase 20% voltage sag for Case 3

At the ending of sag, the load voltage is affected due to instantaneous


shown in the Figure 6.21, DVR comes into standby operation whenever the sag ends.


(IEEE Std 519, 1995).


122

Figure 6.21. Three-phase voltage and current waveforms at ending of double phase

20% voltage sag for Case 3

6.4. Simulation Verification of Proposed OPEN UPQC

In this section, PSCAD/EMTDC simulation results are presented to show the

performance of OPEN UPQC for sag mitigation and current harmonic elimination.

Three cases are comprehensively analyzed: Case 1) No voltage sag and current

harmonic elimination, Case 2) 25% single-phase voltage sag and current harmonic

elimination, Case 3) 20% double phase voltage sag and current harmonic

elimination. PSCAD/EMTDC diagram of proposed OPEN UPQC system is shown in

Figure 6.22.


123

Controller of DVR

0.00607 [H]

0.00614 [H]

0.00621 [H]

4 5 [o hm ]

D D

D D

D D

IrA IrB IrC

VrB

VrC

V c a p

1 3 5

4 6 2

G 1 G3 G5

G4 G6 G2

0.01941[H]

Ifa

Ifb

Ifc

0.02[H]

0.01949 [H]

Va Vb Vc

R=0

2200 [uF]

VrA

R=0R=0R=0

R=0R=0R=0

R=0R=0R=0

Vap

R=0V f

fr

R=0V f

frVbp

R=0V f

frVcp

VdvrA

VdvrB

VdvrC

8 .2 8 [m H ]

8 .4 2 [m H ]

18 [uF]

18 [uF]

8 .1 [m H ]

#1#2

#1#2

#1#2

g2 g4

g3

1

g1

4

23

g6 g8

g7

1

g5

4

23

g10 g12

g11

1

g9

4

23

Controller of APF

R=0R=0R=0

R=0R=0R=0

R=0R=0R=0

Vaa

R=0V f

fr

R=0V f

frVba

R=0V f

frVca

BRK_Ap

BRK_Bp

BRK_Cp

BRK_Aa

BRK_Ba

BRK_Ca

18 [uF]

DYNAMIC VOLTAGE

RESTORER

ACTIVE POWER FILTER

SUPPLY_1

SUPPLY_2

6 BRIDGE

RECTIFIER

CHOKE

REACTOR

SMOOTHING

INDUCTOR DC

CAPACITOR

DC LINK

LC FILTER

INJECTION

TRANSFORMER

H BRIDGE

INVERTER

3 PHASE

INVERTER

HARMONIC

COMPONENTS

Figure 6.22. PSCAD/EMTDC model of OPEN UPQC


124

6.4.1. Case Study4: No Voltage Sag, Current Harmonic Elimination

DVR is in OFF-mode and injects any voltage to the system when no voltage

sags occur on supply voltage. The supply voltages and load voltages are in phase

with each other (blue: phase_A, green: phase_B, red: phase_C) as shown in Figure

6.23 (VlA=VsA-VinjA).


RMS trends of supply and load voltages are shown in Figure 6.24. The rms

trends are identical to each other.


125


APF is on line and eliminates the load current harmonics as shown in Figure

6.25. At stand-by operation (no-fault condition), average load voltage THD is 2.75%

and supply current THD is 4.05%.



126

The load voltage waveform is identical to supply voltage waveform as shown

in Figure 6.26.



The instantaneous THD contents of supply and filtered currents for Phase_A

are presented in Table 6.5. The amplitudes of low order harmonics (5th, 7th, 11th and

13th) are high in load current. APF injects the required compensation current to the

system and the amplitudes of low order harmonics are minimized in the supply

current.

Table 6.5. THD contents of load and supply currents of Phase_A for Case 4 THD content of Phase_A

load current


Order (%) Order (%) Order (%) Order (%) 1 100 18 0.01 1 100 18 0.06 2 0.03 19 0.89 2 0.14 19 0.46 3 1.53 20 0.01 3 1.06 20 0.06 4 0.07 21 0.03 4 0.07 21 0.09 5 22.21 22 0.01 5 2.41 22 0.09 6 0.03 23 0.95 6 0.16 23 0.19 7 7.97 24 0.01 7 2.22 24 0.06


127

8 0.02 25 0.52 8 0.07 25 0.08 9 0.53 26 0.01 9 0.23 26 0.02 10 0.01 27 0.10 10 0.07 27 0.04 11 5.41 28 0.01 11 1.49 28 0.02 12 0.02 29 0.54 12 0.02 29 0.14 13 2.60 30 0.01 13 1.08 30 0.03 14 0.01 31 0.41 14 0.01 31 0.03 15 0.05

15 0.23

16 0.01 THD (%)24.5

16 0.02 THD (%)4.05

17 1.59 17 0.85

6.4.2. Case Study5: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination

25% single voltage sag occurs on phase_A of supply voltage but the phase_A

of load voltage is not affected by voltage sag with the help of DVR. The supply

voltages and load voltages are in phase with each other as shown in Figure 6.27.



128


value of phase_A load voltage is maintained constant at its nominal value during

voltage sag.


The waveform results for 25% sag on phase_ A of supply voltage for 3 s

duration are shown in Figure 6.29. The phase_A load current so its load voltage is

not affected during the voltage sag as shown in Figure 6.29. The load voltage

waveform is identical with load current waveforms because the load is purely

resistive.


129



compensation current to the system in shunt as given in Figure 6.30.




Table 6.6. The amplitudes of characteristic harmonics (5th, 7th, 11th and 13th) are high

in the load current. APF injects the required compensation current to the system and

the amplitudes of characteristic harmonics are minimized in the supply current.


130




Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.23

1 100 18 0.06

2 1.18 19 1.04

2 0.92 19 0.45

3 0.84 20 0.22

3 0.47 20 0.06

4 1.86 21 0.38

4 0.62 21 0.02

5 22.82 22 0.1

5 1.94 22 0.13

6 0.46 23 1.02

6 0.1 23 0.12

7 7.52 24 0.14

7 2.48 24 0.03

8 0.93 25 0.57

8 0.4 25 0.08

9 0.58 26 0.15

9 0.34 26 0.08

10 0.6 27 0.39

10 0.51 27 0.01

11 5.6 28 0.05

11 1.7 28 0.08

12 0.28 29 0.56

12 0.12 29 0.19

13 2.63 30 0.09

13 1.23 30 0.08

14 0.44 31 0.57

14 0.2 31 0.01

15 0.42

15 0.13

16 0.36 THD(%)25.09

16 0.1 THD(%)4.14

17 1.67


reduction of the voltage reference and delay originated from sag detection time. The

waveforms of supply voltages and load currents are shown in Figure 6.31. When the

sag occurs, only the related H-bridge inverter of DVR starts to operate as shown in

Figure 6.31.


131

Figure 6.31. Three-phase voltage and current waveforms at starting of single-phase25% voltage sag for Case 5


reduction of the voltage reference and delay originated from sag detection time. DVR

comes into standby operation whenever the sag ends as shown in Figure 6.32. THD

of the load voltages is always kept below the IEEE voltage harmonic limits (IEEE

Std 519, 1995).


132

Figure 6.32. Three-phase voltage and current waveforms at ending of single-phase


6.4.3. Case Study6: 20% Double Phase Voltage Sag, Current Harmonic

Elimination

DVR comes into ON-mode and injects the missing voltage to the system

during the voltage sag as shown in Figure 6.33. The supply voltage and load voltage

are in phase with each other. 20% voltage sag occurs on phase_A and phase_B of

supply voltages but the phase_A and phase_B of load voltages are not affected by

voltage sag with the help of DVR.


133



values of phase_A and phase_B load voltages are maintained constant at its nominal

value during voltage sag.



134


supply voltage for 3 s duration are shown in Figure 6.35. The phase_ A and phase_B

load currents so their load voltages are not affected by voltage sagas shown in Figure

6.35. The load voltage waveform is identical with load current waveforms because

the load is purely resistive. Phase_A and Phase_B load currents are not affected when

voltage sag occurs on Phase_A and Phase_B of supply voltage.


APF injects the filter current to the system in shunt and DVR injects the

missing voltage to the system in series as shown in Figure 6.36. DC link capacitor



135




Table 6.7.




Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.15

1 100 18 0.05

2 0.49 19 0.89

2 1.3 19 0.37

3 1.46 20 0.05

3 0.75 20 0.03

4 1.08 21 0.17

4 0.34 21 0.09

5 22.49 22 0.03

5 1.97 22 0.04

6 0.47 23 1.03

6 0.15 23 0.08

7 7.88 24 0.09

7 2.68 24 0.05

8 0.44 25 0.5

8 0.26 25 0.07

9 0.32 26 0.02

9 0.31 26 0.09

10 0.22 27 0.16

10 0.11 27 0.05

11 5.47 28 0.02

11 1.74 28 0.02

12 0.13 29 0.5

12 0.15 29 0.18


136

13 2.56 30 0.04

13 1.28 30 0.11

14 0.11 31 0.4

14 0.18 31 0.08

15 0.23

15 0.19

16 0.11 THD(%) 24.77

16 0.01 THD(%) 4.37

17 1.67


reduction of the voltage reference and delay originated from sag detection time as

shown in Figure 6.37. The phase_ A and phase_B load currents so their voltages are

not affected by sag.

Figure 6.37. Three-phase voltage and current waveforms at starting of double phase 20% voltage sag for Case 6

At the ending of sag, the load voltage is affected due to instantaneous


comes into standby operation whenever the sag ends as shown in Figure 6.38. THD

of the load voltages is always kept below the IEEE voltage harmonic limits (IEEE

Std 519, 1995).


137



6.5. Summary

This chapter demonstrates the power conditioning capabilities of UPQC and

OPEN UPQC in PSCAD/EMTDC. The simulation results are presented to show the

performance of UPQC topologies for sag mitigation and current harmonic

elimination. Three possible types of faults that can occur in a typical power

distribution system are comprehensively analyzed:

Case 1) No voltage sag and current harmonic elimination,

Case 2) 25% single-phase voltage sag and current harmonic elimination,

Case 3) 20% double phase voltage sag and current harmonic elimination.

APF eliminates the load current harmonics and keeps the supply current

almost sinusoidal. DVR quickly senses the voltage sag and inject the missing voltage

to the system keeping the magnitude of the load voltage almost constant. UPQC and

OPEN UPQC perform superior performance to mitigate PQ problems during the

various types of faults.

The performance of OPEN UPQC is better than that of UPQC during start

and end points of voltage sag since OPEN UPQC is fed from two separate DC


138

energy supplies. In UPQC, the active power required by series inverter is supplied

from DC capacitor during voltage sag. This can cause a voltage drop and fluctuation

of DC capacitor voltage that causes small anomalies during the start and end of

voltage sag.

The next chapter presents the extensive experimental results to show the

performance of proposed DSP based 6 kVA, 220 Vl-l UPQC and DSP based 6 kVA,

220 Vl-l OPEN UPQC. The experimental results are compared with the simulation

results.

7. EXPERIMENTAL VERIFICATION OF UPQC TOPOLOGIES Ahmet TEKE

139

7. EXPERIMENTAL VERIFICATION OF UPQC TOPOLOGIES

In this section, the minimum energy injection capability of proposed DVR

and the reference current/voltage extraction capabilities of proposed APF/DVR under

distorted supply conditions are presented as experimentally. Six case studies are

presented to test the overall performance of proposed UPQC and OPEN UPQC. The

data of experimental setup parameters are summarized in Table 7.1. The

experimental results are taken from the project “Modeling and Implementation of

Custom Power Park” which is supported by Scientific and Technological Research

Council of Turkey with project number of 106E188.

Table 7.1. Data of the experimental UPQC systems SYSTEM Supply voltage (Phase to neutral)

Phase_ A: 126.26Vrms, 2.39%THD Phase_ B: 131.96Vrms, 2.56%THD Phase_ C: 125.49Vrms, 2.72%THD

System frequency 50 Hz ACTIVE POWER FILTER Main circuit scheme Voltage source inverter scheme DSP controller ezDSP TMS320F28335 IGBT inverter Semikron, SKM 75GB123D, 1200V, 50A IGBT driver Semikron, SKHI 22BH4 R Smoothing inductor Phase_A: 19.41 mH, Phase_B: 20.04 mH,

Phase_C: 19.49 mH Choke reactor Phase_A: 6.14 mH, Phase_B: 6.07 mH,

Phase_C: 6.21 mH Sampling time 25 µs DC link capacitor and voltage 2200µF, 375VDC Voltage measurement LV25-P transducer, LV25-400, LV25-800, LEM Current measurement CTF-5A current transformer DYNAMIC VOLTAGE RESTORER Main circuit scheme Voltage source inverter scheme DSP controller ezDSP TMS320F2812 IGBT Inverter Semikron, SKM 75GB123D, 1200 V, 50 A Switching frequency 10 kHz IGBT driver Semikron, SKHI 22BH4 R Inverter filter Capacitor: 18 µF, 400 V


140

Inductor: Phase_A: 8.42 mH, Phase_B: 8.28mH, Phase_C: 8.1 mH

Transformer Primary/Secondary: 440/88Vrms, 2 kVA DC supply 270 VDC Voltage measurements LV25-P transducer, LV25-400, LEM Sampling time 20 µs SAG/SWELL GENERATOR Variable voltage supplies 18.75 kVA, 25 A, 3x380 V input, 3x(0-435)Vrms

variable output Thyristor module 1200 V, 40 A Semikron SKKT 42/12E Thyristor driver Semikron APTT-841M Timer relay 220 V, single-phase AC time relay, 1 NO and 1

NC contacts, minimum 50 ms range, 3RP 1505-1BP30

3-PHASE BRIDGE RECTIFIER AND LOAD Three-phase rectifier Semikron SKD62/16, 1600V, 60A Three-phase resistive load R=45Ω/6500 W, Two 90Ω resistors in series Cooling Forced air WAVEFORM MEASUREMENTS Power quality analyzer Hioki 3196 Data logger Fluke 1760 PQ recorder Digital oscilloscope Tektronix TDS 2014B

The control algorithms of APF are implemented with TMS320F28335 DSP

using C and assembly programming languages. The control algorithms of DVR are

implemented with TMS320F2812 DSP using C and assembly programming

languages. The software codes of controllers used in APF and DVR were presented

in (Cuma, 2010).

7.1. Experimental Results for Standby Operation of DVR

Two lower IGBTs of each phase H-bridge inverter remain turned on while the

two upper IGBTs remain turned off during standby operation of DVR. Each H-bridge

inverter is controlled independently by using an independent sag detection method

for each phase as mentioned in Section 4.2.3. With this method, minimum energy is


141

injected and switching losses are reduced. The firing signals of Phase_A and

phase_B for H-bridge inverters are demonstrated in Figure 7.1. In this case, sag is

occurred in phase_A of supply voltage, but the amplitude of phase_B of supply

voltage is in its nominal value. Signal_1 and Signal_2 are for the left leg IGBTs of

phase_A and Signals 3 and 4 for the left leg IGBTs of phase_B. The inverter of

phase_A is in operating mode, but the inverter of phase_B is in standby mode.

Figure 7.1. PWM signals for H-bridge inverters of Phase_A and Phase_B

7.2. Experimental Results for Reference Current Extraction

The experimental results of the load current, reference current using

traditional IRPT theory and reference current using improved IRPT theory are

demonstrated in Figure 7.2 when the supply voltage is unbalanced and harmonic

distorted as stated in Table 7.1.


142

Figure 7.2. Reference currents using traditional and improved IRPT methods

As demonstrated in Figure 7.2, traditional IRPT theory fails to generate the

required compensation signal and provides unsatisfactorily performance when the

load voltage is distorted and unbalanced. This disadvantage can be eliminated using

improved IRPT theory in which the load voltage is filtered using all pass filter and

the alpha-beta components are virtually generated as explained in Section 4.1.2.


143

7.3. Experimental Results for Voltage Sag Compensation and Current

Harmonic Elimination with Proposed UPQC

In this section, the results of Hioki 3196 power quality analyzer are presented

to show the performance of UPQC for sag mitigation and current harmonic

elimination. Three cases are comprehensively analyzed:



Case 3) 20% double phase voltage sag and current harmonic elimination,

The experimental diagram of proposed UPQC system with measurement

points are demonstrated in Figure 7.3.

Figure 7.3. Experimental diagram of UPQC system with measurement points


At stand-by operation (no-fault condition), DVR is in OFF-mode and injects

no voltage to the system. The supply voltage and load voltage are in phase with each

other. RMS trends of supply and load voltages are demonstrated in Figure 7.4.


144


APF is in ON-mode and eliminates the load current harmonics as

demonstrated in Figure 7.5. At stand-by operation, average load voltage THD is

2.22% and supply current THD is 4.3%. Phase_A, phase_B and phase_C are

indicated as red (CH1), green (CH2) and blue (CH3), respectively.


The load voltage is identical to supply voltage as demonstrated in Figure 7.6.

The voltage waveforms of CH1, CH2 and CH3 indicate the supply, injected and load

voltages of Phase_A, respectively. The current waveforms of CH1, CH2 and CH3

indicate the supply, injected and load currents of Phase_A, respectively.


145




Table 7.2. The amplitudes of low order harmonics (5th, 7th, 11th and 13th) are high in

the load current. APF injects the required compensation current to the system and the

amplitudes of low order harmonics are minimized in the supply current.




Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.07

1 100 18 0.27

2 0.11 19 0.96

2 0.67 19 0.72

3 0.29 20 0.08

3 0.62 20 0.24

4 0.09 21 0.12

4 0.4 21 0.3

5 21.71 22 0.13

5 3.07 22 0.34

6 0.13 23 0.81

6 0.26 23 0.57

7 7.85 24 0.11

7 1.22 24 0.28

8 0.1 25 0.7

8 0.36 25 0.78

9 0.17 26 0.11

9 0.34 26 0.32

10 0.11 27 0.12

10 0.28 27 0.4

11 5.59 28 0.07

11 1.29 28 0.22


146

12 0.08 29 0.54

12 0.16 29 0.28

13 2.3 30 0.15

13 0.81 30 0.5

14 0.05 31 0.37

14 0.17 31 0.58

15 0.17

15 0.21

16 0.06 THD(%) 23.98

16 0.16 THD(%) 4.30

17 1.77

17 0.98 7.3.2. Case Study2: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination

When voltage sag on phase_A is detected, DVR starts to inject the missing

voltage to the system and keeps the load voltages at their 0.9-1.1 pu of nominal

voltages. The supply voltage and load voltage are in phase with each other. RMS

trends of supply and load voltages are demonstrated in Figure 7.7.


The waveform results for 25% sag on phase_A of supply voltage for 3 s

duration are demonstrated in Figure 7.8. The voltage waveforms of CH1 (red), CH2

(green) and CH3 (blue) indicate the phase_A, phase_B and phase_C supply voltages,

respectively. Similarly, the current waveforms of CH1, CH2 and CH3 indicate the

phase_A, phase_B and phase_C supply currents, respectively. The each division is

40V for voltage waveforms and 2.5A for current waveforms. The phase_A load


147

current so its load voltage is not affected by voltage sag as demonstrated in Figure

7.8. The load voltage waveform is identical with load current waveforms because the

load is purely resistive. The phase_A load current is not affected when a voltage sag

occurs on Phase_A.


The voltage waveforms of CH1, CH2 and CH3 indicate the supply voltage,

injected voltage and load voltage of Phase_A in Figure 7.9, respectively. The current

waveforms of CH1, CH2 and CH3 indicate the supply current, injected current and

load current of Phase_A, respectively.


148

Figure 7.9. Waveforms of Phase_A supply/injected/load voltages; supply/filter/load

currents during Case 2








Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.05

1 100 18 0.1

2 0.31 19 0.66

2 0.53 19 0.89

3 1.86 20 0.07

3 1.4 20 0.21

4 0.18 21 0.24

4 0.33 21 0.25

5 22.47 22 0.11

5 3.25 22 0.41

6 0.09 23 1.02

6 0.25 23 0.51

7 7.28 24 0.11

7 1.02 24 0.29

8 0.16 25 0.43

8 0.27 25 0.71

9 1.31 26 0.1

9 0.34 26 0.26

10 0.15 27 0.17

10 0.33 27 0.33

11 5.86 28 0.07

11 0.92 28 0.3


149

12 0.06 29 0.64

12 0.15 29 0.52

13 1.78 30 0.09

13 0.85 30 0.33

14 0.06 31 0.22

14 0.19 31 0.69

15 0.52

15 0.29

16 0.07 THD(%) 24.64

16 0.13 THD(%) 4.41

17 2.02



waveforms of supply voltages and load currents are demonstrated in Figure 7.10.

When the sag occurs, only the related H-bridge inverter of DVR starts to operate. As

also demonstrated in the current waveforms, the sag occurs only on phase_A and the

phase_A load current so its voltage do not affected by sag.

Figure 7.10. Three-phase voltage and current waveforms at starting of single-phase




comes into standby operation whenever the sag ends as demonstrated in Figure 7.11.


(IEEE Std 519, 1995).


150


25% voltage sag for Case 2 7.3.3. Case Study3: 20% Double Phase Voltage Sag, Current Harmonic

Elimination

At stand-by operation, DVR is in OFF-mode and injects no voltage to the

system. The supply voltage and load voltage are in phase with each other. RMS




151


supply voltage for 3 s duration are demonstrated in Figure 7.13. Each division is 40

V for voltage waveforms and 2.5 A for current waveforms. The phase_A load current

so its load voltage is not affected by voltage sag as demonstrated in the Figure 7.13.

The load voltage waveform is identical with load current waveforms because the

load is purely resistive. Phase_A and Phase_B load currents are not affected when a

voltage sag occurs on Phase_A and Phase_B of supply voltage.



injected voltage and load voltage of Phase_A in Figure 7.14, respectively. The

current waveforms of CH1, CH2 and CH3 indicate the supply current, injected

current and load current of Phase_A, respectively. DVR injects the missing voltage

to the system in series and APF injects the filter current to the system in shunt.


Table 7.4.


152



Table 7.4. THD contents of supply and filtered currents of Phase_A for Case 3 THD content of Phase_A

load current


Order (%) Order (%) Order (%) Order (%) 1 100.00 18 0.11 1 100.00 18 0.20

2 0.38 19 0.66 2 0.44 19 0.93

3 1.86 20 0.04 3 1.23 20 0.14

4 0.32 21 0.16 4 0.36 21 0.39

5 22.39 22 0.04 5 3.20 22 0.07

6 0.17 23 1.05 6 0.12 23 0.39

7 7.27 24 0.10 7 1.15 24 0.19

8 0.15 25 0.44 8 0.42 25 0.61

9 1.19 26 0.13 9 0.46 26 0.28

10 0.18 27 0.17 10 0.21 27 0.38

11 5.80 28 0.12 11 1.09 28 0.37

12 0.13 29 0.60 12 0.15 29 0.39

13 1.82 30 0.11 13 0.85 30 0.38

14 0.09 31 0.19 14 0.35 31 0.46

15 0.53

15 0.21

16 0.10 THD(%)23.55

16 0.18 THD(%)4.38

17 2.00 17 0.83


153

At the starting of sag, the load voltage can be affected due to instantaneous

reduction of the voltage reference and delay originated from sag detection time.

When the voltage sag occurs, only the related H-bridge inverters of DVR start to

operate as demonstrated in Figure 7.15. As also demonstrated in the current

waveforms, the sag occurs on phase_A and phase_B. The phase A and phase_B load

currents so their voltages do not affected by sag.

Figure 7.15. Three-phase voltage and current waveforms at starting of double phase


DVR comes into standby operation whenever the sag ends as demonstrated in

Figure 7.16. For Figures 7.16, THD values of supply voltage and load voltage are

measured as 2.26% and 2.92%, respectively. THD of the load voltages is always kept

below the IEEE voltage harmonic limits (IEEE Std 519, 1995).


154



7.4. Experimental Results for Voltage Sag Compensation and Current

Harmonic Elimination with Proposed OPEN UPQC

The results of Hioki 3196 power quality analyzer and Fluke 1760 PQ recorder

are presented to show the performance of OPEN UPQC for sag mitigation and

current harmonic elimination. Three cases are comprehensively analyzed:



Case 3) 20% double phase voltage sag and current harmonic elimination,

The experimental diagram of OPEN UPQC with measurement points are

demonstrated in Figure 7.17.


155

Figure 7.17. Experimental diagram of OPEN UPQC with measurement points


At stand-by operation (no-fault condition), DVR is in OFF-mode and injects

no voltage to the system. The supply voltage and load voltage are in phase with each

other. RMS trends of supply and load voltages are demonstrated in Figure 7.18.


APF is ON-mode and eliminates the load current harmonics as demonstrated

in Figure 7.19. At stand-by operation (no-fault condition), average load voltage THD


156

is 2.75% and supply current THD is 4.09%. These values are close to values used in

simulation studies. Phase_A, phase_B and phase_C are indicated as red (CH1), green

(CH2) and blue (CH3), respectively.


The load voltage is identical to supply voltage as demonstrated in the Figure

7.20. The voltage waveforms of CH1, CH2 and CH3 indicate the supply, injected and

load voltages of Phase_A, respectively. The current waveforms of CH1, CH2 and

CH3 indicate the supply, injected and load currents of Phase_A, respectively.


157



THD contents of supply and filtered currents for Phase_A are given in Table

7.5. The amplitudes of low order harmonics (5th, 7th, 11th and 13th) are high in load

current. APF injects the required compensation current to the system and the

amplitudes of low order harmonics are minimized in the supply current.




Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.05

1 100 18 0.23

2 0.12 19 1.04

2 0.55 19 0.82

3 1.08 20 0.06

3 0.45 20 0.09

4 0.18 21 0.33

4 0.47 21 0.32

5 22.14 22 0.06

5 2.84 22 0.32

6 0.11 23 0.76

6 0.23 23 0.59

7 7.73 24 0.1

7 1.2 24 0.28

8 0.12 25 0.73

8 0.3 25 0.86

9 0.63 26 0.06

9 0.52 26 0.23

10 0.12 27 0.25

10 0.27 27 0.31


158

11 5.48 28 0.14

11 1.26 28 0.45

12 0.07 29 0.51

12 0.22 29 0.23

13 2.24 30 0.1

13 0.92 30 0.26

14 0.07 31 0.39

14 0.09 31 0.48

15 0.47

15 0.15

16 0.08 THD(%) 24.34

16 0.29 THD(%) 4.09

17 1.74

17 0.79 7.4.2. Case Study5: 25% Single-Phase Voltage Sag, Current Harmonic

Elimination

When a voltage sag on phase_A is detected, DVR starts to inject the missing

voltage to the system and keeps the load voltages between 0.9-1.1 pu of nominal

voltages. The supply voltage and load voltage are in phase with each other. RMS



The waveform results for 25% sag on phase_A of supply voltage for 3 s

duration are demonstrated in Figure 7.22. The phase_A load current so its load

voltage is not affected by voltage sag. The load voltage waveform is identical with

load current waveforms because the load is purely resistive. The phase_A load

current is not affected when a voltage sag occurs on Phase_A.


159






to the system in series and APF injects the compensation current to the system in

shunt.


160










Order (%) Order (%)

Order (%) Order (%)

1 100 18 0.05

1 100 18 0.17

2 0.18 19 0.67

2 0.4 19 0.91

3 2.37 20 0.06

3 1.05 20 0.3

4 0.12 21 0.4

4 0.27 21 0.34

5 22.98 22 0.07

5 3.25 22 0.32

6 0.11 23 0.94

6 0.21 23 0.47

7 6.8 24 0.06

7 1.11 24 0.27

8 0.21 25 0.45

8 0.25 25 0.73

9 1.85 26 0.05

9 0.49 26 0.19

10 0.08 27 0.31

10 0.24 27 0.34


161

11 5.96 28 0.05

11 1.02 28 0.18

12 0.11 29 0.64

12 0.36 29 0.34

13 1.58 30 0.13

13 1.04 30 0.38

14 0.09 31 0.17

14 0.2 31 0.7

15 0.87

15 0.26

16 0.05 THD(%) 24.98

16 0.17 THD(%) 4.28

17 1.96



demonstrated in Figure 7.24, when the sag occurs, only the related H-bridge inverter

of DVR starts to operate.

Figure 7.24. Three-phase voltage and current waveforms at starting of single-phase




demonstrated in Figure 7.25. DVR comes into standby operation whenever the sag

ends. THD of the load voltages is always kept below the IEEE voltage harmonic

limits (IEEE Std 519, 1995).


162


25% voltage sag for Case 5 7.4.3. Case Study6: 20% Double Phase Voltage Sag, Current Harmonic

Elimination

At stand-by operation, DVR is in OFF-mode and injects no voltage to the

system. The supply voltage and load voltage are in phase with each other. RMS




163


supply voltage for 3 s duration are demonstrated in Figure 7.27. The phase_A load

current so its load voltage does not affected by voltage sag as demonstrated in Figure

7.27. The load voltage waveform is identical with load current waveforms because

the load is purely resistive. Phase_A and Phase_B load currents are not affected when

a voltage sag occurs on Phase_A and Phase_B of supply voltage.






to the system in series and APF injects the filter current to the system in shunt.

THD contents of the supply and filtered currents for Phase_A are given in

Table 7.7.


164






Order (%) Order (%)

Order (%) Order (%)

1 100 17 1.92

1 100 17 0.82

2 0.17 18 0.06

2 0.27 18 0.23

3 0.74 19 0.84

3 0.41 19 0.69

4 0.21 20 0.09

4 0.3 20 0.19

5 20.92 21 0.22

5 3.38 21 0.27

6 0.24 22 0.03

6 0.31 22 0.14

7 8.33 23 0.9

7 1.04 23 0.87

8 0.16 24 0.06

8 0.38 24 0.2

9 0.24 25 0.58

9 0.41 25 0.54

10 0.11 26 0.07

10 0.32 26 0.13

11 5.32 27 0.26

11 1.15 27 0.51

12 0.1 28 0.06

12 0.17 28 0.22

13 2.38 29 0.48

13 0.61 29 0.46

14 0.08 30 0.08

14 0.23 30 0.41

15 0.22 31 0.43

15 0.23 31 0.68

16 0.08 THD= 23.32%

16 0.23 THD= 4.2%


165

At the starting of sag, the load voltage can be affected due to instantaneous


voltage and current waveforms at starting of double phase 20% voltage sag are

demonstrated in Figure 7.29. When the sag occurs, only the related H-bridge

inverters of DVR start to operate as demonstrated in Figure 7.29. As also

demonstrated in the current waveforms, the sag occurs on phase_A and phase_B. The

phase_A and phase_B load currents so their voltages are not affected by sag.

Figure 7.29. Three-phase voltage and current waveforms at starting of double phase




demonstrated in Figure 7.30. DVR comes into standby operation whenever the sag

ends. THD values of supply voltage and load voltage are measured as 2.26% and

2.92%, respectively. THD of the load voltages is always kept below the IEEE voltage

harmonic limits (IEEE Std 519, 1995).


166



7.5. Summary

This chapter demonstrates the experimental results of UPQC and OPEN

UPQC performance. Experimental results illustrate the capabilities of UPQC and

OPEN UPQC for sag mitigation and current harmonic elimination. Several cases are

comprehensively analyzed experimentally for UPQC topologies: Case 1) No voltage

sag and current harmonic elimination, Case 2) 25% single-phase voltage sag and

current harmonic elimination, Case 3) 20% double phase voltage sag and current

harmonic elimination. The experimental results are compatible with IEEE power

quality standards.

APF eliminates the load current harmonics and keeps the supply current

almost sinusoidal with a THD of <5%. Dynamic response is a key consideration in

the controller design of DVR. DVR quickly senses the voltage sag and injects the

missing voltage to the system keeping the magnitude of the load voltage almost 0.9-1

per unit. The experimental results demonstrated in this chapter verify the simulation

results given in Section 6. The power quality improvement capabilities of UPQC and

OPEN UPQC are almost the same during steady state and voltage sag. But, the


167

performance of OPEN UPQC is better than UPQC during the start and end of voltage

sag since OPEN UPQC is supplied from two separate DC energy storage. Besides,

the power circuit of OPEN UPQC is much more flexible than that of UPQC.

The next chapter presents the main points, significant results and future works

of the thesis.


168

8. CONCLUSIONS AND FUTURE WORK Ahmet TEKE

169

8. CONCLUSIONS AND FUTURE WORK Voltage sags and current harmonics are the most important power quality

problems in commercial and industrial utility's customers. These power quality

problems can cause tripping of sensitive electronic equipments, abnormal operations

of facilities and tremendous economic losses. Custom Power devices have now been

of interest for more than a decade that are able to improve the reliability and the

quality of power delivered to electric power customers. Unified Power Quality

Conditioner consisting of two voltage source inverters with a common DC link is a

Custom Power device and can simultaneously perform the tasks of Active Power

Filter and Dynamic Voltage Restorer. OPEN UPQC consisting of two voltage source

inverters with separate DC links is a relatively new CP device and can

simultaneously perform the tasks of APF and DVR. UPQC and OPEN UPQC

compensate for current harmonics and voltage sag/swell to protect sensitive process

loads as well as improve service reliability. However, UPQC does not provide

different levels of power for their customers since UPQC solves only end user power

quality concerns. OPEN UPQC overcomes these limitations by using two VSIs with

separate DC links. The power circuit of OPEN UPQC is much more flexible than

that of UPQC. Not much work has yet been reported on theoretical, design procedure

and experimental analysis of OPEN UPQC.

The main aim of this thesis is to develop new control algorithms for UPQC

and OPEN UPQC, reduce power consumed by inverters during standby and injection

modes. For this purpose, UPQC and OPEN UPQC are designed, simulated in

PSCAD/EMTDC program and evaluated experimentally with a 6 kVA, 230Vl-l

laboratory prototypes. Extensive literature surveys on APF, DVR and UPQC are

conducted and the lacks of control strategies are identified. The control algorithms

and minimum energy dissipation methods are analyzed and designed in detail using

PSCAD/EMTDC. Then, the available control algorithms of APF and DVR are

improved to meet the stringent power quality standards. The power circuit design

procedures of UPQC topologies are presented in detail. Finally, the designed system

is setup experimentally, suitable interface circuits have been developed and


170

numerous tests are performed to validate the performance of the proposed UPQC and

OPEN UPQC. When there is no voltage sag in the system (load voltage is within 0.9-

1.1 of its nominal), DVR is in OFF-mode. During this mode, APF eliminates the load

current harmonics and keeps the supply current at the PCC almost sinusoidal.

Dynamic response is very critical for DVR since many industrial loads are very

sensitive to voltage sags. When a voltage sag occurs on the supply voltage, DVR

quickly starts to inject the missing voltage to the system and keeps the load voltage

magnitude nearly at 1 pu. APF continues the current harmonic elimination. The

simulation and experimental results verify the theoretical analysis and designed

system.

A control algorithm for the shunt units of UPQC and OPEN UPQC is

proposed and investigated. TMS320F28335 Digital Signal Processor based 3 kVA

laboratory prototype of voltage source APF is built using three leg three-phase IGBT

based inverter. The nonlinear load generates harmonics with lower order 5th, 7th, 11th

and 13th harmonics being dominant. APF controller based on Instantaneous Reactive

Power Theory extracts the load current harmonics exactly and the required

compensation current is injected to the system in shunt by keeping the THD level of

supply current below 5%. It is known that voltage unbalance and voltage harmonics

on supply voltage result in very high harmonic distortion and affect the performance

of APF. To overcome these voltage harmonics and unbalance problems, a low pass

filter with a cut off frequency of 50 Hz is used in the voltage measurement of

harmonic filtering and a virtual alpha-beta components are generated in the DSP.

This control approach eliminates the negative effect of traditional IRPT under

distorted and unbalanced supply voltage conditions. The switching signals of APF

are then generated using hysteresis current control. A PI controller is used to

compensate the DC link capacitor voltage when APF is in compensation mode. An

experimental overvoltage protection circuit has been also designed and integrated

into the controller board of APF laboratory prototype. The extensive simulation and

experimental test results show that improved IRPT based APF eliminates the current

harmonics and keeps the supply current almost sinusoidal and below 5% THD.


171

A new control algorithm for the series units of UPQC and OPEN UPQC is

proposed and investigated. TMS320F2812 Digital Signal Processor based 3-phase 3

kVA laboratory prototype of voltage source DVR is designed and implemented.

Three single-phase H-bridge IGBT based inverters are used for DVR implementation

to control each phase independently. DVR quickly senses the voltage sag on the

supply voltage and injects the missing voltage to system in series thus the load is

prevented from voltage sag. New voltage sag detection and voltage compensation

methods based on enhanced phase locked loop are developed. E-PLL algorithms are

based on the nonlinear adaptive filter. The adaptive filter has the ability of peak

detection, harmonics extraction and signal decomposition. E-PLL structure is very

robust with respect to pollution in the input signal such as noise, harmonic distortion

and disturbances. The power losses are also minimized by controlling the each H-

bridge inverter independently. DVR is designed to compensate voltage sags with

magnitude lower than 30% of nominal voltage. Sinusoidal pulse width modulation

technique is used to generate the switching signals. The performed case studies are

steady state performance test, 25% single-phase voltage sag and20% double phase

voltage sag. The rms voltage trends of supply and load voltages are given. The

results show that the designed DVR quickly responses to the voltage sags and

restores the load voltage to the presag value. The extensive test result shows that the

E-PLL based DVR mitigates the voltage sags and keeps the RMS of load voltage

nearly 0.9-1 per unit. The load voltage THD is less than 5% during fault that has

conformed to the power quality standards recommended by IEEE standard 519-1995.

The constant DC link voltage for APF is also achieved regardless of voltage sags in

supply voltage with the help of proposed DVR. The harmonic elimination

performance of APF is not affected by voltage sag since DVR keeps the magnitude

of load voltage almost constant.

This thesis introduces new control algorithms which not only improves

UPQC and OPEN UPQC systems performance. The experimental design procedure

and practical recommendations for experimental setup are also presented in detail.

These can help the researchers on their custom power based projects. The proposed

UPQC and OPEN UPQC are tested under unbalanced and harmonic polluted supply


172

voltage. The limitations of UPQC over OPEN UPQC operation in terms of start and

end times of voltage sag are also explained. The simultaneous mitigation of current

harmonics and voltage sags with reduced active power consumption is important

contribution that shows the usefulness of this Ph.D. thesis. The use of a combination

of APF and DVR suggest a cost effective solution to voltage sags and current

harmonics.

In the future, field researches will concentrate on reliability of electric power,

energy conservation, efficient energy use and maximum use of renewable energy

sources. Further research can be carried out in the following areas:

Realization of minimum power dissipation methods for DVR and APF.

Performance comparison of available power quality detection and

reference signal generation methods experimentally.

Implementation of custom power devices using FPGA controller and

performance comparison of the control algorithms using FPGA versus DSP.

Design of a single control algorithm based on E-PLL for APF and DVR

controllers and analysis of the system during dynamic load changes and transients.

Implementation of UPQC (combination of DVR and APF) with different

circuit topologies (e.g. left shunt connected, multilevel voltage source converter

based, three-phase four-wire OPEN UPQC).

Large scale application of UPQC/OPEN UPQC and combination with one

or several distributed generation systems.

The stored energy of DVR can be delivered from different kinds of

renewable energy storage systems such as wind or solar energy.

Harmonic current and reactive power elimination capability of

UPQC/OPEN UPQC using LCL passive filter in its shunt and series units.

UPQC and OPEN UPQC concepts implemented in this thesis can be

extended for the control algorithms of Flexible AC Transmission Systems (FACTS)

and Flexible, Reliable and Intelligent ENergy Delivery System (FRIENDS).

173

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199

BIOGRAPHICAL INFORMATION

Ahmet TEKE was born in Osmaniye, Turkey in 1979. He received his B.S.

and M.Sc. degrees both in Electrical and Electronics Engineering Department from

the Çukurova University in 2002 and 2005, respectively. He has been working as a

research assistant in Electrical and Electronics Engineering Department of the

Çukurova University since 2005.

He joined the power quality research group in 2007 to pursue a Ph.D. degree

in Electrical and Electronics Engineering. He has worked in several research projects

supported by Scientific and Technological Council of Turkey and Scientific Research

Project Unit of Çukurova University. His research areas are custom power, power

converters, energy efficiency and power electronic applications of renewable energy

sources. He is a member of Turkish Chamber of Electrical Engineers and also a

student member of IEEE.

200

APPENDIX A: Most Common Power Quality Problems

Table A.1: Most common PQ problems

1. Voltage sag (or dip)

Description: A decrease of the normal voltage level between 10% and 90% of the nominal rms voltage at the power frequency, for durations of 0.5 cycle to 1 minute. Causes: Faults on the transmission or distribution network, faults in consumer’s installation, connection of heavy loads and start-up of large motors. Consequences: Malfunction of information technology equipment (namely microprocessor-based control systems such as PCs, PLCs, ASDs) that may lead to a process stoppage, tripping of contactors and electromechanical relays, disconnection and loss of efficiency in electric rotating machines.

2. Voltage swell

Description: Momentary increase of the voltage, at the power frequency, outside the normal tolerances, with duration of more than one cycle and typically less than a few seconds. Causes: Start/stop of heavy loads, badly dimensioned power sources, badly regulated transformers (mainly during off-peak hours). Consequences: Data loss, flickering of lighting and screens, stoppage or damage of sensitive equipment, if the voltage values are too high.

3. Harmonic distortion

Description: Voltage or current waveforms assume non-sinusoidal shape. The waveform corresponds to the sum of different sine-waves with different magnitude and phase, having frequencies that are multiples of power-system frequency. Causes: Classic sources: electric machines working above the knee of the magnetic saturation, arc furnaces, welding machines, rectifiers and DC brush motors. Modern sources: all nonlinear loads, such as ASDs, switched mode power supplies, data processing equipment, high efficiency lighting. Consequences: Increased probability in occurrence of resonance, neutral overload in 3-phase systems, overheating of all cables, loss of efficiency in electric machines, electromagnetic interference with communication systems, errors in measures when using average reading meters, nuisance tripping of thermal protections.

4. Very short interruption

Description: Total interruption of electrical supply for duration from few milliseconds to one or two seconds. Causes: Mainly due to the opening and automatic reclosure of protection devices to decommission a faulty section of network. The main fault causes are insulation failure, lightning and insulator flashover. Consequences: Tripping of protection devices, loss of information

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and malfunction of data processing equipment, stoppage of sensitive equipment, such as ASDs, PCs, PLCs, if they are not prepared to deal with this situation.

5. Long interruption

Description: Total interruption of electrical supply for duration greater than 1 to 2 seconds. Causes: Equipment failure in the power system network, storms and objects (trees, cars, etc) striking lines or poles, fire, human error, bad coordination or failure of protection devices. Consequences: Stoppage of all equipment.

6. Voltage spike

Description: Very fast variation of the voltage value for durations from a several microseconds to few milliseconds. These variations may reach thousands of volts, even in low voltage. Causes: Lightning, switching of lines or power factor correction capacitors, disconnection of heavy loads. Consequences: Destruction of components (particularly electronic components) and of insulation materials, data processing errors or data loss, electromagnetic interference.

7. Voltage fluctuation

Description: Oscillation of voltage value, amplitude modulated by a signal with frequency of 0 to 30 Hz. Causes: Arc furnaces, frequent start/stop of electric motors (for instance elevators), oscillating loads. Consequences: Most consequences are common to undervoltages. The most perceptible consequence is the flickering of lighting and screens, giving the impression of unsteadiness of visual perception.

8. Noise

Description: Superimposing of high frequency signals on the waveform of the power-system frequency. Causes: Electromagnetic interferences provoked by Hertzian waves such as microwaves, television diffusion and radiation due to welding machines, arc furnaces and electronic equipment. Improper grounding may also be a cause. Consequences: Disturbances on sensitive electronic equipment, usually not destructive. May cause data loss and data processing errors.

9. Voltage unbalance

Description: A voltage variation in a 3-phase system in which the three voltage magnitudes or the phase-angle differences between them are not equal. Causes: Large single-phase loads (induction furnaces, traction loads), incorrect distribution of all single-phase loads by the three- phases of the system (this may be also due to a fault). Consequences: Unbalanced systems imply the existence of a negative sequence that is harmful to all three-phase loads. The most affected loads are three-phase induction machines.

202

APPENDIX B. Fundamentals of Instantaneous Reactive Power Theory

Instantaneous Reactive Power Theory (p-q theory) is based on set of

instantaneous powers defined in the time domain and uses the Park Transform. No

restrictions are imposed on the voltage or current waveforms and it can be applied to

three-phase systems with or without a neutral wire for three-phase generic voltage

and current waveforms. Thus, it is valid not only in the steady state but also in the

transient state. This theory is very efficient and flexible in designing controllers for

power conditioners based on power electronics devices (Akagi et al., 2007).

In three-phase circuits, instantaneous currents and voltages are converted to

instantaneous space vectors. In instantaneous power theory, the instantaneous three-

phase currents and voltages are calculated as given in following equations. These

space vectors are easily converted into theα –β orthogonal coordinates (Kale et al., 2005), (Akagi et al., 1986).

1 1 / 2 1 / 22

3 0 3 / 2 3 / 2

a

b

c

VV

VV

V

α

β

− − = −

(B.1)

1 1/ 2 1 / 22

3 0 3 / 2 3 / 2

a

b

c

II

II

I

α

β

− − = −

(B.2)

Considering only the three-phase three-wire system, the three-phase currents

can be expressed in terms of harmonic positive, negative and zero sequence currents.

In Equations (B.1) and (B.2), α and β are orthogonal coordinates. Vα and Iα are on α axis, Vβ and Iβ are on β axis. Three-phase conventional instantaneous power is calculated as follows.

ββαα += IVIVp (B.3)

203

In fact, instantaneous real power (p) is equal to following equation:

ccbbaa IVIVIVp ++= (B.4)

Instantaneous real and imaginary powers are calculated as follows.

V V Ip

Iq V V

α β α

ββ α

= −

(B.5)

In (B.5), VαIα and VβIβ are instantaneous real (p) and imaginary (q) powers,

respectively. Since these equations are products of instantaneous currents and

voltages in the same axis, in three-phase circuits, instantaneous real power is p and

its unit is watt. In contrast Vαiβ and VβIα are not instantaneous powers. Since these

are products of instantaneous currents and voltages in two orthogonal axes, q is not

conventional electric unit like watt or VAr. The value q is instantaneous imaginary

power and its unit is imaginer volt ampere (Kale et al., 2005), (Akagi et al., 1984).

These power quantities given above for an electrical system represented in a-b-c

coordinates and have the following physical meaning.

p , the mean value of the instantaneous real power - corresponds to the energy

per time unity which is transferred from the power supply to the load, through a-b-c

coordinates, in a balanced way.

%p , alternated value of the instantaneous real power - it is the energy per time

unity that is exchanged between the power supply and the load through a-b-c

coordinates.

q , the mean value of the instantaneous imaginary power that is equal to the

conventional reactive power.

%q , instantaneous imaginary power - corresponds to the power that is

exchanged between the phases of the load. This component does not imply any

204

exchange of energy between the power supply and the load, but is responsible for the

existence of undesirable currents, which circulate between the system phases.

The instantaneous active and reactive power includes AC and DC values and

can be expressed as follows:

~ ~

q q q, p p p− −

= + = + (B.6)

DC values of the p and q are created from positive-sequence component of

the load current. AC values of the p and q are produced from harmonic components

of the load current (Kale et al., 2005). Equation (B.5) can be written as (B.7):

1V VI p

I V V q

α βα

β β α

−

= −

(B.7)

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