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Comparison of Selected 3 Phase Switched Mode RectifiersP. Ide; N. Froehleke; H. Grotstollen

University of PaderbornPower Electronics and E lectrical DrivesPohlweg 4733098 PaderbornGermanye-mail: ide@lea.uni-paderborn.de

Abstract Prominent members of the large variety of 3-phase switched mode rectifiers constrained tounidirectional power flow are inspected and comparedwith respect to criteria: power losses and density, THD(Total Harmonic Distortion) and count of semi-conductors. Derivatives of the standard switched modeboost-type rectifier bridge topology such as a 6-pulsediode bridge, employing parallel-connected sub-topologies, and a 3-level topology are taken intoaccount. Stress quantities are derived for the analyticalcalculation of conduction and switching losses,measures for the loss and THD minimization arediscussed using conventional or flat-top modulation inorder to facilitate a solid based selection. Identifying theinput filters as the major cost block leads to a 3-levelSMR as being the optimum topology with a highpotential degree of optimization.

1. IntroductionThree-phase high power factor switched mode rectifiers(PFC-SMR) are undergoing a rapid development inrecent years due to tough regulations, such as IEC1000-3-214, hard economic constraints and a large potentialmarket. In face of the large variety of PFC-SMR circuits[l] the work on classification of circuits by Salmon [2]and his detailed studies on 3-phase boost-type SMR (seeFig. 2-Fig. 5 ) employing dual boost sub-topologies inY, A and bridge configuration [3] and his studies on 2-level or 3-level asymmetrical half-bridges [4] representsa good base for the search of the most advantageousrectifier.Since the published results of Salmons investigations donot contain sufficient information on stress quantities tocalculate conduction and switching losses, nor onmeasures for loss and THD minimization by usingdifferent modulation schemes or input filter design,Investigations on the latter subjects reported in thisarticle were performed on those prominent selectedmembers of 3-phase SMR mentioned above in order tofacilitate a thorough comparison.As supplementary topology the 3-level extension of theparallel connected sub-topology in Y configuration (seeFig. 6) treated in [5], [6] is included. This selection and

further investigations were performed to find thetopology, combining attributes such as low current THD(less than 5 ) , high efficiency and reliability at minimalcosts and complexity. The rectifier should of coursecomply with EMI/RFI emission regulations using onlyspare input filters.2. Descriptionof topologiesFig. 1 depicts the well known 6-pulse active bridge (TR),selected as reference topology. It permits power flow inboth directions. The other topologies investigated heredo not show this feature since the maximum phase shiftbetween mains voltage UN and current i is limited to(cpS.- l = 30 . Especially telecom applications do notdemand power regulation. Thus this disadvantage is notcritical.Topologies TR, Ty, TA,TH have in common, that theiroperation is very similar when working in rectificationmode. So, the same modulation scheme is available,leading to similar pulse pattern.Table 1 depicts the corresponding switching states ofthese topologies. Standard space vector modulation canbe used, which is assumed during the followinginvestigations.

Fig. 1.Referencetopology using 6-pulse active bridge0The working principle of these circuits can be describedby distinguishing at least two modes of operation. If

0-7803-3996-7/97/10.0001 97 EEE - 630 -

mailto:ide@lea.uni-paderborn.demailto:ide@lea.uni-paderborn.de

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P-25state TR TY TA T4,TsT,,T6Si.Sz& Si.Sz

TH conditionTI,Tz ,T~

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Table 1: Corresponding switching states of thetopologies TR, Ty, TA, TH acting as rectifiers.conditions have to be fulfilled for Ty, TA, TH.

tT6iFig. 2. Boost-type SMR with 3-phase sub-topology (TH). D D,

Fig. 3. Boost type SMR employing a parallel subtopology in delta configuration(TA)THmakes use of an auxiliary 3-phase full bridge, whileTA nd Tu need bi-directional switches. The latter can be

build according to e.g. those two solutions given in Fig.4.Note, all semiconductors used in TR, TH, TAand TYhave to sustain the maximum output voltage U=,exceptof diodes Dsll - DsI4 n the regime of ideal conditions.But in order to avoid inadlmissible high voltages in caseof asymmetric distribution of blocking voltages, thesediodes should sustain the maximum output voltage, too.

Fig. 4. Two implementations of bi-directionalswitches. A full bridge: with diodes and a singletransistor, e.g. an IGBT (version I), or an antiserialconnection of transistors, e.g. MOSFETsantiparallel diodes (version II .

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Fig. 5. Boost type SMR employing a parallelconnected sub-topology in star configuration Ty)

Fig. 6. Boost type SMR mploying a parallel connected3-level topologyIn contrast to T, topologies T,. TA,TH,T3Yhave a verygood immunity to shoot-through faults in common andTy, TA,T3yneed a reduced number of isolating drivers,thus lowering costs.

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Topology T3y depicted in Fig. 6is quite similar to thetopology Ty. Three bi-directional switches are arrangedin Y-configuration with the star point being connected tothe center point of the output. So the behavior becomessimilar to that of the 3-level inverters, used in highpower drive applications.Since the rearrangement of thecircuit by Kolar outlined in [SI and the availability of asuitable power module produced by IXYS high powerdensity and low cost implementations of the circuit areachieved easily. This novel semiconductor modulecontains the 1-switch using Salmons terminology in [2]and two boost diodes Df, thus representing a completePWM rectifier leg, while the bi-directional switchesdepicted in Fig. 4re not available as module, yet.I Topology Transistors DiodesI TR 6IGBT 12MOSFETTU 1 6IGBT 12MOSFET IlOOOV12 lOOOV

TA version I I 3 IGBT I 6 MOSFET 18 l00OVversion11 6IGBT 12MOSFET I 12 I lOOOVTy version1 3IGBT 6MOSFET I 18 lOOOVversion 11 6 IGB T 12 MO SFE T 12 lOOOVT3Y I 3 IGBT 6MOSFET 18 500V

Table 2: Overview of the number of semiconductorsused for each topologyThe major advantage of topology T3y derives is the lowblocking voltages of the semiconductors. AssumingEuropeans utility, all semiconductors can be designedfor blocking voltages of 500V.Hence the much betterswitching behavior of lower blocking voltage

semiconductor devices can be utilized for raising theswitching frequency. This allows subsequently theminiaturization of boost inductors and input filtercomponents. In telecom applications typically front endSMRs generate the dc-rail voltage which is the inputvoltage for cascaded D C D C converters. The lattersupplies low voltage bus systems. With the use of dc-splitted voltages the input voltages of these converterscan be reduced increasing the efficiency of the totalsystem.When the SMR-topology T3Y is compared to circuitspresented in [4] by Salmon with split dc-rail orasymmetrical half-bridges employing dc-inductors, thefollowing findings are evident:The number of transistors (5 or 7) and its associateddrivers exceeds by far those given by Kolar (3) in[SI.A hysteresis instead of a PWM control is appliedwith its negative effects on the design of EM1 andcurrent filtering.The instability of the output voltage center point,which is highly loaded, requires an additional controlscheme to ensure stability in case of unsymmetricaloutput voltages, e.g. of the mains voltages. Hugeoutput capacitors are needed, producing high losses.Due to the high floating of the output center pointthe two output voltages cannot be used to supply asplitted second stage.The blocking voltage of the output capacitors has tobe as high as the output voltage.

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er switch j.5A T,v per svitch q.7 A

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0 5 10 15 20currents A

10 2currents A

Fig. 7. Current stress on semiconductors in investigated topologies. Note, that semiconductors blocking voltage intopology T3y is only half of the others.

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- P-253. Calculationof stress quantitiesThe investigations were: performed assuming a ratedpower of Pout = 10kW , constant dc-link voltageU L:700V and mains voltage of U N 230V. Theswitching frequency is rassumed as high, so the mainsvoltage does not vary during a switching period. Hence,the current shape is linear during each switchinginterval. A first pulse pattern was generated,, assumingstandard space vector modulation for TR, Ty, TAand TH.The zero space vectors are equally applied yielding adistribution factor of y=05. The pulse pattern wasgenerated using double ramp comparison PWM fortopology T3Y, presented in [lo]. Line currents andsemiconductor's currents in terms of scale are shown inFig. 7. The maximum peak current of all semiconductorsand current stress of TH and TR for the transistors is thesame. Disadvantageous is the low utilization factorU F = I Ipk 4%. When selecting the transistors,the peak current is as relevant as the average current.From this point of view the topologies TYand TSY,withswitches arranged in star connection, are advantageous,because of their better utilization factorUF = I I p k = 15.4% . In most SMR applications thetransistor's current stress is lower than the current stressof the diodes, because tlhe diodes build the main currentpath, while the transistors are used for shaping the inputcurrent.

4. Calculation of 10ssc:sAfter calculation of current stress quantities and theselection of suitable transistors and diodes thedetermination of losses is feasible. For this calculation aswitching frequency of f = 2OkHz was assumed, theuse of IGBTs for TR, TH while the bi-directionalswitches of Ty,A were assumed to be constructedaccording to version I (Fig. 4). The calculation of lossesof T ~ Ys based on the data of module IXYS VUM25-E,which contains MOSFETs. Conduction losses (Pan),turn-on losses (Po,) and turn-off (POff) osses werecalculated based on datal available by data sheets. ForVUM25-E charge-down losses (PChd) are depictedseparately. Simplified models were used to calculatelosses during turn-on, conduction and turn-off accordingto [9], [6]. The losses for transistors (abbr. as Taccording to Fig. 1 - Fig. 6) main diodes (D), auxiliarydiodes (Daux),diodes used to construct bi-directionalswitches (Ds) and the total losses are depicted in Fig. 8,specifying applied transistor types and diodes, too.The losses of T3Y reonly half of the losses produced byother topologies. The major advantage of this topologyis the low blocking voltage of the transistors, leading tothe application of MOSlFETs with improved switchingcapabilities. Here, switlching losses of high voltageIGBTs are much higher than conduction losses.The results depicted in Fig. 8and Fig. 9are obtained byanalytical and numerical calculations using MatLab.Hence different measures to reduce switching losseswere discussed.

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Tovol. Semiconductor tvvesTR SKM44GD 123DTH SKM22GD 123 D,BUP 203, IXYS DSEI 30 12TDTyT3y IXYSVUM25-E

BUP 203, IXYS DSEI 30 12BUP 203, IXYS DSEI 30 12

Fig. 8. Distribution of losses using standard space vector modulation in case of TR,TH, fD, TYand DCCR for TJY Note,that in case of T3Y he scaling is different.) The loss of the bi-directional switches is calculated according to Fig. 4,version 2.

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IXYS VUM25-EFig. 9. Distribution of losses using flat-top-space vector modulation in case of TR, TH,TD,TYand DCCR for T3Y or aninductance of L = 0.3mH. Note, in case of T3y the scaling is different. The pulse frequency is raised to f p = 4OkHz , sothe average switching frequency is f = %f = 27kHz .

3*TSl2*-DS 6 D SUM

Fig. 10. Distribution of losses, based on a the secondversion of bi-directional switch, according to Fig.4.This is very important, because the size of the inputfilter can be reduced by increasing the switchingfrequency. One measure is to apply high voltageMOSFETs for the topologies Ty, TA, TR and TH.Concerning the low utilization factor UF = I,, I,, oftransistor's currents, MOSFETs are more suitable.Varying the modulation technique is also an adequatemeasure to reduce switching losses. Because of the highmodulation index M = s ( 'd)- flat-topmodulation seems to be advantageous: switching lossesas well as the distortion of the input currents can bereduced due to raising the pulse frequencies. The resultsdepicted in Fig. 8, obtained for a distribution of the zerocomponent of y = 0.5 do not surprise. The efficiency ofabout 95 referring to 500 W losses is raised for all

topologies due to the switching loss reduction, whenapplying a flat-top modulation. Fig. 9 and Fig. 10display the distribution of losses in case of MOSFETsand a doubled switching frequency.At this stage, the use of the novel topologies employingparallel connected sub-topologies with variousconfigurations described in [3] do not convincepractically in terms of losses with the exception oftopology TA, because semiconductor devices are alsomore costly for the novel circuits as compared to TR orthey are still not available in integrated modules. This isdue to the fact that although the p.u. rating of theauxiliary switches is generally low, the applicableIGBTs are to overrate for ensuring reliable operation,since no IGBTs exist with the required utilization factorUF = I,, I < 15The poor results for the star topology TY according toFig. 9are completely different, when the star node isconnected to the center node of a split dc-rail outputwhereby the 3-level topology (T3y) s generated given inFig. 6.This center node is available practically in mostcases, due to the use of low-cost, low-voltage capacitors.5. VerificationMeasured results of a 3-level boost SMR employing astar configured sub-topology (T3Y)prototype are givenin Fig. 11.The efficiency of q = 96 corresponds quitewell with the calculation of losses, given in Fig. 9.

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Differences reasoned by losses of inductors, capacitorsand further parasitics, which have not been consideredin loss calculation given in chapter 4.10

8

c 6nI-

4

2

II ,P

Fig. 13. Total harmonic distortion (THD) of 2-level(e.g. TR) and 3-level (e.g. T3Y) opologies at differentfrequencies. At s = 4 kHz flat-top-modulation isassumed for TR.

1V 2.2 3.7 5 7P-out kW 10

Fig. 11. Measured efficiency of T3Y with different inputvoltages at&= 40 kHz. Applying 3-level topologies the THD can be reduced toat least 66%without increasing inductors or frequency.. Input filter considerationsContrary to inverter design, where high order harmonicsof current and filtering is not given much attention, inputfilters of SMR have major impact on the volume of thetotal rectifier. Amplitudes of high order harmonics canbe reduced by raising thle switching frequency and theinductors L and the choice of topology and modulationscheme.

7. ConclusionConsequently a 10 kW 3-phase 3-level boost SMRemploying a star configured sub-topology (T3Y) nd thereference topology (TR) was implemented andcommissioned recently.Hence, the 3-phase 3-level boost SMR employing aparallel connected sub-topology of 3 in star connectedbi-directional switches, was selected. Many results andpublications concerning this topology, which wasinvestigated in depth by Kolar et a1 are summarized in[7] Since there are also low-cost control schemes,which were developed by the authors of this paper [lo]yielding the performance of a space vector control, theoverall costs remain low. Note, that 3-levelconfigurations used in inverters only for high voltageapplications are more frequently applied in rectifiers tolower the voltage stress, the device switching frequency,the boost inductor volume and the THD.

I I

8. Summary15 -10 -5 0 5 10 15P N / 0

Five members of 3-phase switched mode rectifiersconstrained to unidirectilonal power flow are inspectedand compared with respect to different criteria. The 3-level topology with blocking voltages of only 50% ofthe output voltage is most advantageous. Lowerblocking voltages allow the use of transistors with betterswitching capabilities. Due to higher applicableswitching frequencies arid a reduction of the pulsatingvoltage to 50% low THD of input currents can beachieved. The availability of modules, containing thesemiconductors of a rectifier leg and the reduced size ofinput filter raises power density.

Fig. 12. Comparison alf input current waveforms,generated with a 3-level topology like T3Y nd DRCC oron the other hand with ithe reference topology TR singflat-top modulation. The switching frequenciesf = 4OkHz and inductance's L = 300pH are equal.The high order harmonics of the input currents oftopologies TR, Ty, TH ,and TAare equal, because theirexternal behavior is equivalent. Because of its 3-levelarchitecture of topology T3Y the amplitude of thepulsating voltage is reduced to 50%. So, the distortionof the inductors currents can be reduced, too. Fig. 13compares the THD of 2- and 3-level topologies atdifferent switching frequencies.

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AcknowledgmentThe authors would like to express their acknowledgmentof the support by ABB CEAG, Soest, Germany and LustAntriebstechnik, Wetzlar, Germany.References

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Mohan, N., Undeland, T., Robbins, W.; PowerElectronics, 2ndEdition, John Wiley & Sons NewYork, 1995Ide, P., Froehleke N., Grotstollen, H.;,,Investigation of low cost control schemes for aselected 3-level switched mode rectijier ;ntelec1997, Melbourne

Outputs'', APEC, 1995, pp. 473-479

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