Asynchronous Sequential LogicChapter 9

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9.1 IntroductionSynchronous sequential circuitsFlip-flops share a single clock

Asynchronous sequential circuits

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Fig. 9.1Block diagram of an asynchronous sequential circuit

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no clock pulsedifficult to designdelay elements: the propagation delaymust attain a stable state before the input is changed to a new value

DO NOT use asynchronous sequential circuits unless it is absolutely necessarye.g., in you exam

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9-2. Analysis ProcedureThe procedureDetermine all feedback loopsAssign Yi's (excitation variables), yi's (the secondary variables)Derive the Boolean functions of all Yi'sPlot each Y function in a mapConstruct the state tableCircle the stable states

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Examples

the excitation variables: Y1 and Y2Y1 = xy1+ x'y2Y2 = xy1' + x'y2Fig. 9.2Example of an asynchronous sequential circuit

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Maps and transition table

the y variables for the rowsthe external variable for the columnsCircle the stable statesY = yFig. 9.3Maps and transition table for the circuit of Fig. 9.2

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The differencesynchronous design: state transition happens only when the triggering edge of the clockasynchronous design: the internal state can change immediately after a change in the inputThe total statethe internal state + the input valuey: the present stateY: the next state

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The state transition table

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A flow tablea state transition table with its internal state being symbolized with letters

Fig. 9-4(a) is called a primitive flow table because it has only one stable state in each rowFig. 9.4Example of flow tables

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state assignment derive the logic diagram

Fig. 9.5Derivation of a circuit specified by the flow table of Fig. 9.4(b)

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Race conditionswhen two or more binary state variables change value00 1100 10 11 or 00 01 11a noncritical raceif they reach the same final stateotherwise, a critical state

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Noncritical raceFig. 9.6Examples of non-critical races

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Critical race

Fig. 9.7Examples of critical races

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Races may be avoidedrace-free assignment: only one state can change at any one timeinsert intermediate unstable states with a unique state-variable changeA cyclea unique sequence of unstable states

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A cyclea unique sequence of unstable states

Fig. 9.8Examples of cycles

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Stability Considerationsa square waveform generator?

Fig. 9.9Example of an unstable circuit

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9-3 Circuits with LatchesAsynchronous sequential circuitswere know and used before synchronous designthe use of SR latches in asynchronous circuits produces a more orderly patternreduce the circuit complexity

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SR latch - two cross-coupled NOR gates

Fig. 9.10SR latch with NOR gates

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Y = ((S+y)'+R)' = (S+y)R' = SR'+R'ythe state transition tablean unpredictable result when SR: 11 00SR = 0 in operationSR' + SR = S(R'+R) = S Y = S + R'y when SR = 0

two cross-coupled NAND gateS'R' = 0Y = (S(Ry)')' = S'+ Ry when S'R' = 0 S'R' latch

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Fig. 9.11SR latch with NAND gates

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Analysis exampleFig. 9.12Examples of a circuit with SR latch

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Label each latch output with Yi and its external feedback path with yiDerive the Boolean functions for the Si and RiS1 = x1y2R1 = x'1x'2S2 = x1x2R2 = x'2y1Check whether SR=0 for each NOR latch or whether S'R'=0 for each NAND latchS1R1 = x1y2x'1x'2 = 0S2R2 = x1x2x'2y1 = 0

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Evaluate Y = S +R'y for each NOR latch or Y = S' + Ry for each NAND latchY1 = x1y2 + (x1+x2)y1 = x1y2+x1y1+x2y1Y2 = x1x2 + (x2+y'1)y2 = x1x2+x2y2+y'1y2Construct the state transition tableCircle all stable statesRace example:Let initial state is y1y2x1x2=1101 input x2 is changed to 0 if Y1 change to 0 before Y2 then y1y2x1x2=0100 instead of 0000

Fig. 9.13Transition table for the circuit of Fig. 9.12

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Analysis procedure:

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Latch Excitation Table For SR latch:

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Implementation ExampleDetermine the Boolean functions for the S and R inputs of each latchGiven a transition table

From maps: the simplified Boolean functions areNOR latchNAND latch

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Fig. 9.14Derivation of a latch circuit from a transition table

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derive a pair of maps for Si and Riderive the simplified Boolean functions for each Si and RiDO NOT make Si and Ri equal to 1 in the same minterm squaredraw the logic diagramfor NAND latches, use the complemented values of those Si and Ri

General Procedure for Implementing a Circuit with SR Latches

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Debounce circuitremove the series of pulses that result form a contact bounce and produce a single smooth transition of the binary signal

TTL: input = logic-1 when openFig. 9.15Debounce circuit

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9-4 Design ProcedureDesign specificationsa gated latchtwo inputs, G (gate) and D (data)one output, QG = 1: Q follows DG = 0 : Q remains unchanged

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All the total statescombinations of the inputs and internal states

simultaneous transitions of two input variables are not allowed

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Primitive flow table

dash marks in each row that differs in two or more variables from the input variables associated with the stable statedon't care condition for the next state and outputFig. 9.16Primitive flow table

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Reduction of the primitive flow tabletwo or more rows in the primitive flow table can be merged if there are non-conflicting states and outputs in each of the columns

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Fig. 9.17Reduction of the primitive flow table

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Transition table and logic diagramState assignmentdiscussed in details in Sec. 9-6a:0, b:1

Fig. 9.18Transition table and output map for gated latch

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the outputlogic diagram

Fig. 9.19Gated-latch logic diagram

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SR latch implementation

Fig. 9.20Circuit with SR latch

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Assign outputs to unstable statesthe unstable states have unspecified output valuesno momentary false outputs occur when the circuit switches between stable states

00: 01 1: 10 1, 1 0: -

Fig. 9.21Assigning output values to unstable states

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The procedure for making the assignment to outputs associated with unstable states can be summarized follows:

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Summarya primitive flow tablestate reductionstate assignmentoutput assignmentSimplify the Boolean functions of the excitation and output variables and draw the logic diagram

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9-5 Reduction of State and Flow TableEquivalent statesfor each input, two states give exactly the same output and go to the same next states or to equivalent next states

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(a,b) are equivalent if (c,d) are equivalent(a,b) imply (c,d)(c,d) imply (a,b)both pairs are equivalent

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Implication Tablethe checking of each pair of states for possible equivalence

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Fig. 9.22Implication table

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the equivalent states(a,b), (d,e), (d,g), (e,g)the reduced states(a,b), (c), (d,e,g), (f)the state table

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Merging of the flow tableconsider the don't-care conditionscombinations of inputs or input sequences may never occurtwo incompletely specified states that can be combined are said to be compatiblefor each possible input they have the same output whenever specified and their next states are compatible whenever they are specifieddetermine all compatible pairsfind the maximal compatiblesfind a minimal closed covering

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Compatible pairs(a,b) (a,c) (a,d) (b,e) (b,f) (c,d) (e,f)

Fig. 9.23Flow and implication tables

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Maximal compatiblesa group of compatibles that contains all the possible combinations of compatible statesmerger diagramFig. 9.24Merger diagram

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an isolated dot: a state that is not compatible to any other statea line: a compatible paira triangle: a compatible with three statesan n-state compatible: an n-sided polygon with all its diagonals connectedFig. 9.24Merger diagram

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Closed covering conditioncover all the statesclosedno implied states or the implied states are included within the set(a,c,d) (b,e,f)cover all the statesno implied statesanother example

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Fig. 9.25Choosing a set of compatibles

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(a,b) (c,d,e)cover all the statesbut not closed(b,c) are implied but not included(a,d) (b,c) (c,d,e)cover all the statesclosedimplied states: (b,c) (d,e) (a,d)the same state can be repeated more than once

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9-6 Race-Free State AssignmentTo avoid critical racesonly one variable changes at any given timeThree-row flow-table exampleflow-table and transition diagram example

Fig. 9.26Three-row flow-table example

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an extra row is addedno stable state in row d

Fig. 9.27Flow-table with an extra row

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Fig. 9.28Flow-table with an extra rowTransition Table

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Four-row flow-table exampleflow-table and transition diagram

Fig. 9.29Four-row flow-table example

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add extra rows

Fig. 9.30Choosing extra rows for the flow table

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the modified flow table

Fig. 9.31State assignment to modified flow table

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Multiple-row methodless efficientmultiple equivalent states for each state

Fig. 9.32Multiple-row assignment

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9-7 HazardsUnwanted switching transients at the outputdifferent paths exhibit different propagation delaystemporary false-output value in combinational circuitsmay result in a transition to a wrong stable state in asynchronous sequential circuits

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Hazards in combinational circuitsexamples

Fig. 9.33Circuits with hazards

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static 1-hazard (sum of products)the removal of static 1-hazard guarantees that no static 0-hazards or dynamic hazards

Fig. 9.34Types of hazards

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static 0-hazard (product of sum)Y = (x1+x2')(x2+x3)The remedythe circuit moves from one product term to anotheradditional redundant gate

Fig. 9.35Maps illustrating a hazard and its removal

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Hazard-free circuitFig. 9.36Hazard-free circuit

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Hazards in sequential circuitsin general, no problem for synchronous designan asynchronous exampleFig. 9.37Hazard in a asynchronous sequential circuit

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111 110111 010Implementation with SR latchesa momentary 0 signal at the S or R inputs of NOR latch has no effecta momentary 1 signal at the S or R inputs of NAND latch has no effect

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Implementation with SR latchesFig. 9.38Latch implementation

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Implementation with SR latches For NAND SR latch:

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Essential Hazardsasynchronous sequential circuitsunequal delays along two or more paths that originate from the same inputcannot be corrected by adding redundant gatesthe delay of feedback loops > delays of other signals that originate from the input terminals

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Summary of design procedureState the design spec.Derive the primitive flow tableReduce the flow table by merging the rowsRace-free state assignmentObtain the transition table and output mapObtain the logic diagram using SR latches

9.8 Design Example

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Design Specification

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Primitive Flow tableFig. 9.39Primitive flow table

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Merging of the Flow TableFig. 9.40Implication table Compatible pairs: Maximal compatible set:

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Merging of the Flow TableFig. 9.41Merger diagram

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Merging of the Flow TableFig. 9.42Reduced flow table

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State Assignment and Transition TableFig. 9.43Transition diagram

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State Assignment and Transition TableFig. 9.44Transition table and output map

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Logic DiagramFig. 9.45Maps for latch inputs

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Logic DiagramFig. 9.46Logic diagram of negative-edge-triggered T flip-flop