7/28/2019 99046

1/12

Features Built using the advantages and compatibility

of CMOS and IXYS HDMOS

TM

processes Latch-Up Protected up to 0.5A High Peak Output Current: 4A Peak Wide Operating Range: 4.5V to 35V Ability to Disable Output under Faults High Capacitive Load

Drive Capability: 1800pF in

7/28/2019 99046

2/12

2

IXDD404

Unless otherwise noted, TA= 25 oC, 4.5V V

CC 35V.

All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel.

Electrical Characteristics

Symbol Parameter Test Conditions Min Typ Max Units

VIH High input voltage 4.5V VIN 18V 2.5 V

VIL Low input voltage 4.5V VIN 18V 0.8 V

VIN Input voltage range -5 VCC + 0.3 V

IIN Input current 0V VIN VCC -10 10 A

VOH High output voltage VCC - 0.025 V

VOL Low output voltage 0.025 V

ROH Output resistance@ Output high

VCC = 18V 2 2.5

ROL Output resistance@ Output Low

VCC = 18V 1.5 2

IPEAK Peak output current VCC = 18V 4 A

IDC Continuous outputcurrent

1 A

VEN Enable voltage range - 0.3 Vcc + 0.3 V

VENH High En Input Voltage 2/3 Vcc V

VENL Low En Input Voltage 1/3 Vcc V

tR Rise time CL=1800pF Vcc=18V 16 18 ns

tF Fall time CL=1800pF Vcc=18V 13 17 ns

tONDLY On-time propagationdelay

CL=1800pF Vcc=18V 36 40 ns

tOFFDLY Off-time propagationdelay

CL=1800pF Vcc=18V 35 39 ns

tENOH Enable to output highdelay time

30 ns

tDOLD Disable to output lowDisable delay time

30 ns

VCC Power supply voltage 4.5 18 35 V

ICC Power supply current VIN = 3.5VVIN = 0VVIN = + VCC

10

31010

mA

AA

REN Enable Pull-up Resistor 200 k

Absolute Maximum Ratings (Note 1)Parameter Value

Supply Voltage 40 VAll Other Pins -0.3 V to VCC + 0.3 V

Junction Temperature 150 oCStorage Temperature -65 oC to 150 oCLead Temperature (10 sec) 300 oC

Operating RatingsParameter alue

Operating Temperature Range -55 oC to 125 oCThermal Impedance (Junction to Ambient)8 Pin PDIP (PI) (JA) 12 0 oC/W8 Pin SOIC (SIA) (JA) 11 0 oC/W

8 Pin SOIC (SI) (JA) with heat sink**Heat sink area of 1cm 2 71 oC/W

16 Pin SOIC (SIA-16) (JA) 11 0 oC/W

Note 1: Operating the device beyond parameters with listed absolute maximum ratings may cause permanentdamage to the device. Typical values indicate conditions for which the device is intended to be functional, but do notguarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Specifications to change without notice

**Heat sink area is 1 oz. copper on one side of .06" thick

FR4 soldered to metal back plane.

7/28/2019 99046

3/12

3

IXDD404

Symbol Parameter Test Conditions Min Typ Max Units

VIH High input voltage 2 V

VIL

Low input voltage 2.4 V

VIN Input voltage range -5 VCC + 0.3 V

IIN Input current 0V VIN VCC -10 10 A

VOH High output voltage VCC - 0.025 V

VOL Low output voltage 0.025 V

ROH Output resistance@ Output high

VCC = 18V 3.4

ROL Output resistance@ Output Low

VCC = 18V 2

IPEAK Peak output current VCC = 18V 3.2 A

IDC Continuous outputcurrent

1 A

tR Rise time CL=1000pF Vcc=18V 11 ns

tF Fall time CL=1000pF Vcc=18V 13 ns

tONDLY On-time propagationdelay

CL=1000pF Vcc=18V 60 ns

tOFFDLY Off-time propagationdelay

CL=1000pF Vcc=18V 59 ns

VCC Power supply voltage 4.5 18 35 V

ICC Power supply current VIN = 3.5VVIN = 0V

VIN = + VCC

10

310

10

mA

A

A

Unless otherwise noted, temperatureover -55 oC to 150 oC, 4.5V V

CC 35V.

All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel.

Electrical Characteristics

Specifications to change without notice

7/28/2019 99046

4/12

4

IXDD404

Pin Description

SYMBOL FUNCTION DESCRIPTION

EN A A Channel EnableThe Channel A enable pin. This pin, when driven low, disables the AChannel, forcing a high impedance state to the A Channel Output.

IN A A Channel Input A Channel Input signal-TTL or CMOS compatible.

GND GroundThe system ground pin. Internally connected to all circuitry, this pin providesground reference for the entire chip. This pin should be connected to a lownoise analog ground plane for optimum performance.

IN B B Channel Input B Channel Input signal-TTL or CMOS compatible.

OUT B B Channel OutputB Channel Driver output. For application purposes, this pin is connected,through a resistor, to Gate of a MOSFET/IGBT.

VCC Supply VoltagePositive power-supply voltage input. This pin provides power to the entirechip. The range for this voltage is from 4.5V to 35V.

OUT A A Channel OutputA Channel Driver output. For application purposes, this pin is connected,through a resistor, to Gate of a MOSFET/IGBT.

EN B B Channel EnableThe Channel B enable pin. This pin, when driven low, disables the BChannel, forcing a high impedance state to the B Channel Output.

Figure 2 - Characteristics Test Diagram

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when

handling and assembling this component.

VIN

EN A

IN A

GND

IN B

EN B

OUT A

OUT B

VCC

1

2

3

4

8

7

6

5

I

X

D

D

4

0

4

SO8 (SI)

8 PIN DIP (PI)SO16 (SI-16)

Pin Configurations

7/28/2019 99046

5/12

5

IXDD404

Max / M in Input vs. TemperatureCL = 1000pF, V cc = 18V

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

-60 -10 40 90 140 190

Temperature (C)

Max/MinInputVoltage

Min Input High

Max Input Low

Rise And Fall Times vs. TemperatureCL = 1000pF, Vcc = 18V

0

2

4

6

8

10

12

14

-60 -10 40 90 140 190

Temperature (C)

Time(ns)

tF

tR

Rise Times vs. Load Capacitance

0

10

20

30

40

50

60

70

80

0 2000 4000 6000 8000 10000

Load Capacitance (pF)

RiseTime(ns)

8V

10V

12V

18V

25V35V

Rise Times vs. Supply Voltage

0

10

20

30

40

50

60

70

80

5 10 15 20 25 30 35

Supply Voltage (V)

RiseTime(ns)

200pF

1000pF

1800pF

4700pF

6800pF

10000pF

Fall Times vs. Supply Voltage

0

10

20

30

40

50

60

70

80

5 10 15 20 25 30 35

Supply Voltage (V)

FallTimes(ns)

200pF1000p

1800pF

4700pF

6800p

10000p

Typical Performance Characteristics

Fig. 3 Fig. 4

Fig. 5 Fig. 6

Fig. 7 Fig. 8

Fall Times vs. Load Capacitance

0

10

20

30

40

50

60

70

80

0 2000 4000 6000 8000 10000

Load Capacitance (pF)

FallTime(ns)

8V

10V

12V

18V

25V

35V

7/28/2019 99046

6/12

6

IXDD404Supply Current vs. Frequency

Vcc = 8V

0.01

0.1

1

10

100

1000

1 10 100 1000 10000

Frequency (kHz)

SupplyCurrent(m

a)

200 pF1000 pF

1800 pF4700 pF

6800 pF

10000 pF

Fig. 10

Fig. 12

Fig. 14

Supply Current vs. Load CapacitanceVcc = 8V

0

10

20

30

40

50

60

70

80

90

100

100 1000 10000

Load Capacitance (pF)

SupplyCurrent(m

A)

10 kHz50 kHz

100 kHz

500 kHz

1 MHz

2 MHz

Supply Current vs. Load CapacitanceVcc = 12V

0

10

20

30

40

50

60

70

80

90

100

100 1000 10000

Load Capacitance (pF)

SupplyCurrent(mA)

10 kHz

50 kHz

100 kHz

500 kHz

1 Mhz2 MHz

Supply Current vs. Load CapacitanceVcc = 18V

0

10

20

30

40

50

60

70

80

90

100

100 1000 10000

Load Capacitance (pF)

SupplyCurrent(mA)

10 kHz

50 kHz

100 kHz

500 kHz1 MHz2 MHz

Supply Current vs. FrequencyVcc = 12V

0.01

0.1

1

10

100

1000

1 10 100 1000 10000

Frequency (kHz)

SupplyCurrent(ma)

200 pF1000 pF

1800 pF

4700 pF6800 pF

10000 pF

Supply Current vs. FrequencyVcc = 18V

0.01

0.1

1

10

100

1000

1 10 100 1000 10000

Frequency (kHz)

SupplyCurrent(ma)

200 pF1000 pF

1800 pF

6800 pF10000 pF

4700 pF

Fig. 9

Fig. 11

Fig. 13

7/28/2019 99046

7/12

7

IXDD404

Quiescent Supply Current vs. Temperature

Vcc = 18V, Vin = 5V@1kHz, CL = 1000pF

0

0.05

0.1

0.15

0.2

0.25

0.3

-60 -10 40 90 140 190

Temperature (C)

QuiescentV

cc

InputCurrent(mA)

Propagation Delay vs. Input V oltageCL = 1800pF Vcc = 15V

20

25

30

35

40

45

50

2 4 6 8 10 12

Input Voltage (V)

PropagationDelay(ns) tONDLY

tOFFDLY

Propagation Delay vs. Supply VoltageCL = 1800pF Vin = 5V@1kHz

0

10

20

30

40

50

60

70

5 10 15 20 25 30 35

Supply Voltage (V)

PropagationDelay(ns)

tONDLY

tOFFDLY

Supply Current vs. FrequencyVcc = 35V

0.01

0.1

1

10

100

1000

1 10 100 1000 10000

Frequency (kHz)

SupplyCurrent(m

A)

200 pF

1000 pF

1800 pF

4700 pF

6800 pF

10000 pF

Supply Current vs. Load CapacitanceVcc = 35V

0

10

20

30

40

50

60

70

80

90

100

100 1000 10000

Load Capacitance (pF)

SupplyCurrent(m

A)

10 kHz

50 kHz

100 kHz

1 MHz

500 kHz

2 MHz

Fig. 16Fig. 15

Fig. 17 Fig. 18

Fig. 19

Fig. 20

DLY

Propagation Delay T imes vs. T emperatureCL = 1000pF, Vcc = 18V

20

25

30

35

40

45

50

55

60

-60 -10 40 90 140 190

Temperature (C)

Time(ns)

tONDLY

tOFFDLY

7/28/2019 99046

8/12

8

IXDD404

Vcc vs. N Channel Ouput Current

0

2

4

6

8

10

12

14

5 10 15 20 25 30 35

Vcc (V)

N

ChannelOutputCurrent(A)

P Channel Output Current vs. TemperatureVcc = 18V, CL = 1000pF

0

1

2

3

4

5

6

-80 -30 20 70 120 170

Temperature (C)

PChannelOutputCu

rrent(A)

Vcc vs. P Channel Output Current

-12

-10

-8

-6

-4

-2

0

5 10 15 20 25 30 35

Vcc (V)

P

ChannelOutputCurrent(A)

Low State Output Resistance vs. Supply Voltage

0

1

2

3

4

5

6

5 10 15 20 25 30 35

Supply Voltage (V)

Low

StateOutputResistanc

e(Ohms)

High State Ouput Resistance vs. Supply Voltage

0

1

2

3

4

5

6

5 10 15 20 25 30 35

Supply Voltage (V)

HighStateOutputResistan

ce(Ohms)

Fig. 21 Fig. 22

Fig. 23 Fig. 24

Fig. 25N Channel Output Current vs. Temperature

Vcc = 18V CL = 1000pF

0

1

2

3

4

5

6

-80 -30 20 70 120 170

Temperature (C)

N

ChannelOutputCu

rrent(A)

Fig. 26

7/28/2019 99046

9/12

9

IXDD404

Figure 28 - Typical Application Short Circuit di/dt Limit

Enable Threshold vs. Supply Voltage

0

2

4

6

8

10

12

14

16

18

20

0 5 10 15 20 25 30 35 40

Supply Voltage (V)

EnableThreshold(V)

Fig. 27

7/28/2019 99046

10/12

10

IXDD404APPLICATIONS INFORMATION

Short Circuit di/dt Limit

A short circuit in a high-power MOSFET such as the IXFN100N20,(20A, 1000V), as shown in Figure 26, can cause the currentthrough the module to flow in excess of 60A for 10s or moreprior to self-destruction due to thermal runaway. For thisreason, some protection circuitry is needed to turn off the

MOSFET module. However, if the module is switched off toofast, there is a danger of voltage transients occuring on thedrain due to Ldi/dt, (where L represents total inductance inseries with drain). If these voltage transients exceed theMOSFET's voltage rating, this can cause an avalanche break-down.

The IXDD404 has the unique capability to softly switch off thehigh-power MOSFET module, significantly reducing theseLdi/dt transients.

Thus, the IXDD404 helps to prevent device destruction frombothdangers; over-current, and avalanche breakdown due to

di/dt induced over-voltage transients.

The IXDD404 is designed to not only provide 4A per outputunder normal conditions, but also to allow it's outputs to go intoa high impedance state. This permits the IXDD404 output tocontrol a separate weak pull-down circuit during detectedovercurrent shutdown conditions to limit and separately con-trol d

VGS/dt gate turnoff. This circuit is shown in Figure 27.

Referring to Figure 27, the protection circuitry should includea comparator, whose positive input is connected to the sourceof the IXFD100N20. A low pass filter should be added to theinput of the comparator to eliminate any glitches in voltage

caused by the inductance of the wire connecting the sourceresistor to ground. (Those glitches might cause false triggeringof the comparator).

The comparator's output should be connected to a SRFF(SetReset Flip Flop). The flip-flop controls both the Enable signal,and the low power MOSFET gate. Please note that CMOS 4000-series devices operate with a V

CCrange from 3 to 15 VDC, (with

18 VDC being the maximum allowable limit).

A low power MOSFET, such as the 2N7000, in series with aresistor, will enable the IXFN100N20 gate voltage to dropgradually. The resistor should be chosen so that the RC timeconstant will be 100us, where "C" is the Miller capacitance ofthe IXFN100N20.

For resuming normal operation, a Reset signal is needed atthe SRFF's input to enable the IXDD404 again. This Reset can

be generated by connecting a One Shot circuit between theIXDD408 Input signal and the SRFF restart input. The One Shotwill create a pulse on the rise of the IXDD404 input, and thispulse will reset the SRFF outputs to normal operation.

When a short circuit occurs, the voltage drop across the low-value, current-sensing resistor, (Rs=0.005 Ohm), connectedbetween the MOSFET Source and ground, increases. Thistriggers the comparator at a preset level. The SRFF drives a lowinput into the Enable pin disabling the IXDD404 output. TheSRFF also turns on the low power MOSFET, (2N7000).

In this way, the high-power MOSFET module is softly turned offby the IXDD404, preventing its destruction.

10uH

Ld

0.1ohm

Rd

Rs

20nH

Ls

1ohm

Rg

10kohm

R+

IXFN100N20

High_Power

5kohmRcomp

100pF

C+

+

-

V+

V-

Comp

LM339

1600ohm

Rsh

Ccomp

1pF

VCCVCCA

INEN

DGNDSUB

OUT

IXDD404

+

-VIN

+

-VCC

+

-REF

+

-VB

CD4001ANOR2

1Mohm

Ros

NOT2CD4049ACD4011A

NAND

CD4049A

NOT1

CD4001ANOR1

CD4049A

NOT3

Low_Power

2N7002/PLP

1pFCos

0

S

R

EN

Q

One ShotCircuit

SR Flip-Flop

Figure 29 - Application Test Diagram

7/28/2019 99046

11/12

11

IXDD404

10K R3

3.3K R2

Q12N3904

ENOutput

CC

(From Gate DriverPower Supply)

Input)TTL

CMOS3.3K R1VDD

(From LogicPower Supply)

or

High Voltage

(To IXDD404EN Input)

Supply Bypassing and Grounding Practices,

Output Lead inductance

When designing a circuit to drive a high speed MOSFETutilizing the IXDD404, it is very important to keep certain designcriteria in mind, in order to optimize performance of the driver.Particular attention needs to be paid to Supply Bypassing,Grounding, and minimizing the Output Lead Inductance.

Say, for example, we are using the IXDD404 to charge a 2500pFcapacitive load from 0 to 25 volts in 25ns .

Using the formula: I= V C / t, where V=25V C=2500pF &t=25ns we can determine that to charge 2500pF to 25 volts in25ns will take a constant current of 2.5A. (In reality, the chargingcurrent wont be constant, and will peak somewhere around4A).

SUPPLY BYPASSING

In order for our design to turn the load on properly, the IXDD404must be able to draw this 2.5A of current from the power supplyin the 25ns. This means that there must be very low impedancebetween the driver and the power supply. The most commonmethod of achieving this low impedance is to bypass the powersupply at the driver with a capacitance value that is a magnitudelarger than the load capacitance. Usually, this would beachieved by placing two different types of bypassing capacitors,with complementary impedance curves, very close to the driveritself. (These capacitors should be carefully selected, lowinductance, low resistance, high-pulse current-servicecapacitors). Lead lengths may radiate at high frequency dueto inductance, so care should be taken to keep the lengths ofthe leads between these bypass capacitors and the IXDD404to an absolute minimum.

GROUNDINGIn order for the design to turn the load off properly, the IXDD404must be able to drain this 2.5A of current into an adequategrounding system. There are three paths for returning currentthat need to be considered: Path #1 is between the IXDD404and its load. Path #2 is between the IXDD404 and its powersupply. Path #3 is between the IXDD404 and whatever logicis driving it. All three of these paths should be as low inresistance and inductance as possible, and thus as short aspractical. In addition, every effort should be made to keep thesethree ground paths distinctly separate. Otherwise, (forinstance), the returning ground current from the load maydevelop a voltage that would have a detrimental effect on thelogic line driving the IXDD404.

OUTPUT LEAD INDUCTANCE

Of equal importance to Supply Bypassing and Grounding areissues related to the Output Lead Inductance. Every effortshould be made to keep the leads between the driver and itsload as short and wide as possible. If the driver must be placedfarther than 2 from the load, then the output leads should betreated as transmission lines. In this case, a twisted-pairshould be considered, and the return line of each twisted pair

should be placed as close as possible to the ground pin of thedriver, and connect directly to the ground terminal of theload.

TTL to High Voltage CMOS Level Translation

The enable (EN) input to the IXDD404 is a high voltageCMOS logic level input where the EN input threshold is V

CC, and may not be compatible with 5V CMOS or TTL input

levels. The IXDD404 EN input was intentionally designedfor enhanced noise immunity with the high voltage CMOSlogic levels. In a typical gate driver application, V

CC=15V

and the EN input threshold at 7.5V, a 5V CMOS logical highinput applied to this typical IXDD404 applications EN inputwill be misinterpreted as a logical low, and may causeundesirable or unexpected results. The note below is foroptional adaptation of TTL or 5V CMOS levels.

The circuit in Figure 28 alleviates this potential logic levelmisinterpretation by translating a TTL or 5V CMOS logicinput to high voltage CMOS logic levels needed by theIXDD404 EN input. From the figure, V

CCis the gate driver

power supply, typically set between 8V to 20V, and VDD

is thelogic power supply, typically between 3.3V to 5.5V.Resistors R1 and R2 form a voltage divider network so thatthe Q1 base is positioned at the midpoint of the expected

TTL logic transition levels.

A TTL or 5V CMOS logic low, VTTLLOW

=~1K pieces. It isrecommended that the physical placement of the leveltranslator circuit be placed close to the source of the TTL orCMOS logic circuits to maximize noise rejection.

Figure 30 - TTL to High Voltage CMOS Level Translator

7/28/2019 99046

12/12

12

IXDD404

IXYS Semiconductor GmbHEdisonstrasse15 ; D-68623; LampertheimTel: +49-6206-503-0; Fax: +49-6206-503627e-mail: marcom@ixys.de

IXYS Corporation3540 Bassett St; Santa Clara, CA 95054Tel: 408-982-0700; Fax: 408-496-0670e-mail: sales@ixys.net

Dimenional Outline: IXDD404PI

Dimenional Outlines: IXDD404SI-CT and IXDD404SIA

Dimenional Outlines: IXDD404SI-16CT and IXDD404SIA-16