A 1 GS/s 6-bit Time-Based Analog-to-Digital

Converter (T-ADC) for Front-End Receivers

Ali H. Hassan1, Ahmed Ali2, M. Wagih Ismail3, Mohamed Refky4, Yehea Ismail5, and Hassan Mostafa6 1,2,4,6Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt

3Department of Electrical and Computer Engineering, University of Toronto 5,6Center for Nanoelectronics and Devices, AUC and Zewail City of Science and Technology, New Cairo 11835, Egypt

Email: {ali.h.hassan@ieee.org, wagih.ismail@mail.utoronto.ca, refky@eng.cu.edu.eg, y.ismail@aucegypt.edu,

hmoustafa@aucegypt.edu, and hmostafa@uwaterloo.ca}

Abstract— Recently, researchers are targeting low-power

consumption, and integrating more blocks on-chip. This paper

proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-

ADC) for front-end receivers. This T-ADC eliminates the pre-

processing analog blocks, and reduces power consumption by

removing the power-hungry sample and hold circuit. A prototype of

the proposed T-ADC is implemented in 65nm CMOS technology,

where it consumes 1 mW and achieves a maximum SNDR of 35.5 dB

with sampling rate 1 GHZ that corresponds to a Figure of Merit (FoM)

of 20.62 fJ/step.

Keywords— Time-Based ADC, Inherit sample and hold, front end

receivers, voltage-to-time converter, time-to-digital converter.

I. INTRODUCTION

Analog-to-Digital Converter (ADC) is considered one of

the most essential blocks in Software Defined Radio (SDR),

Ultra-Wide Band (UWB) receivers, biomedical applications,

and embedded systems. The majority of the Integrated Circuits

(ICs) today are mixed analog/digital systems to get benefit from

the growing capabilities in Digital Signal Processing (DSP).

The DSP is preferred to the analog signal processing in many

different ways such as: power consuming and processing speed.

Thus, the main target is to decrease the analog processing

blocks and increase the digital processing blocks in the

aforementioned systems.

Decreasing the percentage of the analog part and increasing

the percentage of the digital part in integrated circuits is the

current trend and is highly recommended to maximize the

benefit of the unceasing CMOS technology scaling. The

unceasing CMOS technology scaling makes transistors channel

length shorter and increases transistors integration density

leading to supply voltage reduction. This reduction in supply

voltage increases the difficulties imposed on the analog circuit

design because the threshold voltage and the noise level do not

scale with the same factor as the supply voltage. Therefore, the

digital circuits are preferred to the analog circuits in deep sub-

micron technology. The switching time becomes smaller and

the circuits that depend on time resolution get a superior

accuracy over the analog circuits.

The time-based ADC (T-ADC) has the advantage of being

highly digitally oriented, thus the scaling of CMOS which

provides better timing accuracy with low power consumption

at high frequencies is a fundamental advantage to it as opposed

to traditional analog circuits.

The T-ADC converts the analog signal to a time delay

representation through a Voltage-to-Time Converter (VTC).

Then, the time-represented signal is converted to digital code

through a Time-to-Digital Converter (TDC). The main idea is

to scale the input voltage 𝑉𝑖𝑛 into a difference between the input

rising edge and the input reference signal. This delay difference

is digitized using a TDC that divide the delay difference into

constant delay steps to be digitized into a digital word.

The rest of the paper is organized as follows. In Section II,

the proposed circuit implementation of each block of T-ADC is

presented, and the chip layout as well as the simulation results

are provided in Section III. Finally, a conclusion is drawn in

Section IV.

II. CIRCUIT IMPLEMENTATION

Fig. 1 Half-Cell VTC Circuit Schematic

A. VTC

Voltage-to-time conversion is the process of sampling an

analog input voltage and converting it into a pulse width

modulated signal. Thus, VTC output is referred either a pulse

position modulator (PPM) or pulse width modulator (PWM)

[1]. Fig. 1 portrays the half-cell schematic of the implemented

VTC circuit, where the first current starved inverter is used to

provide a fixed delay to the falling edge of the input clock.

While the second starved inverter varies the rising edge of its

978-1-5090-6389-5/17/$31.00 ©2017 IEEE 1605

input according to 𝑉𝑖𝑛 , shown in Fig. 2, where biasing

voltage 𝑉𝑐𝑜𝑛𝑠𝑡 is used to control operation region of VTC half-

cell. This provides a time window long enough for the

conversion.

Fig. 2 Output signal with different 𝑉𝑖𝑛

Fig.3 displays the proposed differential VTC circuit that

consists of two identical half-cells, where one of them

processes on the input voltage signal, and the other half-cell

processes on reference voltage signal. The identical two half-

cell VTC circuits are used to generate the two triggering pulses

for the TDC (𝐼𝑛𝑃 𝑎𝑛𝑑 𝐼𝑛𝑁), where 𝐼𝑛𝑃 is modulated by 𝑉𝑖𝑛, and

𝐼𝑛𝑁 is the reference signal.

Fig. 3 VTC Core Block Diagram

VTC introduces a non-linearity and distortion to the output

modulated signal that affects the T-ADC resolution. In order to

increase linearity, and reduce the VTC circuit mismatch: 1) the

main current starving transistor M3 is linearized using source

degeneration that is implemented by cascoding transistor M6,

and 2) the parallel transistors (M4 and M5) with different gate

bias voltages are used in order to ease the compression of the

pulse delay time versus input voltage characteristic at high

input voltages. Using only source degeneration for linearizing,

and increasing the width of the main current starved transistor

(M3) results in a VTC insensitive to the input voltage as the

VTC circuit with the enhanced linearization scheme [2].

Fig. 4, shows the output delay versus the input voltage

𝑉𝑖𝑛 that changes from -86.1 mV to 86.1 mV providing dynamic

input voltage range of 172.2 mV, while achieving the linearity

error less than 3%.

Fig. 4 Linear range of operation

B. TDC

The TDC is used to convert the output delay produced by

the differential VTC into a thermometer code that is encoded

into a binary code. TDC is designed using 6-bit Vernier delay

line architecture [3] that consists of 63 differential delay stages.

Each stage consists of tunable differential delay cell, and sense-

amplifier D-flip-flop [4] as shown in Fig. 5. Each delay stage

of TDC provides a constant delay step (𝑡𝛿) which is given by:

𝑡𝛿 =𝑂𝑢𝑡𝑝𝑢𝑡 𝐷𝑒𝑙𝑎𝑦 𝑅𝑎𝑛𝑔𝑒

2𝑁−𝑏𝑖𝑡𝑠 = 216.5

26 = 3.38 ps

Fig. 5 6-bits Vernier Delay Line

The proposed TDC, shown in Fig. 7, has two input signals

one positive (𝐼𝑛𝑃) signal and another negative signal (𝐼𝑛𝑁). The

delay cells are used to digitize the delay between the 𝐼𝑛𝑃 and

the 𝐼𝑛𝑁, where D-flip-flop acts as a phase detector, i.e. If the

𝐼𝑛𝑃 come before the 𝐼𝑛𝑁 the output of the D-flip-flop is logic

one otherwise the output of the D-flip-flop is logic zero. The

first cell is used to delay 𝐼𝑛𝑁 by 31tδ referred to 𝐼𝑛𝑃, while the

other cells only delay its input signals by tδ only till the end of

the delay line. The two input signals are delayed by 31tδ to

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process the output delay range in parallel. Fig. 6 shows an

example, where input phase difference (∆𝑇𝑖𝑛) equals zero.

Fig. 6 Simulated Waveforms of the illustrated Idea

The two propagating signals 𝐼𝑛𝑃 and 𝐼𝑛𝑁 change over 32

delay stages, where the phase difference became again

equivalent to the same phase difference at the input stage after

these 32 delay stages, so we make use of this to divide the delay

line that consists of 63 stages into two parallel lines as shown

in Fig. 7 at the input signals travel through both lines at same

time. This almost doubled the throughput speed of TDC.

Fig. 7 6-bits parallel Vernier Delay Line

The tuneable delay cell, shown in Fig. 8, is implemented

using a current starved inverter circuit which consists of 6

transistors, the basic CMOS inverter which is formed from the

2 transistors M3 and M4 are followed by another inverter

formed from the transistors M5 and M6. The devices M7 and

M8 will operate in saturation region in order to control the

amount of current passing through the first inverter. While the

transistors M1 and M2 are very small compared to M7 and M8,

as they are used to control the beginning of operation of the

current starved inverter circuit.

Fig. 8 Schematic of Tuneable Delay Cell

The tunable delay stage used in the TDC design uses a

current starved inverter to delay the rising and the falling edges

of the input signal by the same amount to maintain a constant

pulse width. Using the tuning voltages (𝑉𝑔𝑁 and 𝑉𝑔𝑃) to adjust

the 63 stages of the T-ADC to compensate the non-idealities of

the VTC and get 63 constant delay stages. Based on [3], the

number of these tuning voltages equal to 63. By analogy, it is

noticed that first cell, the middle cells, and the last cell

experience different loading effect. Based on that the number

of tuning voltages is optimized to be only 3 per delay line.

A 6-bit mux-based thermometer-to-binary encoder is used

to count the number of logic ones in the output thermometer

code, then coverts it to the corresponding binary code. The

mux-based thermometer-to-binary encoder provides lowest

power consumption, smaller area on chip, minimum path delay,

and its architecture is easy to be extended [7].

III. CHIP LAYOUT AND SIMULATION RESULTS

A prototype of the T-ADC is implemented on 65 nm CMOS

technology process as shown in Fig. 9, where the T-ADC

layout is highlighted with the main design blocks. Table I

illustrates the key performance parameters where it shows that

the effective number of bits (ENOB) equals to 5.6 bits using

sampling rate equals 1 GS/s. Moreover, the T-ADC consumes

1 mW from 1V supply. In Fig. 10, fast fourier transform (FFT)

is applied on the output reconstructed signal where the signal

to noise and distortion ratio (SNDR) at different sampling

frequency remains above 30 dB while varying the input signal

frequency.

Fig. 9 T-ADC Chip Layout

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Fig. 10 Output Spectrum due to input frequency = 110 MHz without sample

and hold circuit

Walden in [6] defined a Figure of Merit (FoM) to make a

fair comparison with other ADCs operating at different speeds

and resolutions is:

FoM= 𝑃

2𝐸𝑁𝑂𝐵∗ 𝐹𝑠

Where P is the power consumption, and 𝑓𝑠 is the sampling

frequency. Based on the shown comparison in Table II with

state-of-the-art ADCs, this T-ADC has one of the best power

efficiencies.

IV. CONCLUSION

Using 1V supply and 65 nm CMOS process technology,

A 1 GS/s 6-bit T-ADC is introduced for low-power, high-speed

front-end receivers. In this T-ADC, the proposed VTC

enhanced the sensitivity up to 1.25 ps/mV that fulfills the TDC

time resolution of wide range of applications. Moreover, the

proposed TDC circuit doubles the throughput to achieve a high

resolution with high sampling rate. This T-ADC helps in

decreasing the analog part, and increasing the digital part in the

circuits to save time and effort in the design cycle, and make

use of technology scaling.

ACKNOWLEDGMENT

This research was partially funded by Cairo University,

ITIDA, NTRA, NSERC, Zewail City of Science and

Technology, AUC, the STDF, Intel, Mentor Graphics, SRC,

ASRT and MCIT.

REFERENCES

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TABLE I: T-ADC Performance

Technology Process TSMC 65 nm CMOS

Sampling Rate 1 GHZ

Resolution 6 bits

ENOB @ 150 MHZ 5.6

Input Dynamic Range 172.2 mVpp

Supply Voltage 1 V

Power Consumption 1 mW

Area 0.024 𝑚𝑚2

TABLE II: Performance Comparison of State of the Art ADCs

Reference Architecture Technology Process Power Resolution 𝑭𝒔 FOM (fJ/conv. Step)

[5] Delay-Line 65 nm 2 mW 4 1.2 GS/s 196

[8] Delay-Line 65 nm 1.8 mW 6 500 MS/s 74

[9] Async. SAR 65 nm 6.7 mW 6 1 GS/s 209

[10] 2b/cycle SAR 65 nm 4 mW 8 400 MS/s 73

[11] pipelined SAR 65 nm 11.1 mW 13 160 MS/s 41.6

[12] T-ADC 65 nm 1.9 mW 8 200 MS/s 39.7

This Work T-ADC 65 nm 1 mW 6 1 GS/s 20.62

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