IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018 1999
A 2-MHz BW 82-dB DR Continuous-TimeDelta–Sigma Modulator With a Capacitor-
Based Voltage DAC for ELD CompensationSusie Kim, Seung-In Na, Youngtae Yang, and Suhwan Kim , Senior Member, IEEE
Abstract— In this paper, we present a third-order nine-levelcontinuous-time delta–sigma modulator, in which a capacitor-based voltage digital-to-analog converter is used to compensatefor excess loop delay of up to half a clock period, with margins of±30%. To evaluate its effectiveness, the prototype is implementedin 65-nm CMOS technology with an active area of 0.516 mm2.The experimental results show a dynamic range (DR) of 82 dB,a signal-to-noise ratio of 75.8 dB, a signal-to-noise-and-distortionratio of 72.1 dB, and a spurious-free DR of 78.8 dB at a samplingfrequency of 128 MHz and a bandwidth of 2 MHz. The totalpower consumption is 3.8 mW from a 1.2-V supply.
Index Terms— Capacitor-based voltage digital-to-analog con-verter (CV-DAC), continuous-time delta–sigma modulator(CTDSM), excess loop delay (ELD), wireless.
I. INTRODUCTION
THE wireless electronics market has experiencedremarkable growth over the last decade, fueling demand
for low-power, wide-bandwidth (BW), and high-resolutionanalog-to-digital converters (ADCs). A modern ADC isrequired to achieve BW in the megahertz range and adynamic range (DR) of at least over 74 dB [1]. The delta–sigma configuration is one of the best ways of meeting theserequirements. There are two types of delta–sigma ADC:one is the discrete-time (DT) delta–sigma ADC, but this isbased on switched-capacitor circuits, which limit its samplingfrequency; the other is the continuous-time (CT) delta–sigmaADC, in which sampling occurs inside the feedback loop, andthe sample-and-hold errors are noise shaped. CT delta–sigmaADCs have the additional advantage of inherent antialiasingproperties.
However, CT delta–sigma ADCs also have disadvantages:high sensitivity to clock jitter, nonlinearity of the feed-back digital-to-analog converter (DAC), and excess loopdelay (ELD). Using a multibit quantizer can reduce thesensitivity to clock jitter by reducing the step size in the
Manuscript received January 24, 2018; revised April 21, 2018; acceptedMay 15, 2018. Date of publication June 7, 2018; date of current versionSeptember 25, 2018. This work was supported in part by the IC DesignEducation Center and in part by the Inter-university Semiconductor ResearchCenter of Seoul National University. (Corresponding author: Suhwan Kim.)
S. Kim, Y. Yang, and S. Kim are with the Department of Electrical andComputer Engineering, Seoul National University, Seoul 08826, South Korea(e-mail: [email protected]).
S.-I. Na is with Samsung Electronics, Hwaseong 18448, South Korea.Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2018.2841058
feedback waveform and makes higher order modulator morestable for large signal [2]. Nonlinearity issues in multibitfeedback DACs can be addressed by dynamic element match-ing (DEM) techniques; and the provision of providing anadditional high supply voltage to the feedback DAC can alsomitigate its nonlinearity [3], [4], but this requires an extralevel-shifter circuit, which increases propagation delay, powerconsumption, and the active area [5]. Combining a single-bitquantizer with a finite impulse response (FIR) DAC [6] isan alternative way of improving linearity, which also reducessensitivity to clock jitter. However, a FIR DAC requires anadditional compensation FIR DAC to recover the transformednoise transfer function (NTF).
ELD is inherent in CT delta–sigma ADCs, and it degradesboth the performance and stability of the modulator. The ELDcompensation is not necessary if the ELD is small and theoversampling ratio (OSR) is high [7]. Since the high OSRincreases the sampling frequency and power consumption, it isinevitable to use a multibit modulator to achieve the targetspecifications with low OSR in wireless applications. Theeffect of ELD increases with speed and becomes even moresevere, including the nonlinearities of the multibit feedbackDACs. Asynchronous SAR (ASAR) quantizers and digitalmodulation techniques can be used instead of flash quantizersto save power and area [2], [3], but these circuits introduce fur-ther logic delays which limit the sampling frequency [8], [9].Several techniques have been introduced to mitigate the effectof ELD. A low-latency DEM can be used [10] to reduce thedelay between the quantizer and the feedback DAC, and adirect feedback path around the quantizer can be used [11]to compensate for the fixed delay between the quantizer andthe feedback DAC, but the latter requires an additional adder.An adder can be eliminated by routing a compensation pathto the input of the final integrator [12] or utilizes the residualsignal for ELD compensation [3]. The ELD compensationsare implemented in current mode by a combination of currentDACs and resistors, but sensitive to process and temperaturevariations.
To alleviate the effect of process and temperature varia-tions on ELD, we propose a third-order nine-level CT delta–sigma modulator (CTDSM) with a capacitor-based voltageDAC (CV-DAC). Its ELD is compensated with sufficientaccuracy since the coefficient for ELD compensation KELDis set to the ratio of the capacitance of the CV-DAC to the
2000 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018
Fig. 1. (a) Proposed behavioral-level design procedure. (b) Behavioral-level model of a CTDSM.
feedback capacitance of the final integrator, which is largelyunaffected by process and temperature variations.
The rest of this paper is organized as follows. In Section II,we present an architecture and its behavioral-level design witha model of nonidealities. Section III describes the specificcircuit implementation of our CTDSM using CV-DAC forELD compensation. Experimental results of our CTDSM aregiven in Section IV. Section V concludes this paper.
II. ARCHITECTURE AND BEHAVIORAL-LEVEL DESIGN
The delta–sigma toolbox is a well-established open-sourcelibrary for high-level design and simulation of delta–sigmamodulators. However, when it is used to design a CTDSM,there is an issue in scaling the coefficients. The realizeNTF_ct function converts an NTF from the DT domain to theCT domain using an impulse-invariant transformation (IIT).However, coefficient scaling in the DT domain is performedby function, which uses a state-space transformation to convertthe state-space matrix from the CT domain to the DT domain.Since different methods are used for conversion between the
DT and CT domains, and back again, unexpected coefficientsmay appear in the state-space matrix and modify the chosenNTF.
Fig. 1(a) shows a proposed behavioral-level design proce-dure [13], [14]. First, an NTF generated in DT domain (NTFZ)is converted to CT domain (NTFS) using IIT. Second, an ELDcompensated NTF in CT domain (NTFS_ELD) is verified byimpulse response to be identical to NTFZ. Third, the coef-ficient scaling is performed in the CT domain. Unlike theDelta–sigma toolbox, which uses two different transformationmethods for converting an NTF from DT domain to CTdomain and vice versa, the proposed procedure uses IIT to anNTF from DT domain to CT domain. Therefore, unexpectedcoefficients do not appear and the stability of the modulatorin CT domain is preserved. Assuming a third-order modulator,the scaling factor T is determined by the maximum level ofthe integrator output, which is user-defined value, and themaximum level of the integrator outputs, which are obtainedfrom the behavioral simulation. This approach to coefficientscaling can be applied to any structure.
KIM et al.: 2-MHz BW 82-dB DR CTDSM WITH CV-DAC FOR ELD COMPENSATION 2001
Fig. 2. Behavioral-level models of (a) nonidealities of the integrator,(b) DAC with ELD, and (c) clock jitter.
The nonidealities in a CTDSM include limited gain-BW (GBW), slew-rate, output saturation, clock jitter, feedbackDAC errors, and ELD. By modeling these nonidealities withina behavioral simulation, we can estimate their effect and deter-mine the margins required to achieve the target performance.Fig. 1(b) shows a behavioral-level model of a CTDSM. Thesignificant nonidealities of the integrator and the DAC withELD are modeled as shown in Fig. 2(a) and (b), respectively.Clock jitter is modeled as an amplitude error of the DAC,rather than as a timing error of the clock, as shown in Fig. 2(c);this approach does not require a smaller time-step than theclock period, which helps to avoid excessive simulation time.
Fig. 3 shows that the modulator can maintain the desiredsignal-to-quantization noise ratio (SQNR) even when KELDvaries by as much as ±30%. Assuming that the absoluteaccuracy of the resistor is ±30% [15], current-mode ELDcompensation can lead to a value of KELD which varies bymore than ±30%, and the situation is worsened by the parasiticdelay. Therefore, the circuit needs to be calibrated to yielda value of KELD which achieves the target SQNR. For theabove reasons, it is better to implement ELD compensationwith a CV-DAC, in which KELD can be expressed as a ratio ofcapacitances, and therefore robust to process and temperaturevariations.
Fig. 3. SQNR of the modulator against the ELD compensation coefficientKELD.
III. CIRCUIT IMPLEMENTATION
Fig. 4 shows a third-order nine-level CTDSM with aCV-DAC for ELD compensation. By utilizing thedesign methodology and behavioral-level models shownin Figs. 1 and 2, it is possible to get accurate expectationsfor the effect of nonlinearities within a short time. The targetsampling frequency and BW are 128 and 2 MHz, respectively.The NTF includes a zero inside the signal band near 2 MHzto improve the effect of noise shaping.
The loop filter is implemented as a cascade of integratorsand a resonator, within a feedforward structure [10]. Theintegrator is designed with an active-RC topology for lownoise and high linearity. It is well known that the noise of thefirst integrator is a dominant noise source in DSM. Thermalnoise generated from the first integrator can be expressed asfollows [16]:
PN = 32 KT fB R1 (1)
where K is Boltzman’s constant, T is the absolute temperature,fB is the BW, and R1 is the resistor of the first integrator. Thevalue of R1 is set to 4 k� so that the thermal noise occupies45% of the total noise. The coefficients of the DT delta–sigmamodulator are determined by ratios of capacitances, butthe coefficients of the CTDSM are determined by absolutevalues of resistances and capacitances. The modulatorbecomes unstable if these values are outside a certain range.Each capacitance in the integrator is, therefore, implementedas a bank of capacitors, which is arranged for 5-bit tuningusing an autocalibration circuit based on an SAR scheme [17].The autocalibration circuit is turned off after the capacitanceshave been calibrated. To realize a zero of the NTF, a largeresistor is required, which is implemented by using bothpositive and negative feedback resistors Rn and Rp [10].
The loop filter uses a feedforward structure, and thus anadder is required in front of the quantizer. An active adderconsumes more power than a passive adder because it requiresan additional operational amplifier (op-amp), but an activeadder ensures the linearity of the modulator and improvesthe signal-to-noise-and-distortion ratio (SNDR). In our design,an active adder can be realized without using an additional
2002 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018
Fig. 4. Third-order nine-level CTDSM with a CV-DAC for ELD compensation.
Fig. 5. Schematic of the FF op-amp.
op-amp by sharing the op-amp in the final integrator. Althoughthis shared op-amp uses somewhat more power, the increaseis less than the power drawn by an additional op-amp.
A. Feedforward Amplifier
The performance of a CTDSM is strongly influenced bynonlinearities in its op-amps, including limited GBW, slew-rate, and output swing, together with circuit noise. In par-ticular, limited GBW induces a nondominant pole into theintegrator transfer function and eventually transforms the NTF.A feedforward-compensated op-amp (FF op-amp) [18], withboth a high-gain path and a wide- BW path, is appropriateto achieve sufficient GBW to preserve the NTF. Fig. 5 showsa schematic of the FF op-amp. The FF op-amp of the firstintegrator has PMOS input transistors to improve its noiseperformance. The second and third integrators also used the
Fig. 6. Schematic of the nine-level flash ADC.
same FF op-amp topology as the first integrator and are poweroptimized.
B. Nine-Level Flash ADC
A multilevel quantizer is used to achieve a SQNR of 90 dBand to mitigate the effects of clock jitter. A schematic ofthe nine-level flash ADC is shown in Fig. 6, which is usedas a quantizer. To avoid possible instability, the output ofeach integrator is kept within a specified range through thecoefficient scaling in the behavioral-level simulation. Theprocedure as shown in Fig. 7 is used to prevent the modulatorfrom becoming unstable. Inputs to the quantizer which are1-LSB or more outside the specified range cause a resetsignal, which stops the modulator operating for 1024 sampling
KIM et al.: 2-MHz BW 82-dB DR CTDSM WITH CV-DAC FOR ELD COMPENSATION 2003
Fig. 7. Procedure for overload detection.
Fig. 8. Schematic of the current-steering DAC.
Fig. 9. Schematic of the CV-DAC.
periods. After this reset cycle, an enable signal is raised,and the modulator resumes operation in a provisional modefor 64 sampling periods. If an overload is again detectedduring these 64 periods, the modulator begins the reset cycleagain, and the entire procedure is repeated until the signal
Fig. 10. Microphotograph and magnified layout of the CTDSM.
remains within the specified range. The quantizer is in theform of a thermometer code, which can contain bubbles ifstatic or dynamic errors occur in the comparator. Bubbleerror correction logic is, therefore, used to prevent bubblesfrom causing incorrect decisions. Switching errors in theresistive ladder are prevented using a four-input comparator.The comparator is firmly designed to achieve the offset ofthe comparator less than 1/3-LSB, where 1-LSB is 50 mV.Monte-Carlo simulation is used to confirm 99.7% (3σ) of thecomparator offsets are within 1/3-LSB, which results that anoffset calibration is unnecessary.
C. Feedback DACs
A strong determinant of the performance of any modulatoris the performance of its feedback DAC, especially in aCTDSM. Errors in the feedback DAC can be caused by clockjitter and current mismatches in individual cells of the DAC.These errors are transmitted to the first integrator, whichcontributes a significant portion of the overall noise. Thisissue can be addressed by using a feedback DAC in the formof a nonreturn to zero (NRZ) DAC, which is less affectedby clock jitter than a return-to-zero (RZ) DAC. A switched-capacitor resistor (SCR) DAC or a FIR DAC would haveeven less sensitivity to clock jitter [6]. However, an SCRDAC requires precharging of its capacitor, which limits themaximum sampling frequency, and an FIR DAC requires anadditional FIR DAC to restore the correct NTF. We, therefore,chose an NRZ DAC with a current-steering topology.
Although the multilevel quantizer reduces the effect of clockjitter, it causes current mismatches in feedback DAC cells. TheDEM logic rotates the use of the feedback DAC cells, and thusrandomizes the noise from the feedback DAC. Using a data-weighted averaging scheme is sufficient to randomize the noiseeffectively.
2004 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 10, OCTOBER 2018
Fig. 11. Experimental setup.
Fig. 12. Measured spectrum at (a) −3 dBFS, with a 300-kHz input and (b) −4.2 dBFS, with a 500-kHz input.
Fig. 8 shows a schematic of the current-steering DAC usedas the first feedback DAC. A push–pull current-steering DACis used with a low-crossing driver DRVP and a high-crossingdriver DRVN , which reduce the transient peaks at the currentsource nodes VP and VN , respectively. The effect of themismatch between IP and IN is reduced by increasing thelengths of the current source devices MP and MN . The W/L ofMP and MN is 72 μm/12 μm and 28 μm/14 μm, respectively.The distortion is generated by the combination of the parasiticcapacitances at the current source nodes CP and CN , andthe offsets of the first integrator [19]. Moreover, CP,N andthe transitions of VP,N are proportional to an intersymbolinterference error current [20]. Therefore, the parasitic capac-itance of each current source node, including the capacitanceof the layout, is kept below 5 fF. The current- steering DACis designed to achieve 10-bit resolution and it is verified byMonte-Carlo simulation. The additional current sources IP0−2and IN0−2 are used to reduce the mismatch of the push andpull currents.
To compensate for ELD, the second feedback DAC isimplemented as a CV-DAC, as shown in Fig. 9. Each flip-flop in the feedback path produces a half period delay. TheELD compensation path is fed back to the input of the finalintegrator, and KELD is set to the ratio of the capacitance,8 CDAC/Cint3, where CDAC is the capacitance in individualcells of the CV-DAC, and Cint3 is the capacitance of the final
integrator. This arrangement for voltage-mode ELD compen-sation, which uses a CV-DAC does not need calibration. OurELD compensation has lower design complexity compared tocurrent-mode ELD compensation, which uses current DAC.The supply voltage VDD and VSS are used as referencevoltages. Sharing the supply voltage as a reference voltageof the CV-DAC might be concerned at the aspect of powersupply noise; however, it can be alleviated by using a largeon-chip decoupling capacitor [21]. The output of the CV-DACis connected to the input of the final integrator.
IV. EXPERIMENTAL RESULTS
The third-order nine-level CTDSM with a CV-DAC for ELDcompensation is implemented in a 65-nm CMOS process.Fig. 10 is a microphotograph and magnified layout of theCTDSM, which has an active area of 0.516 mm2. The experi-mental setup is shown in Fig. 11. A differential input signal isproduced by connecting a signal source through a bandpassfilter and a transformer, and a differential clock signal isgenerated by passing a 128-MHz pulse wave through a secondtransformer. The output from the modulator goes to a logicanalyzer, where 15 sequences of 216 captured data pointsare averaged, and a Kaiser–Bessel window is applied. Theoutput spectrums for input frequencies of 300 and 500 kHzare shown in Fig. 12(a) and (b), respectively. The measuredsignal-to-noise ratio (SNR), SNDR, and spurious-free DR are
KIM et al.: 2-MHz BW 82-dB DR CTDSM WITH CV-DAC FOR ELD COMPENSATION 2005
Fig. 13. Measured SNR and SNDR against (a) input amplitude and (b) temperature at −3 dBFS, with a 300-kHz input.
TABLE I
PERFORMANCE SUMMARY
75.8/72.1/78.8 dB with a 300-kHz input and 73.8/72/78 dBwith a 500-kHz input. Fig. 13(a) shows the measured SNRand SNDR against input amplitude, which achieves the DRof 82 dB. Fig. 13(b) shows the measured SNR and SNDRagainst temperature at −3 dBFS, with a 300-kHz input. Thevariations of SNR and SNDR over a commercial temperaturerange from −20 °C to 80 °C are 2 and 1.9 dB, respectively.The measured results show that our modulator is robust totemperature variation [22]. The total power consumption is3.8 mW with a 1.2-V supply, and the power breakdownis shown in Fig. 14. Table I shows the comparison of theperformance of our CTDSM against other recent designswith similar BWs. The CTDSM in [3] provides the bestFOM1 and FOM2, but it requires an additional high-voltagesupply to the feedback DAC. Our modulator has higher valuesof the FOMs than other CTDSMs which use flash quantizers.
Fig. 14. Power breakdown.
V. CONCLUSION
We have presented a 2-MHz BW CTDSM which uses aCV-DAC for ELD compensation. Implementing ELD compen-sation with a CV-DAC is less affected by process and tempera-ture variations than modulators with other ELD compensationschemes. The variations in SNR and SNDR are within 2 dBin the commercial temperature range of −20 °C–80 °C. Ourmodulator achieved the DR of 82 dB, which is sufficientto be utilized in wireless applications. The FOMs show thefeasibility of our modulator among the modulators using aflash quantizer. The power consumption is 3.8 mW from a1.2-V supply voltage.
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Susie Kim received the B.S. degree in electricaland computer engineering from Seoul National Uni-versity, Seoul, South Korea, in 2011, where she iscurrently working toward the Ph.D. degree.
Her current research interests include analog andmixed-signal integrated circuits and systems.
Seung-In Na received the B.S. degree in electricalengineering from the Korea Advanced Institute ofScience and Technology, Daejeon, South Korea,in 2009 and the M.S. and Ph.D. degrees in electricaland computer engineering from Seoul NationalUniversity, Seoul, South Korea, in 2011 and 2016,respectively.
In 2016, he joined Samsung Electronics,Hwaseong-si, Gyeonggi-do, South Korea, wherehe was involved in oversampling ADC design forthe audio application. His current research interests
include analog circuit designs for audio application.
Youngtae Yang received the B.S. degree in electri-cal and computer engineering from Seoul NationalUniversity, Seoul, South Korea, in 2013, where heis currently working toward the Ph.D. degree.
His current research interests include oversamplingADC for audio and motion sensor applications.
Suhwan Kim (S’97–M’01–SM’07) received theB.S. and M.S. degrees in electrical engineeringand computer science from Korea University, Seoul,South Korea, in 1990 and 1992, respectively, and thePh.D. degree in electrical engineering and computerscience from the University of Michigan, Ann Arbor,MI, USA, in 2001.
From 1993 to 1999, he was with LG Electron-ics, Seoul, South Korea. From 2001 to 2004, hewas a Research Staff Member at IBM ThomsonJ. Watson Research Center, Yorktown Heights NY,
USA. In 2004, he joined Seoul National University, Seoul, South Korea, wherehe is currently a Professor of Electrical and Computer Engineering. His currentresearch interests include low-power high-resolution analog and mixed-signalintegrated circuits and high-speed input/output circuits.
