Chart 1
A 204.8GHz Static Divide-by-8 Frequency Divider
in 250nm InP HBT
Zach Griffith, Miguel Urteaga, Richard Pierson, Petra Rowell,
Mark Rodwell*, and Bobby Brar
Teledyne Scientific Company, Thousand Oaks, CA 91360, USA
*Department of Electrical and Computer Eng., UC Santa Barbara
e-mail: [email protected], phone: 805-373-4104
Compound Semiconductor IC Symposium 2010
Chart 2
MS flip-flops are very widely-used high speed digital circuits: • Dividers are master-slave flip-flop with inverting feedback
• Connection as 2:1 frequency divider provides simple test method
Standard benchmark of logic speed: • Performance comparisons across technologies
Dynamic, super-dynamic, frequency dividers: • Higher maximum frequency than true static dividers
• Narrow-band operation applications are limited
High speed technology performance for static dividers: • 250nm InP HBT: NGAS 200.6GHz (2009), TSC/UCSB 204.8GHz (2010)
• Advanced SiGe HBT: Infinion 110+GHz
Why Static Frequency Dividers ?
Chart 3
clock clock clock clock
inin
out
out
cexLOGIC
LOGIC
Ccb
becb
becb
C
LOGIC
IRq
kTV
V
IR
CCR
CCI
V
6
leastat bemust swing logic The
resistance base the through
charge stored
collector base Supplying
resistance base the through
charging ecapacitancDepletion
swing logic the through
charging ecapacitancDepletion
:by DeterminedDelay Gate
bb
depletion,bb
depletion,
Fast divider design – identifying dominant gate delays
maxτ
logic
emitter
collector
depl
f& f not speed, clock for design to ...Need
high at low forlow very be must
objective. design HBTkey a is Low
total. of 80%-60% is
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eex
effective
C
CE
LOGIC
C
LOGICcb
ccb
becbCLOGIC
JVR
v
T
A
A
V
V
I
VC
IC
CCIV
f
22
/
min,
,
Chart 4
base
emitter
collector
subcollector
base
emitter
collector
subcollector
Collector Field Collapse (Kirk Effect)
Collector Depletion Layer Collapse
)2/)(/( 2 cdsatcb TqNvJV
)2/)(( 2
min, cTqNV dcb
2
min,max /)(2 ccecesat TVVvJ
e,1e,1
logic
C,1
c,1ro
C
logic
cb,1AJ
ΔV
T
Aεε
I
ΔVC
0.5um HBT, 150GHz divider, Je = 5mA/um2
0.25um HBT, 200GHz divider – vertical, lateral scaling for Je = 10mA/um2
Lateral scaling, current spreading for Je = 10mA/um2
(1-D collector current flow)
C
logic
cb,1
e,1e,1
logic
C,1
c,1ro
C
logic
cb,2I
ΔVC
4
3
A2
12J
ΔV
T3
2
A2
1εε
I
ΔVC
C
logic
cb,1
e,1e,1
logic
C,1
c,1ro
C
logic
cb,2I
ΔVC
2
1
A2
12J
ΔV
T
A2
1εε
I
ΔVC
33% reduction
200GHz dividers – collector design for 250nm HBTs
Chart 5
.1/TJ where; AJ
ΔV
T
Aεε
I
ΔVC 2
cmaxe,
emittere
logic
C
collectorro
C
logic
cb
ex 7 m2 needed for 200 GHz clock rate
ECL delay not well correlated with f or fmax
Key HBT Scaling Limit Emitter Resistance
Io
RL
Rex
Noise margin
2kT/q+IoRex
Vin
Vout
Vlogic=IoRL
Vlogic
Largest delay is charging Ccb
Je 10 mA/m2 needed for 200 GHz clock rate
Voltage drop of emitter resistance becomes excessive
RexIc = exJe = (15 m2) (10 mA/m2) = 150 mV
considerable fraction of Vlogic 300 mV
Degrades logic noise margin
This slide presented at BCTM 2004 for phase-I 150GHz divider.
HBT metrics here invoked to demonstrate the phase-III 200GHz divider.
Chart 6
Ccb/Ic Charging Rate: ECL delays lower than CML
Vcb
= -0.3 V
0
2
4
6
8
10
0 2.5 5 7.5 10 12.5
0
5
10
15
20
25
Ccb/A
e (
fF/
m2)
Je (mA/m
2)
Ccb (fF
)
-0.2 V
0.0 V
0.2 V
Vcb
= 0.6 V
Zo
CML
ECL
Zo
Vcb
= -0.3 V
0
2
4
6
8
10
0 2.5 5 7.5 10 12.5
0
5
10
15
20
25
Ccb/A
e (
fF/
m2)
Je (mA/m
2)
Ccb (fF
)
-0.2 V
0.0 V
0.2 V
Vcb
= 0.6 V
Vlogic
= 300mV
Chart 7
Design approach for 200GHz logic
Block diagram of Divide-by-8
Schematic of a flip-flop configured as a static divider
Approach: (new design elements presented in bold)
• Emitter coupled logic (ECL) topology
• Faster HBTs with lower Ccb and lower Rex (-um2)
• Scaled device from 0.5um to 0.25um
• 150nm collector, 30nm base (400GHz ft, 650GHz fmax)
• Reduce signal bus and loading delays
• Decreased device-to-device spacing
• Thin-film microstrip with low loss r = 2.7
• Resistive pulldown voltage biasing
• Small peaking inductance Lpeak
• Emitter-follower HBTs having reduced Ccb (Q1, Q2)
• Collector-base DC voltage Vcb increased
Q1, Q2 Ccb reduction
Chart 8
IC micrographs of the TSC 200GHz Static Frequency Dividers
Final fabrication, top-metal ground plane omitted
Divide-by-2 circuit, 36 HBTs (0.420.41-mm2) Divide-by-8 circuit, 108 HBTs (0.680.45-mm2)
Chart 9
TSC/UCSB/GSC 150GHz divider (September 2004)
x = 500um
y =
470
um
Technology cross-section, phase-I
112um
190um
Close-up view of flip-flop interconnect, configured for divide-by-2
Summary of divider physical size:
• 5um device-to-device spacing
• Two-sided collector HBT
• Latch width = 112um
• Latch-to-buffer signal distance = 190um
CMET = Blue
MET-1 = Red
DC power ~ 600mW
-90
-80
-70
-60
-50
-40
-30
-20
-10
0.00 19.50 39.00 58.50 78.00
Outp
ut
Pow
er
(dB
m)
frequency (GHz)
-80
-70
-60
-50
-40
75.9975 76.0000 76.0025
dB
m
GHz
Phase-I divider @ 152GHz
Chart 10
TSC/UCSB 200GHz divider – scaling summary
x = 420um
y =
410
um
TSC mixed-signal technology cross-section
50um
64um
Close-up view of flip-flop interconnect, configured for divide-by-2
Summary of divider physical size:
• 2um device-to-device spacing
• One-sided narrower collector HBT
• Latch width = 50um (55% reduction)
• Latch-to-buffer signal distance = 64um
• 66% reduction
DC power ~ 592mW
Simulated CLK rate, 213GHz
Chart 11
Probe-station for 200GHz divider testing
WR-05 output power sweep
Probe station for 200GHz testing
Output
Close-up showing wafer probes
Mechanical attenuator
200GHz source
200GHz 8x VDI source from UCSB
Output at 204.8GHz operation
Chart 12
-100
-80
-60
-40
-20
0
0 5 10 15 20 25
Ou
tput
Pow
er
(dB
m)
Frequency (GHz)
Divide-by-8 static divider operating to 204.8GHz
Divider output – fclk = 204.8GHz, fout = 25.60GHz Divider output – fclk = 4.0GHz, fout = 500MHz
• Peak divider toggle rate is 204.8GHz
• Expected output at 25.60GHz, no spectral content at lower frequencies
• Input divider operational down to 4.0GHz to confirm static operation at all frequencies
• 3rd-stage divider is operating at 1.0GHz clock (differential 350mVp-p), 500MHz final output
• PDC of divide-by-8 circuit = 1.82W
• Input divider operating at 204.8GHz, PDC = 592mW
-100
-80
-60
-40
-20
0
0 10 20 30 40 50
Ou
tput
Po
wer
(dB
m)
Frequency (GHz)
-100
-80
-60
-40
-20
0
25.5975 25.6000 25.6025
dB
m
GHz
5MHz span
Low-frequency verification
Chart 13
-30
-20
-10
0
10
0 50 100 150 200
Input
Po
wer
(dB
m)
Frequency (GHz)
Source-free self-oscillation @ 143GHz
Sensitivity plot of the 204.8GHz static divider
Divider output – fclk = 204.8GHz, fout = 25.60GHz Sensitivity plot, 204.8GHz static divider
• Sensitivity plot of the divider: 0.1-50GHz, 61.5-113.25GHz, 182.4-204.8GHz
• Expected trends of input power sensitivity versus frequency observed
• Source-free self oscillation (no input signal) reference to the input is 143GHz
-100
-80
-60
-40
-20
0
0 10 20 30 40 50
Ou
tput
Po
wer
(dB
m)
Frequency (GHz)
-100
-80
-60
-40
-20
0
25.5975 25.6000 25.6025
dB
m
GHz
5MHz span
61-113GHz tripler
182-209GHz 8x FEM
0.1-50GHz source
Chart 14
Summary
• A record static divide-by-8 frequency divider has been demonstrated – 108 HBTs, all having 250nm features – TSC 4-metal layer, mixed-signal interconnect – Operational from 4.0GHz to 204.8GHz – Total PDC = 1.82W, input divider only (no buffers) = 592mW
• Continued increases to static divider toggle rate require balanced reductions to HBT base Rbb and emitter resistance Rex, and junction capacitances Cje, Ccb. – Presentation (Tues-F1) by M. Urteaga discusses recent HBT developments
Chart 15
Acknowledgement
• This work was supported under the DARPA TFAST program, Sanjay Raman program manager.
Thank you!!
