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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
A 2.4-GHz Frequency-Drift-CompensatedPhase-Locked Loop With 2.43 ppm/°C
Temperature CoefficientCheng-En Hsieh and Shen-Iuan Liu , Fellow, IEEE
Abstract— A frequency-drift-compensated phase-locked loop(PLL) with an LC voltage-controlled oscillator (VCO) is fabri-cated in TSMC 40-nm CMOS process. The proposed frequencydrift compensator employs an analog-to-digital converter tomonitor the control voltage of the PLL in background. Thecapacitor banks are adjusted to compensate for the frequencydrift of the LC-VCO. The measured reference spur is −65.15 dBc.The measured best phase noise of this PLL is −108.32 and−130.26 dBc/Hz at the frequency offset of 1 and 10 MHz,respectively, among five chips. This chip occupies 0.223-mm2
active area. The power dissipation of this PLL is 6.32 mW froma 0.9-V supply voltage. The average temperature coefficient is2.43 ppm/°C from 20 °C to 100 °C.
Index Terms— Analog-to-digital converter (ADC), frequencydrift, frequency drift compensator (FDC), phase-lockedloop (PLL), reference spur.
I. INTRODUCTION
COMPARED to the ring-based voltage-controlled oscilla-tors (VCOs), the LC VCOs are widely used in phase-
locked loops (PLLs), frequency synthesizers, and clock gen-erators due to its high spectral purity. The resistance ofthe inductor may induce losses and thermal noise. Besides,the lossy LC-tank of a VCO will induce the frequency drift dueto the temperature variations. For example, when a high-speedprocessor operates, its dramatic power brings the thermaldiffusion on a chip, which affects the thermal resistance ofthe active and passive components. If the drifting frequencyis larger than the tuning range of an LC-VCO, the PLL willunlock.
To deal with the frequency drift due to the tempera-ture variations, one can interrupt a frequency synthesizer byrecalibrating the LC-VCO. However, some applications donot allow interrupting the frequency synthesizer in the fullduplex systems such as CDMA receivers. Besides, a frequencysynthesizer using a large VCO gain might deteriorate spurand noise performances. In general, the wide tuning range
Manuscript received June 20, 2018; revised September 30, 2018; acceptedNovember 6, 2018. This work was supported in part by the National TaiwanUniversity under Donation Grant FD105012 and in part by the Ministry ofScience and Technology, Taiwan. (Corresponding author: Shen-Iuan Liu.)
The authors are with the Department of Electrical Engineering, Grad-uate Institute of Electronics Engineering, National Taiwan University,Taipei 10667, Taiwan (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2018.2880477
of a low-gain LC-VCO is realized by discrete switched-capacitor or switched-varactor arrays to tolerate the process,voltage, and temperature variations. While a frequency synthe-sizer adopts a low-gain LC VCO, its temperature sensitivitymust be considered.
Several temperature compensation methods for a low-gain LC-VCO have been presented in [1]–[6]. In [1], theproportional-to-absolute-temperature (PTAT) voltage sourcesare used to reverse bias the diodes of the switching transistorsin the capacitor bank and bias the back-side voltage of thelinearized MOS varactors. An LC-VCO with the temperaturecoefficient (TC) less than 10 ppm/°C is achieved [1]. However,to generate these PTAT voltages, the voltage regulators areused which consume an additional power and chip area.In [2]–[5], a PTAT voltage is used to reverse bias the varactors,which cancel the frequency drift of an LC-VCO. Unfortu-nately, this kind of the compensation methods cannot properlycancel the frequency drift due to the process variations.In [6], a peak detector is used to detect the amplitude of anLC-VCO. An automatic leveling control loop is adopted tocalibrate the frequency drift of the VCO by using digitallycontrolled current sources. However, additional active devicesmay induce the noises to degrade the phase noise of the VCO.In [7] and [8], a parallel feed-forward compensation pathadjusts the control voltage of an auxiliary varactor to reducethe frequency drift. However, a large RC filter is needed forthe bias voltage of the auxiliary varactor.
To address these issues, a PLL with a frequency driftcompensator (FDC) is presented. To sense the control voltageof a PLL, a successive-approximation-register (SAR) analog-to-digital converter (ADC) is used. The FDC adjusts thecapacitor banks of the LC-VCO to compensate the frequencydrift owing the temperature variations. It does not need thevoltage regulator and the PTAT current sources to save thearea and power. This paper is organized as follows. Section IIdescribes the frequency drift on the VCO’s oscillation fre-quency and the PLL’s phase noise performance. The circuitimplementation of this PLL and FDC are also discussed.Section III gives the experimental results. Finally, conclusionsare given in Section IV.
II. CIRCUIT DESCRIPTION
A. Temperature Effects of an LC-VCO and a PLL
To consider a lossy LC tank [9]–[11], an inductor L and acapacitor C are modeled in series with the parasitic resistances
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 1. Models for the lossy LC tank.
RL and RC , respectively, as shown in Fig. 1. Its resonancefrequency can be expressed as
ω = ω0
√√√√
1 − CL R2
L
1 − CL R2
C
, (1)
where ω0 = √1/(LC). Since the effective resistance RC of
a lossy capacitor is sufficiently smaller than that of a lossyinductor [11], (1) is approximated as
ω ∼= ω0
√
1 − C
LR2
L . (2)
To consider the temperature effect, the effective seriesresistance RL of a lossy inductor is modeled as
RL ∼= R0[1 + αR · (T − T0)] (3)
where R0 is the resistance at the temperature T0 and αR is thefirst-order TC. For an instance, the TC of an aluminum layerfor the inductor is around 3.89 × 10−3 K−1. By substituting(3) into (2), the resonance frequency is approximated as
ω ∼=√
1
LC− 1
L2 R20 −
1L2 R2
0√
1LC − 1
L2 R20
· αR · (T − T0). (4)
In the above expression, the oscillation frequency of theLC-VCO exhibits a negative TC. Moreover, its voltage gainKVCO can be expressed as
KVCO =∣∣∣∣
∂ω
∂Vctrl
∣∣∣∣=
∣∣∣∣
∂ω
∂Cvar
∣∣∣∣·∣∣∣∣
∂Cvar
∂Vctrl
∣∣∣∣
(5)
where Vctrl is the control voltage of the MOS varactor of Cvar.To combine (4) and (5), the temperature-dependent VCO gaincan be derived as
KVCO(T ) =
⎡
⎢⎢⎢⎣
− 1
2√
L·√
1− R20
L C·C1.5
−√
L· R20
L2
2√
C·(
1− R20
L C)1.5
· αR · (T − T0)
⎤
⎥⎥⎥⎦
·∣∣∣∣
∂Cvar
∂Vctrl
∣∣∣∣,
(6)
where C = Cvar + Cfixed, Cfixed is a constant capacitor and|∂Cvar/∂Vctrl| is the voltage sensitivity of the varactor. Forexample, consider a second-order charge pump (CP) PLLusing an LC-VCO. When it operates in the overdamped case,the closed-loop bandwidth of this PLL is approximated as [12]
ω−3dB ≈ R1 · IP · KVCO(T )
2π · N(7)
where IP is the CP current, N is the division ratio ofthe divider, and R1 is the loop filter (LF) resistor. Whenthe temperature changes, both KVCO(T ) and the closed-loopbandwidth will be altered. Moreover, the nonconstant PLLbandwidth may degrade the phase noise.
In order to reduce the temperature variation of KVCO(T ),a temperature-compensated gain �KVCO(T ) is introduced tocorrect the frequency drift. The PLL output frequency with�KVCO(T ) is given as
where ω0 is the free-running PLL output frequency.Assume that the PLL is locked at a temperature of T0, ωout
is the desired PLL output frequency. It means that the productof KVCO(T0) + �KVCO(T0) and Vctrl(T0) is fixed. To toleratethe temperature variations as large as possible, an FDC has tokeep Vctrl(T0) close to a half of the tuning range; i.e., Vctrl(T0)close to VDD/2 where VDD is the tuning range.
Consider a second-order CP PLL without �KVCO(T ), whenthe temperature T0 is changing toward T , KVCO(T ) mayincrease or decrease. Then, this PLL has to adjust Vctrl(T )in order to keep ωout fixed. Once Vctrl(T ) exceeds the tuningrange, the PLL will unlock. With �KVCO(T ), the FDC willmonitor Vctrl(T ) and keeps it close to Vctrl(T0); i.e., a half ofthe tuning range, VDD/2. It implies that KVCO(T )+�KVCO(T )is almost kept constant and closed to KVCO(T0)+�KVCO(T0),while the temperature is varying. Note that the FDC can detectthe direction of the temperature variations by using Vctrl(T )and Vctrl(T0). Since KVCO(T ) + �KVCO(T ) is kept constant,a fixed PLL bandwidth can be achieved if IP R1 is temperatureindependent according to (7). To simplify (7), the thermalnoise produced by the LF resistor R1 is not considered, onlyused a temperature compensated gain to correct the frequencydrift. The detail circuits will be discussed as follows.
B. Frequency-Drift-Compensated PLL
The frequency-drift-compensated PLL is shown in Fig. 2(a).It consists of a conventional PLL, a coarse frequency selector(CFS) [13], and the FDC. This conventional PLL is composedof a phase frequency detector (PFD), a CP, an LF, an LC-VCO, and a divide-by-32 divider. The frequency fREF of thereference clock is equal to 75 MHz. Fig. 2(b) shows the timingdiagram of this PLL. First, when the clock �CFS is active,the control voltage Vctrl is tied to VDD/2 and the CFS is enabledto calibrate the frequency of the LC-VCO, which is equal to2.4 GHz. Subsequently, when �CFS is OFF and �SW is active,this PLL enters in the phase acquisition mode. Once the PLL islocked, the clock �FDC is active to enable the FDC. The FDCmonitors the control voltage VC in background to compensatethe frequency drift of the LC-VCO due to the temperaturevariations.
C. CFS and the FDC
Fig. 3 shows the LC-VCO with a CFS and an FDC. ThisLC-VCO has a fixed capacitor Cfixed, two switched-capacitorbanks, and a MOS varactor connected to a second-orderLF. All capacitors in the capacitor banks are customized by
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HSIEH AND LIU: 2.4-GHz FREQUENCY-DRIFT-COMPENSATED PLL WITH 2.43 ppm/◦C TEMPERATURE COEFFICIENT 3
Fig. 2. (a) Frequency-drift-compensated PLL and (b) its timing diagram.
Fig. 3. VCO with a CFS and an FDC.
the intended parasitic capacitance between two nodes of themetal–metal layer, which uses topper metal 6, 7, and 8 stackedtogether with minimum width and spacing [14] as shownin Fig. 4. All parameters of this VCO are listed in Table I.Fig. 5 shows the postlayout simulated frequency drift of the
LC-VCO with the slow–slow (SS), typical–typical (TT), andfast–fast (FF) process corners for the NMOS and PMOSdevices. The frequency drifts for the SS, TT, and FF processcorners are 16.1, 127.2, and 76.9 MHz from the temperature−10 °C to 100 °C, respectively. The CFS controls one of
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 4. Capacitor bank and the unit capacitor implementation.
TABLE I
PARAMETERS FOR THE VCO
Fig. 5. Simulated frequency drift of the LC-VCO for three process corners.
two capacitor banks to select the PLL’s frequency in order totolerate the process variations. The FDC monitors the controlvoltage VC, which is close to Vctrl, to adjust another capacitorbank in order to compensate the temperature variations.
When �CFS is active and the CFS is turned ON, the controlvoltage Vctrl and the back-side bias voltage of the MOSvaractor are connected to VDD/2. Assume that the outputfrequency of the LC-VCO is fVCO. First, fVCO and fREF aredivided by k and m, respectively. After these two dividers, twosubsequent counters are counted by the frequency of fVCO/kwithin a timing window of 0.5 m/ fREF. The sum ncnt of twocounters is compared with a target number ntarget, which is
Fig. 6. Flowchart of the FDC.
equal to 2× m×k. In this paper, m and k are equal to 32 and 4,respectively. When ncnt > ntarget or ncnt < ntarget, it means thatfVCO is higher or lower than ftaget, respectively, where ftagetis equal to 2.4 GHz. As the result, the SAR controller willswitch a capacitor array to reduce or increase fVCO. After6-bit conversion steps, ncnt is close to ntarget and thus, fVCOis close to ftaget. While the CFS is finished, the PLL entersthe phase acquisition mode.
Once the PLL is locked, the clock �FDC is active toenable the FDC. The FDC is composed of a 6-bit SAR ADC,two selectors, a finite state machine (FSM) with an up/downcounter.
Fig. 6 shows the flowchart of the FDC. Dn[5:0] is the ADCoutput code. DMID[5:0] is the self-defined code, which setsas possible as a half tuning range. DREF[5:0] is the FDCreference code, Dn[5:0] will close to DREF[5:0] after severaltimes iteration. The detail operation illustrates as follows.
First, the 6-bit SAR ADC converts the control voltageVC (∼=Vctrl) into a digital code Dn[5:0]. Initially, the firstDn[5:0] is set as a reference one DREF[5:0]. In addition,a middle digital code DMID[5:0] like “100 000” is also chosen.Then, the ADC continually measures the control voltageVC(T ) to have the nextDn[5:0]. If |DMID[5:0]-Dn[5:0]| <|DMID[5:0]-DREF[5:0]|, DREF[5:0] will be replaced by thepresent Dn[5:0]. It means that VC(T ) (∼=Vctrl(T )) is kept asclose to VDD/2 as possible, no matter the temperature is.In addition, KVCO(T ) + �KVCO(T ) is almost kept constant.
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HSIEH AND LIU: 2.4-GHz FREQUENCY-DRIFT-COMPENSATED PLL WITH 2.43 ppm/◦C TEMPERATURE COEFFICIENT 5
Fig. 7. Six-bit SAR ADC building blocks and its timing diagram.
If not, |DMID[5:0]-Dn[5:0]| > |DMID[5:0]-DREF[5:0]|, theabsolute difference between DREF[5:0] and Dn[5:0] is cal-culated and compared with a given error ε. If |Dn[5:0]-DREF[5:0]| < ε, it represents that the variation of VC(T ) issmall and within an allowed error. Then, the code T [63:0]will not update the capacitor bank since both the frequencydrift and the temperature variation are small. On the contrary,if |Dn[5:0]-DREF[5:0]| > ε, the frequency drift is large andthe temperature compensation is needed. Assume Dn[5:0]>DREF[5:0], it indicates that the control voltage VC(T ) isincreased; i.e., KVCO(T ) is decreased due to the temperaturevariations. It should increase �KVCO(T ) to maintain a fixedVC(T ). Therefore, the code T [63:0] will decrease one least-significant bit (LSB) of the capacitor bank to increase the oscil-lation frequency. On the contrary, when Dn[5:0]< DREF[5:0],VC is decreased and KVCO is increased. Similarly, �KVCOshould be decreased to maintain a fixed VC. Then, T [63:0]is increased by 1 LSB to decrease the oscillation frequency.Finally, the FDC continually monitors VC in background andfinds the next Dn[5:0] by using the SAR ADC. DREF[5:0] hasa D-flip-flop to register a reference value for each comparisonwith Dn[5:0]. The operation frequency of this FDC is chosenas 73.24 kHz (75 MHz/1024). Note that since the temperaturechanges slowly, the disturbance from the FDC to the PLL istiny, because the step 7 in the flowchart is always true and thecontrol code T [63:0] would not be updated.
D. Successive-Approximation-Register (SAR)Analog-to-Digital Converter (ADC)
The 6-bit SAR ADC building blocks and the timing dia-gram are shown in Fig. 7. The CKdiv128 and CKdiv8 are thedivide-by-128 and the divide-by-8 signals from the referenceclock fREF, respectively. The comparison clock CKcomp issimilar to CKdiv8 before enables the finishing clock Clk6.There are six comparison cycles �comp,1–�comp,6 in CKcomp
TABLE II
PARAMETERS FOR THIS PLL
TABLE III
POWER DISTRIBUTION OF THIS PLL
are required. Once the comparator outputs a comparison resultof Comp_out, the ready signal will be produced subsequently.
The ADC architecture consists of a sample-and-hold (S/H)switch, a rail-to-rail comparator [15], an SAR logic, and acapacitive digital-to-analog converter (DAC). The samplingcapacitor C2 comes from the loop filter being to 10 pF.The comparator uses both PMOS and NMOS input pairs forthe rail-to-rail signal swing. The total DAC capacitance is320 fF, which composes of 32 unit elements Cu (stacked metallayer 3–8) and can achieve a KT/C-related SNR of 67 dB,which is enough large for the 6-bit resolution. Note that theKT/C represents the thermal noise, K is Boltzmann’s constant,
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
TABLE IV
PERFORMANCE SUMMARY AND COMPARISON WITH THE STATE OF THE ARTS
Fig. 8. PFD.
T is the absolute temperature, and C is the total DACcapacitance.
In the sampling phase, �SW is active, the control voltage issampled to the capacitor C2. The SAR logic resets the digitalcodes while CKdiv128 is low. Besides, all capacitors in the DACarray are charging to Vcm. In the conversion phase, CKdiv128 ishigh and �comp,1 is active to compare the control voltage VCwith Vcm, the most significant bit (MSB) b5 is generated by theReady signal. Subsequently, the MSB capacitor 16 Cu switchesto the reference voltage VREF or VGND to approach VC by b5.
After six times comparison phase and the DAC switching,the SAR ADC outputs the parallel digital codes Dn[5:0] tothe FSM. In other words, the control voltage VC at everytemperature will be monitor by the SAR ADC, and the FDC
Fig. 9. CP circuit.
will compensate the frequency drift according to the ADCoutput codes. In addition, after delivering the digital codes,the ADC enters to the standby state until the next CKdiv128phase. The measured power consumption of this SAR ADCis 1.1 μW.
E. Circuits in the PLL
Figs. 8 and 9 show the PFD and the CP, respectively.A sampled-and-hold technique is used to reduce the cur-rent mismatch [16]. The divide-by-32 divider is realized bythe static CMOS logic circuits. The simulated VCO gainis 30 MHz/V. All parameters of this PLL are listed in Table II.The phase margin and the loop bandwidth of this PLL aredesigned to be 60° and 300 kHz, respectively.
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HSIEH AND LIU: 2.4-GHz FREQUENCY-DRIFT-COMPENSATED PLL WITH 2.43 ppm/◦C TEMPERATURE COEFFICIENT 7
Fig. 10. Measured oscillation frequency of the VCO versus temperature andthe calculated frequency drift.
III. EXPERIMENTAL RESULTS
A PLL with an LC-VCO is fabricated by TSMC 40-nmCMOS process. The reference frequency is 75 MHz and themeasured output frequency is 2.4 GHz. The power distributionof this PLL is listed in Table III. The total power dissipationis 6.32 mW from a 0.9-V supply voltage. The measuredVCO oscillation frequency versus temperature is shownin Fig. 10.
From five chips observations, the average drifting frequencyis 65.7 MHz over −10 °C to 100 °C. Compared with Fig. 5,the transfer curves of the measured chips are close to those atthe FF process. Fig. 11 shows the measured phase noise versustemperature variation with and without calibration. When thetemperature is swept from 20 °C to 100 °C, the measuredminimum and maximum RMS jitter are 0.939 ps at 40 °Cand 3.264 ps at 20 °C, respectively. The capacitor bank inthe FDC is composed of 64 unit-capacitors, and each oneis 1.5 fF. At 20 °C, all capacitors in the FDC are connectedto the VCO (i.e., T [63:0] = [111…11]). At 100 °C, all ofthem are floated (i.e., T [63:0] = [000…00]). The measuredtemperature range of the FDC calibration is narrower than thesimulation due to the insufficiently compensated codes. Forexample, to compensate the frequency drift for the temperaturelower than 20 °C, the FDC needs more than 64 unit-capacitors.However, it will increase the core area and decrease theresonance frequency due to the parasitic capacitance.
When the FDC is enabled, both the measured RMS jitter andthe PLL bandwidth are approximately fixed. The temperaturecoefficient (TC) is expressed as
TC = KVCO × �Vctrl
ftarget × �T(ppm/°C) (9)
where KVCO is the VCO gain and �Vctrl is the variationof the control voltage over the temperature range, �T .ftarget is the PLL output frequency, which is correspondingto 2.4 GHz. Fig. 12(a) shows the measured tuning range over20 °C to 100 °C when the FDC is disabled. The TC of the
Fig. 11. Measured phase noise versus temperature (a) without and (b) withFDC calibration.
control voltage before compensation is 77.2 ppm/°C in aver-age. When the FDC is enabled, the ADC monitors the controlvoltage of Fig. 12(a), and compensates the �KVCO by adjust-ing the capacitor banks to the VCO. The TC of the controlvoltage is improved to 2.43 ppm/°C in average as shownin Fig. 12(b). Note that the control voltage is almost keptconstant over 20 °C to 100 °C. Besides, the changing trendof the control code T [63:0] is according to the DREF[5:0] andDn[5:0], where Dn[5:0] is the ADC outputs from the controlvoltage of Fig. 12(a). In Fig. 13(a), the measured best phasenoise of this PLL is −108.32 dBc/Hz and −130.26 dBc/Hz atthe frequency offset of 1 and 10 MHz, respectively, among fivechips. The measured RMS jitter is 0.939 ps by integrating thephase noise from 1 kHz to 30 MHz. Furthermore, the measuredreference spur at 75 MHz offset is −65.15 dBc as shownin Fig. 13(b).
Fig. 14 shows the measured transient response of theCFS calibration by Agilent 53310A modulation domain
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8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 12. Measured tuning range (a) w/o (b) w/i calibration.
analyzer. While the CFS is enabled, the PLL output frequencyof 2.485 GHz will converge toward the target frequencyof 2.4 GHz within 4.7 μs.
Table IV summarizes the performances of this paper andthe state-of-the-art papers. The first figure-of-merit (FOM1) isdefined as
FOM1 = L( fm) + 10 × log
[(
fm
ftarget
)2
×(
P
1mW
)]
(10)
where L( fm) is the phase noise at the offset frequency of fm.P represents the power consumption of the PLL. The calcu-lated FOM1 is −170 dB for the proposed PLL. The secondfigure-of- merit (FOM2) is define as
FOM2 = 20 × log(jitterRMS/1s) + 10 × log(P/1mW).
(11)
The FOM2 can be calculated as −233 dB. Considered the TCand area, the third figure-of-merit (FOM3) is define as
FOM3 = 10 × log
(
ftarget × L2
P × TC × A
)
, (12)
Fig. 13. Measured best (a) phase noise and (b) reference spur among fivechips.
Fig. 14. Measured CFS transient response.
where L and A represent the minimum channel length andthe PLL core area, respectively. In Fig. 15, this chip occupies0.223 mm2 active area excluding PADs. The FOM3 is cal-culated as 90.5 dB. In this paper, most of the area is spenton the inductor and the loop filter; however, it used for the
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HSIEH AND LIU: 2.4-GHz FREQUENCY-DRIFT-COMPENSATED PLL WITH 2.43 ppm/◦C TEMPERATURE COEFFICIENT 9
Fig. 15. Chip photograph.
temperature compensation is only 0.0028 mm2. Comparedto [5]–[7], the proposed calibration circuit has a small area.
IV. CONCLUSION
An LC-VCO-based PLL with an FDC has been presentedin a 40-nm CMOS process. The FDC technique monitorsthe control voltage of the PLL in background. The FDCcompensates the frequency drift by adjusting the capacitorbanks of the VCO while the temperature is varying. As aresult, a constant PLL bandwidth and a fixed control voltagecan be achieved. Compared to the conventional approaches,the proposed technique digitalizes the calibration mechanismwithout using the PTAT/CTAT passive components to reducerequirement of the power and area. Referred to the per-formance summary of Table II, a 2.4 GHz PLL with thetemperature compensation is realized with the good FOMs.
ACKNOWLEDGMENT
The authors would like to thank TSMC University ShuttleProgram to fabricate the chip.
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Cheng-En Hsieh was born in Kaohsiung, Taiwan,in 1987. He received the B.S. degree in electricalengineering from the National University of Kaoh-siung, Kaohsiung, Taiwan, and the M.S. degree inapplied electronics technology from National TaiwanNormal University, Taipei, Taiwan, in 2009 and2012, respectively, where he is currently workingtoward the Ph.D. degree in electrical engineering.
His current research interests include PLLs andADCs for low-power applications.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Shen-Iuan Liu (S’88–M’93–SM’03–F’10) was bornin Keelung, Taiwan, in 1965. He received the B.S.and Ph.D. degrees in electrical engineering fromNational Taiwan University (NTU), Taipei, Taiwan,in 1987 and 1991, respectively.
From 1991 to 1993, he was a second Lieutenantwith the Chinese Air Force. From 1991 to 1994, hewas an Associate Professor with the Department ofElectronic Engineering, National Taiwan Institute ofTechnology, Taipei. In 1994, he joined the Depart-ment of Electrical Engineering, NTU, where he has
been a Professor since 1998, and has been a Distinguished Professor since2010. His current research interests include analog and digital integratedcircuits and systems.
Dr. Liu is a member of the Institute of Electronics, Information andCommunication Engineers. He was a recipient of the Engineering PaperAward from the Chinese Institute of Engineers in 2003, the Young ProfessorTeaching Award from MXIC Inc., the Research Achievement Award fromNTU, the Outstanding Research Award from National Science Councilin 2004, Award from Ministry of Science and Technology in 2014, and alsothe Himax Chair Professorship at NTU in 2010. He has the Outstanding
Research served as the Chair of the IEEE SSCS Taipei Chapter from2004 to 2008, which achieved the Best Chapter Award in 2009. He hasserved as the General Chair of the 15th VLSI Design/CAD Symposium,Taiwan, in 2004, and as a Program Co-Chair of the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka, Japan,in 2004. He served as a Technical Program Committee Member of ISSCCfrom 2006 to 2008, the IEEE VLSI-DAT from 2008 to 2012, and the A-SSCCfrom 2005 to 2012. He also served as the Technical Program CommitteeCo-Chair and the Chair for A-SSCC 2010 and 2011, respectively. He was anAssociate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from2006 to 2009, the IEEE TRANSACTION ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS from 2006 to 2007, the IEEE TRANSACTION ON
CIRCUITS AND SYSTEMS–I: REGULAR PAPERS from 2008 to 2009, andthe IEICE Transactions on Electronics, from 2008 to 2011. He was aGuest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS SpecialIssue in 2008 and 2012, respectively. He was on the Editorial Boardof Research Letters in Electronics from 2008 to 2009. He has been anAssociate Editor of the ETRI Journal and the Journal of SemiconductorTechnology and Science, South Korea, since 2009. He has also been onthe Editorial Board for International Scholarly Research Network Electronicssince 2011.
