A 2Gbps Optical Receiver with Integrated Photodiode in ... · A 2Gbps Optical Receiver with...

A 2Gbps Optical Receiver with Integrated Photodiode in

90nm CMOS

by

Alain Rousson

A thesis submitted in conformity with the requirementsfor the degree of Master of Applied Science

Graduate Department of Electrical and Computer EngineeringUniversity of Toronto

c© Copyright by Alain Rousson 2011

A 2Gbps Optical Receiver with Integrated Photodiode in

90nm CMOS

Alain Rousson

Master of Applied Science, 2011

Graduate Department of Electrical and Computer Engineering

University of Toronto

Abstract

The objective of this work was to integrate an optical receiver in a modern standard

technology in a form amenable to multiple lanes. To accomplish this goal, a photo-

diode was integrated with the receiver in a standard 90nm CMOS process and the

nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated

on chip with a pitch compatible with existing industry photodiode arrays. This work

uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3

times higher than values typically reported for SML photodiodes. This receiver is

the first integrated optical receiver reported in a standard CMOS technology with

a feature size smaller than 0.13µm, which is necessary for the eventual integration

of optical receivers with modern digital processing blocks on a single die. The tra-

ditional analog equalizer used in most integrated optical receivers is replaced with

a high-pass filter and hysteresis latch for equalization. The receiver occupies a core

area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate,

while consuming 46.3mW.

ii

Acknowledgments

I would like to sincerely thank my supervisor, Professor Tony Chan Carusone. His

guidance, and in particular, his patience, made writing this thesis enjoyable. He also

provided the resources to acquire the necessary equipement to perform optical testing

here at the University of Toronto.

Thank you to Professor Glenn Gulak, Professor Sorin Voinigescu, and Professor

Olivier Trescases for serving on my thesis examination committee.

Thanks to CMC for providing access to the TSMC 90nm CMOS technology node.

Thanks to Jaro Pristupa for providing CAD support. Thanks to the guys at FIB-X

for helping me get the chip up and running.

I’d also like to thank my colleagues: Kentaro for his help in the lab and all of the

students in BA5000 for making BA5000 such a fun place to work.

Finally, a great big high-five goes to Janessa.

iii

Contents

List of Figures vi

List of Tables ix

1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Background 62.1 Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.1 Photodiode Physics . . . . . . . . . . . . . . . . . . . . . . . . 62.1.2 Photodiode Model . . . . . . . . . . . . . . . . . . . . . . . . 72.1.3 Photodiode Simulation . . . . . . . . . . . . . . . . . . . . . . 9

2.2 State of the Art (extended) and Proposed Solution . . . . . . . . . . 102.2.1 Analog Equalizer to Extend the System Bandwidth . . . . . . 102.2.2 Decision Feedback Equalizer to Remove ISI . . . . . . . . . . 112.2.3 Proposed Solution . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 High-Pass Filter and Hysteresis Latch . . . . . . . . . . . . . . . . . . 122.3.1 High-Pass Filter Equalizer . . . . . . . . . . . . . . . . . . . . 132.3.2 Hysteresis Latch Model . . . . . . . . . . . . . . . . . . . . . . 14

2.4 System Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Circuit/System Design and Simulation 173.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . 173.1.2 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.1.3 Simulation Corners . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Transimpedance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 183.3 High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.4 Linear Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.5 Hysteresis Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.6 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.7 Complete Receiver Simulation Results . . . . . . . . . . . . . . . . . 34

4 Layout and Measurements 35

iv

Contents

4.1 Circuit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.1.1 Photodiode Layout . . . . . . . . . . . . . . . . . . . . . . . . 354.1.2 Chip Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.2.1 Electrical Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.2.2 Photodiode Responsivity Test . . . . . . . . . . . . . . . . . . 394.2.3 Optical Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5 Conclusion 555.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Layout Considerations 58

References 61

v

List of Figures

1.1 Optical receiver for long distance communications [1]. . . . . . . . . . 11.2 Cross section of a photodiode in a modified SiGe process [2]. . . . . . 31.3 Cross section of an unmodified photodiode that uses avalanche opera-

tion [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 Cross section of SML photodiode [4]. . . . . . . . . . . . . . . . . . . 41.5 Optical receiver using equalization to extend the system bandwidth [5]. 4

2.1 Cross section of CMOS photodiode. . . . . . . . . . . . . . . . . . . . 72.2 Photodiode current response. . . . . . . . . . . . . . . . . . . . . . . 92.3 (a) Photodiode response to -5dBm 5Gbps PRBS13 (b) Input signal. . 102.4 Block diagram of receiver using an analog equalizer [6]. . . . . . . . . 112.5 Block diagram of receiver using a IIR DFE [7]. . . . . . . . . . . . . . 122.6 Frequency response of proposed solution. . . . . . . . . . . . . . . . . 132.7 High pass filter equalizer model. . . . . . . . . . . . . . . . . . . . . . 132.8 (a) High-pass filter response (b) Step response. . . . . . . . . . . . . . 142.9 High-pass filter equalizer with hysteresis latch. . . . . . . . . . . . . . 142.10 The input to the photodiode model is a 5Gbps PRBS13 signal (a)

Output of the hysteresis latch (b) Hysteresis latch eye diagram (c)Equalizer output (d) Equalizer output eye diagram (e) Photodiodeoutput (f) Photodiode output eye diagram. . . . . . . . . . . . . . . . 16

3.1 Receiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 TIA block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.3 TIA core amplifier schematic. . . . . . . . . . . . . . . . . . . . . . . 193.4 TIA bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.5 High-pass filter schematic. . . . . . . . . . . . . . . . . . . . . . . . . 243.6 Eye diagram after the high-pass filter; 5Gbps PRBS31 -4dBm aver-

age power and 8.5dB extinction ratio input into the photodiode. Thesimulation covers 10000UIs. . . . . . . . . . . . . . . . . . . . . . . . 25

3.7 Block diagram of offset compensation. . . . . . . . . . . . . . . . . . 263.8 Linear amplifier schematic for one stage. . . . . . . . . . . . . . . . . 263.9 Linear amplifier input schematic for offset compensation. . . . . . . . 273.10 Linear amplifier frequency response. . . . . . . . . . . . . . . . . . . . 283.11 Eye diagram after the linear amplifiers; 5Gbps PRBS31 -4dBm aver-

age power and 8.5dB extinction ratio input into the photodiode. Thesimulation covers 10000UIs. . . . . . . . . . . . . . . . . . . . . . . . 29

3.12 Block diagram of the hysteresis latch [8]. . . . . . . . . . . . . . . . . 29

vi

List of Figures

3.13 Hysteresis latch schematic. . . . . . . . . . . . . . . . . . . . . . . . . 303.14 Threshold adjustments by changing Itail. . . . . . . . . . . . . . . . . 313.15 Eye diagram after the hysteresis latch; 5Gbps PRBS31 -4dBm average

power and 8.5dB extinction ratio input into photodiode. The simula-tion covers 10000UIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.16 Output buffer schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 333.17 Output buffer frequency response. . . . . . . . . . . . . . . . . . . . . 333.18 Eye diagram after the output buffer; 5Gbps PRBS31 -4dBm average

power and 8.5dB extinction ratio input into photodiode. The simula-tion covers 10000UIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 Annotated photo of the photodiode n-well/p-substrate photodiode. Itis 72µm × 78µm. The n-well is connected to metal 2, while the p-substrate is connected to metal 1. . . . . . . . . . . . . . . . . . . . . 36

4.2 Photo of bare die. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3 Photo of the die after the ablation of the aluminium over the photodiodes. 384.4 Close-up photos of the photodiode (a) The photodiode after original

manufacturing is covered by aluminium. (b) The photodiode after theablation of the aluminium. . . . . . . . . . . . . . . . . . . . . . . . . 38

4.5 Photo of the PCB used to test the chip. . . . . . . . . . . . . . . . . 394.6 Test setup for electrical testing. . . . . . . . . . . . . . . . . . . . . . 394.7 Eye diagrams with an electrical PRBS7 input to the board of 200mVpp

(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. . . . . . . . . 404.8 Eye diagrams with an electrical PRBS31 input to the board of 300mVpp

(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. . . . . . . . . . . 414.9 Test setup for photodiode responsivity testing. . . . . . . . . . . . . . 414.10 Photodiode responsivity test structure. . . . . . . . . . . . . . . . . . 424.11 Test setup for the optical testing. . . . . . . . . . . . . . . . . . . . . 424.12 Photo of the test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 434.13 Photo of the optical probe coupling to the integrated photodiode. . . 444.14 Eye diagrams with an average input power of -3.0dBm at 2.5Gbps (a)

Archcom Technology AC6538 (b) NewFocus 1554-A. . . . . . . . . . 444.15 Eye diagrams with an average input power of -1.9dBm and extinction

ratio of 4.8dB at 2.5Gbps (a) NewFocus 1554-A (b) receiver chip. . . 464.16 Eye diagrams with an optical PRBS7 input with an average input

power of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. . . . . . . . . 47

4.17 Eye diagrams with an optical PRBS31 input with an average inputpower of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. . . . . . . . . . . 48

4.18 BER vs. average optical input for a constant 9dBm extinction ratioand a 1.2V supply (a) PRBS7 input (b) PRBS31 input. . . . . . . . . 49

vii

List of Figures

4.19 Eye diagrams with an optical PRBS7 input with an average inputpower of -3.7dBm and an extinction ratio of 9dB and supply voltageof 1.3V (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. . . . . 50

4.20 Eye diagrams with an optical PRBS31 input with an average inputpower of -3.7dBm and an extinction ratio of 9dB and supply voltageof 1.3V (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. . . . . . 51

4.21 BER vs. average optical input for a constant 9dBm extinction ratioand a 1.3V supply (a) PRBS7 input (b) Pseudo-Random Bit Sequence(PRBS)31 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.22 Spice simulation output of the linear amplifier, with the plot on theleft having a PRBS7 input, and the plot on the right having PRBS31input. The blue lines represent a possible threshold value. . . . . . . 52

4.23 Eye diagram after the output buffer with revised photodiode model,4.25Gbps PRBS7 -4dBm average power and 8.5dB extinction ratioinput into photodiode. The supply voltage is 1.2V and the simulationtemperature is 27oC (a) TT simulation corner (b) SS simulation corner. 54

viii

List of Tables

3.1 Simulation corner parameters. . . . . . . . . . . . . . . . . . . . . . . 183.2 Comparison of TIA design parameters with [4] and [7]. . . . . . . . . 213.3 TIA simulation summary. . . . . . . . . . . . . . . . . . . . . . . . . 223.4 TIA monte-carlo simulation summary. . . . . . . . . . . . . . . . . . 223.5 Linear amplifier simulation summary. . . . . . . . . . . . . . . . . . . 283.6 Power consumption breakdown by voltage rail, which are both set to

1.2V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 Measurement results for optical testing. The chip is built in a stan-dard 90nm CMOS. The wavelength used is 850nm. The simulationresults are for a 1.2V supply voltage with a temperature of 27oC. Theextracted simulation are for 1000UIs. It is not possible to infer theoptical sensitivity from that length of simulation. . . . . . . . . . . . 53

5.1 Comparison of non-SML optical receivers. . . . . . . . . . . . . . . . 565.2 Comparison of most recently published optical receivers. . . . . . . . 56

ix

List of Acronyms

BER Bit Error Rate

BERT Bit Error Rate Tester

BiCMOS Bipolar Complementary Metal-Oxide-Semiconductor

CMOS Complementary Metal-Oxide-Semiconductor

DFE Decision Feedback Equalizer

ESD Electrostatic Discharge

FIB Focused Ion Beam

FPGA Field-Programmable Gate Array

IC Integrated Circuit

IIR Infinite Impulse Response

ILO Injection Locking Oscillator

ISI Inter-Symbol Interference

LAN Local-Area Network

LED Light Emitting Diode

MOSFET Metal-Oxide-Semiconductor Field Effect Transistor

OEIC Optoelectronic Integrated Circuit

NRZ Non-Return-to-Zero

PCB Printed Circuit Board

PRBS Pseudo-Random Bit Sequence

QFN Quad Flat No leads

RGC Regulated-Cascode

SML Spatially Modulated Light

x

List of Acronyms

SOI Silicon-on-Insulator

TIA Transimpedance Amplifier

TSMC Taiwan Semiconductor Manufacturing Company

UI Unit Interval

VCSEL Vertical-Cavity Surface-Emitting Laser

VGA Variable Gain Amplifier

xi

1 Introduction

1.1 Motivation

Fiber-optic interconnects have replaced electrical interconnects in long-distance data

communication. The receivers for these optical links are implemented on multiple

die as shown in Figure 1.1 [1], and on expensive technologies, such as GaAs [9],

or InP-InGaAs [10]. These solutions are relatively cost-insensitive due to the large

number of users per channel. For short-reach optical connections such as Local-Area

Network (LAN), board-to-board or chip-to-chip interconnects, there is only one user

per channel, meaning the system cost must be low. Short-reach optical links offer

advantages over electrical interconnects, since they are immune to crosstalk or other

electrical conductor affects that negatively impact performance [1].

The need for a low cost system puts certain limits on the system design, as low-cost

fibers and lasers are needed. Single-mode fibers are relatively inexpensive, however,

multi-mode fibers have relaxed alignment tolerances and a smaller bend radius, reduc-

ing the complexity of connectors and installation costs. The diameter of a multi-mode

fiber is approximately 50µm, therefore the photodiode area must be at least 50µm

in diameter [5]. Vertical-Cavity Surface-Emitting Lasers (VCSELs) that operate at

wavelengths of 850nm are the lowest cost lasers available, and are easy to test and

Figure 1.1: Optical receiver for long distance communications [1].

1

1 Introduction

mass-produce. Furthermore, silicon can absorb 850nm light. A receiver implemented

entirely in a standard Complementary Metal-Oxide-Semiconductor (CMOS) process

offers a very low manufacturing cost. Moreover, it is a single-chip solution, which

presents further advantages, such as eliminating ground-bounce issues, Electrostatic

Discharge (ESD) problems, and bond-wires [5].

The problem with optical receivers in CMOS technology is the low speed of silicon

photodiodes. The photodiode is built as a reverse bias PN junction, which creates a

depletion region that is used to collect the electron-hole pairs created when incident

photons are absorbed. However, the penetration depth of 850nm light is far greater

than the width of the depletion region, resulting in carriers generated deep in the

silicon that must diffuse to the depletion layer. This limits the bit-rate to tens of

Mbps [11]. Furthermore, smaller technology nodes operate at lower voltages with

higher doping levels, resulting in a smaller depletion region, which leads to smaller

photodiode intrinsic bandwidth, and photodiode responsivity [1][4]. However, it is

desirable to implement the optical receivers in nanoscale technologies where they can

be integrated alongside large amounts of digital logic.

1.2 State of the Art

Several methods were investigated to remove slow diffusing current in order to increase

the speed of the photodiode in CMOS Optoelectronic Integrated Circuits (OEICs).

Photodiodes built in modified Bipolar Complementary Metal-Oxide-Semiconductor

(BiCMOS) [2][12] technology have better performance than their unmodified CMOS

counterparts. Figure 1.2 shows the cross section of a modified photodiode. The

buried N+ layer is 10µm deep, creating a deep depletion region, resulting in a high

quantum efficiency. Furthermore, the N+/p-substrate junction shields the photodiode

from any slow diffusion currents generated in the p-substrate. The bandwidth of the

photodiode reported in [2] was 2.2GHz. The problem with this solution is that it is

expensive.

Another method is to increase the width of the depletion layer by using high reverse

bias voltages permitting avalanche operation [13][3]. Figure 1.3 shows the cross section

of an PIN photodiode fabricated in an unmodified CMOS process. The slow diffusion

currents generated in the p-substrate are still shielded by the deep n-well/p-substrate

junction, however, to completely deplete the p- layer, a voltage that is significantly

2

1 Introduction

Figure 1.2: Cross section of a photodiode in a modified SiGe process [2].

Figure 1.3: Cross section of an unmodified photodiode that uses avalanche opera-tion [3].

higher than the nominal supply voltage is required. This voltage can lead to reliability

issues, and can cause the system to be more complicated and expensive. In [3], a 6V

reverse bias voltage is required to to operate the receiver at 2.5Gbps. A 2V reverse

bias voltage limits the operation to 622Mbps.

Receivers also use a Spatially Modulated Light (SML) photodiode to increase the

photodiode intrinsic bandwidth [4][14][15]. Figure 1.4 shows a cross section of an SML

photodiode. An SML photodiode consists of uncovered photodiodes interleaved with

covered photodiodes. The covered photodiodes do not generate any drift current in

their depletion region. Diffusion currents generated deep in the substrate are collected

by both covered and uncovered diode connections. When the current collected by

both diodes are subtracted from each other, the diffusion currents are eliminated,

leaving only the drift current. This increases the bandwidth. Unfortunately, SML

photodetectors have a lower responsivity than a standard photodiode [1], since some

of the current is subtracted, and since the photodiode is more than 50% covered by

metal.

Finally, equalization is frequently used to extend the data rate. The concept is

illustrated in Figure 1.5. In [4][5][16][17][18], a high-pass analog equalizer is used to

3

1 Introduction

Figure 1.4: Cross section of SML photodiode [4].

Figure 1.5: Optical receiver using equalization to extend the system bandwidth [5].

extend the system bandwidth, while in [7], an Infinite Impulse Response (IIR) De-

cision Feedback Equalizer (DFE) is used to remove Inter-Symbol Interference (ISI).

A popular and promising approach is to combine an SML photodetector with equal-

ization, as seen in [4][16][17][18]. Since an SML photodiode has a larger bandwidth,

only modest equalization is required.

The highest data rate reported in a monolithically integrated CMOS optical re-

ceiver is 8.5Gbps at a sensitivity of -3.2dBm with a Bit Error Rate (BER) of 10−12

and 47mW power consumption [18]. The receiver uses a Regulated-Cascode (RGC)

Transimpedance Amplifier (TIA) to extend the TIA bandwidth, however, this ar-

chitecture also increases the total input-referred noise, thus decreasing the receiver

sensitivity.

In [19], a receiver with a 5.5Gbps data rate at a sensitivity of -3.4dBm with a BER

of 10−12 and 58.5mW power consumption is reported, using a standard shunt-feedback

TIA.

4

1 Introduction

1.3 Objective

The objective of this work is to enable parallel optical receivers integrated with digital

logic in standard nanoscale CMOS. To accomplish this goal, the photodiode is inte-

grated with the receiver in a standard 90nm CMOS process and the nominal process

voltage is not exceeded. This is the first receiver built in a CMOS technology that

is smaller than 0.13µm, other than the work published in [1]. The receiver in [1] is

built in 65nm CMOS, and integrates photodiodes connected to TIA and a 50Ω output

buffer to drive test equipment, but doesn’t consist of a complete optical receiver. The

work characterizes the intrinsic bandwidth and responsivity of different photodiode

structures.

In smaller feature-size CMOS processes, the lower supply voltage and smaller device

dimensions lead to a smaller depletion region. For the same incident wavelength, the

proportion of light captured in the depletion region compared to deep in the substrate

decreases, which decreases the intrinsic bandwidth of the photodiode [1][5]. This

explains why there are no other receivers in technologies smaller than 0.13µm.

The most exciting applications for this type of receiver are when it is integrated

alongside CMOS logic, which today are all in nanoscale technologies. In fact, Al-

tera has announced that they will integrate optical transceivers onto their Field-

Programmable Gate Arrays (FPGAs) to increase their bandwidth, and reduce the

system cost and power [20].

To allow parallel optical receivers on the same chip, there are two lanes integrated

with a pitch compatible with existing industry photodiode arrays.

The photodiode integrated with the receiver is a non-SML photodiode, since SML

photodiodes block over 50% of the light. Since a non-SML photodiode has severe

bandwidth limitations, linear equalization will be difficult. To perform the equaliza-

tion, the receiver will use pulse-signalling and a hysteresis latch.

1.4 Thesis Organization

Chapter 2 provides background information on CMOS photodiodes and simulation

results for the proposed system. In Chapter 3, the transistor-level design and simu-

lation results for each individual block in the system are shown. Chapter 4 discusses

the layout and the measurement results. Chapter 5 concludes the thesis and suggests

future research.

5

2 Background

This chapter provides background information on CMOS photodiodes in Section 2.1.

Section 2.2 revisits the receivers found in literature, and introduces the proposed

receiver architecture. Section 2.3 covers the proposed receiver in more detail, while

Section 2.4 provides system-level simulation results.

2.1 Photodiode

Photodiodes convert optical energy into electrical energy using the optical absorption

process, which is covered in more detail in [21]. This chapter will summarize the

information needed to understand photodiode operation. The model and simulation

results are for a silicon CMOS photodiode, as this is the most inexpensive semi-

conductor used in electronics. The photodiode model parameters of other popular

semiconductors can be found in [21].

2.1.1 Photodiode Physics

Light sources (Light Emitting Diodes (LEDs), lasers) are described by the vacuum

wavelength λ0 since it is independent of the medium. Photons have a fixed energy E

E = hυ =hc

λ=

hc0

λ0

. (2.1)

where υ is photon frequency, c is the photon velocity and λ is the photon wavelength.

The bandgap energy of the semiconductor material is denoted as Eg. When a

photon collides with an electron in the semiconductor valence band, it transfers its

energy if that energy is greater than the bandgap energy of the semiconductor (E >

Eg). The photon is absorbed, generating an electron-hole pair. The semiconductor

is transparent to light with wavelengths longer than λc = hc0/Eg. For silicon Eg =

1.1eV , and the longest wavelength that can be absorbed is λc = 1110nm.

6

2 Background

p-substrate

n-well

n+ p+

Light

AnodeCathode

Figure 2.1: Cross section of CMOS photodiode.

The optical absorption coefficient α of a semiconductor determines the penetration

depth 1/α, according to Lambert-Beer’s Law

Φ(x) = Φ0e−αx. (2.2)

Φ(x) is the light flux at depth x into the semiconductor. The absorption coefficients

of silicon for a 850nm wavelength is 0.06µm−1.

Photons absorbed in the semiconductor depletion region will cause carrier drift,

since there is an electric field present. Photons absorbed below and above the deple-

tion region will create minority carrier diffusion, which is much slower than carrier

drift. For light with a wavelength of 850nm, the average penetration depth is 18µm [7],

meaning that the ratio of light collected in the depletion region versus light collected

in the substrate below the depletion region is small.

2.1.2 Photodiode Model

The photodiode model is based on the frequency response of the carrier drift current,

Jdrift, and the minority carrier diffusion currents, Jdiff,e and Jdiff,h. A CMOS photo-

diode cross section is shown in Figure 2.1. The photodiode PN junction is formed by

the p-substrate and the n-well. When a reverse bias voltage is applied, a depletion

region is formed at the PN junction.

Photons absorbed in the depletion region form the Jdrift current. The photons

absorbed above and below the depletion region cause minority carrier diffusion in

7

2 Background

both the n-well (Jdiff,h) and the p-substrate (Jdiff,e). The total current is

Jtotal = Jdrift + Jdiff,h + Jdiff,e. (2.3)

The equations modelling the behaviour of the three currents are shown below.

Readers interested in the derivation of these equations are invited to consult [22].

The drift current is swept out of the depletion region by the electric field present.

According to [22], the drift current is much faster than the minority carrier diffu-

sion currents and the speed of the TIA. Consequently, the response is considered

frequency independent and proportional to the absorption coefficient and the width

of the depletion region [22]

Jdrift = qαWDR. (2.4)

α is the absorption coefficient, WDR is the width of the depletion region.

The Jdiff,e current equation is determined by the behaviour of minority carriers

(electrons) in the p-substrate within the first few diffusion lengths Ln below the

depletion region [22]

Jdiff,e = qαLne−αlx

∞∑

n=l

4

π2(2n − 1)2

1√

(

(2n−1)2πLn

l

)2

+ 1 + jωτn + αLn

. (2.5)

where lx is the depth of the n-well, τn is the electron lifetime, and l is the periodicity

of the structure. This parameter is used to model SML photodiodes. See [22] and [6]

for further reading on SML photodiodes. For regular photodiodes, l = 1. The current

response proves that for smaller α, the photodiode has a lower bandwidth, which is

caused by the photons penetrating deeper into the the p-substrate, causing greater

electron diffusion lengths.

The Jdiff,h current equation is determined by the behaviour of minority carriers

(holes) in the n-well above the depletion region. Holes have lower mobility than

electrons. However, since the depth of the n-well is very shallow in modern processes,

the diffusion lengths are much smaller than for Jdiff,e. The equation is [22]

Jdiff,h = qL2

p

l

32

π2

(1 − e−αlx)

lx

∞∑

n=1

∞∑

m=1

2lxly

(

12n−1

)2+ ly

2lx

(

12m−1

)2

(

(2n−1)πLp

2lx

)2

+(

(2m−1)πLp

ly

)2

+ 1 + jωτp

. (2.6)

8

2 Background

106

107

108

109

1010

−30

−25

−20

−15

−10

−5

Frequency [Hz]

Cur

rent

[dB

(A/W

)]

Total CurrentElectron Diffusion CurrentHole Diffusion CurrentDrift Current

Figure 2.2: Photodiode current response.

where lx is the depth of the n-well, ly is the length of the n-well, Lp is the diffusion

length of holes, and τp is the hole lifetime. The responsivity is small in this region

due to the shallow depth of the n-well in modern processes.

In smaller feature-size CMOS processes, the lower supply voltage and smaller de-

vice dimensions lead to a smaller depletion region, meaning the proportion of light

captured in the depletion region compared to deep in the substrate decreases. This

leads to a decreases of the intrinsic bandwidth of the photodiode [1][5].

2.1.3 Photodiode Simulation

The total current response of the photodiode along with the current response of the

three regions of interest are shown in Figure 2.2. The 3dB bandwidth is 33MHz

and the responsivity is 0.4A/W. Figure 2.3 shows the photodiode output for a 20ns

segment of a 5Gbps PRBS13 sequence. The DC value of the signal shifts from bit to

bit, which makes equalization more complicated.

9

2 Background

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−8

0

1

2

3

4

5

6x 10

−5

Time [sec]

Cur

rent

[A]

(a)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−8

−0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time [sec]

Pow

er −

Nor

mal

ized

[W]

(b)

Figure 2.3: (a) Photodiode response to -5dBm 5Gbps PRBS13 (b) Input signal.

2.2 State of the Art (extended) and Proposed

Solution

This section discusses solutions previously investigated to extend the bandwidth of

the photodiode model developed in Section 2.1. As mentioned in Section 1.2, a SML

photodiode can be used to eliminate slow diffusing current [6][14][15]. The two equal-

izer structures previously published are the use of an analog equalizer [6][5][16][17][18]

to extend the system bandwidth, and the use of an IIR DFE [7] to remove ISI. Finally,

the proposed architecture of this thesis is discussed.

2.2.1 Analog Equalizer to Extend the System Bandwidth

The block diagram of the receiver proposed in [6] is shown in Figure 2.4. The square

around the photodiode indicates it is covered, and does not convert light. This

structure is similar to the structure proposed in [5][16][17][18], especially regarding

the use of the equalizer.

The AC coupling serves two purposes. Since the input to the TIA is single-ended,

the AC coupling removes any DC offset in the differential output signal. The value

of the DC offset is dependent on the average input power. Furthermore, it allows

the TIA to be connected to the remaining circuit blocks, which operate at a different

supply voltage and DC offset voltage. The subtracter is used to improve the common-

mode rejection. The analog equalizer extends the bandwidth of the system, removing

10

2 Background

Figure 2.4: Block diagram of receiver using an analog equalizer [6].

ISI, however, this structure amplifies high frequency noise. The post-amplifier and

output buffer are needed to drive 50Ω per side external loads.

2.2.2 Decision Feedback Equalizer to Remove ISI

Using a DFE to remove the long tail of post-cursor ISI created by the slow diffusion

carriers requires too many taps, and therefore makes the power consumption excessive.

In [7], a DFE that uses a IIR filter to mimic the exponential tail of the photodiode

response is proposed. The DFE required the sum of 3 exponential responses to

properly model the photodiode response. The advantage of this structure is that only

one flip-flop is required, and once the coefficients of the IIR filters are set, they do

not need to be re-adjusted for different data rates.

The proposed block diagram is illustrated in Figure 2.5. The AC coupling block is

still needed to remove any DC offset in the differential output due to the single-ended

input, and allows the TIA to be connected to the remaining circuit blocks, which op-

erate at a different DC offset voltage. The Variable Gain Amplifier (VGA) guarantees

signal power to the DFE is constant regardless of the input optical signal power. The

half-rate IIR DFE follows the VGA, with its clock provided by an Injection Locking

Oscillator (ILO). The output buffer is used to drive 50Ω per side external loads.

This receiver requires many coefficients to be set for proper equalization. Further-

more, it is not very forgiving of inaccuracies in the photodiode model without some

kind of adaptation, which hasn’t been investigated as of yet.

2.2.3 Proposed Solution

The solutions presented in Section 2.2.1 and 2.2.2 attempt to remove the long tail of

the post-cursor ISI through two different mechanisms. However, both solutions use

11

2 Background

Figure 2.5: Block diagram of receiver using a IIR DFE [7].

AC coupling to connect the output of the TIA to the input of the equalization block,

and to remove the common-mode offset in the differential output signal caused by

the single-ended input. The corner frequency in both solutions is quite low, around

100kHz.

Pushing the corner frequency out to a multi-GHz value removes the common-mode

offset cause by the single-ended input, but it also removes all low-frequency content.

However, this property can be used to remove the slow-moving diffusion current from

the photodiode response. This mechanism is shown in Figure 2.6.

Recent work on replacing DC interconnects between a transmitter and receiver

with an AC interconnect is shown in [23]. The AC interconnect removes all low-

frequency content from the signal resulting in pulse-signaling. Since the problem

with the photodiode response is the shifting of the DC value, an AC interconnect can

be used as an equalizer within a receiver. The problem is returning the signal pulses

to Non-Return-to-Zero (NRZ) format, as this requires a non-conventional receiver.

This is achieved through a hysteresis latch, which is a non-linear circuit. This type

of equalization has been used in electrical links in the past [24].

2.3 High-Pass Filter and Hysteresis Latch

This section describes the combination of two components, the high-pass filter and

the hysteresis latch, used to perform the equalization of the receiver.

12

2 Background

105

106

107

108

109

1010

1011

−40

−35

−30

−25

−20

−15

−10

−5

0

Frequency [Hz]

Gai

n [d

B(A

/W)]

Photodiode ResponseHigh−Pass Filter ResponseTotal Response

Figure 2.6: Frequency response of proposed solution.

RCAC

Figure 2.7: High pass filter equalizer model.

2.3.1 High-Pass Filter Equalizer

The AC coupling is done through a standard RC high pass filter. The model is shown

in Figure 2.7. If the resistor R is set to a constant 200Ω differential, the capacitance

CAC can be modified to change the high-pass filter corner frequency.

A higher corner frequency reduces the pulse width, and consequently the total ISI.

This effect is shown in Figure 2.8. For proper equalization, the pulse width must be

less than 1Unit Interval (UI), and so a smaller capacitance value results in equalization

of data at higher bit rates. However, the smaller capacitance values will decrease the

pulse amplitude. The pulse amplitude must be greater than the minimum hysteresis

threshold and provide sufficient noise margin.

13

2 Background

105

106

107

108

109

1010

1011

−40

−35

−30

−25

−20

−15

−10

−5

0

Frequency [Hz]

Gai

n [d

B]

300fF5pF200pF

(a)

0 1 2 3 4 5

x 10−10

0

0.2

0.4

0.6

0.8

1

Time [s]

Am

plitu

de [V

]

300fF5pF200pF

(b)

Figure 2.8: (a) High-pass filter response (b) Step response.

Figure 2.9: High-pass filter equalizer with hysteresis latch.

2.3.2 Hysteresis Latch Model

The hysteresis latch is the receiver for the high-pass filter equalizer. It converts the

pulse signals to NRZ signalling. Figure 2.9 shows the receiver block diagram.

In the hysteresis latch, the received signal is compared to two threshold voltages,

Vth and −Vth. If the signal is above Vth, the output of the hysteresis latch is driven

to a logic 1. If the signal is below −Vth, the output of the hysteresis latch is driven

to a logic 0. If the received signal is between −Vth and Vth, the hysteresis latch holds

its value.

14

2 Background

2.4 System Simulation

Figure 2.10 shows the results of a MatLab model of the proposed receiver system

simulation. The input to the photodiode model is a 5Gbps PRBS13 signal. The

photodiode model output is shown in Figure 2.10(e). The time display is of a 20ns

segment of the input. For this simulation, the output buffer after the hysteresis latch

has a bandwidth of 6.5GHz. The pulse-signalling seen at the output of the high-pass

filter equalizer is shown in Figure 2.10(c). The corresponding eye diagrams are for a

5000UI segment of the 5Gbps PRBS13 input sequence.

15

2 Background

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−8

−0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time [sec]

Hys

tere

sis

Latc

h O

utpu

t [V

]

(a)

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−0.2

0

0.2

0.4

0.6

0.8

1

1.2

2UI

Hys

tere

sis

Latc

h O

utpu

t Eye

Dia

gram

[V]

Eye Diagram

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−8

−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15

0.2

Time [sec]

Equ

aliz

er O

utpu

t [V

]

(c)

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15

0.2

2UI

Equ

aliz

er O

utpu

t Eye

Dia

gram

[V]

Eye Diagram

(d)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10−8

0

1

2

3

4

5

6x 10

−5

Time [sec]

Pho

todi

ode

Out

put [

A]

(e)

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.50

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1x 10

−4

2UI

Pho

todi

ode

Out

put E

ye D

iagr

am [A

]

Eye Diagram

(f)

Figure 2.10: The input to the photodiode model is a 5Gbps PRBS13 signal (a) Out-put of the hysteresis latch (b) Hysteresis latch eye diagram (c) Equalizeroutput (d) Equalizer output eye diagram (e) Photodiode output (f) Pho-todiode output eye diagram.

16

50Ω

50Ω

Af 50Ω Vout

1.36kΩ

200Ω

300fF

Dummy

10pF

6MΩ

Photodiode TIA High-pass filter Hysteretic Comparator Output Buf.

Figure 3.1: Receiver block diagram.

3 Circuit/System Design and Simulation

This chapter presents the block and system level design of the optical receiver. The

system architecture is described in Section 3.1. Block level schematic design and

simulations are provided in Section 3.2 to Section 3.6. Section 3.7 details the full

system simulation results.

3.1 System Description

3.1.1 Circuit Description

The receiver is designed to handle signal data rates up to approximately 5Gbps, with

a change of input current signal of approximately 20µA.

The receiver block diagram is shown in Figure 3.1. The receiver begins with the

two photodiodes. The photodiode surrounded by the box is covered by metal, there-

fore it will not convert any optical power to electrical power. The purpose of this

photodiode is to balance the capacitance at both input nodes of the differential TIA.

The remaining photodiode will convert the optical signal to an electrical signal.

17


Table 3.1: Simulation corner parameters.

Corner Transistor Corner Temperature Supply VoltageTypical TT 27oC 1.2VSlow SS 85oC 1.2VFast FF 0oC 1.2V

The electrical signal is fed to the differential TIA, which converts the signal current

to a signal voltage. The TIA drives the high-pass filter described in Section 2.3, which

is used to remove ISI. The high-pass filter also acts as AC coupling between the TIA

and the linear amplifier stage, since they operate at different common-mode voltages.

The linear amplifier increases the signal swing. Any offset in the differential voltage

at the input will by amplified by the gain of this stage to overwhelm the signal at the

output. To solve this problem, offset compensation is included in this stage.

The hysteresis latch returns the signal to NRZ signalling levels, as described in

Section 2.3. The output buffer is included for testing. It needs to drive a 50Ω load

per side.

3.1.2 Technology

The design was implemented in the Taiwan Semiconductor Manufacturing Company

(TSMC) 90nm CMOS technology. It has 1 polysilicon layer, and 9 metal layers. The

supply voltage for this design is 1.2V.

3.1.3 Simulation Corners

The design was tested with three simulation corners, listed in Table 3.1, to ensure

that the circuit would operate properly despite process variations. The current den-

sities are controllable through external pins, and were kept constant across the three

simulation corners.

3.2 Transimpedance Amplifier

The TIA is the most critical block of the receiver design. The TIA is the first block,

meaning that its noise contributions dominate the total receiver noise. The other

18


Rf

Rf

1.36kΩ

1.36kΩ

VoutAf0.64V

Figure 3.2: TIA block diagram.

RD1 RD2

150Ω150Ω

Cm 135fF Vout

Vin

Vb

7.4mA7.4mA

100 × 2µm/0.12µm100 × 2µm/0.12µm

60 × 2µm/0.12µm60 × 2µm/0.12µm

VDD

M1 M2 M3 M4

M5 M6

Figure 3.3: TIA core amplifier schematic.

important specifications are the bandwidth, transimpedance and stability.

The TIA architecture is taken from [4]. The TIA block diagram is shown in Fig-

ure 3.2, and the core amplifier schematic is shown in Figure 3.3.

The transistor sizes have the format of Nf × Wf/Lf where Nf is the number of

fingers, Wf is the width of the fingers, and Lf is the length of the fingers. This

convention is used for all schematics.

19


In [4], the supply voltage for the TIA is 3.3V. In [7], the TIA uses the same

architecture as [4], but with a 1.2V supply voltage. Thus, the transistor sizing is

taken from [7], which is why the transistors do not have minimum lengths.

For this architecture, the bandwidth is

BWTIA =1

2πRin,T IACPD. (3.1)

where Rin,T IA is the input impedance of the TIA, and CPD is the parasitic capacitance

of the photodiode. The targeted bandwidth in [4] is 2.8GHz, while it is 3GHz in [7].

The input impedance of the TIA is

Rin,T IA =Rf

Af. (3.2)

where Rf is the feedback resistor, and Af is the gain of the core amplifier, both shown

in Figure 3.2. The core amplifier in [7] draws 9.3mW, and the core amplifier in [4]

draws 31.7mW. While the core amplifier gain is not specified in either work, the power

drawn suggests that the core amplifier in [4] has a higher gain, since the core gain is

given by

Af = (gmRD)2 . (3.3)

where gm is the transconductance of the transistors forming the differential pair,

and RD is the load resistances of the differential pair. Furthermore, the photodiode

capacitance in [4] is reported as 500fF, while the photodiode capacitance reported

in [7] is 2pF. To achieve the desired bandwidths, the feedback resistance, Rf , is 5.6kΩ

in [4], while it is only 300Ω in [7].

The transimpedance of the TIA is

RT =RfAf

Af + 1. (3.4)

and is approximately equal to Rf if the core amplifier gain is significantly higher

than 1. The transimpedance in [4] is 75dBΩ while it is only 49.5dBΩ in [7]. This

implies higher input-referred noise in [7], which is determined by integrating the TIA

output noise spectral density vn,out (f) from a low non-zero frequency (to ensure a

finite result in the presence of 1/f-noise) to twice the TIA bandwidth, and dividing it

20


Table 3.2: Comparison of TIA design parameters with [4] and [7].

Parameter [4] [7] This WorkPower Supply (V) 3.3 1.2 1.2

Core Amplifier Power (mW) 31.7 9.3 17.8Photodiode Capacitance (pF) 0.5 2 1.35

Feedback Resistor (kΩ) 5.6 0.3 1.36Midband Transimpedance (dBΩ) 75 49.5 62.3

Bandwidth (GHz) 2.8 3 3.3Input-referred noise current (µARMS) 0.19 2.9 1.1

by the midband transimpedance.

irmsn,TIA =

1

RT

∫ 2BWTIA

0+

vn,out (f) df. (3.5)

The input-referred noise reported in [4] is 0.19µArms, while it is 2.9µArms in [7].

Increasing the transimpedance from the 300Ω reported in [7] is a priority, since

it will relax gain requirements for subsequent stages, and reduce the input-referred

noise. To do so, the current through each stage of TIA is approximately doubled

from [7]. The widths of the transistors are increased to maintain a similar over-drive

voltage. This doubles the gm of the transistors. To keep the transistors in saturation,

but still keep the core amplifier gain high, the load resistors are only reduced from

200Ω to 150Ω. This reduces the TIA input DC bias voltage from 0.8V to 0.64V.

With these changes in place, a photodiode capacitance of 1.35pF, and a target

bandwidth of 3.5GHz, the value of the feedback resistor can be increased to 1.36kΩ.

Compared to [7], this increases the transimpedance to 62.7dBΩ and decreases the

input-referred noise to 1.1µA. The TIA input impedance is 32.7Ω. The parameters

of the three designs are tabulated in Table 3.2.

The frequency response of the TIA under the different corner conditions is shown

in Figure 3.4. The value of Cm was chosen to eliminate peaking in the frequency

response.

A summary of the TIA performance is shown in Table 3.3. Monte-carlo simulation

results for the TIA, which include mismatch and process variations in Rf , are shown

in Table 3.4.

A minimum open-loop phase margin of 60o would be a good target to robustly

21


107

108

109

1010

56

57

58

59

60

61

62

63

Frequency [Hz]

Tra

nsim

peda

nce

[dBΩ

]

Typical CornerSlow CornerFast Corner

Figure 3.4: TIA bandwidth.

Table 3.3: TIA simulation summary.

Corner Typical Slow FastMidband transimpedance (dBΩ) 62.3 62.4 62.3

Bandwidth (GHz) 3.3 2.5 4.0Peaking (dBΩ) 0 0 0

Phase margin (degree) 85 84.8 85.4Input-referred noise current (µARMS) 1.1 0.96 1.13

Table 3.4: TIA monte-carlo simulation summary.

Mean Standard deviation Number of ointsMidband transimpedance (dBΩ) 62.3 0.467 1000

Bandwidth (GHz) 3.05 0.421 1000Peaking (dBΩ) 4.05m 1.84m 1000

Phase margin (degree) 85.0 0.838 1000

22


minimize overshoot and guarantee stability. From these simulation results, the phase

margin is 85o, significantly higher than the required 60o. A re-designed TIA could fea-

ture less phase margin for better bandwidth and input-referred noise. The bandwidth

could be increased by reducing Rf , although this would decrease the transimpedance

and increase the input-referred noise. In [17][19], the core amplifier of the TIA has

four stages. Additional stages could be added to the core amplifier of the TIA in

this work to increase the core amplifier gain, which would increase the bandwidth. A

combination of additional stages in the core amplifier, and an increase in Rf would

result in a similar bandwidth, but higher transimpedance and lower input-referred

noise, with lower phase margin.

A further area of improvement would be using minimum-length transistors in the

TIA. In fact, if the length was decreased by a factor of λ = 120nm/100nm = 1.2 to a

minimum size of 100nm, either the bandwidth, or the transimpedance/input-referred

noise could be improved.

If the transistor is kept at a minimum length, and the overdrive voltage stays

constant, the total current per stage, I, will increase by λ. If RD1 and RD2 are kept

constant, the input and output common mode will decrease by 0.5 × IRD2 (λ − 1),

which should still leave enough headroom to keep all six transistors in the saturation

region. Furthermore, the poles at the inner node and at the output will increase by

λ.

The core amplifier gain, Af , will increase by λ2. If the feedback resistor, Rf , is kept

constant, the bandwidth will increase by a factor of λ2. The inpact on input-referred

noise is hard to quantify analytically. Since the closed-loop bandwidth increases,

the phase margin might decrease. However, if the feedback resistor is also increased

by λ2, then the bandwidth will stay constant, but the transimpedance will increase

by λ2. The input-referred noise is still hard to quantify analytically, but since the

transimpedance increases, the input-referred noise should decrease.

3.3 High-Pass Filter

The high-pass filter converts the output of the TIA to pulse-signalling. It also doubles

as an AC interconnect between the TIA and the linear amplifiers, so they can operate

at different DC offsets. Furthermore, it removes the common-mode offset in the

differential output of the TIA caused by the single-ended input.

23


VIN VOUTVCM

CAC

CAC

300fF

300fF

R

R

100Ω

100Ω

Figure 3.5: High-pass filter schematic.

The high-pass filter is taken from the work presented in [8]. The schematic is

shown in Figure 3.5. The input common-mode voltage of the linear amplifiers is set

to 900mV using the VCM pin. The corner frequency is

f3dB =1

2π

1

CACR= 5.3GHz. (3.6)

The eye diagram shown in Figure 3.6 is generated using a spice simulation. The

input is a 5Gbps PRBS31 signal with 5ps rise and fall time. It has a 400µV DC offset,

and a 600µVpp swing, to emulate an optical signal with -4dBm average power, and

8.5dB extinction ratio. This signal is passed through the photodiode model developed

in Section 2.1. The output of the photodiode model modulates a current source at

the input of the TIA. The eye diagram covers 10000UIs, and is of the output of

the high-pass filter. There are three distinct levels, a high-pulse, a low-pulse and no

pulse. The high-pulse indicates a low-to-high data transition. A low-pulse indicates a

high-to-low data transition. A zero means there was no transition in the data signal.

3.4 Linear Amplifier

The output of the high-pass filter is only 5mVpk, and needs to be amplified to be

able to reliably trigger the hysteresis latch. This is accomplished by a multi-stage

linear amplifier. In order to amplify the 5mV signal outputted by the filter to at least

120mV for the hysteresis latch, the gain must be at least 28dB. If the gain is increased

significantly more than 28dB, there is greater power consumption without increasing

24


Figure 3.6: Eye diagram after the high-pass filter; 5Gbps PRBS31 -4dBm averagepower and 8.5dB extinction ratio input into the photodiode. The simula-tion covers 10000UIs.

the effectiveness of the receiver. Furthermore, the linear amplifiers contribute to the

total input-referred noise of the receiver, but this contribution is reduced with a higher

gain per stage [25].

The architecture is shown in Figure 3.7. The schematic for each gain stage is

shown in Figure 3.8. The transistors are sized to have a bandwidth greater than

the bandwidth of the TIA, and cumulative gain of 28dB. The resistors are sized to

maintain the 900mV output common-mode voltage. The input of the linear amplifier

is shown in Figure 3.9, and is also taken from [4].

Since any offset voltage in the linear amplifier would be amplified and saturate

other stages, offset cancellation is required, as seen in Figure 3.7. The low-pass filter

is made using a 6MΩ resistor and two 5pF capacitors connected differentially, which

are smaller than the values reported in [4]. In [4], the resistor is 11MΩ and the single-

ended capacitor is 70pF. The capacitor can be halved with a differential structure.

The components are smaller in order to meet the 250µm pitch requirement for multiple

optical lanes [26][27][28]. Spice simulations confirm that the corner frequency is low

enough to properly compensate an offset caused by a difference of 20% in the width

of the first gain stage input pair.

The frequency response of the linear amplifier is shown in Figure 3.10. The midband

25


Figure 3.7: Block diagram of offset compensation.

RD

150Ω

VIN

VOUT

VB

20 × 2µm/0.12µm

50 × 2µm/0.12µm

2.7mA

VDD

M1 M2

M3

Figure 3.8: Linear amplifier schematic for one stage.

26


RD

150Ω

VIN

VOUT

VB2

20 × 2µm/0.12µm 20 × 2µm/0.12µm

50 × 2µm/0.12µm 50 × 2µm/0.12µm

2.7mA

VIN,OC

VB1

3.3mA

VDD

M1 M2 M3 M4

M5 M6

Figure 3.9: Linear amplifier input schematic for offset compensation.

27


102

104

106

108

1010

−10

−5

0

5

10

15

20

25

30

35

40

Frequency [Hz]

Gai

n [d

B]

Typical CornerSlow CornerFast Corner

Figure 3.10: Linear amplifier frequency response.

Table 3.5: Linear amplifier simulation summary.

Corner Typical Slow FastMidband gain (dBΩ) 30.0 29.3 33.3Bandwidth (GHz) 4.50 4.53 4.49

Offset compensation cut-off (kHz) 50.1 43.8 71.9

gain is 30.0dB. The total bandwidth is 4.50GHz, which is greater than the TIA

bandwidth. A summary of the linear amplifier performance is shown in Table 3.5.

The simulated differential output of the linear amplifier is shown in Figure 3.11.

The test input is the same as the input described in Section 3.3. The signal has

an opening of approximately 150mV, which is large enough to trigger the hysteresis

latch. An area of improvement would be using minimum-length transistors. The

linear amplifier power could be reduced while maintaining the same gain.

3.5 Hysteresis Latch

The hysteresis latch re-generates the low-frequency content of pulse-signalling, out-

putting NRZ signalling. The pulse signal is compared to a threshold value, which is

28


Figure 3.11: Eye diagram after the linear amplifiers; 5Gbps PRBS31 -4dBm aver-age power and 8.5dB extinction ratio input into the photodiode. Thesimulation covers 10000UIs.

Vin

Vout

RD1 RD2

RD3

gm−in gm−1

gm−2

Itail

Figure 3.12: Block diagram of the hysteresis latch [8].

set by a feedback path. The polarity is determined by the value of the most recent

pulse bit. The block diagram of the hysteresis latch, which is taken from [8][23], is

shown in Figure 3.12.

The hysteresis condition is [23]

gm−1R2gm−2R1 > 1. (3.7)

29


RD1

170Ω

RD2

200Ω

RD3

100Ω

VIN

VOUT

VB1VB2

10 × 2µm/0.12µm

10 × 2µm/0.12µm10 × 2µm/0.12µm

40 × 2µm/0.12µm40 × 2µm/0.12µm40 × 2µm/0.12µm

2mA Adjustable Adjustable

VDD

M1 M2 M3 M4

M5 M6

M7 M8 M9

Figure 3.13: Hysteresis latch schematic.

There is flexibility to minimize the settling time, since there are two gain stages, and

RD1 and RD2 can be manipulated. Furthermore, gm−2 works as a buffer between the

critical node and the next stage.

This design also uses a split-load [29], taking the feedback from the low-impedance

fast-settling node, and taking the output from the high-swing node. The feedback-

loop settling time is given by the time-constant RD1C1, where C1 is the capacitance

at the output of the feedback loop, and the output settling time is given by (RD2 +

RD3)CL, where CL is the output capacitance. See [23] for more details.

The schematic for the hysteresis latch is shown in Figure 3.13, which is the schematic

used in [8] to implement the hysteresis latch seen in Figure 3.12. The threshold volt-

age is set by changing the bias voltage VB2. A smaller current through M8 and M9

results in a smaller threshold voltage.

With the current through M8 and M9 set to approximately 1.5mA, the value of

gm−1 is 8.85mA/V and the value of gm−2 is 9.26mA/V. The hysteresis condition is

30


Figure 3.14: Threshold adjustments by changing Itail.

gm−1R2gm−2R1 = 8.85mA/V × 200Ω × 9.26mA/V × 170Ω = 2.8. (3.8)

which is greater than 1, and leaves a large safety margin for process, voltage and

temperature variations.

A plot of the differential output versus the differential input voltage is shown in

Figure 3.14, which shows the receiver hysteresis. The threshold voltage increases with

the current through M8 and M9.

The simulated differential output of the hysteresis latch is shown in Figure 3.15.

The test input is the same as the input described in Section 3.3. The output has

been re-generated to NRZ signalling levels. An area of improvement would be using

minimum-length transistors. There would be more flexibility in choosing the values

of gm, RD1, RD2 and RD3 to minimize the settling time, while keeping the power

consumption constant.

3.6 Output Buffer

The receiver performance will be measured by an oscilloscope and Bit Error Rate

Tester (BERT) which have a 50Ω input resistance. In order to provide proper match-

31


Figure 3.15: Eye diagram after the hysteresis latch; 5Gbps PRBS31 -4dBm averagepower and 8.5dB extinction ratio input into photodiode. The simulationcovers 10000UIs.

ing and signal swing, an output buffer whose output resistance is matched to 50Ω is

included after the hysteresis latch.

The output buffer’s bandwidth must be greater than the TIA. Despite the fact

that the small-signal approximation isn’t very accurate because of the relatively large

input signal, it can still be used as an approximation [6].

The BERT requires a minimum swing of 100mVpp per side. The load output

impedance is 25Ω per side, as the 50Ω output impedance of the buffer is in par-

allel with the 50Ω input impedance of the oscilloscope/BERT. The output buffer is

driving a bondwire inductance of 2nH and a package pin capacitance of approximately

1pF.

The swing requirement means the output buffer must drive a large current, 100mV/25Ω =

4mA. Consequently, the transistors need to be large, which loads the output of the

hysteresis latch. To reduce the load, multiple differential stages are used. The hys-

teresis latch can drive the first stage. The second stage draws more current, to be

able to drive the larger final stage, which must drive the 25Ω load per side. The

schematic is shown in Figure 3.16.

The small-signal bandwidth is 4.2GHz, as seen in the frequency response shown

in Figure 3.17. The simulated single-ended output of the output buffer is shown in

32


RD1

170ΩRD2

85Ω

RD3

50Ω

VIN

VOUT

VB1 VB2 VB3

20 × 2µm/0.12µm20 × 2µm/0.12µm 30 × 2µm/0.12µm

50 × 2µm/0.12µm 80 × 2µm/0.12µm80 × 2µm/0.12µm

2.7mA 5.2mA 5.2mA

VDD

M1 M2 M3 M4 M5 M6

M7 M8 M9

Figure 3.16: Output buffer schematic.

107

108

109

1010

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

Frequency [Hz]

Gai

n [d

B]

Figure 3.17: Output buffer frequency response.

Figure 3.18. The test input is the same as the input described in Section 3.3. The

swing is approximately 150mVpp per side, which is greater than the 100mVpp per side

needed by the BERT.

33


Figure 3.18: Eye diagram after the output buffer; 5Gbps PRBS31 -4dBm averagepower and 8.5dB extinction ratio input into photodiode. The simulationcovers 10000UIs.

Table 3.6: Power consumption breakdown by voltage rail, which are both set to 1.2V.

Block VDD Power (mW) oVDD Power (mW)TIA 17.5 0

Linear Amplifiers 23.2 0Hysteresis Latch 6.3 0Biasing Circuitry 3.0 0Output Buffer 0 17.4

Total 50.0 17.4

3.7 Complete Receiver Simulation Results

The simulation results of the complete receiver are presented in this chapter. The dif-

ferential signal at different stages of the receiver (Figure 3.1) are shown in Figure 3.6,

Figure 3.9, Figure 3.15, and Figure 3.18.

The power consumption breakdown is shown in Table 3.6. The measurement results

are reported in Chapter 4.

34

4 Layout and Measurements

This chapter presents the layout, test setup, and the measurement results for the

optical receiver chip. The chip was built in TSMC’s 90nm CMOS process, as de-

tailed in Section 3.1. Section 4.1 details the chip layout and Section 4.2 presents the

measurement results.

4.1 Circuit Layout

4.1.1 Photodiode Layout

The photodiode is built using an n-well/p-substrate structure, as detailed in Sec-

tion 2.1. An annotated photo of the photodiode is shown in Figure 4.1. It uses two

columns of seven fingers in order to reduce the transit time of the diffusion and drift

current components from the doped region to the metal contacts. The photodiode is

approximately 72µm by 78µm to facilitate the alignment of the 50µm fibre.

The n-well is connected to metal 2, which appears dark purple in the photo. The

metal 2 strip is 0.5µm wide, and uses two rows of contacts to the n-well. The p-

substrate is connected to metal 1, which appears blue in the photo. The metal 1 strip

is 1µm wide, and uses four rows of contacts to the n-well.

4.1.2 Chip Layout

A photo of the bare die is shown in Figure 4.2. The chip’s dimensions are 1.5mm by

1.0mm, resulting in an area of 1.5mm2. In addition to the DC optical test structure,

the chip has two optical receiver lanes, and an electrical breakout lane. Existing

high-speed photodiode arrays which operate at 850nm wavelength have a 250µm

pitch [26][27][28]. In order to meet this pitch requirement, each optical lane has a

dimension of approximately 895µm by 220µm for an area of 0.197mm2.

There are three visible photodiodes on the chip, with two more photodiodes that

are not visible. The photodiodes that are not visible are used to balance the input

35


Figure 4.1: Annotated photo of the photodiode n-well/p-substrate photodiode. It is72µm × 78µm. The n-well is connected to metal 2, while the p-substrateis connected to metal 1.

capacitive load to the TIA. The top two visible photodiodes create the two optical

receiver lanes, while the bottom photodiode is used in a DC test structure.

Figure 4.2 shows that the three photodiodes detailed above were covered in alu-

minium after the initial fabrication. The aluminium was placed over all passivation

layer openings, regardless of the actual aluminium layer definition. The aluminium

definition was only located under passivation openings used by the bond pads. This

aluminium blocked all light from entering the photodiodes, and had to be removed

using a Focused Ion Beam (FIB) which can do site-specific ablation of metal. The

die photo after the FIB process is shown in Figure 4.3. This figure also shows the

bondwires that connect the die to a 44 pin Quad Flat No leads (QFN) package. The

eighteen leftmost pads don’t have any electrical connections, and consequently are

not wirebonded. Close-up photographs of the photodiode before and after the FIB

process are shown in Figure 4.4.

36


Figure 4.2: Photo of bare die.

4.2 Measurements

The QFN package was mounted on a custom Printed Circuit Board (PCB), which

can be seen in Figure 4.5, for electrical and optical testing. The supply and common-

mode voltages were generated using voltage regulators. The bias currents were set by

varying potentiometers. This section details an electrical breakout test, a photodiode

responsivity test, and an optical speed test.

4.2.1 Electrical Test

The block diagram of the electrical test setup is shown in Figure 4.6. For all test setup

diagrams, solid lines represent high-speed electrical connection, dashed lines represent

optical connections, and dotted lines represent multimeter leads. The electrical test

was performed at a room temperature of 24oC. The PRBS generator has an output

impedance of 50Ω, but the input impedance of the TIA is significantly smaller, which

leads to a lot of reflections at the input. For this reason, it is hard to determine

the actual eye magnitude seen at the input of the TIA. The output of the electrical

breakout has a high BER if the input is smaller than 200mVpp for a PRBS7 input.

37


Figure 4.3: Photo of the die after the ablation of the aluminium over the photodiodes.

(a) (b)

Figure 4.4: Close-up photos of the photodiode (a) The photodiode after original man-ufacturing is covered by aluminium. (b) The photodiode after the ablationof the aluminium.

38


Figure 4.5: Photo of the PCB used to test the chip.

Figure 4.6: Test setup for electrical testing.

The eye diagrams of the electrical breakout are shown in Figure 4.7.

However, with a PRBS31 input, the input must be increased to 300mVpp, and there

are still obvious bit errors in the eye diagrams at 2.5Gbps and 3.125Gbps data rates.

The eye diagrams are shown in Figure 4.8.

4.2.2 Photodiode Responsivity Test

The block diagram for the photodiode responsivity test is shown in Figure 4.9. The

schematic of the test structure is shown in Figure 4.10. A 50µm/125µm optical

fibre couples the power emitted from a 850-nm VCSEL (Finisar HFE6192-562) to the

photodiode. The voltage drop across the resistor shown in Figure 4.10 is measured

39


(a) (b)

(c) (d)

Figure 4.7: Eye diagrams with an electrical PRBS7 input to the board of 200mVpp

(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps.

using a multimeter (Agilent 34401A), and the input optical power is measured using

a power meter (Noyes OPM4). The photodiode responsivity test was performed at a

room temperature of 24oC.

With an input signal of -0.16dBm (0.964mW), the voltage drop across the resistor

was 0.326V, for a total current of 135.6µA. The responsivity is 0.141A/W.

4.2.3 Optical Test

The block diagram of the optical test setup is shown in Figure 4.11. The transmit and

receive clock of the BERT (Centellax TG1B1-4) are generated by two synchronized

generators (Agilent 83712B and E8257D). The BERT can only adjust the phase of

40


(a) (b)

(c) (d)

Figure 4.8: Eye diagrams with an electrical PRBS31 input to the board of 300mVpp

(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps.

Figure 4.9: Test setup for photodiode responsivity testing.

the receive clock in 90o increments, so the two function generator setup allows for

more precision to set the receive clock phase.

The BERT generates the PRBS7 or PRBS31 signal which drives the VCSEL

41


2.4kΩ Pad

Photodiode

Figure 4.10: Photodiode responsivity test structure.

Figure 4.11: Test setup for the optical testing.

42


Figure 4.12: Photo of the test setup.

driver (Mindspeed M02171-EVM) which in turn modulates the VCSEL (Finisar

HFE6192-562). The power emitted from the VCSEL is coupled to the chip through

a 50µm/125µm optical fiber. The electrical output is differential; one of the outputs

is captured by an oscilloscope (Agilent DCA-J 86100C) to measure the eye diagram

while the second output is used by the BERT to compute the BER and determine

the optical sensitivity. A photo of the setup is shown in Figure 4.12. A photo of the

optical probe coupling to the integrated photodiode is shown in Figure 4.13. The

optical test was performed at a room temperature of 24oC.

To determine the extinction ratio, the optical signal is applied to a discrete pho-

todiode/TIA package. Two packaged photodiode/TIAs were used: the NewFocus

1554-A (with a conversion gain of -200V/W), and the Archcom Technology AC6538

(with a conversion gain of -450V/W). The outputs for both photodiode/TIA packages

are captured on an oscilloscope and shown in Figure 4.14.

The average input power is -3.0dBm (0.5mW). The eye is approximately 180mVpp

per side for the AC6538, and 150mVpp for the 1554-A. The extinction ratio for the

AC6538 is shown in Equations 4.1-4.4. The extinction ratio for the 1554-A is shown

in Equations 4.5-4.8. They are quite close, and so the extinction ratio is assumed to

be approximately 9dB.

Ppp =360mV

450V/W= 0.8mW (4.1)

43


Figure 4.13: Photo of the optical probe coupling to the integrated photodiode.

(a) (b)

Figure 4.14: Eye diagrams with an average input power of -3.0dBm at 2.5Gbps (a)Archcom Technology AC6538 (b) NewFocus 1554-A.

Phigh = 0.5mW + 0.4mW = 0.9mW = −0.46dBm (4.2)

Plow = 0.5mW − 0.4mW = 0.1mW = −10dBm (4.3)

ER = 9.5dB (4.4)

44


Ppp =150mV

200V/W= 0.75mW (4.5)

Phigh = 0.5mW + 0.375mW = 0.875mW = −0.58dBm (4.6)

Plow = 0.5mW − 0.375mW = 0.125mW = −9dBm (4.7)

ER = 8.5dB (4.8)

The overshoot shown in Figure 4.14(b) is due to the VCSEL turning on with such

a large extinction ratio, which causes relaxation oscillation [25]. The large extinction

ratio also causes the turn-on delay to experience random variations, meaning the

optical data has more jitter [25]. The extinction ratio and, hence, overshoot and

jitter, can be reduced by increasing the DC signal power while keeping the signal

swing constant. However, this increases the offset seen in the outputs of the TIA.

Furthermore, the power supply has to provide enough headroom for the TIA to

perform as expected despite this DC offset. For example, a 2.5Gbps optical signal

with -1.9dBm output and an extinction ratio of 4.8dB output has the same optical

swing as the previous setup, and the output of the NewFocus 1554-A photodiode/TIA

shown in Figure 4.15(a) shows the eye has significantly less ringing. Furthermore, the

rms-jitter decreases from 5.3psrms to 4.4psrms. However, Figure 4.15(b) is the output

of the chip, and the eye diagram is closed, since there is too much DC offset at the

output of the TIA. This suggests that offset compensation should act right on the

input of the TIA to remove the signal-dependent DC offset as in [28][30][31]. On the

other hand, offset cancellation right at the input would add input-referred noise.

The measured output eye diagrams with an average input power of -3.7dBm and

an extinction ratio of 9dB with a 1.2V supply is shown for various data rates with

a length-(27 − 1) pseudo-random pattern PRBS7 in Figure 4.16 and with a length-

(231 − 1) pseudo-random pattern PRBS31 in Figure 4.17.

Figure 4.18 shows a plot of BER against average input power for both the PRBS7

and PRBS31 input. These plots indicate the input optical sensitivity is -3.7dBm for

a 2Gbps PRBS31 input and -4.9dBm for a 2.5Gbps PRBS7 input. Hence, the optical

sensitivity can be greatly improved through the use of data encoding schemes, such

as 8b/10b. Furthermore, the BER at 4.25Gbps for the PRBS7 input, and the BER

at 3.125Gbps for the PRBS31 input, improve very little with an increase of input

optical power. This suggests that the receiver is limited by bandwidth, not noise.

The eye diagram measurements were repeated with the supply voltage increased to

45


(a) (b)

Figure 4.15: Eye diagrams with an average input power of -1.9dBm and extinctionratio of 4.8dB at 2.5Gbps (a) NewFocus 1554-A (b) receiver chip.

1.3V and all other measurement conditions that same as in Figure 4.16 and 4.17. The

results are shown in Figure 4.19 for a PRBS7 input and Figure 4.20 for a PRBS31

input.

Figure 4.21 shows a plot of BER against average input power for both the PRBS7

and PRBS31 inputs with the supply voltage increase to 1.3V. The BER gets better for

the PRBS31 inputs, but worse for the PRBS7 inputs. This suggests that the increased

supply voltage improves bandwidth (the main limitation in PRBS31 patterns) but

that the increased noise bandwidth hurts the PRBS7 patterns.

Hysteresis Threshold Dependence on Data Rate

The hysteresis threshold level was optimized to minimize BER for each data rate,

with an average input power level of -3.7dBm. This resulted in a higher hysteresis

threshold for lower bit rates. Figure 4.22 shows the spice simulation output of the

linear amplifiers with a PRBS7 input on the left, and a PRBS31 input on the right.

There is no noise in this simulation. The blue line shows one possible threshold value,

with the distance A showing the distance between the threshold value and the lowest

possible logic-1 pulse value. The distance B shows the distance between the threshold

value, and the highest possible ’no-transition’ value.

A higher hysteresis threshold, which increases the distance B, makes the receiver

less sensitive to noise. The pulses created by the PRBS31 input have a wider range

46


(a) (b)

(c) (d)

Figure 4.16: Eye diagrams with an optical PRBS7 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a)1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps.

of amplitudes compared to the pulses created by PRBS7. This is because the pulses

created by the PRBS31 input suffers from more baseline wander before the high-pass

filter. This decreases the distance A in the case of the PRBS31 input. Furthermore,

the pulse amplitudes decrease when the data rate is increased. The threshold value

is decreased to keep a similar value A.

This hysteresis threshold configuration leads to the BER of the receiver with a

small average input power being occasionally lower for higher input data rates, as

seen in Figure 4.21. For instance, in Figure 4.21(a), the BER of the 3.125Gbps signal

is lower than the 2.5Gbps signal at input average powers below -6dBm.

The reason this happens is that while a higher hysteresis threshold is less sensitive

47


(a) (b)

(c) (d)

Figure 4.17: Eye diagrams with an optical PRBS31 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a)1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps.

to noise, it won’t trigger properly with a very small input signal. However, a lower

hysteresis threshold is more sensitive to noise, but it will trigger properly for very

small input signals.

Analysis of Simulation Results

Increasing the supply voltage from 1.2V to 1.3V, and optimizing the TIA bias current

to minimize BER doesn’t change the TIA DC input bias from 0.63V. The photodiode

capacitance, responsivity, and intrinsic bandwidth are unchanged. The power drawn

by the core amplifier increases from 18.2mW to 23.2mW, using the calculation below

and the schematic shown in Figure 3.3.

48


−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510

−12

10−10

10−8

10−6

10−4

10−2

Average Optical Input Power [dBm]

Bit

Err

or R

ate

1.25 Gbps2.5 Gbps3.125 Gbps4.25 Gbps

(a)

−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510

−12

10−10

10−8

10−6

10−4

10−2


Bit

Err

or R

ate

1.25 Gbps2 Gbps2.5 Gbps3.125 Gbps

(b)

Figure 4.18: BER vs. average optical input for a constant 9dBm extinction ratio anda 1.2V supply (a) PRBS7 input (b) PRBS31 input.

IM5 = IM6 = 2 ×1.2V − 0.63V

150Ω= 7.6mA (4.9)

PTIA = 1.2V × (2 × 7.6mA) = 18.2mW (4.10)

The increase in power leads to an increase in the core amplifier gain, which will

decrease the input impedance. Since the photodiode capacitance is unchanged, the

TIA bandwidth increases. The transimpedance is unchanged. Since the output noise

spectral density is now integrated over a wider bandwidth, the total input-referred

noise increases. Spice simulations suggests the input-referred noise increases from

1.1µArms to 1.13µArms, and the bandwidth increases from 3.6GHz to 3.9GHz.

The change in supply voltage also increases the gain per stage of the linear am-

plifiers. Spice simulations also suggest that the linear amplifiers bandwidth remains

approximately constant, which is still significantly higher than the TIA bandwidth.

From these results, it is probable that the signal-to-noise ratio at the input of the

TIA degrades slightly with the change in power supply voltages.

The receiver had sufficient bandwidth with a 1.2V supply to equalize a PRBS7

input pattern. Hence, the increase in bandwidth with a 1.3V supply doesn’t improve

the performance. The higher input-referred noise degrades the BER. However, the

increase in bandwidth does improve the performance of the receiver with a PRBS31

input pattern, since this kind of pattern is more bandwidth dependent than a PRBS7

49


(a) (b)

(c) (d)

Figure 4.19: Eye diagrams with an optical PRBS7 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps.

input pattern. The bandwidth dependence of a PRBS31 input is due to the additional

baseline wander before the high-pass filter. This causes the pulses after the filter to

have a wider range of amplitudes, as shown in Figure 4.22. Increasing the bandwidth

of the TIA decreases the total amount of baseline wander, since the output signal

settles to its final value faster. This in turn decreases the vertical spread of the

pulse signal after the high-pass filter, resulting in a greater distance A, as seen in

Figure 4.22.

The measurement results are presented in Table 4.1. The simulation and measure-

ment results agree with respect to power consumption.

DC optical measurement results show that the DC responsivity is 0.141A/W instead

50


(a) (b)

(c) (d)

Figure 4.20: Eye diagrams with an optical PRBS31 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps.

of the 0.4A/W of the photodiode model. While the effect of the FIB process on the

optical responsivity is hard to measure, the difference is likely due to the inaccuracies

of the analytical model of the photodiode presented in Section 2.1. The analytical

model depends on dopant concentrations and diffusion lengths that are not published,

so they can only be estimated. A device simulator or actual photodiode measurement

results would provide a significantly more accurate model.

The intrinsic bandwidth of the photodiode can’t be measured using this prototype.

Furthermore, the bias currents are lower than the bias currents seen in TT simulations,

suggesting that the die is slower than the TT corner.

Figure 4.23 shows a new circuit simulation, where the response of the photodiode

51


−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510

−12

10−10

10−8

10−6

10−4

10−2


Bit

Err

or R

ate

1.25 Gbps2.5 Gbps3.125 Gbps4.25 Gbps

(a)

−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510

−12

10−10

10−8

10−6

10−4

10−2


Bit

Err

or R

ate

1.25 Gbps2 Gbps2.5 Gbps3.125 Gbps

(b)

Figure 4.21: BER vs. average optical input for a constant 9dBm extinction ratio anda 1.3V supply (a) PRBS7 input (b) PRBS31 input.

(a)

Figure 4.22: Spice simulation output of the linear amplifier, with the plot on the lefthaving a PRBS7 input, and the plot on the right having PRBS31 input.The blue lines represent a possible threshold value.

52


Table 4.1: Measurement results for optical testing. The chip is built in a standard90nm CMOS. The wavelength used is 850nm. The simulation results arefor a 1.2V supply voltage with a temperature of 27oC. The extractedsimulation are for 1000UIs. It is not possible to infer the optical sensitivityfrom that length of simulation.

Simulation 1.2V Supply 1.3V SupplyTotal chip area 1.5mm2

Receiver area 0.197mm2

Receiver power (minus output buffers) 50.0mW 46.3mW 55.2mWOutput buffer power 17.4mW 19.6mW 22.4mWOptical Sensitivity - -3.7dBm -4.7dBm

@ 2Gbps @ 2Gbps

is shifted down to the measured value, with the bandwidth left unchanged. This is

a complete noise transient simulation done using a full RC-extraction. The simula-

tion shows 1000UIs with a PRBS7 input. It is impossible to simulate the 1012UIs

necessary to measure a 10−12 BER. However, the eye opening is smaller with the

full RC-extraction and updated photodiode model than the eye shown in Figure 3.18.

Measurement results show that the BER should be approximately 10−4 with this

setup, according to Figure 4.18.

53


(a)

(b)

Figure 4.23: Eye diagram after the output buffer with revised photodiode model,4.25Gbps PRBS7 -4dBm average power and 8.5dB extinction ratio in-put into photodiode. The supply voltage is 1.2V and the simulationtemperature is 27oC (a) TT simulation corner (b) SS simulation corner.

54

5 Conclusion

5.1 Summary

Photodiodes in standard CMOS have intrinsic bandwidths that are at most in the

tens of megahertz, and very poor optical responsivity, resulting in small input current

swing, and long tail currents. There have been multiple methods explored to enable

multi-Gbps communications, but there are two solutions in particular that are the

most cost-effective and reliable, and consequently the most common in recent work.

The first is the use of SML photodiodes, which increase the intrinsic bandwidth of

the photodiode, but greatly reduce the optical responsivity [6][14][15]. The second

is the use of some method of equalization [6][5][16][17][18]. These two solutions are

frequently used together [6][16][17][18].

The objective of this work was to integrate an optical receiver in modern standard

technologies in a form amenable to multiple lanes. To accomplish this goal, the

photodiode was integrated with the receiver in a standard 90nm CMOS process and

the nominal process voltage was not exceeded. Two optical lanes were integrated on

chip with a pitch compatible with existing industry photodiode arrays.

The design uses a non-SML photodiode in order to provide higher optical respon-

sivity. The receiver uses a high-pass filter and hysteresis latch instead of an analog

equalizer to remove the long tail currents, since the severe bandwidth restrications

caused by th enon-SML photodiode make using an analog equalizer very difficult.

A chip was fabricated in TSMC’s 90nm CMOS to validate this design. The photo-

diodes were originally covered in aluminium, which was removed using a FIB process,

allowing optical communications. The measurement results of the optical receiver are

compared to other recent non-SML photodetector receivers in Table 5.1 and to the

most recently published optical receivers in Table 5.2.

55

5 Conclusion

Table 5.1: Comparison of non-SML optical receivers.

[5] [3] This work This workTechnology 0.18µm 0.18µm 90nmArea N/A 0.53mm2 0.197mm2

Supply Voltage 1.8V 6V / 3.3V / 1.8V 1.2V 1.3VPower Dissipationwo Output Buffer

34mW 108mW 46.3mW 55.2mW

Power Dissipation wOutput Buffer

50mW 138mW 65.9mW 77.6mW

Data Rate 3Gbps 2.5Gbps 2GbpsTest Pattern PRBS31 PRBS31 PRBS31Bit Error Rate 10−11 10−12 10−12

Sensitivity -19dBm -4.5dBm -3.7dBm -4.7dBmResponsivity - - 0.141A/W 0.236A/W

Table 5.2: Comparison of most recently published optical receivers.

[6] [18] [19] This work This workTechnology 0.18µm 0.13µm 0.13µm 90nmArea 0.72mm2 0.1mm2 1.88mm2 0.197mm2

Supply Voltage 3.3V / 1.8V 1.5V 1.2V / -1V 1.2V 1.3VPower Dissipationwo Output Buffer

168mW 47mW - 46.3mW 55.2mW

Power Dissipationw Output Buffer

183mW - 58.5mW 65.9mW 77.6mW

Data Rate 5Gbps 8.5Gbps 5.5Gbps 2GbpsTest Pattern PRBS31 PRBS31 PRBS7 PRBS31Bit Error Rate 10−12 10−12 10−12 10−12

Sensitivity -3dBm -3.2dBm -3.4dBm -3.7dBm -4.7dBmResponsivity 0.05A/W 0.05A/W - 0.141A/W 0.236A/W

56

5 Conclusion

5.2 Future Work

The next step is to conduct multi-channel testing to determine how simultaneous

operation of the two channels will effect the optical sensitivity. To do so, a more

specialized package is required to align a fiber optic multi-channel ribbon cable. The

two photodiodes have a separation of 250µm, the same as the channels in a standard

fiber optic ribbon [26][27][28].

To increase the data rate to at least 5Gbps, the receiver blocks should be re-designed

to be faster, with the main design objective being to reduce the settling time of the

hysteresis latch and increase the TIA bandwidth. The input-referred noise at the

input of the TIA also needs to be reduced.

This receiver operated with a small supply voltage, so there was less voltage head-

room to handle the DC offset in differential output of the TIA created by the single-

ended input. Hence, the VCSEL had to be operated with a large extinction ratio,

distorting the input eye. Adding offset compensation at the input of the TIA would

solve this problem.

Finally, it has been argued that scaled CMOS technologies degrade the intrinsic

photodiode bandwidth [1][5], but since the nominal supply voltage and the p-substrate

dopant concentration is very similar in both the 65nm and 90nm CMOS technology

nodes, the effect on the intrinsic bandwidth won’t be drastic. Consequently, an

integrated optical receiver should be validated in a standard CMOS technology with

a feature size of 65nm or smaller.

57

Layout Considerations

Pin Number Pin Name Pin Description

1 NC

2 NC

3 NC

4 NC

5 NC

6 NC

7 NC

8 NC

9 NC

10 NC

Continued on Next Page. . .

58


Continued


11 NC

12 NC

13 NC

14 NC

15 Vinp Differential input of electrical test structure.

16 Vinn Differential input of electrical test structure.

17 PDtest Output of photodiode DC test structure. The

schematic is shown in Figure 4.10.

18 Vdd Power supply. Nominal current is 116mA with a

1.2V supply.

19 Vcm Common-mode voltage. 900mV.

20 Vss Ground.

21 Vss Ground.

22 oVdd Output buffer power supply. Nominal current is

49mA with a 1.2V supply.

23 NC

24 Vss Ground.

25 Voutp3 Differential output of electrical test structure.

26 Voutn3 Differential output of electrical test structure.

27 Vss Ground.

28 Voutp2 Differential output of the second optical receiver.

29 Voutn2 Differential output of the second optical receiver.

30 Vss Ground.

31 Voutp1 Differential output of the first optical receiver.

32 Voutn1 Differential output of the first optical receiver.

33 Vss Ground.





Continued on Next Page. . .

59


Continued


36 bias1 Current that sets the biasing of the TIA. Nomi-

nal current is 230µA with a 1.2V supply, however,

it should be set so that the input common mode

voltage is approximately 630mV.

37 bias3 Current that sets the strength of the positive feed-

back in the hysteresis latch. The nominal cur-

rent is 395µA for a 1.25Gbps input, 380µA for a

2.5Gbps input and 310µA for a 3.125Gbps input,

all with a supply voltage of 1.2V

38 bias2 Current that sets the biasing of the remaining cir-

cuitry. The nominal current is 340µA with a 1.2V

supply.

39 Vcm Common-mode voltage. 900mV.


1.2V supply.


1.2V supply.

42 NC

43 NC

44 NC

60

References

[1] Anthony Chan Carusone, Hemesh Yasotharan, and Tony Kao, “Progress andtrends in milti-gbps optical receivers with cmos integrated photodiodes”, inCustom Integrated Circuits Conference, 2010. CICC ’10. IEEE, September 2010.

[2] R. Swoboda and H. Zimmermann, “11gb/s monolithically integrated siliconoptical receiver for 850nm wavelength”, in Solid-State Circuits Conference, 2006.ISSCC 2006. Digest of Technical Papers. IEEE International, February 2006, pp.904–905.

[3] Wei-Zen Chen and Shih-Hao Huang, “A 2.5 gbps cmos fully integrated opticalreceicer with lateral pin detector”, in Custom Integrated Circuits Conference,2007. CICC ’07. IEEE, September 2007, pp. 293–296.

[4] T.S.-C. Kao, F.A. Musa, and A.C. Carusone, “A 5-gbit/s cmos optical receiverwith integrated spatially modulated light detector and equalization”, Circuitsand Systems I: Regular Papers, IEEE Transactions on, vol. 57, no. 11, pp. 2844–2857, nov. 2010.

[5] Sasa Radovanovic, Anne-Johan Annema, and Bram Nauta, “A 3-gb/s opticaldetector in standard cmos for 850-nm optical communication”, Solid-State Cir-cuits, IEEE Journal of, vol. 40, no. 8, pp. 1706–1717, August 2005.

[6] Tony Kao, “A 5-gbps optical receiver with monolithically integrated photode-tector in 0.18µm cmos”, Master’s thesis, University of Toronto, 2009.

[7] Hemesh Yasotharan, “Equalization of integrated optical photodiodes using aninfinite impulse response decision feedback equalizer”, Master’s thesis, Universityof Toronto, 2011.

[8] M. Hossain and A.C. Carusone, “10 gb/s 70 mw burst mode ac coupled receiverin 90-nm cmos”, Solid-State Circuits, IEEE Journal of, vol. 45, no. 3, pp. 524–537, march 2010.

[9] Joongho Choi, Bing J. Sheu, and Oscal T.-C. Chen, “A monolithic GaAs receiverfor optical interconnect systems”, Solid-State Circuits, IEEE Journal of, vol. 29,no. 3, pp. 328–331, March 1994.

[10] Martin Bitter, Raimond Bauknecht, Werner Hunziker, and Hans Melchior,“Monolithic InGaAs-InP p-i-n/hbt 40-gb/s optical receiver module”, Photon-ics Technology Letters, IEEE, vol. 12, no. 1, pp. 74–76, January 2000.

61

References

[11] Carolien Hermans and Michiel S. J. Steyaert, “A high-speed 850-nm opticalreceiver front-end in 0.18-µm cmos”, Solid-State Circuits, IEEE Journal of, vol.41, no. 7, pp. 1606–1614, July 2006.

[12] J. Sturm, M. Leifhelm, H. Schatzmayr, S. Groiss, and H. Zimmermann, “Opticalreceiver ic for cd/dvd/blue-laser application”, Solid-State Circuits, IEEE Journalof, vol. 40, no. 7, pp. 1406–1413, July 2005.

[13] W.-K. Huang, Y.-C. Liu, and Y.-M. Hsin, “A high-speed and high-responsivityphotodiode in standard cmos technology”, Photonics Technology Letters, IEEE,vol. 19, no. 4, pp. 197–199, February 2007.

[14] C. Rooman, D. Coppee, and M. Kuijk, “Asynchronous 250 mbit/s optical re-ceivers with integrated detector in standard cmos technology for optocouplerapplications”, in Solid-State Circuits Conference, 1999. ESSCIRC ’99. Proceed-ings of the 25th European, September 1999, pp. 234–237.

[15] M. Jutzi, M. Grozing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-gb/s cmosoptical integrated receiver with a spatially modulated photodetector”, PhotonicsTechnology Letters, IEEE, vol. 17, no. 6, pp. 1268–1270, June 2005.

[16] Wei-Zen Chen, Shih-Hao Huang, Guo-Wei Wu, Chuan-Chang Liu, Yang-TungHuang, Chin-Fong Chin, Wen-Hsu Chang, and Ying-Zong Juang, “A 3.125 gbpscmos fully integrated optical receiver with adaptive analog equalizer”, in Solid-State Circuits Conference, 2007. ASSCC ’07. IEEE Asian, November 2007, pp.396–399.

[17] F. Tavernier and M. Steyaert, “Power efficient 4.5gbit/s optical receiver in 130nmcmos with integrated photodiode”, in Solid-State Circuits Conference, 2008.ESSCIRC 2008. 34th European, September 2008, pp. 162–165.

[18] Dongmyung Lee, Jungwon Han, Eunsoo Chang, Gunhee Han, and Sung MinPark, “An 8.5gb/s cmos oeic with on-chip photodiode for short-distance opticalcommunications”, in Solid-State Circuits Conference Digest of Technical Papers(ISSCC), 2010 IEEE International, February 2010, pp. 362–363.

[19] F. Tavernier and M. Steyaert, “A 5.5 gbit/s optical receiver in 130 nm cmoswith speed-enhanced integrated photodiode”, in ESSCIRC, 2010 Proceedings ofthe, sept. 2010, pp. 542 –545.

[20] Altera Corporation, “Altera charts new course for the industry with optical in-novation”, http://www.altera.com/corporate/news_room/releases/2011/

products/nr_lightyear.html, March 2011.

[21] Horst Zimmermann, Silicon Optoelectronic Integrated Circuits, Springer, 2004.

62

References

[22] Jan Genoe, Danniel Coppee, Johan H. Stiens, Roger A. Vounckx, and M. Kuijk,“Calculation of the current response of the spatially modulated light cmos de-tector”, Electron Devices, IEEE Transactions on, vol. 48, no. 9, pp. 1892–1902,September 2001.

[23] Masum Hossain, Low-power Multi-Gb/s Wireline Communication, PhD thesis,University of Toronto, 2010.

[24] Mohammad Hossein Shakiba, “A 2.5gb/s adaptive cable equalizer”, in Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEEInternational.

[25] Behzad Razavi, Design of Integrated Circuits for Optical Communication Sys-tems, McGraw–Hill, 2003.

[26] Kyosemi Corporation, “InGaAs photodiode array kpa4-2n/8-2n (4/8 channel)”,http://www.kyosemi.co.jp/product/data/en2/KPA4-2N_8-2N.html, 2011.

[27] Hamamatsu Corporation, “GaAs PIN photodiode array g8921-01”, http:

//sales.hamamatsu.com/assets/pdf/parts_G/g8921-01_kgpd1009e02.pdf,January 2004.

[28] C. Kromer, G. Sialm, C. Berger, T. Morf, M.L. Schmatz, F. Ellinger, D. Erni,G.-L. Bona, and H. Jackel, “A 100-mw 4 times;10 gb/s transceiver in 80-nmcmos for high-density optical interconnects”, Solid-State Circuits, IEEE Journalof, vol. 40, no. 12, pp. 2667 – 2679, dec. 2005.

[29] Y. M. Greshishev and P. Schvan, “A 60db gain 55db dynamic range 10gb/sbroadband SiGe hbt limiting amplifier”, in Solid-State Circuits Conference, 1999.Digest of Technical Papers. ISSCC. 1999 IEEE International, February 1999, pp.382–383.

[30] C. Kromer, G. Sialm, D. Erni, H. Jackel, T. Morf, and M. Kossel, “A 40 gb/soptical receiver in 80-nm cmos for short-distance high-density interconnects”, inSolid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, nov. 2006, pp.395 –398.

[31] F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H.F.Moghadam, X. Zheng, J.E. Cunningham, A.V. Krishnamoorthy, E. Alon, andR. Ho, “10 gbps, 530fj/b optical transceier circuits in 40nm cmos”, VLSI Cir-cuits, 2011. Digest of Technical Papers. 2011 Symposium on, pp. 290 –291, june2011.

63

Date post:	16-Jun-2020
Category:	Documents
Upload:	others
View:	2 times
Download:	0 times

A 2Gbps Optical Receiver with Integrated Photodiode in ... · A 2Gbps Optical Receiver with...

Documents