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NoCVision Design Space Exploration of Heterogeneous System Interconnect Dong-Hyeon Park, Vaibhav Gogte, Ritesh Parikh and Valeria Bertacco Bertacco Lab Designing correct heterogeneous systems Intel i7 980X - 2010 6 core; point-to-point bus Intel Xeon Phi – 2010-2013 >50 cores; 2D mesh Snapdragon 810 - 2014 SoC; custom network on chip Architectures are moving toward Heterogeneous Computing Future NoCs need to support wide range of complex IPs Interconnect designs need to be robust and flexible 1. Motivation Two tools for exploring complex NoCs Traffic Generator for interconnects of Heterogeneous Systems PacketGenie: Traffic Visualizer for Network-on-Chip Systems NoCVision: PacketGenie Purpose: Allow quick design-space exploration of heterogeneous NoC interconnect Extract application behavior and generate traffic based on system model PacketGenie Goals: Quick, light-weight simulation of NoC traffic behavior Highly flexible and configurable to accommodate heterogeneous architectures Easy to integrate with existing network simulators 2. PacketGenie CORE CORE CRYPTO MEM GPU CRYPTO GPU CORE MEM SIMD SIMD SIMD Traffic Testbench PacketGenie Heterogeneous System 3. NoCVision Debugging complex NoCs: Issues Analyze millions of cycles Debug large logs Proposed debug approach Graphical representation of traffic flow Extraction of relevant traffic details e.g. network congestion, bottlenecks etc. Implementation Capturing interval-based and event-based packet flow Visualization of a network topology: router, link or VC level information Traditional approach Topology configuration Simulation parameters NoC Simulator Traffic log Proposed approach 4. Injection Models Network Interconnect CORE CORE CORE CORE CORE GPU GPU GPU GPU SIMD SIMD SIMD SIMD Uniform Injection time Injection Rate Bursty Injection time Injection Rate Gaussian Injection time Injection Rate OnOff Injection CRYPTO CRYPTO CRYPTO CRYPTO SIMD SIMD 5. Example Configuration Memory MEM MEM MEM Encyption Engine CRYPTO CRYPTO GPU GPU GPU Compute CORE CORE CORE SIMD SIMD SIMD SIMD OnOff 6. Reply Timing Model Request Packet Reply Packet DRAM Memory Model: Fixed Reply Wait time Reply Time Probabilistic Reply Wait time P(reply) CORE GPU CORE CRYPTO 7. NoCVision Flow Link congestion Router utilization Packet Traversal Parameter Threshold Network topology configuration Traffic data associated with router, link or VC of NoC Mode of operation - Interval mode or event mode time intervals events 8. NoCVision – Modes of Operation Type 1: Interval Mode Interval-based packet flow Link, router and VC utilization across time windows Color intensity represents parameters e.g. congestion, utilization etc. Type 2: Event Mode Determine region-of-interest and log data for specific events Parse through the data across events Interval 1 Heavily utilized routers Link gets congested in the next interval Interval 2 Event 2 Event 3 Events plotted – Traversal of packet IDs 4 & 6 Event 1 Packet id 4 Packet id 6 9. Case-study – High Radix vs. Low Radix High Radix Hybrid router Longer path due to routing restrictions Heavily communicating pairs (color indicates the pairs) Hybrid: Adaptive 3D torus Avg Hop Count = 3.5 Application-adaptive topology reconfiguration: Employs routers with few ports as in low-radix topologies and many links as in high-radix routers Reconfigures network to enable low-latency path between heavily communicating src-dest pairs NoCVision was used to analyze the routing in various topologies: low-radix, high-radix and hybrid Low-radix: 2D mesh Avg Path Length = 5 High-radix: 3D torus Avg Path Length = 3 PacketGenie
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Page 1: A Back-End Design Flow for Single Chip Radiosweb.eecs.umich.edu/~valeria/lab/prosp/PG_NoCV_poster.pdfDong-Hyeon Park, Vaibhav Gogte, Ritesh Parikh and Valeria Bertacco Bertacco Lab

No

CV

isio

n

Design Space Exploration of Heterogeneous

System Interconnect Dong-Hyeon Park, Vaibhav Gogte, Ritesh Parikh and Valeria Bertacco

Bertacco Lab Designing correct

heterogeneous systems

Intel i7 980X - 2010

6 core; point-to-point bus

Intel Xeon Phi – 2010-2013

>50 cores; 2D mesh

Snapdragon 810 - 2014

SoC; custom network on chip

Architectures are moving toward Heterogeneous Computing

• Future NoCs need to support wide range of complex IPs

• Interconnect designs need to be robust and flexible

1. Motivation

Two tools for exploring complex NoCs

Traffic Generator for interconnects of Heterogeneous Systems

PacketGenie:

Traffic Visualizer for Network-on-Chip Systems

NoCVision:

PacketGenie Purpose:

• Allow quick design-space exploration of heterogeneous NoC interconnect

• Extract application behavior and generate traffic based on system model

PacketGenie Goals:

• Quick, light-weight simulation of NoC traffic behavior

• Highly flexible and configurable to accommodate heterogeneous architectures

• Easy to integrate with existing network simulators

2. PacketGenie

CORE

CORE CRYPTOMEM

GPU

CRYPTO

GPU

CORE MEM

SIMDSIMD

SIMD

Traffic

TestbenchPacketGenie

Heterogeneous System

3. NoCVision

Debugging complex NoCs: Issues

• Analyze millions of cycles

• Debug large logs

Proposed debug approach

• Graphical representation of traffic flow

• Extraction of relevant traffic details e.g. network congestion, bottlenecks etc.

Implementation

• Capturing interval-based and event-based packet flow

• Visualization of a network topology: router, link or VC level information

Traditional

approach

Topology configuration

Simulation parameters

NoCSimulator

Traffic log

Proposed

approach

4. Injection Models

Network

Interconnect

CORE CORE

CORECORE

CORE

GPU

GPU

GPUGPU

SIMDSIMDSIMD

SIMD

Uniform Injection

time

Inje

ctio

n R

ate

Bursty Injection

time

Inje

ctio

n R

ate

Gaussian Injection

time

Inje

ctio

n R

ate

OnOff Injection

CRYPTO

CRYPTOCRYPTO

CRYPTO

SIMD

SIMD

5. Example Configuration

Memory

MEMMEMMEM

Encyption

Engine

CRYPTOCRYPTO

GPU

GPUGPU

Compute

CORECORE

CORE

SIMD

SIMDSIMDSIMD

OnOff

6. Reply Timing Model

Request Packet

Reply Packet

DRAM Memory Model:

Fixed Reply

Wait time

Rep

ly T

ime

Probabilistic Reply

Wait time

P(r

eply

)

CORE

GPU

CORE

CRYPTO

7. NoCVision Flow

Link

congestion

Router

utilization

Packet

Traversal

Parameter

Threshold

Network topology

configuration

Traffic data associated

with router, link or VC of

NoC

Mode of operation -

Interval mode or

event mode

time intervals

events

8. NoCVision – Modes of Operation

Type 1: Interval Mode

• Interval-based packet flow

• Link, router and VC utilization across time windows

• Color intensity represents parameters e.g. congestion, utilization etc.

Type 2: Event Mode

• Determine region-of-interest and log data for specific events

• Parse through the data across events

Interval 1

Heavily utilized routers

Link gets congested in

the next interval

Interval 2

Event 2

Event 3

Events plotted –Traversal of packet

IDs 4 & 6

Event 1

Packet id 4

Packet id 6

9. Case-study – High Radix vs. Low Radix

High Radix

Hybrid router

Longer path due to routing restrictions

Heavily communicating pairs (color indicates the pairs)

Hybrid: Adaptive 3D torus

Avg Hop Count = 3.5

Application-adaptive topology reconfiguration:

• Employs routers with few ports as in low-radix topologies and

many links as in high-radix routers

• Reconfigures network to enable low-latency path between

heavily communicating src-dest pairs

NoCVision was used to analyze the routing in various topologies: low-radix, high-radix and hybrid Low-radix: 2D mesh

Avg Path Length = 5

High-radix: 3D torus

Avg Path Length = 3

PacketG

en

ie

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