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A concept for theMVD-DAQ

C.Schrader, S. Amar-Youcef, N. Bialas, M. Deveaux, I.Fröhlich, J. Michel, B. Milanovic, C. Müntz, S. Seddiki, J. Stroth,

T. Tischler, B. Wiedemann

C.Schrader; April 2010, CBM Collaboration Meeting

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2C.Schrader; April 2010, CBM Collaboration Meeting

Outline:

1. Requirements on the prototype

2. The prototype sensor (Mimosa26)

3. The prototype readout concept

based on existing hardware

4. Network concept

5. Status and conclusion

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C.Schrader; April 2010, CBM Collaboration Meeting

The Demonstrator

analogue output

sync. signals

demo-AUX

MAPS add-on board

Trb2(TRBnet)

file server

monitoring

data transfer: I/O-card

data transfer: OP

-link

or

Beam test @ Cern-SPSNov 2009

Demonstrator project

accomplished

See talk of Samir

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C.Schrader; April 2010, CBM Collaboration Meeting

The project aims at improve:

• low material budget

• mechanical integration

• cooling

• fast sensor readout

• scalable DAQ-system for the full MVD (e.g. 20 sensors first station)

• a whole network structure

from the front-end to the PC

Why a prototype?

A prototype to meets the requirements for the CBM MVD A prototype to meets the requirements for the CBM MVD

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C.Schrader; April 2010, CBM Collaboration Meeting

M. Deveaux, ULISI kick-off meeting, GSI, Feb. 17-18, 2010

CBM

wish list

MAPS*

(2003)

MAPS*

(2009)

Mimosa26

Binary, 0

Single point res. ~ 5 µm 1.5 µm 1 µm 4 µm

Material budget < 0.3% X0 ~ 0.1% X0 ~ 0.05% X0 ~ 0.05% X0

Rad. hard. non-io. >1013 neq 1012 neq/cm² >3x1013 neq few 1012 neq

Rad. hard. io > 3 Mrad 200 krad > 1 Mrad > 300 krad

Time resolution < 30 µs ~ 1 ms ~ 25 µs 110 µs

Best values reached Current compromise

Sensors of the prototype

Mimosa26 offers:• logic for data reduction• huge pixel array (form factor for the final MVD)• multiplexer for faster readout• inspiration for the final MVD sensor (MimoSIS-1)

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* best of

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C.Schrader; April 2010, CBM Collaboration Meeting

Mimosa26analogue Outputsanalogue Outputs

pixel array:1152 columns x 576 rows

(18,4 µm pitch and 115,2 µs readout time)

pixel array:1152 columns x 576 rows

(18,4 µm pitch and 115,2 µs readout time)

JTAGJTAG Digitalinput

Digitalinput

Digital outputDigital output PLLPLLTemp

probeTempprobe

Discritest

Discritest PowerPower

Signal discriminationzero suppression logic

correlated double sampling

2 channels80 MHz

160 Mbit/s ~ 80 Mbit/s (570 words of 16 bit ~ 9120 bit/frame)

9 hits/ row

Mi26 protocol allows:∑ 570 hits

multiplexingDemonstrator: Mimosa20 with analogue readout2.4Gbit/suncompressed

chip slow control

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C.Schrader; April 2010, CBM Collaboration Meeting

• readout board for 3x Mimosa 26• platform to study online data

specification for data reduction • compatibility with HADES DAQ

(Trb2) for testing purposes

developed by IKF electronic workshop

The add-on board with a FPGA Is mounted on the TRBv2 back side

The Trbv2 (HADES) provides a flexible add-on board concept

• high data-rate digital interface

connector (15 Gbit/s)

• FPGA configuration

• high data transfer with optical link

(2 Gbit/s)

• application process interface (API)

• power supply +5V,10A

• clock distribution

The readout boards

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C.Schrader; April 2010, CBM Collaboration Meeting

The prototype readout

A telescope to study:• Protocol

– scalable (unique ID for 512 sensors)– time/trigger stamps (for assynchronous readout

of the sensors)– safety aspects (check- sum and data length)– data reduction (160 Mbit/s down to 80 Mbit/s)– buffered readout

• JTAG chain• Online monitoring• Beam tests

• Offline analysis/tracking (CBM-root) 2m2m

2m2m

1x Start,clk,Rst(LVDS)1x Start,clk,Rst(LVDS)

15 cm15 cm

3x D0,D1,CLK(LVDS)3x D0,D1,CLK(LVDS)

2m2m

3 stations „telescope“ vacuum

133 Mbyte/s~ 13 sensors

JTAG chainJTAG chain

control chaincontrol chain

data outputdata output

Mimosa26 Digi Aux

JTAG board

MAPS add-on

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Scalable DAQ-system

To study:• Scalable system (unique ID for boards)• Board synchronisation• Repeater for signal conditioning

1x RJ451x RJ45

1x Start,clk,Rst(LVDS)1x Start,clk,Rst(LVDS)

3x D0,D1,CLK(LVDS)3x D0,D1,CLK(LVDS)

3x D0,D1,CLK(LVDS)3x D0,D1,CLK(LVDS)

MAPS add-onI/O limitation for only 3 sensors

Mimosa26 Digi Aux

JTAG board

MAPS add-on

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C.Schrader; April 2010, CBM Collaboration Meeting

Data rate of the sensors was simulated accounting for: pile-up, delta electrons, clustering,fake hits rates with the data protocols of Mimosa26

Conclusions:

Total data rate of the MVD 10 GBytes/s

First MVD station located at 5 cm

See talk ofS.Seddiki

Data rate for the MVD

Data rate of individual sensor < 2.4 Gbit/s

Data reduction on FPGA boards

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C.Schrader; April 2010, CBM Collaboration Meeting

4x LVDS JTAG3x LVDS clk/start/rst

3x LVDS D0,D1,clk

2x optical link (each 2 Gbit/s)> 30 Mimosa26/board

2x optical link (each 2 Gbit/s)> 30 Mimosa26/board

.

.

.

New add-on board:- chip controlling- chip mointoring- protocol for front-ends- network protocol (TrbNet)- … (telescope studies)

Trbv2:- JTAG- power supply- monitoring

digital chip data via optical link (2 Gbit/s)

2m2m

New readout board

The readout board can be used as computing node• Fake hit suppression

cluster building• Hit finding

…

The readout board can be used as computing node• Fake hit suppression

cluster building• Hit finding

… N S

N N S

√ -N N S

MIMOSA26 readout:Seed pixel andthe successive two Neighbor pixels

N

Algorithms h

ave to be stu

died

Algorithms h

ave to be stu

died

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C.Schrader; April 2010, CBM Collaboration Meeting

Hub-AddOn (HADES)

• 20x up to 3.125 Gbit/s

(~1.2 Gbit/s raw data)

• Capable of Gigabit-Ethernet to

send data to standard PCs (TCP)

• Implements basic data processing

features

• Buffered readout

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Successf

ul teste

d

Successf

ul teste

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C.Schrader; April 2010, CBM Collaboration Meeting

PC-Interface: PEXOR 3

• PCI-Express card (x4)

• Fast Lattice SCM40 FPGA

• 4 optical links up to 3.8 Gbit/s each

• PCI-Express bus up to 4 Gbit/s

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Hardware available jet

Hardware available jet

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C.Schrader; April 2010, CBM Collaboration Meeting

.

.

.

.

.

.

.

.

.

PCoptical

link- PCI-express-

card

TrbNet protocolFPGA boards

PCI Express card4x 3.8 Gbit/sPCI express bus: 4 Gbit/s~ 50 x Mimosa26 unbuffered

PCI Express card4x 3.8 Gbit/sPCI express bus: 4 Gbit/s~ 50 x Mimosa26 unbuffered

up to 2 Gbit/s

MVD readout setup

HubInput: 16 x optical links (8x 30 Mimosa26)Output: 4x optical links~ 240 sensors buffered

HubInput: 16 x optical links (8x 30 Mimosa26)Output: 4x optical links~ 240 sensors buffered

up to 3.8 Gbit/s

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See talk of B. Milanovic

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C.Schrader; April 2010, CBM Collaboration Meeting15

The new front-endDigi AuxMIMOSA-26

JTAG board

• All in one• Highly integrated• Vacuum compatible• Suffix to cooling concept• Radiation tolerant• Bus concept• Advanced flex print cable (e.g. IMEC :

sensors in ultra thin polyamide film)• …

• All in one• Highly integrated• Vacuum compatible• Suffix to cooling concept• Radiation tolerant• Bus concept• Advanced flex print cable (e.g. IMEC :

sensors in ultra thin polyamide film)• …

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Summary and conclusion

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Thank you

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