Abstract—A dual-mode built-in self-test (BIST) scheme whichpartitions the fixed (instead of movable) capacitance plates of acapacitive microelectromechanical system (MEMS) device is pro-posed. The BIST technique divides the fixed capacitance plate(s) ateach side of the movable microstructure into three portions: one forelectrostatic activation and the other two equal portions for capac-itance sensing. Due to such a partitioning method, the BIST tech-nique can be applied to surface- and bulk-micromachined MEMSdevices and other technologies. Further, the sensitivity and sym-metry dual BIST modes based on this partitioning can also be de-veloped. The combination of both BIST modes covers a larger de-fect set, so a more robust testing result for the device can be ex-pected. The BIST technique is verified by three typical capacitiveMEMS devices. Simulation results show that the proposed tech-nique is an effective BIST solution for various capacitive MEMSdevices.
Index Terms—Built-in self-test (BIST), capacitive microelec-tromechanical system (MEMS), MEMS testing, sensitivity test,symmetry test.
I. INTRODUCTION
ACCORDING to the International Technology Roadmapfor Semiconductors, 2002 Updates, MEMS will begin to
be integrated into system-on-Chip (SoC) designs soon.1 Thus,we can expect that MEMS devices will be fabricated on thesame chip with digital, analog, memory, and field programmablegate-array (FPGA) circuit technologies very soon. For this pur-pose, a thorough and effective testing solution for MEMS de-vices is in an emergent need to ensure reliability. However, thegreat diversity of MEMS structures and their working princi-ples, various defect sources, multiple field coupling, as well asthe essential analog features, make MEMS testing very chal-lenging [1]–[6].
MEMS devices are calibrated before shipping. However, newdefects may be developed during in-field usage. Calibration isnot convenient after MEMS devices are released. Sensitivity
Manuscript received August 12, 2004; revised May 31, 2005. This work wassupported in part by Hong Kong RGC Grant CUHK4229/03E, NSFC/RGCN_CUHK405/02, RGC Direct Grant 2050320, and the Ohio Board of Regent.
X. Xiong is with the Department of Electrical and Computer Engineering,University of Bridgeport, Bridgeport, CT 06604 USA (e-mail: [email protected]).
Y.-L. Wu is with the Department of Computer Science and Engineering,The Chinese University of Hong Kong, Shattin, Hong Kong (e-mail:[email protected]).
W.-B. Jone is with the Electrical and Computer Engineering and ComputerScience Department, University of Cincinnati, Cincinnati, OH 45221 USA(e-mail: [email protected]).
Digital Object Identifier 10.1109/TIM.2005.855094
1Available: http://public.itrs.net
BIST has been proposed by researchers [3]–[5], and the majorapplication is for in-field testing. Its basic concept is simple: atesting stimulus (e.g., electrostatic force) is applied to activatethe device to its full working range, and failure to demonstrate afull-range output within some tolerance level means the deviceis faulty. Sensitivity testing is an easy way to check whether thedevice is free to move according to the design expectation. How-ever, it requires the electrostatic force (or other test stimuli) tobe calibrated before it can be applied. Also, it is not effectivein identifying some hard-to-detect defects, such as the capaci-tance asymmetry caused by local defects. In order to solve theseproblems, Symmetry BIST suitable for CMOS MEMS deviceshas also been proposed [6]. The basic idea of symmetry BISTis to partition the central mass (movable capacitance plate) intotwo separate portions connected by an insulated layer. By com-paring the test responses between symmetric parts of the device,the symmetry test approach can detect any left–right asymmetrycaused by local defects. The symmetry BIST method aims atlocal defects which alter the device symmetry, and no test stim-ulus calibration is needed. It can be used in manufacturing test aswell as in-field test. Since most capacitive MEMS devices havesome extent of structure symmetry, this method can be appliedto many different kinds of capacitive MEMS devices. Comparedto sensitivity test, it has the advantage that no test stimulus cal-ibration is needed. It aims at local hard-to-detect defects whichalter the symmetry of the device. However, for global defectswhich change both sides of the device in the same amount, thesymmetry test approach cannot be used. Since each of sensi-tivity test and symmetry test has its own defect coverage, bycombining them together, a more robust test for MEMS devicescan be expected.
In this paper, a BIST technique which partitions the fixed (in-stead of the movable) capacitance plates is introduced. Due tothis partitioning, the movable capacitance plate is not divided,so the BIST scheme is not limited to CMOS MEMS devices,and it can be easily extended to bulk micromachined MEMS de-vices and other technologies. Another major contribution of thiswork is that both sensitivity and symmetry BIST modes basedon this partitioning are also implemented. Since each of sensi-tivity and symmetry BIST methods has its own defect coverage,by combining them together, a more robust test can be expected.The proposed BIST technique has been verified using three typ-ical capacitive MEMS devices: surface-micromachined combaccelerometer, bulk-micromachined capacitive accelerometer,and surface-micromachined comb resonator. The criterion forselecting these three devices as examples is to ensure the diver-sity of technologies for demonstrating the versatility of the BIST
1740 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 5, OCTOBER 2005
TABLE IDIVERSITY OF THE THREE MEMS DEVICE EXAMPLES
technique, as shown in Table I. Results obtained by ANSYS2
fault simulation show the effectiveness of the BIST technique.Section II first gives the basic working principle of capaci-
tive MEMS devices, and the basic idea of sensitivity test. Theproposed symmetry BIST scheme by virtually partitioning thefixed plates is then described in detail. Finally, the dual-modeBIST technique is presented. Section III explains how to applythe dual-mode BIST method to three different MEMS tech-nologies. Simulation results are provided in Section IV to showthat each of the dual BIST modes has its own defect coverage,and this proves the effectiveness and the requirement of usingthe dual-mode BIST scheme. Section V discusses the relation-ship between driving capacitance, sensing capacitance as wellas the effect of fringing capacitance due to the partitioning offixed plates. The relationship between BIST and built-in self re-pair (BISR) is also discussed. Finally, Section VI concludes thispaper.
II. BASIC CONCEPTS OF THE PROPOSED BIST TECHNIQUE
In order to make the following discussion clearer, we definesome biasing voltages first.
• : the modulation voltage in positive (negative)phase (high frequency, e.g., 1 MHz).
• : the test driving voltage (usually dc) applied to thefixed driving plates to activate the device in the BISTmodes.
• : the nominal voltage on the movable plate, usuallythe time average value of modulation voltage .
• , : the complementary driving voltages applied tothe fixed driving plates to activate an actuator in normalmode.
A. Basic Knowledge for Capacitive MEMS Devices
A typical MEMS differential capacitance structure is shownin Fig. 1 where M represents the movable plate, F1 and F2 de-note fixed plates, while B1 and B2 are both beams of the MEMSdevice. As shown in Fig. 1, the movable plate M is anchoredto the substrate through two flexible beams B1 and B2. It con-stitutes differential capacitances and with the top andbottom fixed plates (F1 and F2). In the static mode, the mov-able plate M is located in the center between F1 and F2, thus
2Available: http://www.ansys.com
Fig. 1. Schematic diagram of a capacitive MEMS devices.
where is the dielectric constant of air, is the overlap area be-tween M and F1/F2, and represents the static capacitance gapbetween M and F1/F2. A vertical stimulus (such as accelerationetc.) will result in the deflection of beams and a certain displace-ment of movable plate M along the vertical direction. Assumethe central movable mass moves upward with a displacement of
. Given , and under the test stimulus can be de-rived by
In order to sense the displacement of the movable plateM, modulation voltage and are applied to F1 and F2separately
where represents the modulation voltage amplitude, de-notes the frequency of the modulation voltage, and gives thetime for operation. According to the charge conservation law,the charge in capacitances and must be equal, so we have
where is the voltage level sensed by the movable plate M.Solving the above equations, we have
It can be observed from this result that under the above modu-lation voltage biasing, the central movable plate M acts just asa voltage divider between the top and bottom fixed plates F1and F2, respectively. By measuring the voltage level on centralmovable electrode , we can find the displacement of thecentral movable plate M, which in turn is directly proportionalto the physical stimulus. Thus, we can derive the value of the ap-plied physical stimulus. This is the working principle for mostdifferential capacitive MEMS devices.
In the sensitivity BIST mode, a certain amount of drivingvoltage can be applied to the driving plate to mimic the actionof a physical stimulus with electrostatic force. In the above ex-ample, if voltage is applied to the fixed plate F1 and nominalvoltage is applied to M, an electrostatic attractive forcewill be experienced by the central movable mass
XIONG et al.: DUAL-MODE BUILT-IN SELF-TEST TECHNIQUE FOR CAPACITIVE MEMS DEVICES 1741
Fig. 2. MEMS capacitance structure for our symmetry test scheme.
The electrostatic force is used to mimic the input stimulusduring the BIST mode, and the device response to the electro-static force is measured and compared with the good deviceresponse to check whether the device is faulty. This is the basicidea for the sensitivity test mode of a capacitive MEMS device.For vertical electrostatic driving, the driving voltage cannotexceed a threshold value by which the deflection exceeds 1/3of the capacitance gap . Otherwise, the movable plate willbe stuck to the fixed plate through a positive feedback, and ashort-circuit will occur.
B. Symmetry BIST Scheme
Now, we introduce our symmetry test scheme. A simplifiedMEMS capacitance structure is given in Fig. 2 where S1–S4 arefixed plates. As shown, each of the top and bottom fixed ca-pacitance plates is divided into two equal portions. For simplifi-cation, here we omit the capacitance for electrostatic actuationwhich is necessary for BIST implementations. The basic ideaof our symmetry test scheme is to check whether the two sym-metric capacitances (e.g., and in Fig. 2) on the same sideof the movable microstructure remain equal all the time, afteractivation.
In Fig. 2, fixed plates S1 and S2 lie at the same side of themovable plate M. The capacitance between M and S1 (S2) isdefined as . The modulation voltages and areapplied to S1 and S2 separately. If the device is fault-free, re-gardless whether the movable plate is at rest or moving a cer-tain displacement along the vertical direction, the values ofand should always remain equal. Take the voltage level oncentral movable plate M as , according to the charge conser-vation law, charge and in capacitances and mustremain equal
Since , from the above equation we have
If equals , we have: . Under the above voltagebiasing scheme, the voltage level on the central movable plateis always zero for good devices. However, if there is any localdefect which alters the symmetry of the device, the movableplate will tilt, and will not be equal to . In this way, theoutput voltage will not be zero anymore. Thus, by checking
Fig. 3. Fixed capacitance plates partition for MEMS device.
the voltage output on the movable plate, we can find any de-fect which alters the symmetry of the device. Furthermore, ac-cording to the phase polarity of , we can know whether thedefect lies at the left or right side of the device. For example, ifa stiction defect in the right side (which introduces in Fig. 2)of the mass causes to be smaller than , will have hesame phase polarity as and vice versa.
The above analysis is for checking both capacitances in thetop side of the device. However, the verification for both bottomcapacitances ( and ) can be easily performed in a similarway, and they should have the same result.
C. Dual-Mode BIST Technique
As discussed above, our BIST technique for capacitiveMEMS devices is to divide the fixed capacitance plate(s) ateach side of the movable microstructure into three portions:one for electrostatic activation and the other two equal portionsfor capacitance sensing, as shown in Fig. 3. Note that M is themovable plate, D1 and D2 are the fixed driving plates, while{S1, S2, S3, S4} are the fixed sensing plates. As shown inFig. 3, after capacitance partitioning, two BIST modes (sensi-tivity test and symmetry test) can be easily implemented on thedevice. During normal operation, we have Test Enable signalTE . If the device is a sensor, the modulation voltageis applied to {S1, D1, S2}, and the complementary modulationvoltage is applied to {S3, D2, S4} [Fig. 4(a)]. The voltageon central mass M is sensed as the output voltage indi-cating the device sensitivity. If the device is an actuator (e.g.,microresonator), the driving voltage is applied to {S1, D1,S2}, and the complementary driving voltage is applied to{S3, D2, S4} separately to implement the electrostatic actu-ation in normal operation. In a word, the driving capacitanceplates (D1 and D2) for BIST will also participate the normaloperation, so there is no loss of capacitance area due to theBIST implementation.
In the BIST mode TE 1 , the Test Selection (TS) signalcan select one of the two BIST modes. When TS 0, the deviceis in the sensitivity test mode. Test driving voltage is appliedto D1 to activate the device, modulation voltage is appliedto {S1, S2}, and is applied to {S3, S4} [Fig. 4(b)]. Thevoltage level on the movable electrode (i.e., plate) M is mea-sured for the device sensitivity analysis. Voltage is com-pared with the expected value (calibrated) within a tolerancelevel to find whether the device is faulty.
When TS 1, the device is in the symmetry test mode, andthe proposed new symmetry test scheme is used here. In this
1742 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 5, OCTOBER 2005
Fig. 4. Voltage biasing schemes for the three modes of MEMS device. (a) Normal operation. (b) Sensitivity BIST mode. (c) Symmetry BIST mode.
case, test driving voltage is applied to D1 to activate the de-vice. The modulation voltage is applied to S1, and isapplied to S2 separately [Fig. 4(c)]. The voltage level of themovable electrode is measured to see whether it is a constantzero. If there is a nonzero voltage output on movable electrodeM, it indicates there is a local defect which causes the asym-metry of the device. Based upon the value and polarity of ,we can also have an idea about the approximate location of thelocal defect. The above analysis (and the following examplesin Section III) is for the case where the movable electrode isdriven upward ( is applied to D1). However, for the case inwhich the movable electrode is driven downward ( is appliedto D2), the implementation can be easily extended. Note that inthe BIST mode, the device should be driven in both directionsfor a thorough test. Since both the sensitivity test and symmetrytest has its own defect coverage, by combining them together, amore robust testing result can be ensured.
The defect on driving electrodes D1 and D2 can also be de-tected, if it causes sensitivity change or left–right asymmetry tothe MEMS device. For example, if the left part of D1 is missingdue to improper photoetching, the mass will experience a largerelectrostatic force in its right part than its left part in BIST.Hence, the movable mass M will tilt and a symmetry test candetect the defect.
To implement the BIST technique, a control circuit is neededto switch the device among normal operation mode and bothBIST modes. Such a control circuit is not complex and onlycontains some switches made of analog Muxes. Taking the pro-posed BIST method for capacitive microsensors as an example,the control circuit design is shown in Fig. 5.
In this circuit, totally, only six Muxes are needed: three 3-to-1Muxes and three 2-to-1 Muxes. The differential capacitancedetection circuit for BIST modes can be shared with that ofthe normal operation mode. Thus, the circuit overhead for theBIST technique implementation is small. In the following,we will apply our BIST technique to three typical capacitiveMEMS devices: surface-micromachined comb accelerometer,bulk-micromachined accelerometer, and poly-Si microres-onator. Through these examples, we can see how our BISTtechnique can be applied to various capacitive MEMS devices.
Fig. 5. Control circuit for dual BIST technique.
III. DUAL-MODE BIST FOR DIFFERENT TECHNOLOGIES
A. Surface-Micromachined Comb Accelerometer
Surface-micromachined comb accelerometers have beenpopular examples for MEMS testing in many papers, becausethe surface micromachining technology is compatible withthe well-developed CMOS VLSI fabrication technology. Atypical comb accelerometer structure [6] is shown in Fig. 6. Thedevice prototype comes from the ADXL series accelerometersdeveloped by Analog Devices Inc. [7], [8]. In Fig. 6, M1–M8are movable fingers, Ms is the central mass, D1–D8 are drivingfingers, and S1–S8 are sensing fingers. All beams are connectedto the substrate through four anchors. For simplicity, only fourgroups of driving/sensing fingers are given here. The fixed por-tion of the device includes driving fingers D1–D8 and sensingfingers S1–S8. Differential capacitances are constructed be-tween the movable fingers and the sensing fingers. If the deviceexperiences an acceleration in the vertical direction which isperpendicular to the beam, the central mass will experience aninertial force which will deflect the beam connected to the
XIONG et al.: DUAL-MODE BUILT-IN SELF-TEST TECHNIQUE FOR CAPACITIVE MEMS DEVICES 1743
Fig. 6. Structural diagram of a comb accelerometer.
central mass. Thus, the movable fingers will also experience thesame amount of displacement. This will change the differentialcapacitance, which can be detected by the interface circuit sothat we know the value of the acceleration . Since the fixedcapacitance electrodes are separate fingers, partitioning for thedual-mode BIST technique can be easily realized.
During normal operation, TE 0, modulation voltageis applied to {S1, S3, S5, S7, D1, D3, D5, D7}, and is ap-plied to {S2, S4, S6, S8, D2, D4, D6, D8}. The voltage level
in the movable fingers is measured as the output voltageto determine the acceleration. When TE 1 and TS 0, thedevice works in the sensitivity test mode. A certain test drivingvoltage is applied to {D1, D3, D5, D7} to activate the devicewith electrostatic force. The modulation voltage is appliedto {S1, S3, S5, S7}, while is applied to {S2, S4, S6, S8}.The output voltage on movable mass Ms is measured for the de-vice sensitivity. This value is compared with the expected gooddevice value within a certain tolerance level to find whether thedevice is faulty. When TE 1 and TS 1, the device is in thesymmetry test mode. Test driving voltage is applied to {D1,D3, D5, D7}, modulation voltage is applied to {S1, S5},while is applied to {S3, S7}. The sensing circuit checkswhether the output voltage on movable fingers is a constant zeroto detect any asymmetry caused by local defects. If there is anonzero voltage on the movable electrode Ms, then it indicatesthere are local defects which alter the symmetry of the device.Defects on driving electrodes can also be detected if they causesensitivity change or left-right asymmetry to the MEMS device.For example, if part of D1 in Fig. 6 is missing, the movablemass will experience a smaller electrostatic force in its left partthan its right part during BIST. Hence, the movable mass Mswill tilt, and symmetry test can detect this defect. The voltagebiasing scheme for the comb accelerometer in the normal andboth BIST modes is shown in Table II using a notation similarto [6].
B. Bulk-Micromachined Capacitive Accelerometer
The structure of a silicon symmetric bulk-micromachinedcapacitive accelerometer [9], [10] is shown in Fig. 7. The top
TABLE IIVOLTAGE BIASING SCHEME FOR COMB ACCELEROMETER
and bottom glass covers are bonded to the central Si microstruc-ture through the silicon–glass anodic bonding technique, so thewhole device is in the glass–silicon–glass sandwich structure.The movable Si mass is connected to the frame through fourbeams. On the top and bottom sides of the central mass, Alsquare electrodes are deposited on the corresponding glasssurfaces, such that differential capacitance can be constructed.When there is acceleration along the vertical direction perpen-dicular to the device plane, the mass will experience an inertialforce, and the beams will bend along the vertical direction.The capacitance gap between the central mass and the Alelectrodes will change. Thus, by measuring the differentialcapacitance change with a sensing circuit, we get the value ofthe experienced acceleration.
For the BIST implementation, we revise the design by par-titioning each of the top and bottom Al electrodes into threeportions: the central portion for electrostatic activation and theleft/right portions for sensing. The partitioning must ensureequal size for the left and right portions of each Al electrode.As shown in Fig. 8, the top (bottom) Al electrode is partitionedto sensing electrodes {S1, S2} ({S3, S4}) and driving electrodeD1 (D2).
During normal operation TE 0 , the modulation voltageis applied to all top Al electrodes {S1, D1, S2}, and
is applied to all bottom Al electrodes {S3, D2, S4}. The drivingelectrodes {D1, D2} also participate the normal operation ofthe device, and there is no capacitance area loss due to the BISTimplementation. By measuring the voltage output on the central
1744 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 5, OCTOBER 2005
mass, we obtain the acceleration value. When TE 1, the de-vice enters either one of both BIST modes. When TS equals 0,the device is in the sensitivity test mode, and a certain amountof test driving voltage is applied between D1 and centralmass M to activate the device with electrostatic force. Modu-lation voltage is applied to {S1, S2}, and is appliedto {S3, S4}. The voltage level in the central mass M indicatesthe device sensitivity. This value is compared with the expectedgood device value within some tolerance level to check whetherthe device is faulty.
When TS 1, the device is in the symmetry test mode, andthe test driving voltage is applied to D1 to activate the de-vice. The modulation voltage is applied to S1 and isapplied to S2. If the device is defect-free, based upon the sym-metry of the device structure, the capacitance between M and S1will always equal to the capacitance between M and S2. Thus,the output voltage on the central mass will be a constant zero.If there is any local defect which alters the symmetry of the de-vice, the displacement of the central mass in the left side maynot be equal to that in the right side. Thus, the capacitance be-tween M and S1 will not be equal to the capacitance betweenM and S2 anymore. This will lead to a nonzero output voltageat the central movable mass. By checking whether the outputvoltage on central mass M is a constant zero, such local defectscan be detected. The voltage biasing scheme of the bulk-micro-machined capacitive accelerometer in normal operation and twoBIST modes are given in Table III.
C. Poly-Si Surface-Micromachined Microresonator
Poly-Si comb microresonator has broad applications in sen-sors, filters, and oscillators [11], [12]. A typical microresonatorstructure is shown in Fig. 9(a) [13]. As an actuator, the normaloperation of a microresonator is to activate the device into oscil-lation. Several driving schemes are available, among them, the
TABLE IIIVOLTAGE BIASING FOR BULK-MICROMACHINED ACCELEROMETER
most popular one is the push–pull driving. In normal operation,driving voltages and are applied to the top and bottomfixed fingers, and nominal voltage is applied to the cen-tral movable fingers. The driving voltages and are highfrequency ac voltages with dc biasing. Assume the following bi-asing for and
where is the dc biasing for driving voltages, is the voltageamplitude for ac component of driving voltages, is the roundfrequency, and is the time for operation.
Such a voltage biasing scheme induces a side-driving elec-trostatic force on the movable fingers. The electrostatic forceson the central movable fingers generated by the top and bottomfixed fingers are defined as F1 and F2 separately. We have
where is the thickness of the device, is the capacitance gapbetween movable and fixed fingers, and is the dielectric con-
XIONG et al.: DUAL-MODE BUILT-IN SELF-TEST TECHNIQUE FOR CAPACITIVE MEMS DEVICES 1745
Fig. 9. Structure diagram of a comb microresonator. (a) Microresonator. (b) Revised design.
stant of air. Thus, the total electrostatic force experiencedby the central movable mass is
From this result, we find that the central mass will experiencean alternative electrostatic driving force (with frequency ) andoscillate around its equilibrium location.
For the BIST implementation, we revise the device design bypartitioning the top (bottom) fixed fingers into three portions:the central portion D1 (D2) for driving, and the left–right por-tions {S1, S2} ({S3, S4}) for sensing, as shown in Fig. 9(b).
During normal operation, TE 0, the normal driving voltageis applied to the top fixed fingers {S1, D1, S2}, and is
applied to all the bottom fixed driving fingers {S3, D2, S4}. Thecentral movable mass will be driven by the electrostatic forcein a push–pull mode. The sensing electrodes {S1, S2, S3, S4}also participate the normal operation of the device, so there isno capacitance area loss due to the BIST implementation. WhenTE 1 and TS 0, the device is in the sensitivity test mode,and test driving voltage is applied between D1 and centralmass M to activate the device with electrostatic force. Modula-tion voltage is applied to {S1, S2} and is applied to{S3, S4}. The voltage level in the central mass M indicates thedevice sensitivity to the given test driving voltage. This valueis compared with the expected good device value within a cer-tain tolerance level to check whether the device is faulty. WhenTE 1 and TS 1, the device is in the symmetry test mode,and the test driving voltage is applied to D1 to activate the de-vice. The modulation voltage is applied to S1, and isapplied to S2. By checking whether the voltage output on thecentral movable plate is a constant zero, we can know whetherthere are local defects. The voltage biasing scheme of the mi-croresonator in normal operation and two BIST modes is listedin Table IV.
IV. SIMULATION RESULTS
In order to verify the effectiveness of our BIST technique,ANSYS (v6.1) was used for the fault simulation of the above
TABLE IVVOLTAGE BIASING SCHEME FOR MICRORESONATOR
three devices. We simulated three categories of MEMS defects:stiction, finger height mismatch, and etch variation [6]. Stictionis a very popular defect type in surface micromachined MEMSdevices, and can be caused by molecular force, particle in pho-tolithography, or etching, and many other possible reasons. Fora stiction defect, the movable microstructure is stuck to the sub-strate or the fixed microstructure at certain locations, and itsmovement is hindered. A height mismatch defect is one that thefloating microstructure bends upward or downward due to its in-ternal residual stress, and thus the overlap capacitance betweenthe movable and fixed electrodes will be changed. An etch vari-ation defect is one that the thickness of the device structure doesnot meet the design expectation (under-etch or over-etch) due tothe etch variations caused by fluctuation of temperature, etchantconcentration, and other reasons. In the following experiments,the amplitude of biasing voltage is 5 V, the noise floor is as-sumed to be 1 mV, and the output voltage should be larger than1 mV in order to be detected. Any voltage output below 1 mVis treated as 0.
A. Surface-Micromachined Comb Accelerometer
A stiction defect [6] at different locations of the right centralmovable finger is simulated. The location of the stiction defect isexpressed in percentage of the total finger length. The 0% pointis defined as the finger tip location, and the 100% point is de-fined as the finger root location connected to the central mass.The simulation results are shown in Table V. A finger heightmismatch defect [6] is also simulated for the comb accelerom-eter. Without the loss of generality, we assume the left side of
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TABLE VSTICTION DEFECT SIMULATION RESULTS FOR COMB ACCELEROMETER
TABLE VIFINGER HEIGHT MISMATCH SIMULATION OF COMB ACCELEROMETER
the device is fault-free, and a finger height mismatch only oc-curs on the right side of the device. The device is simulated fora finger height mismatch with changes from 0.1 to 0.4 m, andthe results are shown in Table VI.
From the simulation results, we can see that for the stictiondefect on the movable finger, sensitivity test can detect the de-fect very effectively. When there is a stiction defect on the mov-able finger, the sensitivity drops dramatically from 967.6 mV(faulty-free value) to 107.8 mV and below. Hence, by com-paring the sensitivity BIST output with the good device value,the stiction fault can be easily detected. When the stiction de-fect moves from the movable finger tip to the root, the devicedisplacement is increasingly hindered, and thus the device sen-sitivity output further reduces. While there is a nonzero voltagefor the symmetry BIST output indicating the existence of a stic-tion defect, its change is not as apparent as the sensitivity BISToutput. Thus, sensitivity test performs better than symmetry testin detecting stiction defects at movable fingers. However, thesimulation results also show that symmetry BIST exceeds sen-sitivity BIST in detecting finger height mismatch defects. For afinger height mismatch of 0.4 m, the sensitivity output dropsonly 6% when compared with the good device response, but thesymmetry BIST output changes from 0 to 181.3 mV.
B. Bulk-Micromachined Accelerometer
Both stiction and etch variation defects [6] are simulated fora bulk-micromachined accelerometer. For a stiction defect, it isassumed to be present on the surface of the central mass, whichis very vulnerable to stiction defect due to the small capacitancegap there. The stiction defect location is expressed as the per-centage of the half mass width. Here, the 0% point is at the rightedge of the mass, while the 100% point is at the center point ofthe mass. The simulation results are shown in Table VII. Etchvariance defects are very popular for bulk-micromachined de-vices due to the etching speed fluctuation caused by temperatureand etchant concentration changes. Without the loss of gener-ality, we assume an under-etch variation defect and it is only forthe right portion of the central mass (the left portion of the mass
TABLE VIISTICTION SIMULATION RESULTS FOR BULK ACCELEROMETER
TABLE VIIIETCH VARIATION SIMULATION RESULTS FOR BULK ACCELEROMETER
is fault-free). Assume the central mass thickness of the good de-vice as 320 m. The etching variance defect with changes from0 to 1 m in step of 0.25 m is simulated, and the results areshown in Table VIII.
From the simulation results, we can see that for a stiction de-fect on the mass, it will seriously hinder the mass displacementdue to the large rigidity of the mass. Thus, the mass can hardlyhave any displacement, and the sensitivity drops to zero. Thesensitivity BIST technique is very effective in detecting such adefect, because the sensitivity BIST output will drop from 20.9mV (good device response) to zero if there is any stiction on thecentral mass. However, since the mass almost stays at its staticposition, each of both top/bottom sensing capacitances will keepits static value. Thus, the symmetry BIST output remains zeroall the time, which indicates it is not able to detect such a stic-tion defect for the device. However, for an etch variation defect,the sensitivity output will change only about 3% (from 20.9 to21.6 mV) for an etch variation of 1.0 m. But, the symmetryBIST output will change from 0 to 149.6 mV, demonstrating itseffectiveness in detecting the etch variation defect.
C. Poly-Si Surface-Micromachined Resonator
Both stiction and finger height mismatch defects [6] are simu-lated for a microresonator. For a stiction defect, it is assumed tooccur at the top movable finger of the resonator, and its locationis expressed by the finger number counted from the right edge.There are totally 36 movable fingers in the top side of the device,and the stiction can occur at one of fingers 1 to 5. The simulationresults are shown in Table IX. For a finger height mismatch, weassume the fingers at the left-side (right-side) of the axis inFig. 9(b) are fault-free (faulty). A finger height mismatch defectwith values from 0 to 0.4 m in step of 0.1 m is simulated andthe results are shown in Table X.
From the simulation results, we can see that if there is anystiction at a movable sensing finger, it will greatly hinder themovement of the movable fingers and the sensitivity outputdrops to zero. Thus, sensitivity test is very effective in detectingsuch kind of defects. However, for symmetry BIST, since thedevice remains in its static location after activation, both the
XIONG et al.: DUAL-MODE BUILT-IN SELF-TEST TECHNIQUE FOR CAPACITIVE MEMS DEVICES 1747
TABLE IXSTICTION DEFECT SIMULATION RESULTS FOR MICRORESONATOR
TABLE XFINGER HEIGHT MISMATCH SIMULATION OF MICRORESONATOR
left and right sensing capacitance pairs will remain equal, andthe symmetry BIST output will be always zero for both goodand faulty devices. Thus, the symmetry BIST method is noteffective in detecting stiction defects on the movable fingersof a microresonator. However, for a finger height mismatchdefect, the symmetry BIST method is very effective. Thesymmetry BIST output changes from 0 (for fault-free device)to 181.4 mV (height mismatch of 0.4 m), while the sensitivityoutput only changes about 3% (from 66.5 to 64.1 mV). Thus,symmetry BIST exceeds sensitivity BIST in detecting fingerheight mismatch defect of the microresonator.
D. Testing of Defects in Fixed Capacitance Plates
The above discussion has demonstrated the effectivenessof the dual-mode BIST technique for defects in movablemicrostructures. However, the fixed capacitance plates of acapacitive MEMS device may also contain some defects. De-pending on their locations and extents, such defects may befatal and lead to device failure. Thus, an effective BIST solutionmust also be able to detect all defects in the fixed capacitanceplates. In this subsection, the dual-mode BIST technique willbe applied to deal with typical defects in the fixed capacitanceplates of a MEMS device. The simulation results prove theeffectiveness of the dual-mode BIST method for these defectswhich lead to either device symmetry or sensitivity change.Since the resonant frequency of a MEMS device is fully de-termined by its movable microstructure, defects in the fixedcapacitance plates do not change the device resonant frequencyat all. Thus, no frequency test method is able to detect suchdefects.
1) Broken-Via Defect of Comb Accelerometer: In a CMOSMEMS comb accelerometer, the fixed driving (sensing) fingersare connected together into a group by interconnects throughvias. The interconnects are in turn connected to the corre-sponding driving voltage or the capacitance sensing circuit.If the via between a fixed finger and its corresponding inter-connect is broken, as a result, the fixed finger is electronicallyseparated from the driving voltage or the capacitance sensingcircuit. That is, the fixed finger is electronically missing. Thisis a broken-via defect of the comb accelerometer. Multiple
TABLE XIBROKEN-VIA DEFECT SIMULATION RESULTS OF COMB ACCELEROMETER
TABLE XIIGAP VARIATION DEFECT SIMULATION RESULTS OF BULK ACCELEROMETER
broken-via defects can occur simultaneously. For simplifi-cation, single and double broken-via defects in driving andsensing fingers are simulated, separately. The simulated singlebroken-via defect in a driving (sensing) finger is assumed tooccur in the right-most (left-most) driving (sensing) fixed fingerof the top plate. The simulated double broken-via defects occurin the right-most (left-most) driving (sensing) fixed fingers ofboth top and bottom plates. The ANSYS simulation results areshown in Table XI.
From the table, it can be concluded that each broken-via de-fect can be effectively detected by sensitivity BIST, since a sig-nificant difference in sensitivity between the defect-free and de-fective devices is observed. However, symmetry BIST can de-tect broken-via defects only when they occur in the sensing fin-gers asymmetrically. The asymmetric distribution of broken-viadefects on driving fingers does not lead to any asymmetric re-sponse due to the twist-resistance effect of the device structure.However, if broken-via defects occur in the fixed sensing fingersasymmetrically, both sensitivity BIST and symmetry BIST candetect them effectively.
2) Gap Variation Defect of Bulk-Accelerometer: For aglass–silicon–glass sandwich bulk-accelerometer, due to varia-tions of the silicon-glass anodic bonding process, the Al fixedcapacitance plates may be farther or closer to the movableplate than the expected value. This is called a gap variationdefect. Without the loss of generality, the gap variation defectis assumed to occur uniformly only to the top fixed capacitanceplates. The bottom fixed capacitance plates are assumed to bedefect-free. If the gap variation is small, the device can stillexhibit a linear response to the acceleration in its sensitive di-rection. However, the zero-point of the device will shift. Thus,the device needs to be adjusted by a zero-calibration process.The ANSYS simulation result for each different amount ofgap variation is listed in Table XII. The capacitance gap of thedefect-free device is assumed 15 m.
The simulation results show that each gap variation defectcan be effectively detected by sensitivity BIST, since there isa significant sensitivity difference between the defect-free anddefective devices. However, because the gap variation occurs
1748 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 5, OCTOBER 2005
TABLE XIIISIDE-ETCH VARIANCE DEFECT SIMULATION RESULTS FOR MICRORESONATOR
uniformly to the top plates, the symmetry BIST method cannotdetect it.
3) Side-Etch Variation of Microresonator: Due to the un-avoidable side-etch effect in a dry/wet etching process, the side-wall of a fixed capacitance plate may shrink by a certain amountof value. This, in turn, will lead to the increase of the corre-sponding capacitance gaps. This is called a side-etch variationdefect. Without the loss of generality, we assume that the side-etch variation defect occurs only in the left portion of a microres-onator, and the right portion is defect-free. That is, all fixed fin-gers of the left part of the microresonator have thinner sidewalls.In this way, the capacitance gap of each pair of fixed and movingfingers (in the left part of the microresonator) is increased. TheANSYS simulation result for each different side-etch variationdefect in the fixed fingers of the left portion of a microresonatoris shown in Table XIII.
According to the simulation results, the symmetry BISToutput voltage changes from 0 V (for defect-free device) to41.0 137.3 mV (for defective devices). In fact, the sym-metry BIST output voltage increases with the amount of theside-etch variance. Thus, symmetry BIST is effective to detectside-etch variance defects of the microresonator. However,the sensitivity BIST output voltage only changes from 105.4mV (for defect-free device) to 97.6 mV (for defective devices)which is not significant enough. This indicates that sensitivityBIST is not effective for side-etch variance defects of themicroresonator.
The above simulation results show that all the defects dis-cussed in fixed capacitance plates can also be detected by thedual-mode BIST method, either by sensitivity BIST or sym-metry BIST or both.
V. DISCUSSIONS
A. Capacitance and Sensitivity
For capacitance partitioning, the driving capacitance platecan be smaller than the sensing capacitance plate for bettersensing. However, reduced driving capacitance plate areameans a higher test driving voltage is required. Thus, there isa tradeoff between driving plate area and sensing plate area,and a suitable partitioning size must be decided for individualMEMS device. The overhead of the control circuit consistsonly of a group of switches. Since the driving capacitance canalso participate the normal operation, essentially there is noarea loss. If there is any, it is the gap among the capacitanceplate partitions which is very small.
Fringe capacitance will be introduced due to the partitioningof fixed capacitance plates. Our ANSYS simulations take fringe
capacitances into account, and the results show that the BISTscheme works properly for the MEMS devices. This indicatesthat the fringe capacitance effect is small and does not cause anyproblem to the BIST scheme.
B. Calibration and Sensitivity BIST
The calibration process provides a specific stimulus with aknown result to create a direct mapping between sensor out-puts and expected values. In this way, the graduations of thesensor are determined. Since a special apparatus is needed togenerate the stimulus of a real measurand, calibration is gen-erally performed by manufacturers before devices are released.Calibration is not convenient during in-field applications. Sen-sitivity BIST uses some easily attained stimuli (such as electro-static force, etc.) to mimic the action of the measurand input, soit is suitable for in-field test. MEMS devices must be calibratedafter fabrication, and those with “tolerable” defects will be cal-ibrated and released as good devices. However, during in-fieldusage, some unstable defects in a device may change the situ-ation and cause the device to deviate from its calibrated value.Such a change of unstable defects may not cause any left-rightasymmetry, and hence symmetry test cannot detect these de-fects. But, they may change the sensitivity of the device, so that asensitivity BIST can detect them. Furthermore, MEMS devicesmay still develop new defects during in-field usage, e.g., brokenbeams, material fatigue, etc. Thus, an in-field sensitivity BIST isstill very necessary, even though MEMS devices are calibratedbefore releasing.
Take the surface-micromachined comb accelerometer as anexample, if an impermanent elastic particle blocks the movablemass, it may hinder the movement of the mass to a degree, butthe mass is still somewhat flexible. Since the particle only im-pact the central mass, it will not cause left–right asymmetry tothe device and symmetry test cannot detect this defect. The de-vice may be calibrated and released as a good device. However,during in-field usage, the particle may be released due to re-peated movement of the mass. Thus, the mass is free and the de-vice sensitivity becomes larger than the calibrated value. Sym-metry test cannot detect this deviation, but an in-field sensitivityBIST can detect it.
For a bulk-micromachined accelerometer, the residual stressmay cause the four beams to curl in the same amount, so thatthe mass will be lifted above the central position of the capaci-tance gap. Symmetry test cannot detect this defect since it doesnot cause any left–right asymmetry. Such a device may be cal-ibrated and released as a good device. During later usage, thestress is gradually released, and the beams become flat; thus, themass moves toward its central position. As a result, the zero po-sition of the device will deviate from its calibrated value. Sym-metry test cannot detect it since it does not lead to left–rightasymmetry. However, sensitivity BIST can detect it, since theelectrostatic force will change due to the change of the drivingcapacitance gap.
For a microresonator, the residual stress may also cause thefolded-beam to curl after fabrication, and the movable fingersare lifted up uniformly for a certain amount. Since it does not
XIONG et al.: DUAL-MODE BUILT-IN SELF-TEST TECHNIQUE FOR CAPACITIVE MEMS DEVICES 1749
cause left–right asymmetry, symmetry test cannot detect this de-fect. It may be calibrated and released as a good device. How-ever, during later usage, the residual stress is gradually releasedand the movable fingers move down toward the device plane.The overlap area between fixed and movable fingers increases,and for the same amount of driving voltage, the resonator willhave larger displacement output than the calibrated value. Sym-metry test cannot detect it since there is no left–right asymmetry.However, an in-field sensitivity BIST is able to detect it. Thus,an in-field sensitivity BIST is still necessary.
C. Built-In Self Repair of MEMS Devices
A thorough BIST solution is the prerequisite for the built-inself-repair (BISR) of MEMS devices. MEMS have found broadapplications in many safety-critical fields, such as automobile,aerospace, etc. MEMS reliability becomes a critical issue inthese areas. Additionally, the low yield (compared to well-de-veloped VLSI fabrications) of MEMS has become a barrier forthe commercialization of MEMS technologies. If MEMS canhave BISR features implemented, both reliability and yield canbe greatly improved. Self-repair techniques through redundancyfor VLSI circuits have been well developed [14], [15]. Similarly,the idea of redundancy for repairing may also be a promisingsolution for MEMS devices. However, in reality, the applica-tion of BISR implemented by redundancy to MEMS devices ismuch more difficult than that to VLSI circuits. The reason isthat, in a VLSI circuit, the replacement of a faulty circuitry by aredundant component can be easily realized by using switchesto prevent the defective one from contributing its signals; whilein a MEMS device, all the parts are mechanically connected asa whole, which makes it very difficult to physically separate afaulty portion from the main device. For example, it is impos-sible to use a good moving finger to replace a defective one bymultiplexer switching.
A novel built-in self-repair solution for comb MEMS ac-celerometers through redundancy has been developed by theauthors recently. In the BISR scheme, the comb accelerometeris divided into number of identical modules, and numberof redundant modules are available for self-repair. Before theBISR process can be performed, the control circuit of a MEMSdevice needs to know whether each module is good or faulty.Thus, each module must be implemented with a BIST function,and the BIST results will be reported to the control circuit. Ifany of the working modules is faulty, it will be replaced witha good redundant module. In this way, the MEMS device canbe self-repaired into a good device given the number of faultymodules is smaller than the number of redundancy. Hence,BIST is a prerequisite for the BISR of a MEMS device, and thiswork has laid a cornerstone for this purpose.
VI. CONCLUSION
In this paper, a dual-mode BIST technique applicable to ca-pacitive MEMS devices is proposed. Based on the fixed-plate(instead of movable-plate) capacitance partitioning, the devices
are guaranteed to work in both the sensitivity test and sym-metry test modes. Due to this capacitance partition scheme,the dual-mode BIST can be extended to bulk and other MEMStechnologies. Three typical capacitive MEMS devices (surface-micromachined comb accelerometer, bulk-micromachined ac-celerometer, as well as microresonator) are used as examplesfor verifying our proposed dual-mode BIST scheme. The ca-pacitance partitioning and the voltage biasing schemes for thesethree MEMS devices are demonstrated. The detections of threedifferent defects (stiction, finger height mismatch, and etch vari-ation) with sensitivity and symmetry BIST modes are simulated.Simulation results show that each of sensitivity and symmetryBIST methods has its own defect coverage. By combining bothBIST methods together, a more robust test can be expected. Acontrol circuit is needed to switch the voltage biasing schemesfor the dual-mode BIST technique. However, the control circuitonly consists of several Muxes, and the area overhead due to thecircuit is small. The dual-mode BIST technique has been provedto be an effective BIST solution for capacitive MEMS devices.
REFERENCES
[1] R. Rosing, A. Richardson, A. Dorey, and A. Peyton, “Test support strate-gies for MEMS,” in Proc. 5th Int. Mixed Signal Test Workshop, Jun.1999, pp. 345–350.
[2] R. Rosing, A. Lechner, A. Richardson, and A. Dorey, “Fault simulationand modeling of microelectromechanical systems,” Comput. Contr. Eng.J., vol. 11, no. 5, pp. 242–250, Oct. 2000.
[3] B. Charlot, S. Mir, F. Parrain, and B. Courtois, “Electrically inducedstimuli for MEMS self-test,” in Proc. 19th IEEE VLSI Test Symp., May2001, pp. 210–215.
[4] M. Aikele, K. Bauer, W. Ficker, F. Neubauer, U. Prechtel, J. Schalk, andH. Seidel, “Resonant accelerometer with self-test,” Sens. Actuators A:Phys., vol. 92, no. 1–3, pp. 161–167, Aug. 2001.
[5] R. Puers and S. Reyntjens, “RASTA—Real-Acceleration-For-Self-TestAccelerometer: a new concept for self-testing accelerometers,” Sens. Ac-tuators A: Phys., vol. 97–98, pp. 359–368, Apr. 2002.
[6] N. Deb and R. D. Blanton, “Built-in self test of CMOS-MEMS ac-celerometers,” in Proc. Int. Test Conf., Oct. 2002, pp. 1075–1084.
[7] W. Kuehnel and S. Sherman, “A surface micromachined silicon ac-celerometer with on-chip detection circuitry,” Sens. Actuators A: Phys.,vol. 45, no. 1, pp. 7–16, Oct. 1994.
[8] W. Kuehnel, “Modeling of the mechanical behavior of a differential ca-pacitor acceleration sensor,” Sens. Actuators A: Phys., vol. 48, no. 2, pp.101–108, May 1995.
[9] Q. Zou, B. Li, X. Xiong, B. Xiong, D. Lu, and W. Wang, “Structuredesign and fabrication of symmetric capacitive force-balance micro-machining silicon accelerometer,” Proc. SPIE, vol. 3223, pp. 284–293,1997.
[10] X. Xiong, Q. Zou, D. Lu, and W. Wang, “Balance approach for mechan-ical properties test of microfabricated structures,” Proc. SPIE, vol. 3223,pp. 294–302, 1997.
[11] R. T. Howe, “Applications of silicon micromachining to resonator fab-rication,” in Proc. 48th IEEE Int. Frequency Control Symp., Jun. 1994,pp. 2–7.
[12] W. C. Tang, T.-C. H. Nguyen, and R. T. Howe, “Laterally drive polysil-icon resonant microstructures,” Sens. Actuators, vol. 20, no. 1–2, pp.25–32, Nov. 1989.
[13] G. K. Fedder, S. Iyer, and T. Mukherjee, “Automated optimal synthesisof microresonators,” in Proc. Int. Conf. Solid State Sensors Actuators,TRANSDUCERS, vol. 2, Jun. 1997, pp. 1109–1112.
[14] H. Kim, D. Yi, J. Park, and C. Cho, “A BISR (built-in self-repair) circuitfor embedded memory with multiple redundancies,” in Proc. 6th Int.Conf. VLSI CAD, Oct. 1999, pp. 602–605.
[15] L. M. Guerra, M. Potkonjak, and J. M. Rabaey, “Behavioral-level syn-thesis of heterogeneous BISR reconfigurable ASIC’s,” IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 6, no. 1, pp. 158–167, Mar. 1998.
1750 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 5, OCTOBER 2005
Xingguo Xiong was born in Hubei, China. Hereceived the B.S. degree in physics from Wuhan Uni-versity, Wuhan, China, in 1994, and the Ph.D degreein electrical engineering from Shanghai Instituteof Microsystem and Information Technology (Theformer Shanghai Institute of Metallurgy), Shanghai,China, in 1999. He is currently pursuing the Ph.D.degree in computer engineering in the Departmentof Electrical and Computer Engineering, Universityof Cincinnati, Cincinnati, OH.
His research interests include microelectrome-chanical system (MEMS), microsensors and microactuators, as well as VLSIdesign and testing.
Yu-Liang (David) Wu received the M.S. degree incomputer science from University of Miami, Miami,FL, in 1984 and the Ph.D. degree in electrical andcomputer engineering from University of California,Santa Barbara, in 1994.
In 1985, he was with Internet Systems Corpora-tion as a System Programmer working on networkcommunication protocols (DARPA TCP/IP, Telnet).From 1986 to 1988, he was with AT&T Bell Labsworking on the development of several telephone op-eration systems. From 1988 to 1989, he was with the
Amdahl Corporation working on tester software designs for super computers.Before he joined the Chinese University of Hong Kong, Shattin, Hong Kong,in January 1996, he had worked at Cadence Design Systems Incorporation as aSenior MTS since December 1994, where he worked in the R&D of the siliconsynthesis product (PBS) targeting at binding the gap between logic and physicallevel optimizations for deep-submicrometer chip designs. His current researchinterests mainly relate to optimization of logic and physical design automationof VLSI circuits and FPGA-related CAD tool designs and architectural anal-ysis/optimization.
Wen-Ben Jone (S’85–M’88–SM’01) was born inTaipei, Taiwan, R.O.C. He received the B.S. degreein computer science in 1979, the M.S. degree incomputer engineering in 1981, both from NationalChiao-Tung University, Hsinchu, Taiwan, and thePh.D. degree in computer engineering and sciencefrom Case Western Reserve University, Cleveland,OH, in 1987.
In 1987, he joined the Department of ComputerScience, New Mexico Institute of Mining and Tech-nology, Socorro, where he was promoted to an As-
sociate Professor in 1992. From 1993 to 2000, he was with the Department ofComputer Engineering and Information Science, National Chung-Cheng Uni-versity, Chiayi, Taiwan. He was a Visiting Research Fellow with the Departmentof Computer Science and Engineering, the Chinese University of Hong Kong,in Summer 1997. Since 2001, he has been with the Department of Electrical andComputer Engineering and Computer Science, University of Cincinnati, Cincin-nati, OH. He was a Visiting Scholar with the Institute of Information Science,Academia Sinica, Taipei, in Summer 2002. His research interests include VLSIdesign for testability, built-in self-testing, memory testing, high-performancecircuit testing, MEMS testing and repairing, and low-power circuit design. Hehas published more than 100 papers and holds one U.S. patent.
Dr. Jone served as a Reviewer in these research areas in various technicaljournals and conferences. He is also listed in the Marquis Who’s Who in theWorld (New Providence, NJ: Marquis Who’s Who, 15th Ed., 1998, 2001).He also served on the program committee of VLSI Design/CAD Symposium(1993–1997, in Taiwan), was the General Chair of the 1998 VLSI Design/CADSymposium, served on the program committee of the 1995, 1996, and 2000Asian Test Conference, the 1995–1998 Asia and South Pacific Design Au-tomation Conference, the 1998 International Conference on Chip Technology,the 2000 International Symposium on Defect and Fault Tolerance in VLSISystems, and the 2002 and 2003 Great Lake Symposium on VLSI. He receivedthe Best Thesis Award from The Chinese Institute of Electrical Engineering(Republic of China) in 1981. He is a corecipient of the 2003 IEEE Donald G.Fink Prize Paper Award. He is a Member of the IEEE Computer Society TestTechnology Technical Committee.
