A Flexible Hybrid Simulation Platform Targeting Multiple Configurable Processors SoC
1
TIMA Laboratory
*Hao Shen Frédéric PétrotSystem Level Synthesis Group, TIMA Laboratory,
CNRS/Grenoble INP/UJF43, Avenue Félix Viallet, 38031, Grenoble, France
Outline
2
TIMA Laboratory
Outline
3
TIMA Laboratory
Configurable Processors
4
TIMA Laboratory
GPP DSP Configurable Processor ASIC
Low HighPerformance/Gate and Power Efficiency
High LowFlexibility and Time-to-Market
AcceleratorConfigurable Processor
MPSoC ArchitectureTIMA Laboratory
5
Communication
DSP RISC
Memory DMA Peripherals
Configurable Processor
Configurable Processor
CPUCPU
Motivation of the Hybrid SimulationTIMA Laboratory
6
HAL API
CPU
MEM DMA
SIMD
?
TA level
EDMA
Outline
7
TIMA Laboratory
What Is Hybrid Simulation Platform?
TIMA Laboratory
8
DCacheInstruction Set SimulatorsInstruction Set Simulators
Hybrid Simulation MPSoC PlatformTIMA Laboratory
9
Applications + OS
HAL APIs
Hardware Abstraction Layer(Target Assembly Codes)
DCacheInstruction Set Simulators
ICache DCache
Memory Periph
Applications + OS
HAL APIs
Hybrid Instruction Set Simulators
ContextSwitch
BootCode
I/OAcces
sLock Interrupt
Handler
Memory Periph
TLM SystemC
Outline
10
TIMA Laboratory
Hybrid Simulation Platform DetailsTIMA Laboratory
11
Hybrid Instruction Set Simulator
HAL APIs RealizationTIMA Laboratory
12
Applications and Operating Systemvoid scheduler_commute(pthread_t self){…HAL_CONTEXT_SWITCH(self->reg, thread->reg);}
HAL APIs Wrapper#define HAL_CONTEXT_SWITCH(store_addr, load_addr) ¥xt_iss_simcall(HOST_HAL_CONTEXT_SWITCH, 0, store, load,0,0)
SystemC HAL APIs RealizationInt host_hal_context_switch(int store_addr, int load_addr){map<string, sc_unsigned> current=core.get_all_registers();saveRegWindow(context_map[store_addr], current);loadRegWindow(context_map[load_addr], current);core.set_all_registers(current);}
1
23
Instruction Set Simulators
ICache DCacheInstruction Set Simulators
ICache DCache
Driver Hybrid SimulationTIMA Laboratory
13
Applications
HAL+DriverReadB(DMA_STATUS …);WriteB(DMA_ADDR …);
Instruction Set Simulators
ICache DCache
Control Registers
Address Registers
Status Registers……
DMA Device with SystemC
0x00
0x08
0x40
Applications
HAL+DriverDMA_Reset();DMA_Copy(from, to…);
DMA_Reset()
DMA_Copy()
DMA_Check_Status()……
DMA Device with TLM
Hybrid Instruction Set Simulators
Outline
14
TIMA Laboratory
Motion-JPEG Decoder Example
15
TIMA Laboratory
Accuracy of Hybrid PlatformTIMA Laboratory
16
Hybrid Platform
Traditional ISS Platform Difference
Extended Instructions Acceleration Ratio 1.71 1.53 10%
DMA Transfer ExampleTIMA Laboratory
17
int ta_dma::dma_ss_copy ( xtsc_core &core,int from, int to, int size)
{// Copy original data to DMA buffer.core.peek_physical(from, size, buff);// Consume time for this copy operationconsume(size/4*time_per_word);// Copy DMA buffer to Target Memory core.poke_physical(to, size, buff);return size;
}
Development EffortTIMA Laboratory
18
Module Name SLOC of the hybrid platform
SLOC of the traditional platform
DMA 79 267context 202 257 (206 lines of asm code)stack 48 14 (6 lines of asm code)
Outline
19
TIMA Laboratory
Conclusion and Future Works
20
TIMA Laboratory