A Heterogeneous SDR MPSoC in 28nmCMOSfor Low-Latency Wireless Applications
Sebastian Haas1, Tobias Seifert1, Benedikt Nöthen1, Stefan Scholze1, Sebastian Höppner1,Andreas Dixius1, Esther Pérez Adeva1, Thomas Augustin1, Friedrich Pauls1, Sadia Moriam1,
Mattis Hasler1, Erik Fischer1, Yong Chen1, Emil Matúš1, Georg Ellguth1,Stephan Hartmann1, Stefan Schiefer1, Love Cederström1, Dennis Walter1,Stephan Henker1, Stefan Hänzsche1, Johannes Uhlig1, Holger Eisenreich2,
Stefan Weitho�er3, Norbert Wehn3, René Schü�ny1, Christian Mayr1, Gerhard Fettweis1
1Technische Universität Dresden 2Racyics GmbH 3Technische Universität KaiserslauternCenter for Advancing Electronics Dresden (cfaed) Dresden, Germany Microelectronic Systems Design
ABSTRACTCurrent and future applications impose high demands on software-de�ned radio (SDR) platforms in terms of latency, reliability, and�exibility. This paper presents a heterogeneous SDR MPSoC witha hexagonal network-on-chip to address these issues. It featuresfour data processing modules and a baseband processing enginefor iterative multiple-input multiple-output (MIMO) receiving. In-tegrated memory controllers enable dynamic data �ow mappingand application isolation. In a 4 × 4 MIMO application scenario, theMPSoC achieves a throughput of 232Mbit/s with a latency of 20 µswhile consuming 414mW. It outperforms state-of-the-art platformsin terms of throughput by a factor of 4.
1 INTRODUCTIONCurrent and future applications in areas like Car2X, augmentedreality, or Internet of Things (IoT) connected via 5G cellular willimpose high demands on processing platforms. The challengesfor terminal devices are twofold: �rstly, systems should deal with�exible and energy-e�cient data processing such as audio/videocoding, web browsing, payment systems, etc. Secondly, they shouldhandle signal processing applications of wireless technologies from2G to 5G, WiFi, and NarrowBand-IoT [15]. Similar requirements arealso present on the infrastructure side. Emerging paradigms likethe Tactile Internet [5] or Mobile Edge Computing [9] will imposestringent latency and reliability constraints as oftentimes requiredby mission-critical applications.
Consequently, a �exible software-centric solution is essentialwhich still provides high throughputs with low energy consump-tion. One key towards this solution is hence the use of multi-ple application-speci�c processors tailored, e.g., by instruction
set extensions since they provide high throughputs while beingenergy-e�cient. However, �exible communication schemes andlow-latency data transfers between the cores are major prerequi-sites to avoid wasting the mentioned energy gain. Furthermore,combining the applications listed above into one single SDR systemdemands fast switching between protocol and physical layer whileisolating their dedicated resources.
Previous work [4, 11, 14] show multi-core SDR architectures withadvanced hardware accelerators for signal processing. They focuson the individual components which aim to tackle the aforemen-tioned requirements but lack proper interaction and data transfercapabilities between the processing elements. This paper proposesa heterogeneous SDR MPSoC for low-latency wireless applicationswhich is capable of interweaving the necessary protocol, signal, andbit processing by fast local switching of computing fabric. This isenabled by (1) heterogeneous data processing modules with single-cycle task switching, (2) a high-throughput baseband processingengine for multi-iterative MIMO receiving, (3) a hexagonal network-on-chip (NoC) topology for improved resiliency and latency, and(4) sophisticated memory controllers with hardware-supported data�ow control, data manipulation (�ltering, reordering), memorypooling, and application isolation.
2 MPSOC ARCHITECTUREOur SDR MPSoC is built upon the Tomahawk concept [2] primarilydesigned for signal processing applications. Tomahawk provides aplatform with multiple heterogeneous processing modules (PMs)or clusters which integrate two or more processing elements (PEs)equipped with local memories for data and instructions. A centralapplication core together with a global memory and peripheralsrepresent the top-level in the system hierarchy. It de�nes the control�ow of the application by using data �ow graphs (DFGs) such asKahn process networks [6] and synchronous DFGs [10]. A centralscheduling unit, called CoreManager, dynamically maps the DFG tothe platform by performing an adaptive runtime scheduling withpower management capabilities and data transfer management.
In particular, the presented SDR MPSoC, called Tomahawk4, com-prises six PMs: four data PMs (DPM), one baseband PM (BBPM),
DAC ’17, June 18-22, 2017, Austin, TX, USA S. Haas et al.
as well as an application control module (ACM), as depicted inFigure 1. All modules have a separate local synchronous clock (all-digital phase-locked loop, ADPLL) and are globally asynchronouslyconnected via NoC (GALS). Besides the local memories (SRAM) ineach PM, an LPDDR2 interface connects 128MB of global mem-ory (SDRAM). The LPDDR2 controller runs at 400MHz and sup-ports a bandwidth of 12.5Gbit/s. The FPGA interface allows to inter-connect multiple chips by using on-chip SerDes links with speeds ofup to 5Gbit/s. The periphery includes register �les to access eightGPIO pins and UART. It further contains an OpenMSP430 controllerfor mathmatical computations as well as application-speci�c hard-ware supporting the advanced encryption standard (AES). Table 1summarizes the MPSoC speci�cations.
The packet-switched hexagonal NoC employs parallel links oper-ating on 80Gbit/s at 500MHz. The high-speed serial link betweenrouters 6 and 7 allows to bridge large on-chip distances. With a66 % higher bisection bandwidth, the hexagonal NoC has improvedtra�c distribution as well as greater fault resilience compared to anXY mesh NoC. The routing logic of the routers uses programmablelook-up tables (LUTs) which allow for adaptation of the routingfunction. This is necessary to re-route the tra�c when the linksmay be blocked, either due to failures or because of link reservationby a PE for accessing memory of neighboring PEs. The hexagonalNoC is especially suited to apply the mentioned re-routing tech-niques since it provides greater path diversity than the XY mesh.The LUTs can be altered by sending con�guration �its over the NoCto the a�ected routers. Moreover, for the purpose of monitoringthe tra�c over the NoC, all links have �it counters which can beread via read-request �its.
2.1 Data Processing ModuleEach DPM contains a customized Tensilica LX5 RISC and a general-purpose ARM Cortex-M4F with 64 kB memories each for data(DMEM) and instructions (IMEM). Both memories are dual-ported,accessible from the NoC side and shared on the core side. Thearchitecture allows to show the interoperability of di�erent code
binaries. In general, Tensilica processors are used for physical layersignal processing tasks while ARM cores are more bene�cial inhigher protocol layers. In future work, we plan to investigate and tocompare the strengths and weaknesses of both. The LX5 is extendedby application-speci�c functional units (FUs) to accelerate selectedbit operations (application-speci�c instruction-set processor, ASIP),as demonstrated by [8]. In this HW/SW codesign approach, the FUsrepresent an additional instruction set extending the processor’shardware and can be accessed by the PE’s software via assemblermacros. For data processing purposes, the FUs support hashingalgorithms of integers and strings, bit and integer count functions,and an integer sorting algorithm. Furthermore to improve SDRfunctionalities, one FU contains an accelerated 128-point FFT op-erating on 32-bit �xed-point complex values. The LX5 has two128-bit data interfaces and two load/store units to provide SIMDcapabilities to fully exploit the data parallelism of the implementedFUs. The IMEM interface exhibits a width of 64 bit for a 3-issueVLIW architecture. The DPMs are connected to three power supplyrails variable in the range of 0.6 − 1.1V. Each power rail is set toa speci�c supply voltage which thus de�nes the maximum clockfrequencies. The integrated power management (PMGT) controllerenables ultra-fast dynamic voltage and frequency scaling (DVFS).Furthermore, each DPM is equipped with an adaptive voltage scal-ing (AVS) controller for voltage adaptations according to the chip’sprocess corner and temperature.
2.1.1 iDMA Controller. Each PM connects to the NoC via aniDMA (intelligent direct memory access) controller, which com-prises the functionality of a conventional DMA controller, plushandling of data �elds by means of: byte-wise data �ltering, datamodi�cation (based on a 3-stage butter�y network with eight 8-bit input values) and data distribution. The iDMA supports eightcon�gurable virtual channels between PEs or between a PE andSDRAM. The channel concept ensures strict isolation of memoryregions of di�erent applications. Memory mapped FIFOs allow dy-namic size adaptation to the application needs. To avoid over�ow ofFIFO bu�ers, a credit-based �ow-control mechanism is supported.
A Heterogeneous SDR MPSoC in 28 nmCMOSfor Low-Latency Wireless Applications DAC ’17, June 18-22, 2017, Austin, TX, USA
NoC 0.357 - - 667 80 Gbit/s 23Periphery 0.101 0.041 16 - - -FPGA IF 0.046 - - 500 5 Gbit/s -LPDDR2 IF 1.535 - - 400 12.5 Gbit/s -1) Includes iDMA, MM, Mux. 2)Averaged over multiple functional units. 3)Based on exp()-calculation benchmark.
2.1.2 Memory Manager. On-chip SRAM is a very expensiveresource in terms of area. This constrains the size of local mem-ories within a PM. Tasks which need to use more memory thanlocally available can either not run at all on the platform or need amechanism to gain access to more memory. Since the architectureenforces strict memory isolation, a separate unit is needed whichopens up the visible address space in a de�ned manner. This unitis called memory manager (MM) and is integrated into each PM.It can transparently extend the local data memory to up to 192 kBby utilizing currently unused memories of a di�erent PM (whichcan provide 128 kB of SRAM at maximum). The advantage of usingSRAM of neighboring modules instead of SDRAM is that it providesa �xed and predictable latency which is essential for giving hardreal-time guarantees. NoC routes can be reserved to enforce this.If predictability and thus �xed latency is not important, memorycan also be mapped to SDRAM. In this case, the maximum amountthe local memory can be extended to is 2MB for the current im-plementation. It is only limited by the address space con�gurationof the PE. In contrast to a highly variable load-speci�c SDRAMlatency (min. 33 cycles), the read latency to a neighboring modulestays constant at 29 cycles. Also, in the latter case the memory andNoC load can be more evenly distributed over the chip since tra�cdoes not need to be routed through the SDRAM interface. Thus, theMM provides a scalable solution, which increases memory place-ment �exibility and reduces tra�c to and from SDRAM while stillensuring isolation.
2.2 Baseband Processing ModuleThe BBPM comprises three accelerators for computationally inten-sive receiver algorithms: a minimum mean square error (MMSE)based equalization (EQ) core, a MIMO sphere detection (SD) core,and a turbo decoding (TD) core. The BBPM area is 1.687mm2 in-cluding 0.879mm2 for 186 kB memory.
The architecture of the TD core is based on eight radix-4 maxi-mum a posteriori (MAP) kernels optimized for high communica-tions performance. It supports 3GPP-LTE-A block sizes of up to2016 bit and on-the-�y iteration control. Furthermore, it also fea-tures cyclic redundancy checks (CRC) for up to four LTE transport
blocks and supports soft value computation.The soft-input soft-output (SISO) SD core is based on a set of
programmable FUs which are controlled by the opcode of 64-bitVLIWs. In contrast to previous implementations, the partial met-rics of the log-likelihood ratio values are calculated by exploitingsymmetric properties of the QAM modulated symbols [1], whichreduces the enumeration e�ort and results in an increased detectionthroughput. At the same time, close to full max-log a posterioriprobability communications performance is still provided.
The EQ core extends a basic LX5 RISC by two dedicated FUsfor e�cient SISO MMSE-based equalization. While the �rst FUcombines multiple MAC operations to perform complex-valued dotproduct computations, the second FU enables accelerated process-ing for recursive algorithms such as forward/back substitution andCholesky decomposition.
2.3 Application Control ModuleThe ACM includes a Tensilica 570T CPU used as application corewith 16 kB cache for data and instructions each. It furthermorecomprises a dynamic scheduling unit, called CoreManager, to or-chestrate the platform. The CoreManager is based on a TensilicaLX5 RISC with tailored instructions for e�cient data �ow mapping.The core is attached to 64 kB DMEM and 32 kB IMEM. The totalACM area is 0.701mm2 of which 0.452mm2 is occupied by theSRAM and caches. To ensure security, only the CoreManager isallowed to access speci�c MPSoC con�gurations such as the LUTsor the �it counters integrated in the NoC routers. Monitoring the �itcounters and recon�guring the routing enables the CoreManagerto control the tra�c distribution and hence to reduce latency.
3 EVALUATIONThis section presents the manufactured Tomahawk4 chip and themeasurement results of the single MPSoC components as well as aperformance analysis of two multi-core application benchmarks.
3.1 Implementation ResultsThe 14-core SDR MPSoC was fabricated in Globalfoundries28 nm SLP CMOS technology and occupies 3 × 6mm2 with
DAC ’17, June 18-22, 2017, Austin, TX, USA S. Haas et al.
Table 2: Data Processing ASIP: Single-core Measurements of Functional Units at 500MHz, 1.0V
24.43 M NAND2 gate equivalents and 844 kB total on-chip memory.A high-speed serial link between routers 6 and 7 bridges the 4.5mmon-chip distance as can be seen in the chip photo of Figure 2.
The measurement set-up, depicted in Figure 3, includes the chipmodule with MPSoC and SDRAM which is placed on a power supplyboard. The board is plugged into a Xilinx Virtex-7 FPGA to enableinter-chip packet communication for system scalability. The physi-cal inter-chip communication is realized by the mentioned FPGAinterface employing high-speed serial links. In addition to this, theFPGA integrates an UDP/IP stack connecting the MPSoCs witha host-PC for control/debug purposes Further, the power supplyboard integrates an analog-to-digital converter to measure voltageand current of each power rail. Hardware performance counters ineach PE are used to monitor the execution time. Both power con-sumption and performance can be accessed by the CoreManager’ssoftware to support scheduling decisions.
As explained in Section 2.1, the LX5 core of each DPM is ex-tended by additional FUs to accelerate bit operations. Hence, we�rst evaluate the performance and power consumption of the indi-vidual FUs. For these experiments, the input data contains randomlygenerated values with uniform distribution and is located in thelocal DMEM of the DPM. Since the bandwidth of the global mem-ory is the bottleneck in the system, loading the data from SDRAMwould limit the performance and hide the e�ective throughput ofthe cores. Table 2 summarizes the measurement results of eachFU. Hashing extracts bits from a 32-bit integer value speci�ed by aspeci�c bit mask or applies the CityHash32 algorithm [7] of 8-bitstrings. Bit and integer count create an histogram to illustrate thevalue distribution of bits and 32-bit values, respectively. The sortingoperator is based on a merge-sort scheme and performs on a listof 32-bit integer values. The throughput for the 128 �xed-pointFFT is determined for 32-bit complex values and interpreted for a64-QAM signal. Compared with the pure RISC implementation, theFUs achieve speedups of up to more than three orders of magnitudewhile increasing the power consumption by 36% on average. As
Figure 3: Tomahawk4 Measurement Set-up.
the power increase is low compared to the speedups, the FUs leadto energy gains between 9× and 678× .
In the next set of experiments, we evaluate the BBPM cores.Table 3 lists their characteristics and performances along with state-of-the-art competitors. Based on the throughput and power valuesin Table 3, energy-delay pro�les expressed as EDP and ED2P �g-ures can be derived for the given operating points (clock frequencyand supply voltage). The delay is taken from the throughput andcalculated with 64 bit. Regarding the EQ core, its area and energye�ciency is signi�cantly lower (by more than a factor of 4) com-pared to the ASIC implementation. However, due to the highly�exible implementation, the ASIP EQ core can be reused for a rangeof transmission scenarios (both uplink and downlink) as well asiterative and non-iterative receiver schemes. Columns 3 and 4 ofTable 3 show that the SD core outperforms a comparable ASICimplementation in terms of both area and energy e�ciency by6.8× and 1.4× , respectively. Considering the last two columns, theTD core demonstrates to be a powerful but still energy-e�cientsolution, outperforming the TD presented in [12] by a factor ofalmost 3 for EDP and ED2P each. Since ED2P emphasizes perfor-mance, we can con�rm that our TD mainly bene�ts from a lowerpower consumption. Besides the individual results, an applicationbenchmark re�ecting the interaction of all BBPM cores has beeninvestigated in Section 3.2.
3.2 Application ScenariosThe presented SDR MPSoC is capable of combining high-throughput data processing with low-latency wireless applications.In a �rst benchmark, we execute integer hashing employing theLX5 cores of the DPMs which support the algorithm by instructionset extensions. The three power supply rails are set to 1.1, 1.0, and0.9V which corresponds to maximum clock frequencies of 667, 444,and 333MHz, respectively. We further de�ne the requirement toachieve a total throughput of at least 200Gbit/s. The CoreManager
A Heterogeneous SDR MPSoC in 28 nmCMOSfor Low-Latency Wireless Applications DAC ’17, June 18-22, 2017, Austin, TX, USA
Throughput [Mbit/s] at fmax 1683) 7573) 2144)5) 664) 435.96) 390.67)Power [mW] at fmax, VDD 2038) 189 1428) 177.5 3658) 789Area e�ciency [Mbit/s/kGE] 0.39 1.85 0.54 0.08 0.36 0.71EDP [10−15 Ws2] 29.5 1.4 12.7 166.9 7.9 21.2ED2P [10−21 Ws3] 11.2 0.1 3.8 161.8 1.2 3.51)Refers to BBPM area (values in brackets refer to the PE area). 5)At 10−5 BER, SD radius size of 4 candidates.2)Core area only (w/o memories, iDMA, MM). 6)LTE block size of 2016 info bits, 1/3 rate, 5.5 iterations.3)For matrix inversion only (4 × 4 MIMO, 64-QAM). 7)LTE block size of 3200 info bits, 1/3 rate, 5.5 iterations.4)With 2 detection-decoding iterations, 4 × 4 MIMO, 64-QAM. 8) Includes leakage power of total BBPM and NoC.
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Figure 4: CoreManager determines minimal power con-sumption with available PEs to meet the throughput con-straint (>200Gbit/s) by assigning PEs to power supply railswith prede�ned voltages and frequencies.
analyses the throughputs and power consumptions for a speci�cnumber of PEs and their assigned power rail. Figure 4 depicts themeasured power consumption for di�erent numbers of PEs. Sincea single PE delivers only 109Gbit/s, at least two PEs have to beavailable. The CoreManager minimizes the total power consump-tion to 136mW by using four PEs assigned to the power rail at0.9V. Compared to the two-core option, the energy consumptionis reduced by approximately 32 %.
As described in Section 2.2, the BBPM comprises essential re-ceiver components for physical layer processing. Depending onthe communication direction (up-/downlink) and the channel sce-nario, the BBPM cores perform iterative detection-decoding oriterative equalization-decoding. As a second benchmark, we use anon-iterative receiver scheme for a 4 × 4 MIMO-ISI channel sce-nario, which represents SC-FDMA transmission for the LTE uplink.For this purpose, the received signal (present in frequency domain)has to be equalized, transferred to time domain, soft-demodulated,and eventually decoded. To guarantee high communications per-formance at low latency, the data �ow of the processing schemescan be e�ciently mapped to dedicated MPSoC resources (Figure 5).
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The considered codeword length is 6060 bit with a code rateof 1/3. In this scenario, a bandwidth of 128 subcarriers is allocated,which requires two SC-FDMA symbols to accommodate the com-plete code word. It is assumed that the channel does not signi�cantlyvary within one transmission time interval (1ms). Consequently,the equalization �lter matrix does not need to be recalculated foreach SC-FDMA symbol. The 128-points IFFT operation can be car-ried out individually for each transmit layer and is mapped to thefour LX5 RISC cores of the DPMs. The soft demodulation for eachtransmit layer is performed by the sphere detection core. All pro-cessing modules run with 571MHz at 1.04V, resulting in a totalpower consumption of 414mW for this benchmark. Due to theASIP’s memory controllers as well as double bu�ering mechanismsat the sphere detector and turbo decoder input, a high total appli-cation throughput of 696Mbit/s (encoded) or 232Mbit/s (e�ective)can be achieved. The total processing latency from equalizer inputto decoder output is 20 µs.
DAC ’17, June 18-22, 2017, Austin, TX, USA S. Haas et al.
Table 4: State-of-the-art Platform Comparisons.
This work Tomahawk2 [11] 2x MT-ADRES [14] Magali [4]
Platform scope MIMO 3GPP-LTE-A, 802.11n,NB-IoT, SDR
MIMO 3GPP-LTE, WiMAX,802.11n, SDR
MIMO 3GPP-LTE Cat-4,802.11a/n, SISO WiMAX,SDR
MIMO 3GPP-LTE, WiMAX,802.11n, SDR, Cognitive Radio
Die size 18 mm2 36 mm2 10.6 mm2 29.6 mm2
Technology 28 nm 65 nm 40 nm 65 nmClocking and power mgt. GALS, local DVFS and AVS,
power gatingGALS, local DVFS and AVS,power gating - GALS, local DFS
Table 4 compares our SDR MPSoC with state-of-the-art plat-forms. For the described 4 × 4 MIMO application scenario, our SDRMPSoC outperforms the Tomahawk2 platform [11] by a factor of 4while reducing the total power consumption by 13 % and 17 % com-pared also to the Magali MPSoC [4] and the MT-ADRES chips [14],respectively.
4 CONCLUSIONSDR platforms with sophisticated hardware components for digitalsignal processing and bit processing are key to deal with currentand future wireless applications. In this paper, we demonstratedthe energy-e�cient implementation of an iterative MIMO receiverby following an HW/SW codesign approach with tailored dataprocessing modules and a baseband processing engine. Due tothe integrated memory controllers, the data �ow can be directlymapped on the platform to ensure low communication latencies.Furthermore, a hexagonal NoC improves the bisection bandwidth by66% compared to a standard XY mesh NoC. For security reasons onlya single scheduling unit, the CoreManager, controls the platformwhile applying power management techniques such as DVFS andAVS. Comparing a 4 × 4 MIMO application scenario for an LTE-A uplink with state-of-the-art systems, our �nal taped-out SDRMPSoC shows a 4× performance improvement at reduced powerconsumption.
5 ACKNOWLEDGMENTSThis work has been supported in part by the state of Saxony undergrant of the German Research Foundation (DFG) within the Clusterof Excellence “Center for Advancing Electronics Dresden” (cfaed),and SFB912 - HAEC. This work has further been supported bythe European Social Fund in the framework of the Young Inves-tigators Group “Communication Infrastructures for Attonets in3D-Chip-Stacks” (Atto3D), and by the European Union under GrantAgreements No. 604102 and DLV-720270 (Human Brain Project).Furthermore, the authors would like to thank Synopsys, Cadence,and ARM for providing software and IP.
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