IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 40, NO. 3. JUNE 1991 59 I

A High Speed 2-Bit Correlator Chip for Radio Astronomy

Albert Bos, Member, IEEE

Abstract-The design and performance of a 16-channel 2 X 2-b CMOS correlator chip with 22-b on-chip integration, op- erating at a typical clockrate of 64 MHz is presented. The chip, developed by the Netherlands Foundation for Research in As- tronomy (NFRA), is and will be used for the construction of large wideband correlation spectrometers. A 1024 channel module is described as an application example.

I. INTRODUCTION IGITAL correlation spectrometers have been in use D in radio astronomy since Weinreb introduced a

100-channel 1 -b digital autocorrelator built with transis- tors to measure the spectrum of radiation collected by a single antenna [ 11. The basic theory for this type of cor- relator had been developed previously by Van Vleck [ 2 ] and others [ 3 ] , 141. A typical spectrometer of this type consists of a digital correlator built with special purpose hardware which computes the correlation function of the input signal. The power spectrum of the input signal is obtained after a Fourier transform of the correlation func- tion by a gerieral purpose computer. A discussion of al- ternative spectrometer types is beyond the scope of this paper and can be found in [ 5 ] .

The observation of usually weak spectral line radiation requires long integration times, during which the instru- ment parameters should stay constant. Apart from the lower cost and better flexibility, the inherent stability of a digital spectrometer makes it a popular alternative to an analog filter receiver. The availability of low-cost inte- grated circuits make it possible to construct large cross- correlation spectrometers for multi-antenna synthesis ar- rays 161, [7]. This paper presents the design of a high- speed correlator chip developed by The Netherlands Foundation for Research in Astronomy (NFRA) to be used as the building block for the next generation of spectrom- eters within and outside NFRA.

11. DIGITAL CORRELATION A digital correlator calculates an estimate of the cor-

relation function of two sampled and quantized input sig-

Manuscript received June 7 , 1990; revised November 17, 1990. This work has been supported by The Netherlands Organization for the Ad- vancement of Scientific Research (NWO).

A. Bos is with the Netherlands Foundation for Research in Astronomy, 7990 AA Dwingeloo, The Netherlands.

IEEE Log Number 9143073.

nals x(kA t ) and y(kA t ) :

where

A t

B A r K n

f,

N

1 /h the sample interval of the input signal, sampling rate (nominally equal to 2 B ) , bandwidth of the input signal, delay increment (generally equal to A t ) , number of products added, index for the delay difference between x(t) and

y( t ) , (0 I n I N - 1 for auto-correlation (x = y); - N / 2 I n 5 N / 2 - 1 for cross-correla- tion),

number of lags (also referred to as the number of channels).

The basic operations to be performed by a correlator at a ratef, are thus multiplication, time delay, and integration.

In most digital-processing systems a sufficiently large number of bits for quantization and processing is required to allow the digitization effects to be ignored. A digital correlation spectrometer becomes, however, impracti- cally complex unless a small number of bits is used. Hence, digitization effects cannot be avoided. There are two kinds of effects: a nonlinear distortion in the corre- lation function measured and additional quantization noise [ 3 ] , [4], [8], [9], the distortion is correctable whereas the quantization noise is not. The correction for the distortion effect is carried out prior to the Fourier transform. The correction function is derived from the values of the de- cision levels of the analog-to-digital converters, the weight table (see Section 11-B) used and the, in radio as- tronomy Gaussian, probability distribution of the input signals [4], [ 8 ] .

A . Correlator Performance The performance of a correlator system is characterized

by its processing capacity, sensitivity, and flexibility. The processing capacity C of a correlator system is propor- tional to its clockrate and the number of channels N , e.g. ,

c = O12NB (2)

where 01 is a factor which depends on the number of bits used for correlation. The factor C is also a measure of the complexity and cost of a correlator and in addition it is

0018-9456/91/0600-0591$01 .OO 0 1991 IEEE

592 IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT, VOL. 40, NO. 3, J U N E 1991

TABLE I THE DEGRADATION FACTOR d OF THE

PERFORMANCE OF AN n-BIT CORRELATOR WITH RESPECT TO AN ANALOG CORRELATOR FOR DIFFERENT SAMPLING FREQUENCIES~,

AND OPTIMUM DECISION LEVELS AND WEIGHTING

n (bits) f, d

1 2B 1.57 4B 1.35

2 2B 1.14 4B 1.06

3 2B 1.05

-(analog) - 1 .o

approximately proportional to the square of the number of bits used to quantize the input signal(s).

The flexibility requirement follows from difference in the spatial and spectral properties of the objects to be ob- served. For single-dish spectrometers flexibility is re- quired to comply with the variable receiver bandwidth that matches the widths of the spectral lines to be observed. For a synthesis telescope it is also necessary to be able to match the spatial resolution to the size of the observed source. For a given correlator capacity, one needs, there- fore, the flexibility to exchange spectral and spatial res- olution. The WSRT [6], for example, has a maximum of 20 480 complex channels which can be divided over 160, 80, 40, or 20 antenna interferometer combinations with a spectral resolution varying between 8 and 256 points within a bandwidth B . The bandwidth B can, in turn, be vaned between 10 MHz and 78 kHz.

The sensitivity of a digital correlation spectrometer is proportional to the degradation factor d [4]. This is a mea- sure for the extra noise introduced by quantization of the input signals which depends on the correlation scheme used.

B. The Correlation Scheme The selection of the correlation scheme is a compro-

mise between complexity and sensitivity. Table I sum- marizes typical optimum values for the degradation factor d when the number of bits used for quantization and the sampling rate are varied [4]. Use of 1-b quantization in- troduces a sensitivity degradation of 1.57. The highest relative improvement is obtained when 2-b are used (see Table I). The best theoretical value at optimum decision levels and weights is then 1.14 [3.] The corresponding weights assigned to the four signal areas are ( -4 , - I , + 1, +4) which already requires 6 b in the multiplication process of two signals. The increase in complexity and cost hardly justify the use of three or more bits for quan- tization. Oversampling (f, > 2B) can be used to improve sensitivity [4] but has not been considered at chip level because the gain in sensitivity it yields does not compen- sate for the reduction in effective bandwidth it takes. A small sacrifice in sensitivity allows us to use the smaller

TABLE I1 THE BASE (a), REDUCED (b), THE OFFSET (C) WEIGHT TABLE

FOR THE 16 PRODUCTS FORMED WHEN T W O 2-BIT SIGNALS ARE MULTIPLIED

-9 -3 + 3 +9 -3 - 1 + 1 + 3 0 2 4 6 - 3 - 1 + I + 3 - I 0 0 +1 2 3 3 4 + 3 + 1 - 1 - 3 +1 0 0 - 1 4 3 3 2 +9 + 3 -3 -9 + 3 + l -1 - 3 6 4 2 0

weights (- 3, - 1 , i- 1, + 3). This leads to the weights of Table II(a) for the 16 products that can be formed when two signals are multiplied. Cooper [13] has shown that one can safely ignore the inner products with weights + 1 and - 1 . The products (Table II(b)) are then a factor of 3 smaller. The net degradation factor is equal to 1.15 for decision levels of -0.91, 0, +0.91 times the rms value of the input signal. For the accumulation of the products one can use some form of up/down counting. In practical circuits it is however attractive to just use the much sim- pler and cheaper ripple counters. An offset of 3 is there- fore added to each of the products (Table II(c)) and sub- tracted during the processing of the data.

111. THE NFRA CORRELATOR CHIP

The optimum implementation of a practical correlator circuit depends, to a large extent, on the available tech- nology. Initially 1 x 1-b correlators were (and are still) used because of their simplicity, stability, and robustness. The introduction of integrated circuits makes it feasible to increase thenumber of channels, the clockrate, and the number of bits used for correlation. Large correlators have been realized with MSI logic circuits [6], [ 101. For large correlator systems it becomes economically and techni- cally feasible to implement various parts of a correlator with MSI custom integrated circuits. The high-speed, cost, and gate count of the currently available application- specific integrated circuits allow the integration of a com- plete correlator circuit in a single chip. A number of cor- relator circuits are commercially available. These circuits are designed with various technologies for a very specific application (mostly radar) and system architecture. The high-speed circuits in particular, require a relatively large number of external circuits to meet the flexibility require- ments of a practical system [ 111-[ 141.

The design of this correlator chip is based upon a de- tailed study of correlator systems currently in use and the architecture of next-generation correlator systems re- quired for the two main application areas in radio astron- omy: cross-correlation spectroscopy in aperture synthesis arrays and auto-correlation spectroscopy at cm and (sub) mm wavelengths in single-dish, single, or multibeam re- ceivers. It should provide the flexibility to exchange spa- tial and spectral resolution and bandwidth and operate at clockrates of the order of 40 MHz to meet the bandwidth requirements of the various spectrometer types.

BOS: HIGH-SPEED 2-BIT CORRELATOR CHIP 593

A. Chip Architecture A typical correlator circuit has three functional parts: a

tapped delay line, a multiplier, and an integrator. Fig. 1 shows a block diagram of the chip. The two 2-b samples, x-, and y, are fed into an 8-b bidirectional shift register at a clock ratef,. The outputs of the two shift registers are connected to 16 multiplier/adder stages. The added re- sults are accumulated in an 18-b integrator. The multiplier receives two 2-b signals at the clockratef,, calculates the weighted products, and accumulates the result for every clock cycle. The accumulation can be split into an addi- tion of the products at full speed and a ripple counter that integrates the carries at a progressively lower speed (and also at a progressively lower power dissipation when CMOS digital rather than bipolar circuits are used for the implementation). The design of a practical (CMOS) cor- relator circuit for a given power dissipation is therefore a compromise between the number of delay/multiplier/ad- der stages and the length of the ripple counter. One of the problems in designing a high-speed complex correlator chip is the internal signal distribution. Most correlators currently use unidirectional N-b shift registers. One of the two multiplier inputs is connected to a separate shift reg- ister tap. The other input of all multipliers is fed in par- allel by a common input signal. The distribution of this signal is a problem that is solved in a bidirectional archi- tecture with two shift registers of length N/2 shifting in opposite directions. Each of the shift register outputs is connected to two multiplier inputs. Cascading of chips at the board level then becomes simple. The signal distri- bution problem is also present at the system level where one would like to interconnect chips in various patterns for reasons previously mentioned. Careful analysis of the various architectures shows that an on-chip four-input se- lector is sufficient to realize the interconnection patterns required for large correlator systems with no external components.

B. i%e Multiplier/Adder The multiplier/adder is implemented as a three-stage

synchronous pipeline. The multiplier stage (Fig. 2.) forms four base products T6 , T4 , T 3, and T 2 with the weights of 6, 4, 3, 2, respectively, of the (xs, xm) and ( ys, ym) outputs of the x- and y-shift register stages.

In the first adder stage the T 3 product is divided by 2 to form the 2T3 product with weight 6. Next, the prod- ucts with weight 4 (T6, T4 , and 2T3) and the products with weight 2 (T6, 2T3, and T2) are added and the car- ries S4 and S2, respectively, are propagated to the next stage.

The second adder stage contains a divider stage, which produces a carry 2S2 with weight 4. The 2S2 and S4 are then added and the sum S is divided by 2 in the third adder stage, before the carry is sent to the integrator. The IN- HADD lines optionally inhibits the adder by forcing the base products to zero. The PHASESW line optionally in- verts the signs of the weights in Table III(b) (a 180" phase switch) .

X-SELECT +X-DELAY X-SHIFT REGISTER (sign+magnitude) 0 1

a

Y-SHIFT REGISTER (sign+magnituda) Y-SELECT +Y -DELAY

16 bits RAM

MULTIPLIER

Fig. 1, A block diagram of the NFRA correlator chip. The lower part shows the setup of one of the 16 multiplierlintegrator stages.

IWWADD CUA8C8W - 1

I I 1 I I CLOCK I I I I I

Fig. 2 . The synchronous pipelined multiplier. The sign and magnitude bits of the two input signals XS, M and Y S , M are multiplied and the carry C of the accumulated product is propagated to the integrator.

C. The Integrator and Readout The rms noise in an integrated result is proportional to

the square root of the number of products added. Maxi- mally N/2 least significant bits of an N-b result could therefore be ignored when the result is read out. Integra- tion of these results may, however, introduce systematic errors depending on the reset procedure used.

The carries, produced by the muhipliedadder at a max- imum rate of 6/16 times its clockrate, are applied to an 18-stage ripple counter. The first four stages of the ripple counter are part of a prescaler with an effective length of 8 b when the 4 b of the adder are included. The 16 most significant bits are transferred to a latch to allow concur- rent readout after the disabling of the multiplierladder.

The truncation effects of the 8-b ignored are below the 12-b limit. An option has been implemented that reduces the prescaler length by 2-b and the maximum on chip in- tegration time by a factor of 4. This covers applications requiring short integration times in the ms range.

D. Cascading Facilities For large correlator systems one needs more than one

printed circuit board. The chip has, therefore, two pro- visions to accommodate the cascading of chips on differ-

594 IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT, VOL. 40. NO. 3, J U N E 1991

ent boards. First, an option to shift the output tap by one shift register to allow the user to add an (external) synchroni- zation stage at the board inputs to eliminate the interboard propagation delays. Second, an optional extra internal de- lay stage at the input of the chip to compensate for the "missing" delay when a shifted output is fed back locally (see Section 4).

E. Additional Features The chip has provisions for a number of features that

simplify its use in various types of receiver systems. For observations corrupted by strong interference or

observations of time-variable phenomena like solar bursts, it is often advantageous to use 1 X 1-b correlation (1 X 1-b correlators are less sensitive to saturation effects than 2 3 2-b correlators). An option has therefore been added thaf disables the magnitude bits and reduces the weight table to weights of 0 and 6.

A blanking input that forces the correlation coeffi- cient to zero and a correlation inhibit input is provided to simplify gated correlation for interference suppression and pulsar observations.

A 180" phase switch is added to allow implementa- tion of a phase switch mode (used in cross-correlation re- ceivers to suppress dc-offsets and spurious signals).

The combination of the 180" phase switch and the blanking operation can be used as a three-state (- 1, 0, + 1) phase rotator like the one used in correlators for very long baseline interferometry (VLBI) [ 151.

F. Implementation and Pevormance The correlator circuit has been implemented in a 1.5-pm

CMOS gate array with 8000 gates. Bipolar gate arrays have been rejected mainly because of their high power dissipation and cost. Parallel processing with CMOS cir- cuits turned out to offer a cost-effective alternative for the processing requirements of wideband spectrometers. The 16-b internal busses and the complex shift register mul- tiplier connections are responsible for a gate utilization factor of 65 % . The specifications are summarized in Ta- ble I11 (a more detailed description is given elsewhere [16]). The chip proved to operate properly, even when cascaded, at clockrates in excess of 64 MHz.

IV. AN APPLICATION EXAMPLE At system level it turns out that, for the correlator ar-

chitectures required within NFRA (and elsewhere), a module can be defined that correlates two sets of eight inputs using an 8 x 8 array of correlator chips [ 171. The module architecture is shown in Fig. 3. The two sets of signals are fed to eight chips in row-direction for the X-signals and in column-direction for the Y-signals. A single module produces all 64 cross correlations between the X- and Y-signals. Feedback of the X-outputs of the last column of chips to the Y-input lines produces all corre- lations within a single set of eight signals. The diagonal of the array produces the auto correlation of each input

X-CUT

I I

Y-IN

CLOCKS

I , ' I I I L INTEQRATION CONTROL

Fig. 3 . A block diagram of a correlator module that produces all correla- tions between two sets ( X I N , Y l N ) of up to eight input signals using an 8 X 8 array of correlator chips.

TABLE 111 SUMMARY OF THE SPECIFICATIONS OF THE NFRA CORRELATOR CHIP

Clockrate

Number of signal input pairs Number of lags Number of bits correlated Sensitivity degradation Number of accumulator

Data read out

Power dissipation

stages

:

: : 16 : 2 X 2 o r l x l : : 22 or20

55 MHz (worst case), 64 MHz

2 x 4 (sign + magnitude) (typical)

1.15 (2 x 2-bit), 1.57 (1 X I-bit)

:

: 21mW/MHz

16 most significant bits asynchronously from a 16 x 16-b on chip RAM

and a combination of the chips ij andji produces the pos- itive and negative lags of a cross-correlation function. (Note that, respectively, the real and complex spectra end up with the same number of points).

Two of the four chip inputs are used to cascade the chips. The cascading can be done in row-direction and/or in row/column-direction (see Fig. 4). This provides for the flexibility to increase spectral resolution by ignoring inputs. A further increase in resolution can be obtained by cascading modules and/or by using parallel modules to correlate the inputs ignored when the chips are cascaded. The delays introduced by the synchronization of the input signals are compensated by the shifting the tap of the X-outputs of the last column and the Y-outputs of the first column. The internal delay in the chip inputs is used to compensate the signal shift when the output signals are used to cascade chips locally. The integrated results can be read out directly via a standard VME bus P2 connec- tor. Table IV summarizes a selection of the possibilities offered by a single module. One module is currently op- erational at a (system) clockrate of 40 MHz in a 1024-channel spectrometer for the Dwingeloo radiotele- scope. A total of 16 modules will be used in a 2048-channel spectrometer with a bandwidth of 2 x 1 GHz currently under construction at NFRA.

BOS: HIGH-SPEED 2-BIT CORRELATOR CHIP 595

Fig. 4. The cascade interconnection pattern of the correlator chip array of Fig. 3 used to increase the number lags per correlation function at the ex- pense of the number of correlations made.

TABLE IV A SELECTION OF CORRELATOR MODULE

CONFIGURATIONS

# Inputs Correlation # Lags

Correlated Functions per cf

8 x 8 8 x 4 8 x 2 8 x 1 4 x 4 4 x 2 4 x 1 2 x 2 2 x 1 1 x 1

64 32 16 8 16 8 4 4 2 1

16 32 64 128 64 128 256 256 512 1024

V. CONCLUSIONS Currently available custom integrated circuit technol-

ogy makes it feasible to implement a high-speed correla- tor chip that covers a large variety of radio astronomical applications. Careful consideration of these applications

have led to a chip design that minimizes the number of external circuits required as is illustrated in the imple- mentation of a correlator module.

ACKNOWLEDGMENT Phil Dooley, now at the Very Large Array, has been of

great help with the building of the test setup for the chip. R . P. Millenaar and S. Th. Zwier converted the module architecture into a 10-layer printed circuit board.

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[4] F. K. Bowers and R. J. Klinger, “Quantization noise of correlation spectrometers,” Astron. Astrophys. Suppl., vol. 15, pp. 373-380, 1974.

[5] A. Bos, “Backend spectrometers: A review,” in Instrumentsfor Sub- millimeter Spectroscopy (Proc. SPIE, vol. 598), E. Kollberg, Ed., 1985, pp. 134-140.

[6] A. Bos, E. Raimond, and H. W. van Someren Greve, “A digital spectrometer for the Westerbork Synthesis Radio Telescope,” As- tron. Astrophys., vol. 98, pp, 251-259, 1981.

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[8] J. B. Hagen and D. T . Farley, “Digital correlation techniques in ra- dio science,” Radio Sci. , vol. 8, pp. 775-784, 1973.

[9] A. Bos, “On instrumental effects in spectralline synthesis observa- tions,” Thesis, Leiden University, The Netherlands, Sects. 4 and 15, 1985.

[lo] J . G. Ables, B. F . C. Cooper, A. J . Hunt, G. G. Moorey, and J. W. Brooks, “A 1024-channel digital correlator,” Rev. Sci. Insrr., vol.

[l 11 R. Escoffier, “Digital correlator and integrator custom integrated cir- cuits,” VLA Elect. Mem. 140, Nat. Radio Astronomy Observatory, 1986.

[12] W. S . Wilson and D. R. Brown, “The Australia Telescope Correlator Chip,” in IREE Conf., Sydney, Australia, 1987.

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[14] C. R. Lahmeyer and S. S. Broki, “Survey of current correlators and applications,” Jet Propulsion Lab., Pasadena, CA, TDA Progress Rep. 42-90, 1987.

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[I61 A. Bos, “The NFRA correlator chip,” The Netherlands Foundation

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