IEEE Transactions on Nuclear Science, Vol. NS-34, No. 1, February 1987

A HIGH SPEED ADC FOR RABBITSYSTEM DATA ACQUISITION

John OliverHarvard University, High Energy Physics Laboratory

Cambridge, Massachusetts 02138

and

Craig Blocker and Phil KestenBrandeis University, Dept. of Physics

Waltham, Massachusetts 02254

Abstract

A new ADC module for use in the Rabbit data aquisitionsystem is described. It offers significantly increased speedwhile rmi nlaimring the resolution required for a variety of highenergy particle detectors. The speed increase is achieved by theuse of floating point analog to digital conversion.

Introduction

The Rabbit system [1] is a front end analog dataacquisition system used at Fermilab at the CDF detector andother experiments to collect and digitize large numbers ofsignals from a variety of detector elements. It is an analog busbased system with two distinct and redundant data transferbusses. The analog data is produced by a variety of front endanalog signal processing cards such as charge integrators forwire chambers and cathode pad calorimeters, time to voltageconverters, and other special purpose modules.

Signals in the form of differential analog voltages aretransmitted along the analog busses to either of two identicalADC units, called EWEs (for Event Write Encoders), residingin the crate. Each EWE is capable of testing any signal in thecrate and then digitizing any signal found to be over aprogrammed threshold level. The two EWEs typically workconcurrently to scan a crate, however either one can assumetotal responsibility in the event of failure of the other unit orfailure of any component on another card which results inhanging up one of the data transfer busses.

Digitizing time is clearly of prime importance as thiscontributes directly to the dead time of the front end electronicsin an experiment. Of equal importance however is thresholdcomparison time, as channel occupancy rate can be quite low.

In this paper we describe a new ADC module for theRabbit system which provides a significant reduction in bothdigitizing and threshold comparison time. The increaseddigitizing speed is achieved through the use of floating pointanalog to digital conversion .

Physics Reguirements

There are two primary requirements for the ADC's thatdigitize the CDF front end electronics - speed and resolution.The speed required is set by the trigger rate and the necessity ofkeeping the dead time small. At full luminosity, the front endelectronics will be scanned at a rate of 100 hertz. To keep thedead time less than 10%, it is necessary that the scan take lessthan one millisecond. The time tscan required for a EWE to

scan N channels is

tscan = N (tsettle + f tADC + toverhead)where tsettle is the time required for the input to the EWE tosettle before a test-over-threshold can be done, tADC is thetime required by the ADC to digitize, toverhead is the overheadtime, and f is the fraction of channels that are over threshold(typically 0.15). The overhead time, including downloading of

the EWE registers, uploading of the results, and formatting ofthe data, is typically one microsecond per channel. Since eachEWE must scan approximately 250 channels, keeping the scantime under one millisecond requires that (tsettle + f tADC) bekept under 3 microseconds. For the new upgraded EWE, thesettling time is 1.5 microseconds and the digitization time is 4.5microseconds, which gives an average of 2.2 microseconds perchannel.

For the CDF experiment, 16 bits of dynamic range areneeded so that large signals do not overflow the ADC, yetsmall signals associated with low energy and minimumionizing particles are measured with sufficient precision. Forlarge signals it is not necessary to have the 16 bits of precisiongiven by a linear ADC, since the detector signals havevariations that are much larger. The floating point ADC of theEWE has 16 bits of dynamic range spread over five gain rangeswhich differ from each other by factors of 2. By sacrificingprecision for large signals, the floating point ADC gains speedrelative to equivalently priced linear 16-bit ADCs.

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Figure 1. Comparison of the resolutions of a 16-bitlinear ADC (solid line) and 16-bit floating point ADC(dashed line). Also shown are the inherent resolutionsof some typical CDF detector elements - the centralelectromagnetic calorimeter (dotted line) and the centralhadron calorimeter timing measurement (dot-dashedline).

Figure 1. shows the precision of a 16-bit floating pointADC. For small signals it has the same precision as a linear16-bit ADC. For larger signals, a programmable gain amplifierswitches ranges and the precision, expressed as a fraction offull scale, degrades. The discontinuities in the precision aredue to range switches of the programmable gain amplifier. Forcomparison, the inherent resolution of typical components of

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the CDF detector are also shown on figure 1. For all signalsizes, the inherent resolution of the detector componentsdominates the precision of the floating point ADC.

ADC Technigue

The floating point ADC technique is outlined in figure 2.

The DAC output current is summed with a positive currentproportional to the analog signal as shown in Fig. 3.

Analog Input

Comparator

c

0.x

Figure 2. Floating Point ADC

The differential analog signal is taken from thebackplane, an analog pedestal is subtracted, and the result ismultiplied by a constant factor. After this pedestal subtraction,the signal will always be a voltage in the range of 0 to +10volts. It is then presented to the circuits which constitute thefloating point ADC. These include a 4-bit flash ADC, aprogrammable gain amplifier (PGA), and a fast 12 bitsuccessive approximation ADC. The PGA has programmablegains of 1,2,4,8, and 16.

After pedestal subtraction the signal is sampled by theflash ADC to determine the appropriate setting of the PGA. Ifthe signal determined by the FADC is in the upper half range,the PGA gain will be set to 1. If the signal is between 1/4 and1/2 ,the gain is set to 2. If the signal is between 1/8 and 1/4the gain will be 4 and so on up to a gain setting of 16.

This operation effectively increases the dynamic rangeof the system by 16. A PGA gain setting of 1,2,4,8, or 16corresponds to an overall scale multiplier of 16,8,4,2, or 1,respectively, when applied to the result of the subsequent12-bit ADC. Since the scale multiplier is a power of two, it canbe represented as a 3 bit exponent. Thus the result of theoperation is a code of the form

OUTPUT=(12-bit Mantissa) x 2(3-bit exponent)

which will be in the range of 0 to 64k counts. This form of theoutput code assumes that the PGA gains are exact powers oftwo and are accurate and stable to the 16 bit level. In ourimplementation of this technique, no attempt was made toachieve this level of accuracy and stability. Instead, the 3-bitexponent is treated as a code which simply specifies which ofthe PGA gain settings was used. The actual gainscorresponding to each of these settings are measured and storedduring a calibration procedure.

Circuit Implementation

At the time of this design effort, Commercially producedfloating point ADCs were on the market [2]. These units tendedto be large, expensive and in early stages of production. Thedecision was therefore made to incorporate the desired featuresof the technique into our own design.

Threshold Comparator

High speed threshold comparison is achieved throughthe use of current, rather than voltage, subtraction. A 12-bitcurrent output DAC is programmed with the desired thresholdlevel. The DAC acts as a programmable current sink whose fullscale range corresponds to 1/16 of the full scale signal size.

Figure 3. Ground Referenced Threshold Comparator

The summing point voltage is then amplified andcompared to ground potential by a fast comparator (AM686). Ifthe summing point voltage is positive than the signal is overthreshold and should be digitized. This technique is inherentlyrapid as current settling is much quicker for DACs than isvoltage settling. In addition, it is quite stable and insensitive togain stability in the gain stage since comparison is always madeat ground potential. Thus the requirement of the gain stage isthat it be fast at the expense of linearity. In practice a simplematched transistor differential amplifier is used.

The settling time of the threshold comparator circuits israpid enough that this time is essentially determined by thecircuits producing the signal voltage. This time is of the orderof 1.5 microseconds. Test results will be discussed later.

Floating Point ADC - Programmable Gain Amplifier

The FADC is an AM6688 which is a 4-bit device and isstrobed at the same time as the threshold comparator. The resultis sent to a PAL device which produces the 3-bit exponent codeas well as the lines necessary to control the PGA.

Overall circuit performance is critically dependent on thedesign of the PGA. In particular, it must be designed withparticular attention to settling time as this contributes directly tooverall dead time.

Inverted Analog'Input

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AD380

Figure 4. Programmable Gain Amplifier

The implementation shown in Fig. 4 uses two SD5000quad CMOS FETs as the switching elements in a standardmultipying DAC configuration. These devices were chosenbecause of their small gate to drain and gate to sourcecapacitances. These capacitances directly cause charge injectioninto the summing node and affect settling time of the amplifier.As expected, the settling time increases with increasing gainsetting. Bench top analog measurements of switch recoverytime show settling to 1/2 LSB (1.2 mv) at the amplifier outputto be less than 1.5 usee for gains of up to 8. The 16x gain

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setting requires somewhat more. This limitation iscircumvented by having the PGA remain in the 16x state as thedefault setting. Therefore recovery time due to gain switchingis less than 1.5 usec in all cases.

The ADC is an AD578 requiring 3 usec for a 12 bitconversion. Thus the time required for a 16 bit equivilentfloating point conversion is 4.5 usec once the decision is madeto digitize.

Timing

Start Conversion JSequence

Input SettlingTime

Strobe Compargor,Switch PGA

PGA Settling __Time

12 Bit ADCBusy

..0 1 2 3 4 5 6 7

Time (usec)

Figure 5. Conversion Sequence

The time required for threshold comparison is mainlydue to the settling time requirements of the input amplifiers andbus driving circuits and is set at 1.5 usec. If the signal is overthreshold, an additional 1.5 usec is required for PGA settlingand 3.0 usec for the 12 bit ADC for a total of 6 usec conversiontime. For a typical channel occupancy rate of 15% the averagescan time for a large number of channels is approximately 2.2microseconds excluding overhead. Of this time, the conversiontime and comparison time account for approximately equalportions of the total readout time for a crate. Above this averagescan time we must add the bus access time required tocommunicate with the module.

It is an inherent feature of the Rabbit system that no onboard intellegence or memory is included in the crate.Therefore, each channel requires it's pedestal value, channeladdress, and threshold to be loaded before conversion. Asmentioned before, the total bus overhead is typically one usecper channel.

Test Results

Settling Time

In order to do a precise test-over-threshold, it is necessarythat the voltage at the threshold circuit have settled to within afew hundred microvolts of its final value before the test isdone. When the next channel is to be tested, three registers areloaded in the EWE - (1) the pedestal DAC, (2) the thresholdDAC, and (3) the channel address register. The registerassociated with the longest settling time is sent first. If thethreshold DAC is the same as it was for the previous channel,it is not necessary that it be loaded again. This is typically thecase since large numbers of identical signal sources are oftenscanned sequentially.

The settling of the pedestal DAC was measured by firstsetting the threshold DAC to some value. The pedestal DACwas then stepped from an initial value down to a final value.The "test-over-threshold" sequence was initiatedsimultaneously with the pedestal voltage step. This is done inRabbit protocol by activating the XQT (Execute) control line.The final pedestal DAC value was varied until the

test-over-threshold was positive half of the time, indicating theeffective threshold. The settling time from when XQT was sentto when the test-over-threshold occurs was adjusted with apotentiometer on the EWE from 1.1 to 2.5 microseconds.Within this time window, the effective threshold wasessentially independent of the settling time and was the same asthe effective threshold obtained when XQT was sent a longtime (hundreds of microseconds) after the second pedestalDAC was set. This indicates that the pedestal DAC settles towithin a count or two within 1.1 microseconds of being set.This conclusion was independent of the size of the pedestalDAC step.

The settling of the threshold DAC was measured in the samemanner. The pedestal DAC was set to some value, then thethreshold DAC was set, and finally the threshold DAC was setto a second value, along with setting the XQT bit. The value ofthe pedestal DAC where the test-over- threshold was positivehalf of the time represents the effective threshold. As before,for settling times greater than 1 1 microseconds (including verylong times), the effective threshold is flat within a count ortwo, indicating the threshold DAC settles before the minimum1.1 microseconds.

The settling of the signal when a channel is addressed ismuch slower since the output buffers of the front endelectronics card, the RABBIT backplane, and the inputop-amps of the EWE all have to settle. The critical settling timeis when the system steps from a channel with a large signal toone with small or no signal. If the system steps from a smallsignal to a large signal, the test- over-threshold will be positive,even if the voltage at the EWE has not settled precisely. Tomeasure the settling associated with addressing a channel, firstthe pedestal DAC was set to some value, a channel with a largesignal voltage was addressed, and then a channel with pedestal(no signal) was addressed, along with sending XQT. Thepedestal DAC was varied to find the value at which thetest-over-threshold was positive half of the trials, giving theeffective threshold.

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Figure 6. Shift of effective threshold as a function ofthe size of the signal on the previous channel. Thereare four sets of data for settling times of 1.1, 1.3, 1.5,and 1.7 microseconds. The threshold shift is thedifference between the observed threshold and thethreshold measured with a very long settling time.

Figure 6 shows the variation of the effective thresholdwith the size of the large signal for several settling times. Thevertical scale is the difference between the effective threshold atthat settling time and the effective threshold measured with along delay between setting the channel address and sendingXQT. For settling times greater than 1.5 microseconds, theeffective threshold is always under ten counts and reaches thissize only for the largest signal sizes on the previous channel.

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Reolution

Of interest is both the resolution of the thresholdcomparator as well as the ADC circuits. Threshold resolutionwas measured by performing large numbers oftest-over-threshold sequences while using the pedestal DAC tostep the voltage through the 50% firing point of thecomparator. The threshold resolution thus obtained was lessthan 2 counts out of 64k counts independent of thresholdsetting.

ADC resolution was measured in each of the- five gainranges and found to be range dependent. Measurements takenover a large number of boards show the resolution to betypically 0.5 to 0.8 counts out of 4096 counts depending onthe gain range. The larger values correspond to the higher gain(lower signal size) ranges.

Conclusions

A new ADC module has been constructed whichprovides 1.5 microsecond threshold checking and 4.5digitizing over a 16 bit dynamic range. This is done at amoderate cost of approximately $1k per completed ADC unit.Fifty of these units have been produced and are now beingincorpprated into the CDF data acquisition system at Fermilab.

Acknowledgements

The authors would like to acknowledge the considerableefforts of the electronics staff and graduate students of Harvardand Brandeei s who participated in prototyping, p.c. layout,testing and debugging the initial run of fifty completed units.These include R. Carey, S. Harder, E. Kearns, Tom Kepler,Tim Kinnel, J. O'Kane, and E. Strangman.

References

[1] G. Drake, T. Droege, C. A. Nelson, K. Turner "TheRabbit System: Low Cost, High Reliability Front EndElectronics Featuring 16 Bit Dynamic Range" IEEE Trans.Nucl. Sci. Vol. 33, No.1, Feb. 1986

[2] "MN5420 20-Bit Dynamic Range Floating Point ADC"Preliminary Application Note, Micro Networks div of UnitrodeCorp.