Solar Energy Materials & Solar Cells 111 (2013) 133–140

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Solar Energy Materials & Solar Cells

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A joint thermal–electrical analysis of void formation effects on concentratorsilicon solar cells solder layer

Stefano Baricordi, Gabriele Calabrese n, Federico Gualdi 1, Vincenzo Guidi, Matteo Pasquini,Luana Pozzetti, Donato Vincenzi

University of Ferrara, Physics and Earth Science Department, Via Saragat 1, Building C, Ferrara 44122, Italy

a r t i c l e i n f o

Article history:

Received 17 October 2012

Received in revised form

30 November 2012

Accepted 7 December 2012Available online 29 January 2013

Keywords:

Void

Concentrating photovoltaics

CPV

thermal analysis

electrical model

FEA

48/$ - see front matter & 2013 Elsevier B.V. A

x.doi.org/10.1016/j.solmat.2012.12.034

esponding author. Tel.: þ39 532 974213; fax

ail address: gabriele.calabrese@unife.it (G. Ca

esent address: PROMES-CNRS-7, Rue du Four

Odeillo, France.

a b s t r a c t

It is known that the formation of voids in solar cell solder joints leads to a worsening of their heat sinking

capabilities, causing an increase in the average device temperature and thermal resistance. This phenomenon

can be detrimental for the solar cell’s performance, since the open-circuit voltage linearly decreases with

temperature. The performances of silicon solar cells, in the presence of voids in the cell solder joint, are studied

by means of numerical simulations and of an analytical thermal model which can assess the local temperature

increase at cell surface due to a single isolated void in the solder joint. The results show that for small isolated

voids the analytical model gives temperature peaks above the voids which match very well with the

simulations result, within 5% of relative error. The analytical model also gives an estimation of the whole

device thermal resistance, in the presence of a regular pattern of non-interacting voids all with the same

surface area. For a 10�7 pattern of small area voids the analytical value for the device thermal resistance

matches well with the results of numerical simulations, with a maximum error of 17.3% at 70% void coverage.

To determine the temperature profile of the device surface we have implemented a thermal finite element

analysis (FEA) which employs a detailed 3D model of the real morphology of voids in the solar cell, obtained

by X-ray inspection. The resulting temperature map has been used as an input parameter for the subsequent

electrical simulations performed by means of PSPICE software, which is based on a distributed 2.5 D electrical

model of the solar cell. Results show that, for a concentrating factor of 100� , a real void pattern with 36.6%

void coverage does not noticeably affect the performances of a concentrator silicon solar cell.

& 2013 Elsevier B.V. All rights reserved.

1. Introduction

Soldering processes in large area semiconductor devices areoften affected by the formation of voids at the interface betweendevice and substrate. Void formation may be due to a badsoldering process, or arise as a result of thermo-mechanicalstresses introduced during device operations [1–3]. These voidshave a deleterious effect on the heat sinking capabilities of thedevice [4,5] since they are responsible for a local increase inthermal resistance. This, in turn, can drive the formation offurther voids and compromise the reliability of the device.

Concentrating photovoltaic cells are wide area devices thatperiodically undergo large thermal flow variations. In that, anassessment of the impact of void presence on solar cell temperaturedistribution and performances can be very useful.

In this work, four concentrator silicon solar cells manufacturedby Narec Solar, Blyth, UK (with an area of 19 mm�14 mm each)

ll rights reserved.

: þ39 532 974210.

labrese).

Solaire, 66120—Font

have been soldered to a metal core printed circuit board (MC-PCB). The soldering process was carried out by a lead-free Sn/Ageutectic solder paste; in particular, we focused our attention tonon-optimized processes having temperature profiles which gaverise to large density of voids.

A void map has been obtained for each of the four cells by X-rayinspection. One of these maps has been used as input parameter for athermal finite element analysis (FEA), carried out by means of ADINA8.7 (Automatic Dynamic Incremental Nonlinear Analysis) software.As a result we have obtained the temperature map of the selectedsolar cell, exhibiting hot spots in correspondence to the location ofvoids. This map has then been used as input data for the subsequentelectrical analyses performed by ORCAD PSPICE software. To thispurpose a distributed 2.5 D electrical model of the solar cell has beenimplemented; the entire solar cell has been represented by an arrayof subcells whose PSPICE netlist has been generated through aMATLAB script. In this way solar cell electrical performances havebeen evaluated.

Further simulations have been performed for regularly spacedvoid patterns. In particular, we have analysed 2�2 and 10�7void matrices, for different values of void percentage and sinktemperature.

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140134

We have also developed an analytical thermal model useful toassess the local temperature increase of the device surface due to asingle isolated void and the whole device thermal resistance inpresence of a regular void pattern. The obtained results have beencompared to those of finite element analyses.

2. Electrical model

One of the main steps of this work consists of assessing solar cellperformances in terms of delivered power under real operatingconditions. A detailed description of the equivalent electrical modelemployed for simulations can be retrieved in Ref.[6,7]. Basically, thesolar cell has been divided into a large number of subcells through anonlinear binning procedure. Each element has then been repre-sented by an equivalent electrical circuit, as shown in Fig. 1.

This model takes into account the main layers that compose aconventional silicon solar cell, i.e., emitter, base, front contact grid andback contact. Each subcell is equipped with a current generatorsimulating the local photogenerated current, while a diode modelsthe p–n junction behaviour. The electrical parameters of the subcellsand the geometry of the front contact have been obtained from thedevices under test. In order to include in the simulations the devicelocal temperature increases, the electrical parameters of the subcellelements, such as semiconductor layer resistivity and p–n junctioninverse saturation current, have been calculated depending on thespecific temperature value of each grid element, retrieved from thetemperature maps.

The temperature coefficient of resistance (TCR), for both theemitter and base, has been calculated as a function of dopantconcentrations, according to another work [8]. Table 1 reports the

Fig. 1. Pictorial representation of the 2.5D distributed solar cell electrical model.

main parameters of the devices under test at room temperature.The cells under test show a comb-like front contact grid patterncomposed of 10 mm-wide 5 mm-thick fingers and two 700 mm-thick busbars, for a total coverage of 15%; the current is supposedto be extracted by two 3 mm-wide pads from one side of the cell.In the electrical simulations we have modelled the voids, which arelocalized in the solder joint region, as discontinuities in theconnection between the solar cell back contact and the MC-PCB.To this end the void map obtained by X-ray inspection has beenused as an input parameter for the simulations; the obtained solarcell model result composed of 158�215 grid elements. The resultsof the electrical model simulation comprehend maximum powerdelivered by the cell, fill factor and open-circuit voltage.

3. Thermal model

3.1. Analytical approach

In this paragraph we will obtain an analytical expression for boththe steady-state local temperature increase at cell surface and thedevice thermal resistance increase caused by a single void in the dieattach layer, by using the simplified model described below. Further-more, the whole device thermal resistance, in presence of a matrix ofN identical voids, has been estimated using the same model.

For an easy geometrical treatment we have considered thethermal resistance and temperature increase due to a cylindricalshaped void lying in the device solder region, having a radius of baseR and the same thickness of the solder joint. Moreover we haveassumed that the heat flux F, due to solar irradiance, is entirelyinjected at the top surface of the device. The thermal conductionthrough void volume has been neglected since the air thermal con-ductivity – kair¼0.0257 W m�1 K�1 at 300 K – is about four ordersof magnitude smaller than that of silicon – kSi¼148 W m�1 K�1

at 300 K – in the temperature range of interest. As a consequence theheat flux F does not flows across the void volume but instead itspreads out toward the boundary regions and is eventually dissipatedin the direction beneath the copper layer.

As a working hypothesis we consider that the temperature verticalgradient is zero inside the silicon cylinder above the void volume. Thisintroduces a small error in our model but allows us to obtain anapproximate analytical form of the temperature rise caused by solderjoint discontinuities. Due to void presence, the heat flux generated atthe top surface of the silicon cylinder spreads across the plane of thedevice, i.e., the xy plane in Fig. 2, from the inner side of the siliconcylinder to its edge.

A further approximation consists of considering the heat fluxexiting the cylindrical silicon volume above the void to be directlysunk toward the beneath copper layer, without spreading into thesurrounding regions. This approximation does not reflect any realisticcase since a temperature increase is always experienced by the device

Table 1Room temperature parameters used for the elec-

trical simulations.

Cell dimensions 1.9 cm�1.4 cm

Short-circuit current

density

3 A/cm2

Emitter resistivity 30 O/sq

Bulk resistivity 1 O cm

Concentration factor 100�

Metal-semiconductor

resistivity

1�10�6 O cm2

Metal resistivity 2.82�10�6 O cm

Emitter thickness 300 nm

Bulk thickness 250 mm

Fig. 2. Schematic cross-section of the physical model used for the theoretical approach. The heat flux is supposed being generated from the top surface of the device.

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140 135

regions surrounding the void; however, it results useful in theanalytical calculation of the local temperature increase. As a summarywe have assumed that the whole flux generated at the top surface ofthe considered silicon cylinder is vertically dissipated along the lateralsurface of the same volume element. This approximation leads to anunderestimation of the device thermal resistance, because the short-est path length for heat dissipation has been considered. Moreoverthis model neglects the cross-interaction between voids, in case morethan one discontinuity lie in the device solder joint, leading to afurther underestimation of the device thermal resistance.

To obtain an analytical expression for the local temperatureincrease at device top surface, due to a single void in the solderlayer, the silicon cylinder lying above the void volume has beenmodeled as a set of infinitely thin concentric rectangular toroids.A schematic representation of the simplified physical model is shownin Fig. 2

We have focused our attention on the heat flux flowing inside aslice of the silicon cylinder, having an infinitesimal angle aperture da.

The temperature drop across the width dr of a genericinfinitesimal toroid, having a distance r from the center of thesilicon cylinder, is given by:

@T ¼Pe

kSi � Asð Þ� dr ð1Þ

where kSi is the silicon thermal conductivity, while As and Pe arethe cross-section area of each toroid and the power crossing it,respectively. For each toroidal element, As is given by the productbetween the arc of circumference r � da and the thickness of thesilicon slab ts:

As ¼ ts � r � da ð2Þ

while Pe is equal to the power generated in the circular sectorwith area r2 � da=2

� �at the top surface of the silicon cylinder:

Pe ¼F � r2 � da

2ð3Þ

The overall temperature difference DT between the center ofthe silicon cylinder lying above the void volume and its edge canbe obtained by substituting Eq. (2) and Eq. (3) in Eq. (1), andintegrating Eq. (1) over r:

DT ¼

Z R

0@T ¼

F � R2

4� kSi � tsð4Þ

The temperature difference between the center of the siliconcylinder lying above the void volume and its edge can also beexpressed as a function of the void area AV :

DT ¼F � AV

4p� kSi � tsð5Þ

The linear dependence between the temperature increase andthe void area remains valid until a void is centered sufficiently faraway from the perimeter of the device, so that edge effects can bediscarded. A linear relation between temperature variation peakand void area has been also derived by FEM simulations of singlevoids with aspect ratio e¼1 by Ciampolini et al. [9].

Starting from Eq. (5) of temperature peak of the top surface ofthe device due to a single void, it is possible to express ananalytical form for the whole device thermal resistance inpresence of N voids with base area AV . In this derivation weneglect the mutual interactions between voids since the heat fluxgenerated at the top surface of each silicon cylinder lying above avoid element has been assumed to be vertically dissipated alongthe lateral surface of this cylinder.

By definition, the device thermal resistance yD is expressedby:

yD ¼TS�Tsink

Pirrð6Þ

where TS is the average temperature of the top surface of thedevice, Tsink is the temperature of the heat sink and Pirr is the totalpower injected into the top surface of the device.

The average temperature at solar cell top surface can bewritten as:

TS ¼Tno void

S � AD�N � AVð Þþ TSvoid� N � AVð Þ

ADð7Þ

where Tno voidS is the surface temperature of the device regions

without voids in the solder joint, AD is the whole device surfacearea and TS

voidis the average temperature at the top surface of

each silicon cylinder lying above a void volume. The averagetemperature at the device surface of the regions interested byvoid presence is given by:

TSvoid¼ Tno void

S þDT ð8Þ

where DT is the average temperature increase on the top surfaceof each silicon cylinder lying above a void volume.

Table 2Thermal and physical properties of the silicon slab and other layer materials

composing the concentrator package.

Material Density[g/cm3]

Thermalconductivity[W m�1 K�1]

Specific HeatCapacity[J Kg�1 K�1]

Thickness

Silicon 5.3 kSi Eq. (12) 400 400 mm

Conductive

paste

– 49 – 25 mm

Copper 8.96 390 900 70 mm

Insulate – 1.3 – 35 mm

Aluminum 2.7 237 900 1600 mm

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140136

According to Eq. (4) we have:

DT ¼1

R

Z R

0�

F � r2

4� kSi � tsþ

F � R2

4� kSi � ts

" #dr ¼

F � AV

6� p� kSi � tsð9Þ

Substituting Eqs. (7)–(9) in Eq. (6) we obtain the followinganalytical form for the whole device thermal resistance, in case N

non-interacting voids with base area AV lie in the device solderregion:

yD ¼1

Pirr

Tno voidS � AD�N � AVð Þ

ADþ

Tno voidS þ

F�AV

12�p�kSi�ts

� �� N � AVð Þ

AD�Tsink

24

35ð10Þ

In the following paragraphs the obtained expressions for themaximum temperature increase at device surface caused by asingle void, and for the whole device thermal resistance, will becompared with the results of FEM simulations. In this way it willbe possible to quantify the error made by the analytical model fordifferent void sizes and patterns.

3.2. Finite element model

Finite element analyses have been implemented to assess thetemperature distribution profile on the cell surface, for a singleisolated void and for different void sizes and patterns. Moreover,the simulated average temperature on the top surface of thedevice has been used to assess the whole device thermal resis-tance. The obtained results have been compared to that of thedeveloped thermal model.

The temperature profile at the solar cell surface has beenassessed by solving the Poisson’s heat equation for the device,with proper boundary conditions (BCs). To do that, the wholedevice multi-layer structure has been represented by means of adetailed 3D finite element model developed using the commer-cially available software ADINA 8.7.

The power injected at device top surface due to concentratedsolar irradiance (Pirr) has been calculated by taking into accountthe concentrating optical efficiency mopt , the solar cell conversionefficiency mcell and the geometrical concentrating ratio C. In thiswork the simulations have been carried out assuming C¼100� ,mopt ¼0.75 and mcell¼0.2; moreover the standard direct normalirradiance (DNI) value of 850 W/m2 has been considered, for atotal power heat source of 13.57 W.

In the simulations Pirr has been modeled as the powerreleased by a heat source coincident with the top 30 mm of thesolar cell, so that the power released per unit volume results:

H¼ Pirr=V ¼ ½DNI � mopt � ð1�mcellÞ � C� � 1=tH ð11Þ

where V is the volume of the heat source in the simulation and tH itsthickness.

Natural convection BC with a convective heat transfer coeffi-cient of hc ¼ 5 W K�1 m�2 has been applied on top of the devicesurface, while radiative BC have been neglected as being evalu-ated less than 1% of the input power. A Dirichlet BC is set on theback surface of the MC-PCB substrate to simulate the heat sinkbehaviour, for different temperatures ranging from 293 K to338 K. Although this approximation does not reflect the realworking conditions of solar cells, it is useful in order to assessthe contribution of voids to the device thermal resistanceincrease, while introducing only a small error in the obtainedresults.

In the numerical models the voids have been considered ascylindrical volume elements of the solder joint having the samethickness of this region, and the air thermal conductivity expressed inSection 3.1. The solar cells have been modeled as a function oftemperature by interpolating the empirical data for silicon thermal

conductivity, in the temperature range from 293 K to 373 K, using theequation:

kSi ¼ 4:422� 106� T�1:856

þ36:29 ð12Þ

while the thermal properties of the other materials composingthe device have been considered constant within the sametemperature range. In Table 2 the thermal and physical propertiesof the individual materials constituting the photovoltaic receiverstack are listed.

Aiming to assess the influence of voids on temperaturedistribution within the device, and not the real operative condi-tions of the assembly, the domain of the finite element model hasbeen limited to a device volume having a base area equal to thatof the solar cell, i.e., only a portion of the MC-PCB substrate isincluded in the numerical model together with the cell. Thissolution allows a straightforward calculation of the device ther-mal resistance, while drastically reducing the computationaleffort required for simulations.

The finite element models have been meshed using secondorder tetrahedral and hexahedral elements; fine mesh refine-ments have been required for solder joint and insulate layers dueto the existence of high thermal gradients. Grid independencestudies have been carried out by evaluating the maximum andminimum surface temperature and the mean device thermalresistance for different concentrating factors, in order to checkthe local and overall convergence of results, respectively. Theresulting numerical models are constituted by a number ofelements which depends on the void pattern distribution, reach-ing up to 4�105 tetrahedral elements for a real void pattern.

At first, FEM analyses have been implemented to assess thelocal temperature increase at device surface, caused by thepresence of a single isolated void in the solder region. We havecompared the simulated temperature increase with that derivedanalytically in Eq. (4) for a void with same dimensions; in thisway we were able to test the validity of the analytical approachand to quantify the error introduced by the used approximations.

Fig. 3 shows the comparison between the simulated tempera-ture increase at device surface (dotted line) and that obtainedwith the analytical approach (lower solid line), for a void with aradius of base of 2.5 mm. In the analytical approach the tempera-ture increase at device surface is limited to the silicon cylinderlying exactly above the void, since the heat flux generated in thisregion is assumed to be directly sunk along the lateral surface ofthis volume. On the other hand, in the finite element simulationcurve we observe that a temperature increase is also experiencedby device regions lying outside the void area and, in particular,we note that the temperature rise in these regions decreasesexponentially with the distance from void edge.

The simulated temperature profile at device surface in theregion comprised between �2.5 mm and 2.5 mm -correspondingto void size- is well approximated, with 95% of confidence, by aquadratic function having a coefficient of �2:548� 10�1 K mm�2,

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140 137

which is shown in Fig. 3 This value matches, within 7% of relativeerror, with the coefficient found for the analytical temperaturecurve of �2:36� 10�1 K mm�2. We observe that the analyticalapproach underestimates the temperature increase at devicesurface as a consequence of the approximations made in derivingEq. (4). At the void center, the temperature obtained throughanalytical considerations is about 0.34 K smaller than that obtainedthrough finite element analysis. This corresponds to a relative errorof about 20% between the analytical and simulated temperaturepeaks for the case under analysis. This value can be considered as arealistic upper bound for the temperature mismatch between thesimulations and the analytical model, since the considered void islarger than typical voids found in the device solder joint and hencein this case the spreading of the heat flux, which is not consideredin the analytical approach, interests a larger area of the device. As aconsequence, a larger area around the void undergoes a tempera-ture increase, leading to a higher peak temperature above the voidvolume.

In the next paragraph the analytical model will be tested underreal conditions, by comparing the calculated temperature increaseand device thermal resistance with the simulated ones, for a real voiddistribution pattern obtained from the X-ray image of a soldered cell.

Fig. 3. Comparison between the numerical temperature curve retrieved by 1D

sampling the device surface (dotted line) and the theoretical curve obtained using

Eq. (4) (lower solid line), as a function of the distance from void center. The central

portion of the simulated curve has been fitted using a second order polynomial

function which is also shown.

Fig. 4. (a) [left]. X-ray image of the silicon concentrator solar cells showing the underne

solar cell retrieved from finite element analysis, for a heat sink temperature of 318 K. T

and the temperature profile at cell surface is clearly visible.

3.3. Finite element model of a real void pattern

Finite element analysis has also been implemented to assessthe local temperature increases at the device surface caused bythe presence of a real void pattern, obtained from a solderingprocess. In this way the effect of both void size and density ofneighboring discontinuities on the local temperature increase atdevice surface has been estimated for different situations. Thesimulated temperature peaks have been compared to thoseobtained with the analytical approach to identify its range ofvalidity.

Experimentally, we have soldered four 19 mm�14 mm con-centrator silicon solar cells manufactured by Narec Solar, Blyth,UK, onto a 5 cm�5 cm metal core printed circuit board (MC-PCB)substrate, by means of a lead-free Sn/Ag eutectic solder paste.

In Fig. 4(a) we show the X-ray image (60 keV, 40 mA s, Wanode and Mo inherent filtering) of the four solar cells, revealingthe underside of the void pattern. Geometrical data of the voiddistribution pattern have been included into the finite elementsimulation to obtain the temperature profile at device surface. InFig. 4(b) the simulated temperature profile of the bottom rightcell in Fig. 4(a) is shown (sink temperature 318 K and concentrat-ing ratio C¼100� ). In Table 3 the simulated temperature peaksat the device surface, in correspondence of void volumes in thesolder joint, are compared with those obtained analytically, forseveral voids with different areas and shapes. For each void thediscrepancy from a perfect circular shape has been evaluatedusing a digital image processing code script that fits the voidsurface with an equivalent ellipse-like area distribution, andprovide the radius of a circle having the same area [10].

As expected, the device regions with a higher local surfacetemperature correspond to the regions of the solder layer occu-pied by the largest voids. In the particular case under analysis themaximum temperature increase at device surface has beenevaluated as DTmax ¼ 0:76 K, in correspondence of a void withan area of 7.25 mm2. The simulation shows that the high densityof small area voids in the central region of the cell contribute toan overall temperature increase of about 0.2 K, while voids withbase area of about 4 mm2 or more give rise to temperature spikesover 0.4 K. A brief analysis of the results shows that the differencebetween theoretical and simulated temperature peaks at thedevice surface grows with the void area AV and with the densityand size of adjacent voids. The impact of the void area can beexplained considering the effect of heat flux spreading in thedevice plane described in Section 3.2. If two or more voids areclose enough to each other, the heat fluxes spreading out from thesilicon cylinders above them mutually interact, and also in this

ath void pattern. Fig. 4 (b) [right]. Surface temperature profile of the bottom right

he correspondence between the void distribution pattern in the device solder joint

Table 3The base area, eccentricity, simulated and calculated temperature peaks at void center and the relative error between these values are shown for some of the voids in the

bottom right cell in Fig. 4 (a). The voids have been divided in three different groups, depending on their size and on the density of adjacent voids.

Void Base area Eccentricity Simulated Calculated Relative[mm2] [0oeo1] DT [K] DT [K] Error

Small isolated voids which show a good agreement between simulated and analytical

temperature peaks

A 0.99 0.63 0.081 0.077 4.9%

D 1.67 0.58 0.136 0.131 3.6%

Large voids which show a large error between simulated and analytical temperature peaks

B 7.25 0.67 0.76 0.57 25%

C 3.69 0.55 0.4 0.28 30%

E 5.48 0.82 0.6 0.43 28.3%

G 4.26 0.63 0.43 0.33 23.3%

Small voids adjacent to other discontinuities which show a poor agreement between

simulated and analytical temperature peaks

F 2.49 0.33 0.36 0.2 44.4%

H 1.07 0.57 0.14 0.083 40.7%

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140138

case the heat fluxes spread on a larger area in the plane of thedevice before being completely dissipated toward the heat sink.This leads again to a larger increase in the average temperature atthe device surface, and also to higher temperature peaks above thevoid volumes. Increasing the density of proximate voids makes thiseffect more important, leading to higher temperatures above thevoids and in the surrounding regions. Moreover, as a consequenceof these phenomena, also the device thermal resistance increases.These phenomena are not considered in the analytical approachsince it neglects the spreading of the heat flux outside the voidvolume and hence it follows that a larger relative error betweenthe analytical and simulated surface temperature is obtained forlarge voids and for voids with a high density of proximatediscontinuities, as shown in Table 3. A very good agreementbetween theoretical and simulated temperature peaks has beenobtained for small isolated voids with coverage area less than2 mm2, i.e., A and D in Fig. 4(b); for these voids the relativediscrepancy is less than 5%. This means that the spreading of heatflux in the device plane has only a small effect on the temperaturepeak at cell surface at least for voids of such a radius.

A large error between the analytical approach and the simula-tions has been found for large area voids (B, C, E and G) due to theincreasing, with void area, of the heat flux spreading effects; inthis case the relative error is comprised between 23.3% and 30%.

A poor agreement between the analytical temperature peaksand the simulated ones has been obtained for small voids lying indevice regions which surface temperature is influenced by thepresence of neighboring discontinuities (voids F and H). In thiscase the obtained relative error is bigger than 40% indicating thatthe thermal model can not give a good estimation of temperatureincrease at device surface for voids in contact with other dis-continuities, as happens for void F. Void H is not so close to otherdiscontinuities, however, in Fig. 4(b) we observe that it lies in aregion of the device having an average temperature which ishigher than that of void-free regions. This is a consequence of thepresence of large voids in the neighboring region, e.g., void B,whose heat flux spreads in the plane of the device for a largedistance before being completely dissipated. It follows thatdiscontinuities, even if not very close to each other, may mutuallyinteract if their area is large enough. An example of the mutualinteraction effect between adjacent voids can be seen comparingtemperature peaks for A and D voids with that of H void, whichhas an area and eccentricity similar to A but experiences an erroras large as 40.7%. A similar behaviour characterizes the F void forwhich the relative error is 44.4%, due to the strong interactionwith large area voids, clearly visible in Fig. 4(b). The mutual

interactions between voids increase as the distance betweenvoids drops and rises with the size of adjacent voids. Also largevoids experience the interaction with adjacent discontinuities, ascan be seen comparing voids C and G. The second one has a largerarea but the relative error between the thermal model and thesimulations is bigger for the first one, because it is surrounded byseveral voids one of which is very large.

We have used the simulated average temperature at devicesurface TS

FEMto assess the whole device thermal resistance yD

FEM:

yFEMD ¼

TSFEM�Tsink

Pirrð13Þ

The simulations show that the real void pattern under analysis(total area of voids 36.6%) causes an increase in device thermalresistance of 8.8%, which is in good accordance with the 8.5%observed by Fleischer et al. [1] for a pattern of randomlydistributed voids with the same void percentage.

To assess the effect of the temperature increase on theelectrical performances of the device we carried out a finiteelement simulation using a software routine developed for thispurpose, which has been described in a previous work [7]. Thetemperature map in Fig. 4(b) has been used as input parameterfor the electrical simulations of the cell behaviour, for which theresults are shown in Tables 4 and 5. In Table 4 we observe that thepresence of the real void pattern leads to a decrease in themaximum power delivered by the cell of only 0.07% for a sinktemperature of 298 K while, increasing the temperature of theheat sink to 338 K, the maximum power delivered by the celldecreases by 0.24%. This percentage increase in power drop withincreasing temperature of the heat sink can be explained byconsidering that in the temperature range of interest, i.e., from298 K to 338 K, the thermal conductivity of silicon decreases. Thiseffect leads to slightly larger temperature variations at solar cellsurface due to void presence, for devices with higher temperatureof the heat sink, causing larger drops in cell performances. InTable 5 are reported the operating voltages (Vo) of the devicesubcells which lie in correspondence of the center of the studiedvoids, for a heat sink temperature of 338 K. By comparing Table 5and Fig. 4(b) we observe that the obtained values for Vo do notdepend strongly on the void sizes, and hence on the localtemperature peaks at device surface, but instead they dependon the distance between the considered subcell and the solar cellcontacts. In particular, the lower values for Vo are obtained forvoids G, F, E and D which lie in the lower part of the cell, near thecell contacts, while increasing the distance between the

Table 4Power delivered by the cell with and without the real void pattern for different

temperatures of the heat sink.

Heat sinktemperature (K)

Maximum powerdelivered by thecell (W):

Difference between theobtained values (%)

Withvoids

Withoutvoids

298 2.640 2.642 0.08

308 2.463 2.465 0.08

318 2.291 2.294 0.13

338 1.967 1.972 0.25

Table 5Operative voltage values of device subcells located in correspon-

dence of void centers.

Void Measured Vo at void center for a heat sinktemperature of 338 K (mV)

A 599.78

B 600.97

C 597.48

D 593.58

E 593.87

F 595.35

G 595.18

H 600.02

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140 139

considered subcell and the cell contacts leads to an increase in Vo.This can be explained by considering that the forward bias voltageapplied across the cell can bring to the maximum power voltageonly the regions of the cell surrounding the contacts. As thedistance between a subcell element and the cell contactsincreases, the forward bias voltage across that subcell decreasesleading to an increase in Vo and a decrease in output power.

The drop in open-circuit voltage (Voc) due to void presence hasa smaller effect on the operating voltage of the consideredsubcells, since the local temperature increases observed at devicesurface are small. The larger temperature increase is only 0.76 K,so that considering the known voltage drop with temperature ofsilicon solar cells of 2.2 mV/K, we obtain a corresponding max-imum drop in open-circuit voltage of about 1.7 mV. This droponly interests few subcells confined at the center of void B whilethe subcells lying in correspondence of the other voids undergo asmaller drop in Voc. Since the variations in operating voltage ofthe subcells with distance from cell contacts is several timeslarger than the local variations in open circuit voltage due to voidpresence (as can be observed in Table 4) we can neglect it thedetermination of subcells operating voltages.

It follows that the cell performances are not noticeablyaffected by void presence, at least for a concentration factor of100� . The negligible effect of voids on the power delivered bythe cell is a consequence of the small increase in average surfacetemperature with voids and of the high electrical conductivity ofthe cell back contact, which allows the flow of high currentdensities. The electrical simulations show that the maximumpower delivered by the cell only depends on the temperature ofthe heat sink; increasing this temperature causes a worsening ofthe cell performances which is mainly due to the increase injunction inverse saturation current as the cell heats up.

It turned out from the simulations that, in this concentrationregime, the cells performances are affected in a negligible wayfrom the local increases of the device temperature due to voidpresence.

3.4. Finite element model of regularly spaced void patterns

Further simulations have been carried out for two regularlyspaced void patterns, constituted by a matrix of 2�2 and 10�7voids, respectively. The void coverage has been varied from 5% to70% of the solder joint area, in order to assess its influence on boththe thermal resistance of the assembly and the electrical perfor-mances of the solar cell. In Fig. 5 is shown the comparisonbetween the simulated and analytical device thermal resistance,as a function of the void percentage, for the 2�2 and 10�7 voidpattern and for a sink temperature of 308 K. Moreover, also thesimulated thermal resistance of the device, in presence of the realvoid pattern observed by X-ray inspection, is shown. The devicethermal resistance for the real void pattern results very similar tothe simulated one for the 10�7 pattern with the same voidpercentage, indicating that the real pattern could be described asan array of small area voids. This result is consistent with Fig. 4(a),which shows that the real void pattern is actually composed of amultitude of small voids, and only few large voids.

As expected, in Fig. 5 we observe that for all the studied casesthe device thermal resistance grows with the void coverage;moreover, the whole device thermal resistance is bigger for the2�2 void pattern than for the 10�7 pattern for both the thermalmodel and the simulations. We observe that the thermal modelunderestimates the whole device thermal resistance for both voidpatterns. According to Eq. (10), in the thermal model the increasein device thermal resistance is proportional to NA2

V=AD so that, atfixed void percentage NAV=AD, it depends on AV . On the otherhand, in simulations the device thermal resistance increasesfaster with the area of voids, as a consequence of heat fluxspreading in the device plane and interactions between disconti-nuities. As the area of voids increases, the spreading of the heatflux in the device plane interests a larger area of the cell whichheats up, leading to an increase in device thermal resistance.Moreover, the spreading of the heat flux far away from the voidboundaries causes the discontinuities to interact with each otheralso for small values of void percentage, leading to a furtherincrease in surface temperature and hence in device thermalresistance. Since the thermal model does not take into accountthese effects, a larger error between this model and the simula-tions is experienced for larger area voids in the device solder joint.

In particular, for the 10�7 pattern the mismatch at 70% voidcoverage is 15.2%, while it is 3.7% for a void coverage of 20%. Forthe 2�2 pattern the maximum mismatch at 70% void coverage is24.7%, while for a void coverage of 20% it is 8.3%. This means thatthe analytical model, which has been developed for a singleisolated void, cannot be used to accurately assess the devicethermal resistance neither for the real nor for the regularly spacedvoid patterns, even if the peak temperature above a single smallisolated void can be determined with good precision.

4. Conclusions

For this work we have developed an analytical thermal modelwhich is useful in the assessment of the local temperatureincrease at the surface of a concentrator silicon solar cell, due tothe presence of a single isolated void in the device solder joint.We have found that the void size and the density and sizes ofadjacent voids are key factors for a good agreement betweenanalytical and simulations results, since the thermal modelapproximates that the heat flux generated above a void is directlysunk along the lateral surface of the same void, neglecting theeffect of heat flux spreading in the plane of the device. For isolatedvoids smaller than about 2 mm2, which do not interact with othervoids, the model gives temperature peaks at void center which

Fig. 5. Comparison between the analytical and simulated device thermal resistance, as a function of the void percentage, for a 2�2 and a 10�7 void patterns. The

simulated device thermal resistance for the real void pattern is also shown.

S. Baricordi et al. / Solar Energy Materials & Solar Cells 111 (2013) 133–140140

match very well with the simulated ones, within 5% of relativeerror. For large area voids, starting from about 4 mm2, thismismatch grows and reaches a maximum of 30%, while for smallarea voids which lie very close to other voids the mismatch islarger than 40%.

The developed model also allows an assessment of the wholedevice thermal resistance in presence of a pattern of non-interacting regularly distributed voids, all having the same area.The model shows that for a 10�7 pattern of small area voids thewhole device thermal resistance slightly increases with thepercentage of voids, while for a 2�2 pattern of large area voidsthe device thermal resistance increases faster with void coverage.This is a consequence of the linear dependence observed inEq. (10) between the analytical device thermal resistance increaseand the void area AV , at fixed void percentage NAV=AD. However,finite element analyses show that the analytical model under-estimates the device thermal resistance for both the 2�2 and the10�7 patterns, and that the error made by the analytical modelincreases as the area of void and the void coverage increase. Thisis a consequence of the heat flux spreading effects, which areneglected in the analytical thermal model.

Starting from the simulated temperature profile at devicesurface, we have performed an electrical characterization of thecell based on a finite element analysis. It has shown that theperformances of the solar cell under analysis (void coverage36.6%), are not noticeably affected by the presence of voids, fora concentration factor of 100� . The voids lead to a maximumdecrease in the power delivered by the cell of only 0.24%, for atemperature of the heat sink of 338 K. Decreasing the heat sinktemperature leads to lower losses in delivered power caused byvoid presence since the silicon thermal conductivity increases asthe temperature of the cell decreases. The negligible power lossesassociated to void presence are a consequence of the modestincrease in average device temperature with voids and of thepresence of a high electrical conductivity cell back contact, ableto carry high current densities. The only important parameterturns out to be the average cell temperature, which is directlyconnected to the heat sink temperature.

In the thermal model we have assessed the temperatureincrease at void center with respect to its edge temperature,which has been assumed to be the same of device regions at very

large distance from voids. This assumption turns out to be trueonly in case of small isolated voids, since in this case the heat fluxinjected in the regions surrounding the voids can be easily sunkwithin a short range from the void edge. On the other hand, incase of large and/or non-isolated voids, the device regionssurrounding the voids under goes a temperature increase whichis not consistent with the model. It follows that the analyticalmodel is not precise in the assessment of the whole devicethermal resistance unless patterns of very small and separatedvoids are considered.

Further studies will be carried out to evaluate the influence ofheat flux spreading effects on temperature peaks at device sur-face, average temperature at device surface and whole devicethermal resistance.

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