A local oscillator for WCDMA band VII based on frequencymultiplication

Andrea Gerosa • Andrea Bevilacqua •

Andrea Neviani

Received: 10 October 2011 / Revised: 23 January 2012 / Accepted: 27 January 2012 / Published online: 16 February 2012

� Springer Science+Business Media, LLC 2012

Abstract This work explores the generation of a local

oscillator for WCDMA band VII based on frequency mul-

tiplication of a GSM reference. The frequency multiplier is

based on a PLL, which includes a compact VCO based on a

ring oscillator. A proper PLL design allows to sufficiently

reject the relative high VCO phase noise, complying with the

WCDMA requirements. The effectiveness of the proposed

approach is proved with the design of the whole multiplier in

a 90 nm CMOS technology. The generated oscillation ran-

ges from 3 to 6 GHz, while the simulated phase noise is

-120 and -144 dBc/Hz at a frequency offset of 0.6 and

20 MHz, respectively, dissipating 6.3 mW.

Keywords Frequency synthesizer � Voltage controlled

ring oscillator � Multistandard wireless receivers �WCDMA local oscillator

1 Introduction

The interest for monolithic multistandard radio receivers is

a matter of fact in modern communications. In the per-

spective of aggressive system integration, a broad-band

frequency synthesizer that generates the local oscillator

(LO) at all the required frequencies is a key block of a

multistandard transceiver [1–3]. However more efficient

solutions can be envisioned, taking advantage of the fact

that different standards call for frequency synthesizers with

different specifications. Therefore one may prefer to design

a high performance frequency synthesizer over a tighter

bandwidth for the most demanding standard and then

generate the other required LO with additional blocks.

From this perspective, this work explores the potentials

and the limits of generating a LO for the WCDMA band VII

(from 2.5 to 2.69 GHz), starting from a GSM-compliant

reference. The task requires frequency multiplication, hence

the effectiveness of this approach depends on the possibility

to realize a system whose complexity is much lower than a

dedicated frequency synthesizer. We propose to realize the

frequency multiplier using a PLL, whose VCO is based on a

ring-oscillator, which is a good candidate for a compact

solution with large tuning range. Since we can easily expect

that a ring oscillator will have poor phase noise performance,

the main contribution of this work is to prove the feasibility

of a PLL that sufficiently rejects the VCO phase noise, in

order to meet the WCDMA specifications that call for a phase

noise level below �130��140dBc/Hz at a frequency off-

set between few megahertz and tens of megahertz [2–4].

The PLL is described at the system level in Sect. 2.

However the performance of the single basic blocks, espe-

cially in terms of noise, strongly influences the minimum

loop bandwidth required in order to meet the specification

for the generated output signal. For this reason, a circuit

implementation for each block has been singled out, as dis-

cussed in Sect. 3, and the corresponding figures of merit have

been extracted by means of transistor-level simulations,

using the foundry models of a 90 nm CMOS technology. The

design of the PLL is then finalized in Sect. 4, while the

performance of the whole system is discussed in Sect. 5.

2 System description

The block diagram of the proposed frequency multiplier is

reported in Fig. 1: starting from the LO generated for the

A. Gerosa (&) � A. Bevilacqua � A. Neviani

Department of Information Engineering, University of Padova,

Via Gradenigo, 6/b, 35131 Padova, Italy

e-mail: gerosa@dei.unipd.it

123

Analog Integr Circ Sig Process (2012) 72:111–119

DOI 10.1007/s10470-012-9839-2

GSM standard used as a reference (Sref), ranging from

3.3 up to 3.6 GHz1, the signal is first divided by two and

then multiplied by three using a PLL. As a consequence the

generated oscillator will cover a frequency range from 5 to

5.4 GHz, i.e. the band VII.

Assuming that the PLL is in lock state, the system of

Fig. 1 can be studied in the phase domain, by means of the

block diagram of Fig. 2, which includes both the equiva-

lent models for each PLL building block and the equivalent

noise sources for the input reference (U2ref ;n), the phase and

frequency detector and charge pump (ipfd/cp,n2 ), the low-pass

filter (vlpf,n2 ), the VCO (U2

vco;n), and the frequency divider

(U2div;n). The reference noise is estimated from the GSM

standard requirements, as summarized in [4, 3], and its

spectral density is reported in Fig. 3. The other noise

sources depend on how the different blocks are realized at

the circuit level and will be discussed later in the paper.

As mentioned in the Introduction, the VCO of Fig. 1

will be realized using a voltage controlled ring oscillator, in

order to keep the complexity and power consumption of the

frequency multiplier negligible with respect to those of the

frequency synthesizer that generates the GSM LO, used as

an input reference by the proposed multiplier. We can

therefore expect a relatively high phase noise from the

VCO and hence the PLL loop filter must be carefully

designed in order to sufficiently suppress this noise, mak-

ing the total output phase noise (U2out;n) dominated by the

reference one. In order to demonstrate the effectiveness of

the proposed approach for the WCDMA oscillator, a

transistor-level implementation of each block is presented,

as described in Sect. 3 This allows to quantify the

parameters in the diagram of Fig. 1, especially the various

noise spectral densities. Knowing these figures of merit one

can eventually finalize the multiplier design, demonstrating

that the total output noise is within the prescribed level.

3 Circuit implementation

The circuit solutions proposed in this Section have been

designed in a 90 nm CMOS technology with a Vdd = 1 V

power supply and simulations are performed at the tran-

sistor-level, using the foundry models.

3.1 VCO

As mentioned previously, the VCO is based on a simple ring

oscillator. Each delay cell of the ring oscillator is realized as

indicated in Fig. 4(a): transistors M2 and M3 form a differ-

ential inverter, while the p-MOS load with positive feedback

allows to compensate the effect of finite output resistance of

M2–M3, calling for a lower transconductance at a given

oscillation frequency. Transistor M1 operates in triode

region and allows to control the bias current in the differ-

ential inverter, by varying the voltage Vcontrol: in this way the

effective oscillation frequency is tuned. The VCO oscillation

frequency fo can be estimated as

fo ¼1

2Nsd¼ Iav

2NCLVddð1Þ

where N and sd are the number of stages in the ring and the

propagation delay of a single stage, respectively; the

oscillation frequency can be estimated as the ratio between

the average current in the cell during the commutation Iav

and the load capacitance CL and voltage swing Vdd. Given

that both Iav and CL are proportional to the device aspect

ratio, an aggressive downscaling of the transistor sizes

should reduce the power consumption without impairing

the oscillation frequency. However a good phase noise

performance calls for large area devices, as discussed in

[5]. Although the PLL will reduce the effect of the VCO

phase noise, a design optimization is anyway advisable. A

good design compromise is summarized in Table 1. The

VCO is composed of two basic delay cells, as drawn in

Fig. 4(b) and the corresponding oscillation frequency is

reported in Fig. 5 as a function of the control voltage

Vcontrol: the VCO can cover a frequency range from 3 to

6 GHz, dissipating an average power of 2.5 mW. In the

diagram of Fig. 1, the VCO is modeled as an integrator,

whose gain KVCO is the variation rate of the output signal

frequency with respect to the variation of the control

voltage of the VCO: according to Fig. 5, KVCO % 20 MHz/

mV. The phase noise of the free running VCO at 5.22 GHz

is depicted in Fig. 6..

Fig. 1 Frequency multiplier block diagram

Fig. 2 PLL equivalent model in the phase domain, including noise

sources

1 We assume that the frequency synthesizers generate references at a

double frequency, in order to counteract LO leakage and to ease

quadrature generation.

112 Analog Integr Circ Sig Process (2012) 72:111–119

123

A good trade off between power consumption and phase

noise is assessed in Table 2 where the proposed VCO is

compared with previous publications by means of a group

of significant parameters that includes a figure of merit

(FoM), defined as:

FoM ¼ 10logfo

Df

� �21

P

" #� LðDf Þ ð2Þ

where fo is the oscillation frequency, LðDf Þ is the phase

noise at a Df offset from fo, and P is the power

consumption.

3.2 Frequency divider

The frequency dividers in Fig. 1 are realized using flip-

flop based clock dividers; for instance Fig. 7 shows the

divide-by-3 circuit. The circuit is composed of two true

single-phase CMOS (TSPC) latches and a static CMOS

NAND. This solution is insensitive to the effective duty

cycle of the digital signals, because it uses a single phase

and the flip-flops are edge-triggered. The frequency divider

is modeled just as a gain stage (in our case M = 3). The

diagram of Fig. 1 includes also the equivalent noise source

of this divider, whose spectral density is shown in Fig. 8.

104

105

106

107

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

Relative Frequency [Hz]dB

c/H

z

Fig. 3 Power spectral density

of the input reference noise

U2ref ;n

Fig. 4 a Ring voltage-controlled oscillator delay cell circuit sche-

matic; b Proposed 2-stage ring oscillator

Fig. 6 Simulated VCO phase noise

Table 1 Transistors size for the circuit of Fig. 4(a)

M1 20 lm/120 nm

M2–M3 10 lm/120 nm

M4–M5 10 lm/120 nm

Fig. 5 Oscillation frequency at the VCO output versus tuning voltage

of the delay cells

Analog Integr Circ Sig Process (2012) 72:111–119 113

123

3.3 Phase-frequency detector charge pump and loop

filter

The Phase and Frequency detector that compares the input

reference to the PLL Sin to the feedback signal Sfb is

realized using the state machine reported in Fig. 9. When

the output signal Up is high the charge pump in the loop

supplies current on the loop filter, increasing the VCO

control voltage. Conversely, when the output signal Dn is

high, the charge pump draws current from the filter,

decreasing the VCO control voltage. Assuming that in

these two cases the magnitude of the charge pump current

is the same and is equal to Icp, then this block can be

modeled in the diagram of Fig. 2 (where it is indicated as

PFD/CP) as a gain block:

KpdðsÞ ¼Icp

2pð3Þ

The phase and frequency detector of Fig. 9 has been

realized using TSPC circuits, as discussed for the dividers,

and its schematic is reported in Fig. 10. Table 3 summa-

rizes the transistors size for this circuit, while the simulated

power consumption is 1.2 mW.

As reported in Fig. 11, the charge pump driven by the

phase detector has been realized using a current-steering

Table 2 VCO benchmarking

References fo [GHz] Df [MHz] P[mW]

LðDf Þ[dBc/Hz]

FoM [dB] Tuning [%] Process CMOS

This 5.22 10 2.52 -109.4 159.74 150.8 90 nm

This 5.22 1 2.52 -84.98 155.34 150.8 90 nm

[6] 5.65 1 5 -88.4 156.5 139.4 130 nm

[7] 6 10 2.4 -112.3 164 160 130 nm

[8] 5.79 1 – -99.5 – 14 180 nm

[9] 0.9 0.6 30 -117 165.8 46.2 0.6 lm

[10] 5 1 135 -85 137.7 113 180 nm

[11] 5.43 1 80 -98.5 154.2 25 0.25 lm

Fig. 7 Divide-by-3 circuit: ablock diagram; b Schematic

114 Analog Integr Circ Sig Process (2012) 72:111–119

123

architecture, which allows to reduce spurious current peaks

at a little power consumption penalty [12]. The R-C–C3

network connected at the charge pump output realizes the

PLL loop filter. The current supplied to or drawn from the

loop filter, indicated in (3) as Icp, is equal to 960 lA leading

to a power consumption of 1.2 mW. Table 4 summarizes the

transistors size for this circuit. The electronic noise due to the

PFD/CP components is modeled as an equivalent output

current noise source in the phase-domain model: the corre-

sponding spectral density is shown in Fig. 12.

4 Loop filter and PLL parameters

In order to realize a Type-II PLL, the loop filter has to

introduce in the system an additional pole at DC and, for

Fig. 8 Simulated divider phase noiseFig. 9 D Flip Flop phase and frequency detector

Fig. 10 Phase and frequency

detector circuit schematic

Analog Integr Circ Sig Process (2012) 72:111–119 115

123

stability reason, one additional zero. However it is advis-

able to introduce a second additional pole, in order to

contain the voltage ripple at the VCO input, as discussed in

[13]. The filter transfer function, which corresponds to the

load impedance of the charge pump, can be expressed as

Flpf ðsÞ ¼b� 1

b

ssz

sC ssz

b þ 1� � ð4Þ

where b = 1 ? C/C3, and sz = RC.

Having estimated the circuit-dependent parameters of

each block and all the equivalent noise sources of Fig. 2, the

PLL design can be finalized, looking for a good compromise

between noise suppression, loop stability and Vcontrol ripple.

Combining Eqs. 3 and 4 and setting K ¼ Kpd � KVCO; the

closed-loop transfer function of the system of Fig. 2 is:

Uout

UrefðsÞ ¼ K

2

b� 1

b

s � sz þ 1

s3 sz

b þ s2 þ sszK3

b�1b þ K

3b�1

b

ð5Þ

Considering that, as highlighted in Fig. 6, the VCO

noise is significant with respect to the WCDMA standard

limit up to a frequency of about 100 MHz, the PLL

bandwidth should extend up to this frequency. This goal is

achieved, choosing R ¼ 300 X;C ¼ 5 pF; and

C3 = 250 fF (b = 21). The PLL parameters are finally

summarized in Table 5.

The contribution to the total output phase noise of all the

noise sources quantified in Sect. 3 is summarized in

Fig. 13: as predicted, the total phase noise tracks the

Table 3 Transistors size for the circuit of Fig. 10

M1, M2, M3 2 lm/80 nm

M4 1.5 lm/80 nm

MR1, MR2 1 lm/80 nm

M5 0.8 lm/80 nm

M6, M7 1 lm/80 nm

Fig. 11 Current-steering

charge pump and loop filter

circuit schematic

Fig. 12 Simulated phase noise for the phase and frequency detector

and the charge pump

Table 4 Transistors size for the circuit of Fig. 11

M1, M4 10 lm/80 nm

M2, M3 2 lm/80 nm

MP1 5.6 lm/200 nm

MP2 5.6 lm/200 nm

MN1 15 lm/200 nm

MN2 1.5 lm/200 nm

116 Analog Integr Circ Sig Process (2012) 72:111–119

123

reference one at low frequency and the VCO noise

becomes significant only beyond the loop bandwidth of

100 MHz.

5 Simulation results

The whole proposed frequency multiplier has been simu-

lated at the transistor-level and some results are discussed

in this Section. Figure 14 shows a transient simulation of

the output signal Sout: a full-swing oscillation is achieved;

furthermore at time 52.5 ns the output oscillation fre-

quency changes from 6 to 5.4 GHz, responding to a vari-

ation of the input reference oscillation frequency from 4 to

3.6 GHz.

The simulated phase noise is shown in Fig. 15: the noise

spectrum is similar to other published results compliant

with the WCDMA standard, as summarized in Table 6. The

total power consumption of the multiplier is 6 mW and the

contribution of each block is highlighted in Table 7.

The spur components on the output spectrum due to the

reference leakage have been estimated combining a Spec-

tre-RF PSS simulation with a Monte Carlo approach, in

order to account for the effect of mismatch between the two

charge pump currents. The spur level is at least 56 dB

below the carrier and is compliant with the specification

reported in [14].

Table 5 PLL parameters extracted by transistor-level simulations

Kpd 153 lA/rad

KVCO 20 MHz/mV

Icp 960 lA

b 21

sz 1.5 ns

C 5 pF

104

105

106

107

108

109

1010

−260

−240

−220

−200

−180

−160

−140

−120

−100

−80

−60

[Hz]

[dB

c/H

z]

Out

PFD−CP

Div−3VCO

Filter

Ref/2

Fig. 13 Output-referred noise contribution of each block

Fig. 14 Transient simulation of the PLL output signal

Fig. 15 Simulated output-referred total phase noise

Table 6 Simulated phase noise for the generated LO at 5 GHz

Offset Simulated (dBc/Hz) Specification (dBc/Hz)

600 kHz -120 -109 [2]

3 MHz -134 -126 [4]

10 MHz -142 -126 [4]

15 MHz -143 -138 [4]

20 MHz -144 -139 [3]

Table 7 Power consumption of each multiplier block

Power [mW]

VCO 2.5

Phase detector 1.2

Charge pump 1.2

Frequency dividers 0.4

Buffers 1

Total 6.3

Analog Integr Circ Sig Process (2012) 72:111–119 117

123

6 Conclusion

A frequency multiplier for the generation of the LO for

WCDMA band VII from a GSM-compliant input reference

has been demonstrated. Exploiting a ring oscillator as the

core for a PLL, the system can be realized in a very

compact and low complexity form. The optimized design

has been verified with transistor-level simulations, dem-

onstrating that the designed circuit complies with the target

standard.

The proposed approach can be a good candidate for

extending the frequency range of GSM frequency synthe-

sizers and a possible alternative to wide-band PLL’s.

Furthermore, this solution can be used to make present

multistandard synthesizers cover WCDMA band VII, since

usually only the LO’s for the lower bands are generated. In

any case, the power penalty of 6 mW seems definitely

reasonable, considering that GSM and GSM/WCDMA

synthesizers typically dissipate several tens of milliwatts

[14–19]. From the perspective of area consumption, the

overhead of the proposed multiplier is totally negligible: as

a matter of fact, the proposed circuit is based on digital

gates and the area consumption will be dominated by the

passive components of the loop filter of Fig. 11. The total

area of the circuit is less than 0.005 mm2, while all the

above mentioned solutions, integrating an LC-tank, require

an area of some squared millimeters.

Acknowledgement The authors would like to thank Giovanni

Steffan for his contribution to this project.

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Andrea Gerosa received an

MS and Ph.D degree in Electrical

Engineering in 1995 and 1998,

respectively, from University of

Padova, where he is now Associ-

ate Professor. Andrea Gerosa is

senior member of the IEEE and

has published more than 70 papers

in international journals or con-

ference proceedings. His research

activities are within the area of

analog and mixed integrated cir-

cuits, for high-frequency, low-

noise and low-power applications.

Currently he is working on UWB

transceivers and radars.

118 Analog Integr Circ Sig Process (2012) 72:111–119

123

Andrea Bevilacqua received

the Laurea, and Ph.D degrees in

electronics engineering from the

University of Padova, Italy, in

2000, and 2004, respectively.

From 1999 to 2000, he was an

intern with Infineon Technolo-

gies, Munich, Germany. In 2001

he visited the Microelectronics

Laboratory of the University of

Pavia, Italy. From 2002 to 2003,

he was a Visiting Scholar with

the University of California,

Berkeley. Presently, he is an

Assistant Professor with the

Department of Information Engineering, University of Padova, Italy.

His current research interests include the design of RF/microwave

integrated circuits, and the analysis of wireless communication sys-

tems. Dr. Bevilacqua serves as a member of the Technical Program

Committee of the IEEE European Solid-State Circuits Conference,

and was a member of the TPC of the IEEE International Conference

on Ultra-Wideband. He is an Associate Editor of the IEEE Transac-

tions on Circuits and Systems II.

Andrea Neviani received a

‘‘Laurea’’ degree (cum laude) in

Physics from the University of

Modena, Italy in 1989, and the

Ph.D degree in Electronics and

Telecommunication Engineer-

ing from the University of Pa-

dova, Italy, in 1994. He has

been an EAP graduate student at

the University of California,

Santa Barbara, in 1994. From

1994 to 1998 he was a Research

Associate at the University of

Padova, where, from November

1998, he holds an Associate

Professor position. From November 1998 to 1999 he was visiting

engineer at Rutherford Appleton Laboratory, Oxfordshire, UK. In his

early career he worked on numerical simulation, modelling and

characterization of compound semiconductor devices for high fre-

quency applications, and on the study of methods for the statistical

simulation of VLSI circuits. At present his main interest is the design

of RF integrated circuits for communication and radar applications,

and mixed-signal circuits for biomedical applications. In his career,

he has been co-author of about 100 journal articles and conference

papers. Andrea Neviani is serving as an Associate Editor of the IEEE

Transactions on Circuits and Systems I and as a member of the IEEE

Technical Committee on Circuits and Systems for Communication.

Analog Integr Circ Sig Process (2012) 72:111–119 119

123