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A Low-Power Architecture for Sensor Nodes

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A Low-Power Architecture for Sensor Nodes. DEUS EX MACHINA: Octav Chipara Paul Gross Harri Thorvaldsson. Wireless Sensor Networks. Wireless sensor motes sense temperature, humidity etc., transmit and route data - PowerPoint PPT Presentation
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A Low-Power Architecture for Sensor Nodes DEUS EX MACHINA: Octav Chipara Paul Gross Harri Thorvaldsson
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Page 1: A Low-Power Architecture for Sensor Nodes

A Low-Power Architecture for Sensor Nodes

DEUS EX MACHINA:Octav ChiparaPaul GrossHarri Thorvaldsson

Page 2: A Low-Power Architecture for Sensor Nodes

2

Wireless Sensor Networks Wireless sensor motes sense

temperature, humidity etc., transmit and route data

Very limited: e.g. 4KB RAM, 64KB Flash, 40-250Kbps radios, 8/16 bit microcontrollers (MCUs)

Need to run for long time (month, years!) on batteries, i.e. two AA batteries.

Mica2

Telos

Page 3: A Low-Power Architecture for Sensor Nodes

3

Monitoring application characteristics

Workload = multiple periodic queries running concurrently, e.g.

Data flows from leaves to wired base station at top

Alternating low (waiting) and high-activity (working) periods

Data aggregation and processing can be MCU-intensive

SELECT AVG(humidity) AVG(temp)FROM sensors SAMPLE PERIOD 1s

Page 4: A Low-Power Architecture for Sensor Nodes

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Problem: MCU and radio waste power

Time

Power

Activity

1: Non-power aware system

Page 5: A Low-Power Architecture for Sensor Nodes

5

General solution: powersaving modes

Time

Power

2: Power-aware: sleep while idling

Sleep periods

Page 6: A Low-Power Architecture for Sensor Nodes

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Further chipping away at power

Time

Power

3: Sleep Deeper: gating, voltage scaling …

Page 7: A Low-Power Architecture for Sensor Nodes

7

Our enhancements, part A

Time

Power

4: Sleep Longer, exploiting periodicity

Page 8: A Low-Power Architecture for Sensor Nodes

8

Our enhancements, part B

Time

Power

5: Work while sleeping, via specilized chip

Page 9: A Low-Power Architecture for Sensor Nodes

9

Design Approach

Page 10: A Low-Power Architecture for Sensor Nodes

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Background: Essence of ESSAT

Expected time of first child packet

Actual timeSend to parent

Read sensor

Time

Delay

Time

Shift

Period n

Period n+1

Page 11: A Low-Power Architecture for Sensor Nodes

11

Saving power via periodic scheduling Old: MCU is boss, waits for interrupts, controls the

power level of other devices Interrupt-ready sleeping MCU quite power-hungry (5-

600A) Assume nothing devices turned on longer than needed

Clock Flash RAM ADC

CPU

Timer A

Timer B

UART0 UART1

IO Ports

MAB

MDB

Bus

Cov

MCU

Page 12: A Low-Power Architecture for Sensor Nodes

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Saving power via periodic, cont. New: Power Management Unit (PMU) is boss, runs a

periodic task schedule Sets device powerstates, including MCU (to deepest sleep) Maximizes sleep times and minimizes transition penalties PMU: extremely small, simple and power-efficient

Clock Flash RAM ADC

CPU

Timer A

Timer B

UART0 UART1

IO Ports

MAB

MDB

Bus

Cov

PMUPMU

MCU

Page 13: A Low-Power Architecture for Sensor Nodes

13

Deployment target: on-board CPLDs! CPLDs are very energy efficient CPLDs can be reprogrammed in-circuit A modular PMU allows per application customization

and selection of features, yielding a smaller circuit. Plug in aggregation functions, filters Interface with different devices, memories and buses. Adjust ISA to application needs

Page 14: A Low-Power Architecture for Sensor Nodes

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Software/hardware co-design

SELECT AVG(humidity) AVG(temp)FROM sensors SAMPLE PERIOD 1s

Hardware:Hardware:1. New sensor node architecture

• With specialized chip for power management, query processing, I/O

2. Uses periodic ESSAT-style scheduling:• Sleep long and deep without transition penalties• Dynamically adapt to changing workloads

3. Supports energy-hungry MCUs

Software:Software:1. Integration with TinyOS (mote OS kit)2. Design a library for taking advantage

of the new hardware architecture3. Dynamic PMU code generation from

query definition

Page 15: A Low-Power Architecture for Sensor Nodes

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Evaluation Approach: Micro and macro benchmarks

Hardware: VHDL / XSTHardware: VHDL / XSTChip-level simulation

• Show it fits on a CPLD• Show it works• Estimate power (using XPower)

Software: TinyOS / AVRORASoftware: TinyOS / AVRORAMote system-level simulation

• Estimate energy savings• Investigate trade-offs between

different PMU feature sets

SELECT AVG(humidity) AVG(temp)FROM sensors SAMPLE PERIOD 1s

Page 16: A Low-Power Architecture for Sensor Nodes

16

First design: PMU-1 PMU is simple, potential for

energy savings over MCU Schedule loaded into SRAM

by MCU Tiny programs (e.g. 32

instructions) in SRAM PC increments through

instructions in memory Instructions turn on/off

devices, with delay following Counter counts down cycles

of delay, returns control to PC

Comparator used in waiting for interrupt on return instructions

RAM

PC Counter

Addr

InstrDevice ID

Compare

Int ID

On / Off

Interrupt

CLK (advance)

Page 17: A Low-Power Architecture for Sensor Nodes

17

PMU-1 ISA

PMU-1 has three 16-bit instructions (8 bits instruction, 8 bits delay after instruction) Set device power state (SWITCH)

Jump to instruction (GOSUB)

Return from last jump (RETI)

Delay encoded as 2exp + add*2(exp-3)

15 14 - 12 11 - 8 7 - 5 4 - 01 State Device Delay Add Delay Exp

15 - 14

13 - 8 7 - 5 4 - 0

00 Address / 4 Delay Add Delay Exp

15 - 14

13 12 - 8 7 - 5 4 - 0

01 Wait

Interrupt ID

Delay Add Delay Exp

Page 18: A Low-Power Architecture for Sensor Nodes

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Example Waveform

Sample Program Switches 3 devices on with delays Jumps Switches 3 devices off with delays Returns, jumps back to beginning

Page 19: A Low-Power Architecture for Sensor Nodes

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PMU Power estimation Simulate PMU-1 on purely cyclical schedules Analyze simulation with XPower assuming:

Coolrunner XPLA3 CPLD Lowest voltage supported

  I (mA) P (mW)

Function Blocks: 0.216 0.390

Output Loads: 0.049 0.087

Global Resources: 0.028 0.050

Zia: 0.011 0.019

Clocks: 0 0

Inputs: 0 0

Signals: 0 0

Quiescent: 0.027 0.049

Total at 1.80V: 0.330 0.595

Page 20: A Low-Power Architecture for Sensor Nodes

20

PMU-1 Implementation

Implemented PMU-1 on Spartan-3 test board

LEDs “represent” devices turning on/off

Special thanks to David Zar

Program:SWITCH 1 0 0 1SWITCH 1 3 0 1SWITCH 0 0 0 0 SWITCH 0 3 0 0GOSUB 0 0 2

Page 21: A Low-Power Architecture for Sensor Nodes

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Second design: PMU-2

Assume contemporary and near-future hardware More autonomous devices (radios, sensors etc.),

communicating over common buses (SPI, I2C etc.)

Design goal: handle routine tasks while MCU sleeps.1. Runs ESSAT periodic scheduling of communication.

2. Move data between devices (serve as DMA engine)

3. Receive and send packets, sense and aggregate data.

Needs to access buses, RAM, acquire packet header and payload data, aggregate, assemble and transmit packet, adjust query scheduling …

Page 22: A Low-Power Architecture for Sensor Nodes

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PMU-2 Design Task table, co-operative task-switching Device table: dynamic powerstate conflict

resolution Main ISA instructions:

PEEK / POKE: read / write a byte from / to a bus. LOAD / STORE: load a variable into the accumulator ADD / SUB: add or subtract from the accumulator JMP(C) / GOSUB(C) / RET: (conditionally) jump, jump and

store return address and jump to return address S{L/G}E: compare to accumulator and set condition WAIT: wait for a timeout or interrupt

“System software”Too Complex

Page 23: A Low-Power Architecture for Sensor Nodes

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PMU-3 New design goal: run a PMU-1 like MCU

“precooked” schedule but be able to receive, aggregate and transmit packets by itself (as long as no problems) Simpler, less general, more focused design

Has PMU-1-like schedule programs (8-bit ISA) SLEEP, GOSUB, RET: wait, subroutine jumps and returns WRITE: write immediate to bus, to set powerstate or give

command to sensor or radio. RDADDn: read data value from sensor n via bus Precooked schedule no tasks, no need for dynamic

powerstate conflict resolution, no tables

Page 24: A Low-Power Architecture for Sensor Nodes

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PMU-3

Has packet handler subroutines, invoked on arrival of a packet Dispatched on a query ID byte in packet header Instructions to read bytes from radio and add to

aggregate data values in a per-query memory buffer Buffer has exact same layout as data in packet RDADD, RDMAX, RDMIN

4 12 21 3 1 4 5 1Packet Mem:

RDADD

Page 25: A Low-Power Architecture for Sensor Nodes

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PMU-3

Has packet handler subroutines, invoked on arrival of a packet Dispatched on a query ID byte in packet header Instructions to read bytes from radio and add to

aggregate data values in a per-query memory buffer Buffer has exact same layout as data in packet RDADD, RDMAX, RDMIN

4 12 21 3 5 4 5 1Packet Mem:

RDADD

Page 26: A Low-Power Architecture for Sensor Nodes

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PMU-3

Has packet handler subroutines, invoked on arrival of a packet Dispatched on a query ID byte in packet header Instructions to read bytes from radio and add to

aggregate data values in a per-query memory buffer Buffer has exact same layout as data in packet RDADD, RDMAX, RDMIN

4 12 21 3 5 4 5 1Packet Mem:

RDADD

Page 27: A Low-Power Architecture for Sensor Nodes

27

PMU-3 Dynamic state per query:

Pointer in memory Number of child packets received

Static state (from program text) per query: Query ID Memory buffer address Packet handler address

Global static state Mote ID Number of queries Number of children Timeout for waiting for child packets

Page 28: A Low-Power Architecture for Sensor Nodes

28

Experiments

Page 29: A Low-Power Architecture for Sensor Nodes

29

System Integration

Query Definition:Query Definition:SELECT AVG(humidity) AVG(temp)FROM sensors SAMPLE PERIOD 1s

PMU Code:PMU Code:…SWITCH HumiditySensor ONGoSub ReadHumiditySenorSWITCH TempSensor ONGoSub ReadTempSenorSWITCH Radio ONGoSub AggregateQ1SWITCH Radio OFF…

PMU MCUCC1000

Spi/Port

D

Spi/C

onf

Spi/C

onf

Spi/C

onf

ADC

Sensors

Page 30: A Low-Power Architecture for Sensor Nodes

30

System Integration (2)

TinyOS: Implement the PMU code generator in TinyOS Modify the drivers for the CC1000 radio Write drivers for reading/writing from PMU

AVRORA: Hardware platform simulator:

• Atmel MCU (cycle accurate)• SPI buses• Analog/Digital converters

AVRORA estimates energy consumption on the platform

Use XPower numbers for power-consumption of PMU

Page 31: A Low-Power Architecture for Sensor Nodes

31

System Level Experiments

Goal: Track the improvement in energy savings for different PMU architectures in single and multi-hop environments. Baseline 1: TinyOS interrupt-driven power

management Baseline 2: Periodic power management Experiment 1: Periodic power management + PMU1 Experiment 2: Periodic power management + PMU3

Status: Experiment 1: May be run


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