JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2015.15.2.194 ISSN(Online) 2233-4866

Manuscript received Sep. 14, 2014; accepted Jan. 13, 2015 1 School of Information and Electronics, Beijing Institute of Technology 2 Institute of China Electronic Equipment System Engineering Company E-mail : zhoubo07@bit.edu.cn

A Low-Power Low-Complexity Transmitter for FM-UWB Systems

Bo Zhou1 and Jingchao Wang2

Abstract—A frequency modulated ultra-wideband (FM-UWB) transmitter with a high-robust relaxation oscillator for subcarrier generation and a dual-path Ring VCO for RF FM is proposed, featuring low power and low complexity. A prototype 3.65-4.25 GHz FM-UWB transceiver employing the presented transmitter is fabricated in 0.18 μm CMOS for short-range wireless data transmission. Experimental results show a bit error rate (BER) of 10−6 at a data rate of 12.5 kb/s with a communication distance of 60 cm is achieved and the power dissipation of 4.3 mW for the proposed transmitter is observed from a 1.8 V supply. Index Terms—FM-UWB, transceiver, transmitter, relaxation oscillator, ring VCO, low power

I. INTRODUCTION

Ultra-wideband (UWB) transceivers have shown promising features for short-range and low-data-rate wireless data transmissions due to high power efficiency, good coexistence, high range resolution, low radiated power, high penetration capability, low hardware complexity and good interference resilience [1-4]. Especially, low electromagnetic radiation less than –41.3dBm/MHz is safe for human tissue exposure and suitable for hospital and home applications. Hence, the UWB technology has been considered a good candidate

for wireless personal area network (WPAN) and wireless body area network (WBAN) applications [3, 4].

The frequency modulated UWB (FM-UWB) system generates a constant-envelope UWB signal with wideband frequency modulation (FM), featuring a flat in-band power spectral density (PSD) and a steep spectral roll off to enable a well-defined RF bandwidth [4-14]. Fig. 1 shows the block diagram of conventional FM-UWB transceivers. The FM-UWB transmitter employs a dual frequency modulation technique: FSK-modulated triangular subcarrier generation where triangular frequency f1 represents data 0 and f2 represents data 1; followed by RF FM for UWB signal generation by using an RF voltage-controlled oscillator (VCO) with carrier frequency fC calibrated. Accordingly, the FM-UWB receiver employs a dual frequency demodulation method: the UWB FM signal is demodulated by a delay-multiplication technique to recover the triangular subcarrier; followed by a down-conversion based subcarrier processor (SCP) and a digital FSK

Fig. 1. Block diagram of conventional FM-UWB transceivers.

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demodulator to reconstruct the transmitted data. The FM-UWB receiver can perform FM demodulation without a local oscillator (LO) or carrier synchronization, which makes the system simplified [4-6]. Besides, the antenna design of the FM-UWB system is simple because of a well-controlled RF spectrum and avoiding a high peak-to-average transmit power ratio [7].

The existing transceiver prototypes [4, 5] with limited subcarrier modulation index require a four-phase SCP, which complicates the system design and has poor reconfiguration. The existing regenerative receiver [6] and low-complexity transmitter [7] achieve low power consumption but tend to be sensitive to circuit parameter variation or are considered not as robust as the conventional FM-UWB system. The existing receiver [8] with dual band-pass filters (BPFs) is difficult to make the BPF center frequency accurately tuned under wide frequency ranges. The existing transmitter [9] with low power dissipation employs a multi-phase phase-locked loop (PLL) along with a pre-tuned relaxation VCO for subcarrier generation, which increases the hardware cost. The existing transmitters [10, 11] based on direct-digital frequency synthesis (DDFS) encounter limited data rate (DR) or subcarrier frequency deviation (f2 -f1). The existing reconfigurable transmitter [12] aiming for high DR application encounters large subcarrier spurs. The existing transceiver implementation [13] with gated power control is not considered for external wireless communication applications due to lack of RF front-ends. The existing reconfigurable transceiver [14] with simplified receiver design still has high power dissipation due to lack of optimization on the transmitter.

In this paper, we present an FM-UWB transceiver system to verify proposed low-power low-complexity transmitter architecture, which employs a high-robust relaxation oscillator with embedded frequency-synthesis (FS) function for subcarrier generation. This is quite different from the existing works. The paper is organized as follows: Section II proposes the FM-UWB transmitter architecture and presents the FM-UWB transceiver configuration. Section III describes detailed design implementations of the transceiver system. In Section IV, experimental results are shown, followed by conclusions in Section V.

II. ARCHITECTURE

Fig. 2 shows the proposed FM-UWB transmitter architecture and presented FM-UWB transceiver configuration. The transmitter conducts dual frequency modulation: FSK-modulated triangular subcarrier generation based on an FS-embedded high-robust relaxation oscillator where triangular frequency f1 representing data “0” and f2 representing data “1”; followed by RF FM where the triangular amplitude converted to the UWB FM signal by using a dual-path full-differential Ring VCO with fC calibrated by a quasi-continuous buffer-absent frequency-locked loop (FLL). The receiver, consisting of an analog phase-interpolator delay line based FM demodulator, an anti-aliasing filter (AAF), a single-phase SCP and a digital FSK demodulator, conducts dual frequency demodulation: RF FM demodulation followed by low-frequency FSK demodulation.

The presented transceiver has following main features: 1) an FS-embedded high-robust relaxation oscillator for subcarrier generation; 2) a dual-path low-power Ring VCO for RF FM; 3) a quasi-continuous buffer-absent FLL for carrier-frequency (CF) calibration; 4) a phase-interpolation delay line for FM demodulator; 5) a low-complexity single-phase SCP due to high subcarrier modulation index.

Detailed explanation of the receiver with a phase-interpolation based FM demodulator and a low-complexity single-phase SCP, and clarification of the RF front-ends including output amplifier (OA), preamplifier and UWB antenna, can be referred in [13] and [14], respectively. Both the receiver and RF front-ends are

Fig. 2. Proposed FM-UWB transmitter and transceiver.

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presented to verify the transmitter. The on-chip pseudo random bit source (PRBS) with a bit length of 227–1 provides the transmitted data under DR of 12.5 kb/s.

This work focuses on the proposed transmitter architecture, which is different from the existing transmitter configurations [4, 5, 7, 9-14]. From similarity degree, this work is close to [9]. Both have sameness and differences. On the one hand, both employ low-power Ring VCO replace of high-power LC VCO for RF FM and use a quasi-continuous FLL for fC calibration, considering the phase noise requirement of the RF VCO is not stringent for FM-UWB systems. On the other hand, both are fully different in subcarrier generation. In [9], a fast-settling multi-phase PLL along with a pre-tuned relaxation VCO is employed to generate triangular subcarrier. However in this work, a high-robust relaxation oscillator, with switched-capacitor (SC) array and SC-based voltage-to-current (V-to-I) conversion under two-phase non-overlapping clock, has embedded FS feature and thus is used for subcarrier generation. As a result, the proposed transmitter features low power and low complexity when compared to the existing works.

III. IMPLEMENTATION

1. Proposed FM-UWB Transmitter

Fig. 3 shows the proposed subcarrier generation based on a high-robust relaxation oscillator with embedded FS function. The SC array (C or C+ΔC) is charged and discharged by the current mirrors M11-14 and the switches M1-2, all these together with M4-5 form the oscillation cell. The replica cell comprised of M3, M6, M10, M15 and an operational amplifier Y2, controls the effective load resistances of M4-5 to have the constant voltage swing between 0 and VSW at nodes A and B. This inversely sets the fixed voltage swing between VT+∆ and VSW+VT at nodes X and Y. Here VT and ∆ are the threshold voltage and the minimum saturation voltage of M1-2, respectively. Y1 and Y2 employ fold-cascode architecture with capacitors CC1-2 for frequency compensation within respective negative-feedback loops. Strict match design between the oscillation and replica cells is required and the operation principle could be referenced in [15].

The charge-discharge current is generated by a V-to-I

converter consisting of M7, an equivalent resistor and an operational amplifier Y1. The equivalent resistor is implemented by a SC module comprised of the capacitor CREF and switch transistors S1-2, controlled by a two-phase non-overlapping clock with the frequency FREF. Large bypass capacitor CF3 and low-passed filters (LPFs) consisting of RF1-2 and CF1-2 with low cut-off frequencies are employed to suppress the switching ripple caused by the clock. To get differential triangular waveforms, operational amplifiers Y3-4 having class-AB output stage and shunt-shunt feedback configuration are designed with peak-to-peak voltage output of -0.9-0.9 V.

When the SC array is digitally tuned by the transmitted data, the oscillation frequency is digitally reconfigured and the proposed architecture thus performs FS function with low complexity and low power. That is, FSK-modulated triangular subcarrier generation is achieved. Given the size ratio K between M11-12 and M8, the oscillation frequencies f1 and f2 controlled by the transmitted data are depicted in Eqs. (1) and (2), respectively. Considering strict match design among the cascode current mirrors and the MIM capacitors (C, ΔC and CREF), with VREF and VSW provided by an external supply and FREF generated by an external crystal oscillator, when ∆ is enough small in comparison to VSW, both f1 and f2 have high robustness over process, voltage and temperature (PVT) variations.

1 2 2REF REF REF REF

REF REFSW SW

V C V CK Kf F FV C C V C C

= »- D + D + D

(1)

Fig. 3. Proposed subcarrier generation with FS-embedded high-robust relaxation oscillator.

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2 2 2REF REF REF REF

REF REFSW SW

V C V CK Kf F FV C V C

= »- D

(2) In this design, VREF, VSW and VCM are set to 0.6 V,

0.6 V and 0.9 V by an external supply, respectively. The external reference clock FREF is 1MHz and the current-mirror ratio K is fixed to 20. CREF=87Cunit=8.7 pF, C=64Cunit=6.4 pF and ΔC=4Cunit=0.4 pF under typical case, respectively. VSW is slightly tuned to offset the inverse and minor effect of Δ. As a result, the subcarrier frequencies 12.8 and 13.6 MHz are generated with high robustness over PVT variations. The proposed subcarrier generation consumes 0.5 mW from a 1.8 V supply.

Fig. 4 shows the proposed dual-path full-differential Ring VCO for RF FM, which consists of a V-to-I converter, a replica cell, an oscillation cell and an output buffer. The presented Ring VCO in function is similar to an RC oscillator with slow charging and fast discharging feature, whose oscillation frequency is inversely proportional to the time-constant RC. Here R and C are the equivalent resistance and parasitic capacitor at node A (or B), respectively. By changing the equivalent R by control voltages, the oscillation frequency is tuned. The transistors M5-10 with linear working region are employed to implement the equivalent R, which have fixed voltage drop and tuned through current. Control voltages, by modifying the through current, tune the equivalent R of M5-10 and thus the oscillation frequency. That is actually the operation principle of the proposed Ring VCOs.

The negative feedback loop embedded in the replica cell and the strict match design between the oscillation cell and the replica cell, ensure the output swing of the oscillation cell is clamped between VDD and VREF and set the voltage drop of VDD-VREF across M5-10. With the current through M5-10 modified by the control voltages VM and VC via a dual-path V-to-I convertor, the oscillation (carrier) frequency depicted in Eq. (3) is tuned. The Ring VCO has two tuning paths: VM for frequency modulation path; and VC for fC calibration path with the FLL. To achieve 600 MHz RF bandwidth, the modulation VCO gain of 330 MHz/V is required. To cover fC deviation of ±10% under PVT variations, the calibration VCO gain of 440 MHz/V is designed. In this work, VREF is set to 1.2 V and the center frequency fC0 is

fixed to 3.97 GHz. The proposed Ring VCO consumes 3.2 mW from a 1.8 V supply.

0CM

C CDD REF M DD REF C

VVf fC V V R C V V R

- µ +- -（ ） （ ）

(3) In order to solve the undesired fC shift of the Ring

VCO due to PVT variations, a quasi-continuous low-speed FLL shown in Fig. 5 is introduced with the operation principle clarified in [12, 13]. The FLL compares the divided CF by 64 with the reference frequency FCAL in a frequency detector (FD) with a calibration word NCAL, whose outputs make the control word of a bidirectional counter (CNT) self-add or self-subtract by 1. The 8-bit digital control word is sent to a single-loop (SL) delta-sigma (Δ-Σ) modulator (DSM) based digital-to-analog converter (DAC) with low cut-off

Fig. 4. Proposed dual-path Ring VCO for RF FM.

Fig. 5. Proposed quasi-continuous FLL for fC calibration.

198 BO ZHOU et al : A LOW-POWER LOW-COMPLEXITY TRANSMITTER FOR FM-UWB SYSTEMS

frequency and then converted to an analog differential voltage VC for fC calibration. Considering the high-speed current-mode-logic (CML) divider-by-8 is power starving, a 10% gating mechanism (quasi-continuous operation) is applied to save the system power without affecting the calibration function [12, 13]. With quasi-continuous FLL, the carrier frequency of the UWB signal is calibrated with 0.6 mW power dissipation from a 1.8 V supply and conforms to Eq. (4).

64 1 64 64 1CAL CAL C CAL CAL CAL CALN f f N f N f- £ » £ +（ ） （ ）

(4) In [12, 13], an additional analog buffer is added

between the DAC and VCO to avoid the kickback noise from the varactors of LC VCO. However in this work, since the DAC outputs are sent to a CMOS input-pair of Ring VCO, there is not kickback noise and thus additional buffer is absent. In this design, FCAL=1 MHz, NCAL=62, the DSM clock FCK=40 MHz, the gating clock of 2 kHz has a duty cycle of 10% and the loop cut-off frequency is set to 300 Hz. Hence fC is set to 3.97GHz in theory. However, considering the FD is asynchronous logic which causes the maximum counting deviation of 1 from NCAL, fC thus has the maximum shift of 64 MHz from 3.97 GHz.

2. RF Front-Ends and Used Package Model

The RF front-ends including OA, preamplifier and UWB bowtie antenna have been clarified in [14]. Fig. 6 shows the schematics of OA and preamplifier. The OA with two-stage pseudo-differential cascode architecture has −14 dBm output power for 600 MHz RF bandwidth. The active-balun embedded preamplifier is designed with an average power gain of 25 dB and a noise figure (NF) of 6 dB. The receiver front-end is set to −60 dBm sensitivity for a communication range within 60cm. The designed UWB antenna based on FR4-type printed circuit board (PCB) employs radial planar bowtie architecture and achieves the frequency range of 3-5 GHz, average gain of 1.5 dB and voltage standing wave ratio (VSWR) of −13 dB.

For RF front-ends, parasitic parameters introduced by bonding, packaging and soldering cause non-neglected effects on RF performances, and need to be considered in

design. Thus a package model, shown in Fig. 6 and considering bonding wire, electrostatic discharge (ESD) protection and PCB soldering, is applied to the OA and preamplifier designs. Here μ0, ρ, l and r are permeability, resistivity, length and radius of bonding wires, respectively, and f is the frequency range of the UWB signal. The model parameters are strongly related to a certain chip fabrication and package process. For our case, the bonding wire material is aluminum with l=3 mm, r=12.5 μm and f=3.65-4.25 GHz. Under 180nm CMOS, the OA output does not need ESD protection but the preamplifier input does, which makes the corresponding model parameters different.

3. FM-UWB Receiver

The receiver based on a phase-interpolation based FM

demodulator and a low-complexity single-phase SCP has been declared in [13]. Fig. 7 presents the receiver circuit consisting of a FM demodulator, an AAF, a down-converter with a triangular local oscillator (LO), a LPF with on-chip time-constant calibration, and a comparator (hard limiter).

The FM demodulator with an RF pre-gain stage has a demodulation sensitivity of −35 dBm. Delay switches based on a V-to-I converter and CML amplifiers have an effective duty cycle D controlled by an external voltage, setting the equivalent and configurable delay depicted in Eq. (5). The required delay τ for the given fC of 3.97 GHz is 189 ps. Here, the fixed delay τ1=160 ps and the variable delay τ2=60 ps. As a result, a delay range of 160~220 ps is covered and ±16% tuning range of fC is ensured.

Fig. 6. Presented RF front-ends and used package model.

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1 1 2 1 23(1 )( ) (1 )

4 CD D D

ft t t t t t= + - + = + - = (5)

The AAF is based on a 4th-order Butterworth active

RC architecture with the cut-off frequency of 26.4 MHz. The recovered subcarrier signal with effective frequency components of 12.8 and 13.6 MHz, after filtered by the AAF, is down converted to 0 Hz (data “0”) and 800 kHz (data “1”) signals by the sequent down converter based on a Gilbert multiplier. The 12.8 MHz triangular LO employs the architecture shown in Fig. 3 with the SC array always on. After subcarrier down-conversion, a LPF and a sequent comparator reconstruct the digital FSK signal. The LPF employs 5th-order –1 dB-ripple Chebyshev active RC architecture with the cut-off frequency of 900 kHz and on-chip time-constant calibration logic [13].

For the reconstructed digital FSK signal, under DR of 12.5kb/s, the series of 64 (800/12.5) square waveforms represent data “1”, and zero or a few square waveforms represent data “0” during each bit period. That is easy for the sequent digital 2-FSK demodulator implemented in a

field programmable gate array (FPGA) to make distinctions between “0” and “1”.

IV. EXPERIMENTAL RESULTS

A prototype low-DR FM-UWB transceiver employing the proposed transmitter architecture is fabricated in 0.18 μm CMOS. Fig. 8 shows the transceiver chip micrograph with an active core area of 1.7 mm2, in which the transmitter only occupies 0.5 mm2. The transmitter, receiver and RF front-ends have the power dissipation of 4.3 mW, 11.2 mW and 3.2 mW from a 1.8 V supply, respectively.

Fig. 9 shows the transceiver test bench for short-range wireless data transmission. Two same test boards with the presented transceiver chips and digital configuration words provided by Winbond 8051 are used as the transmitting and receiving stations, respectively. Both the digital FSK demodulator and bit error rate (BER) arithmetic are implemented in the FPGA. The measured spectra and transient waveforms can be observed using Agilent and Tektronix instruments.

The FS-embedded high-robust relaxation oscillator centered at 13.2 MHz generates triangular waveforms

Fig. 7. Presented FM-UWB receiver with phase-interpolation based FM demodulator and single-phase subcarrier processor.

Fig. 8. Transceiver chip micrograph.

Fig. 9. Transceiver test bench for wireless data transmission.

200 BO ZHOU et al : A LOW-POWER LOW-COMPLEXITY TRANSMITTER FOR FM-UWB SYSTEMS

with 1% amplitude distortion and achieves the simulated phase noise of –108 dBc/Hz at 1 MHz offset frequency. Fig. 10 shows the measured UWB spectra with different fC setting, showing that the carrier frequency is effectively controlled by the FLL with quasi-continuous operation. For the given FCAL of 1 MHz, the 1-bit LSB change in the control word NCAL causes the frequency band shift of about 64 MHz as expected. The Ring VCO has the total tuning range of 3.55-4.35 GHz with the simulated phase noise of –82 dBc/Hz at 1 MHz offset frequency.

Fig. 11 shows the measured receiver FSK and recovered data with comparison to the transmitted data. The FSK signal simply follows the PRBS data pattern, the series of 64 square waveforms representing data “1”, and zero or a few square waveforms representing data “0” for each bit period with DR of 12.5 kb/s. The result shows that the transceiver successfully conducts wireless

data transmission with a delay of two bit periods. The measured BER of 10−6 is achieved with a wireless communication distance of 60 cm.

The performance of the presented transmitter is summarized and compared to the existing designs in Table 1. The proposed architecture achieves good trade-off between design complexity, power dissipation and phase noise. With advanced process such as 65nm CMOS, the chip area and power dissipation of the transmitter could be further optimized.

V. CONCLUSIONS

An 3.65-4.25 GHz FM-UWB transceiver is fabricated in 0.18 μm CMOS with the proposed low-power low-complexity transmitter architecture, which employs a FS-embedded high-robust relaxation oscillator for subcarrier generation and a dual-path Ring VCO for RF FM with fC calibrated by a quasi-continuous buffer-absent FLL. The experimental results verify that the presented transceiver conducts short-range low-DR wireless data transmission well with a BER of 10−6 at a distance of 60 cm. The proposed transmitter achieves a low power dissipation of 4.3 mW from a 1.8 V supply, excluding the OA.

ACKNOWLEDGMENTS

This work is supported by the National Natural Science Foundation of China (61306037), Beijing Natural Science Foundation (4153063), Basic Research Foundation of Beijing Institute of Technology (20130542009), and the China Scholarship Council (201406035016).

Fig. 10. Measured UWB spectra with different fC setting.

Fig. 11. Measured receiver FSK and recovered data vs. transmitted data.

Table 1. Transmitter performance summary and comparison

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Bo Zhou received the B.S. degree from Hunan University, Changsha, China, in 2002, and the M.S. degree in Shanghai Jiaotong University, Shanghai, China, in 2005, and the Ph.D. degree in Tsinghua University, Beijing, China, in 2012, respectively.

In 2005, he joined STMicroelectronics Co. Ltd., Shanghai, China, and worked on car-body electronic power design. In 2007, he joined Agere System Co. Ltd., Shanghai, China, and worked on magnetic head read-write channel design. In 2012, he joined the faculty of the School of Information and Electronics at Beijing Institute of Technology. His research interests cover delta-sigma PLLs, fully-digital transmitter, polar transmitter and frequency-modulated ultra-wideband transceivers.

Jingchao Wang received the B.S. degree from Tsinghua University, Beijing, China, in 2004, and the M.S. degree in Tsinghua University, Beijing, China, in 2006, and the Ph.D. degree in Tsinghua University, Beijing, China, in 2010, respectively. His research

interests cover fully-digital transmitter, polar transmitter and mobile communication baseband transceivers.