89
A MAXIMUM POWER POINT TRACKING TECHNIQUE
FOR SINGLE-PHASE PHOTOVOLTAIC SYSTEMS WITH
REDUCED DC-LINK CAPACITOR
A Thesis
Presented to
the Faculty of the Department of Electrical and Computer Engineering
University of Houston
In Partial Fulfillment
of the Requirements for the Degree
Master of Science
in Electrical Engineering
by
Sindhu Krishna Yarlagadda
December 2012
A MAXIMUM POWER POINT TRACKING TECHNIQUE
FOR SINGLE-PHASE PHOTOVOLTAIC SYSTEMS WITH
REDUCED DC-LINK CAPACITOR
Sindhu Krishna Yarlagadda
Approved:
Chair of the CommitteeDr. Wajiha Shireen,Professor,Electrical and Computer Engineering,Engineering Technology
Committee Members:
Dr. Yuhua Chen,Associate Professor,Electrical and Computer Engineering
Dr. Robert Provence,Aerospace Engineer,NASA, Johnson Space Center
Dr. Suresh K. Khator,Associate Dean,Cullen College of Engineering
Dr. Badri Roysam,Professor and Chair,Electrical and Computer Engineering
Acknowledgements
I owe my deepest gratitude to my advisor, Dr. Wajiha Shireen, for her sup-
port, guidance and encouragement throughout the course of this work. I would
also like to thank my committee members, Dr. Yuhua Chen and Dr. Robert
Provence, for serving on my thesis committee. My special gratitude is due to
Preetham Goli for his valuable suggestions and moral support.
iv
A MAXIMUM POWER POINT TRACKING TECHNIQUE
FOR SINGLE-PHASE PHOTOVOLTAIC SYSTEMS WITH
REDUCED DC-LINK CAPACITOR
An Abstract
of a
Thesis
Presented to
the Faculty of the Department of Electrical and Computer Engineering
University of Houston
In Partial Fulfillment
of the Requirements for the Degree
Master of Science
in Electrical Engineering
by
Sindhu Krishna Yarlagadda
December 2012
Abstract
Electrolytic capacitors used in photovoltaic (PV) power conditioning units
(PCU) for power decoupling purposes are less reliable in nature. Film capacitors
can be adopted instead of electrolytic capacitors if the energy storage require-
ment of the PCU is reduced, since they offer better reliability and have a longer
lifetime. The energy storage capacitor size reduction is facilitated by allowing
DC-link voltage to have a specified amount of ripple. However, a high DC-link
voltage ripple imposes a double-line frequency ripple in the PV panel voltage
and current. This leads to oscillations in the extracted panel power and thereby
results in power loss. In view of this, this thesis develops a locus line based
maximum power point tracking (MPPT) control algorithm to mitigate this power
loss. The proposed digital control algorithm was simulated in MATLAB Simulink
and implemented in a laboratory prototype using the Digital Signal Processing
(DSP)-based microcontroller, TMS320F28035.
vi
Table of Contents
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Chapter 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Photovoltaic (PV) Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Electrical Equivalent of a Photovoltaic (PV) cell . . . . . . . . . . 2
1.3 Maximum Power Point (MPP) . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Power Conditioning Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.1 Single-Stage PCU . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.2 Two-Stage PCU . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Components of the PCU . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5.1 DC-DC Boost Converter . . . . . . . . . . . . . . . . . . . . . . 7
1.5.2 DC-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.3 Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8 Thesis Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 2 DC-LINK CAPACITOR SIZE REDUCTION . . . . . . . . . . . . . 13
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Failures in Electrolytic Capacitors . . . . . . . . . . . . . . . . . . . . . 14
2.4 DC-Link Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Fluctuations in PV Output Power . . . . . . . . . . . . . . . . . 15
2.4.2 DC-Link Energy Unbalance . . . . . . . . . . . . . . . . . . . . 17
vii
2.5 Effect of DC-Link Voltage Ripple on the PV System . . . . . . . . . . 21
2.6 Methods Addressing DC-Link Voltage Ripple . . . . . . . . . . . . . 23
2.6.1 Active Filter Approach . . . . . . . . . . . . . . . . . . . . . . . 23
2.6.2 Ripple Reduction Control . . . . . . . . . . . . . . . . . . . . . 24
Chapter 3 PROPOSED METHOD . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 MPPT Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Perturb and Observe Method . . . . . . . . . . . . . . . . . . . 27
3.2.2 Incremental Conductance Method . . . . . . . . . . . . . . . . 28
3.2.3 Load Voltage and Load Current Maximization . . . . . . . . . 29
3.2.4 Fractional Open Circuit Voltage (VOC) and Fractional Short
Circuit Current (Isc) . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.5 dP/dI or dP/dV . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 MPP Locus Line Techniques . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.1 Analytical Proof of MPP Locus . . . . . . . . . . . . . . . . . . 32
3.3.2 Approximations of MPP locus methods . . . . . . . . . . . . . 34
3.3.3 Other Methods based on the MPP Locus Line . . . . . . . . . 34
3.4 Principle of the Proposed Method . . . . . . . . . . . . . . . . . . . . 36
3.4.1 Nature of the Control Scheme . . . . . . . . . . . . . . . . . . . 38
3.5 MPP Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5.1 Step Increment in the Irradiance . . . . . . . . . . . . . . . . . 40
3.5.2 Step Decrement in the Irradiance . . . . . . . . . . . . . . . . . 41
3.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6.1 Determination of Duty Cycle . . . . . . . . . . . . . . . . . . . 42
3.7 Functional Evaluation of the Proposed Method . . . . . . . . . . . . . 43
3.7.1 Duty Cycle with PV voltage ripple . . . . . . . . . . . . . . . . 44
3.7.2 Duty Cycle without PV voltage ripple . . . . . . . . . . . . . . 46
viii
3.8 Ripple Compensation by the Proposed Method . . . . . . . . . . . . . 46
Chapter 4 SIMULATION RESULTS . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.1 Case 1 - Large Capacitance Design . . . . . . . . . . . . . . . . 53
4.2.2 Case 2- Reduced Capacitance Design . . . . . . . . . . . . . . 54
Chapter 5 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . 59
5.1 Use of DSP Micro-controllers for PCUs . . . . . . . . . . . . . . . . . 59
5.2 TMS320F28035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3 Development Platform-Code Composer Studio (CCS) . . . . . . . . . 61
5.4 TI’s Solar Explorer Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.4.1 Power Stages on the Kit . . . . . . . . . . . . . . . . . . . . . . 63
5.5 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.6 Discussions Based on Experimental Results . . . . . . . . . . . . . . . 65
5.6.1 Case 1- Large Capacitance Design . . . . . . . . . . . . . . . . 65
5.6.2 Case 2 - Reduced Capacitance Design . . . . . . . . . . . . . . 67
Chapter 6 CONCLUSIONS AND FUTURE WORK . . . . . . . . . . . . . . . 70
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ix
List of Figures
Figure 1.1 Electrical equivalent of single PV cell . . . . . . . . . . . . . . . . 2
Figure 1.2 (a) Short Circuit Current Condition (b) Open Circuit Voltage
Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 1.3 Electrical Equivalent Model of PV panel . . . . . . . . . . . . . . 4
Figure 1.4 I-V Curves at different sun conditions . . . . . . . . . . . . . . . . 4
Figure 1.5 (a) I-V Curve at 0.8 sun (b) P-V Curve at 0.8 sun . . . . . . . . . . 5
Figure 1.6 (a) Single-stage PCU (b) Two-stage PCU . . . . . . . . . . . . . . . 6
Figure 1.7 Block Diagram of Two-Stage PV PCU . . . . . . . . . . . . . . . . 7
Figure 1.8 DC-DC boost converter . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.9 Single-phase inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2.1 Typical Single-phase Inverter topology . . . . . . . . . . . . . . . 17
Figure 2.2 Inverter Output power . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2.3 PV system Power balance . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2.4 Single-phase inverter with DC-link capacitor . . . . . . . . . . . . 19
Figure 2.5 PV array voltage ripple and Power oscillations . . . . . . . . . . . 22
Figure 2.6 Block Diagram of Ripple Reduction Control . . . . . . . . . . . . 25
Figure 3.1 Power vs Voltage curve showing MPP at(
dPdV
)
= 0 . . . . . . . . 28
Figure 3.2 Different load types 1: Voltage source, 2: Resistive, 3: Combina-
tion of all three and 4: Current source . . . . . . . . . . . . . . . . 30
Figure 3.3 I-V characteristics showing the MPP Locus line . . . . . . . . . . 31
Figure 3.4 Electrical Equivalent Model of PV Array . . . . . . . . . . . . . . 32
Figure 3.5 Effectiveness of MPP Locus Line Expression for different values
of Rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 3.6 PV battery charging scheme with PI Control . . . . . . . . . . . . 36
Figure 3.7 PV panel characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 3.8 Load at the terminals of PV panel . . . . . . . . . . . . . . . . . . 38
x
Figure 3.9 I-V curves with actual and controlled load line . . . . . . . . . . . 39
Figure 3.10 MPPT convergence for a postive change in irradiance . . . . . . . 40
Figure 3.11 MPPT convergence for a negative change in irradiance . . . . . . 42
Figure 3.12 Flowchart of the proposed method . . . . . . . . . . . . . . . . . . 44
Figure 4.1 Circuit Diagram of the proposed system . . . . . . . . . . . . . . 48
Figure 4.2 I-V Characteristics of the simulated PV panel . . . . . . . . . . . . 50
Figure 4.3 Proposed System Implementation in Simulink . . . . . . . . . . . 52
Figure 4.4 IncCond Method for Case 1: Transient response for step change
in irradiance from 0.5 → 1 sun . . . . . . . . . . . . . . . . . . . . 54
Figure 4.5 Proposed Method for Case 1: Transient response for step change
in irradiance from 0.5 → 1 sun . . . . . . . . . . . . . . . . . . . . 55
Figure 4.6 IncCond Method for Case 2: Transient response for step change
in irradiance from 0.5 → 1 sun . . . . . . . . . . . . . . . . . . . . 56
Figure 4.7 Proposed Method for Case 2: Transient response for step change
in irradiance from 0.5 → 1 sun . . . . . . . . . . . . . . . . . . . . 57
Figure 5.1 Solar Explorer Kit Overview . . . . . . . . . . . . . . . . . . . . . 62
Figure 5.2 Detailed layout of Solar Explorer Kit . . . . . . . . . . . . . . . . . 63
Figure 5.3 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 5.4 IncCond for Case 1 : PV panel voltage, current and power wave-
forms for a Step Change in Irradiance . . . . . . . . . . . . . . . . 66
Figure 5.5 Proposed Method for Case 1 : PV panel voltage, current and
power waveforms for a Step Change in Irradiance . . . . . . . . . 67
Figure 5.6 InCond for Case 2 : Inverter Output voltage, PV panel voltage,
current and power waveforms . . . . . . . . . . . . . . . . . . . . 68
Figure 5.7 Proposed Method for Case 2 : Inverter Output voltage, PV panel
voltage, current and power waveforms . . . . . . . . . . . . . . . 69
xi
List of Tables
Table 4.1 Photovoltaic Panel Specifications . . . . . . . . . . . . . . . . . . . 49
Table 4.2 Power Condition Unit Specifications . . . . . . . . . . . . . . . . . 50
Table 4.3 PV Power Extracted by Proposed method and IncCond method
for Reduced Capacitor case . . . . . . . . . . . . . . . . . . . . . . . 58
xii
CHAPTER 1 INTRODUCTION
This chapter introduces photovoltaic (PV) power generation systems. The
characteristics of the PV panels and modeling of the PV cell are discussed. The
principles of PV energy conversion with power conditioning unit are described.
The chapter concludes with the aims of the research project, discusses its motiva-
tion and describes the structure of the thesis.
1.1 Photovoltaic (PV) Cell
Photovoltaic cells convert the sunlight into electricity directly [1]. Two cate-
gories of PV cells are used in most of today’s commercial PV modules: crystalline
silicon and thin film.
The crystalline silicon category, called first-generation PV, includes mono-
crystalline and multi-crystalline PV cells, which are the most efficient of the
mainstream PV technologies. These cells produce electricity via crystalline sil-
icon semiconductor material derived from highly refined polysilicon feedstock.
Monocrystalline cells, made of single silicon crystals, are more efficient than mul-
ticrystalline cells but are more expensive to manufacture [2].
The thin-film category, called second-generation PV, includes PV cells that
produce electricity via extremely thin layers of semiconductor material made of
amorphous silicon (a-Si), copper indium diselenide (CIS), copper indium gallium
diselenide (CIGS), or cadmium telluride (CdTe).
1
1.2 The Electrical Equivalent of a Photovoltaic (PV)
cell
A single PV cell can be represented by a current source in parallel with a
diode, a series resistance, and a shunt leakage resistance as shown in Fig. 1.1.
The photo-generated current (Ig) is proportional to the solar insolation to which
it is exposed.
RS
RSHIgVPV
+
-
IPV
VD
+
-
ID
ISH
Figure 1.1: Electrical equivalent of single PV cell
The short-circuit current and the open-circuit voltage are the two important
parameters used to characterize the performance of a PV cell. The short-circuit
current or photo-generated current (Ig) is the current that flows when the leads
of the PV cell are short-circuited as shown in Fig. 1.2(a). The voltage across the
PV cell when the terminals are left open is called the open-circuit voltage (VOC).
This is shown in Fig. 1.2(b).
It can be seen from Fig. 1.1, that the PV cell current, IPV , is given by
IPV = Ig − ID − ISH , (1.1)
where ID is the diode current.
2
PV
I = ISC V = 0
V = VOC PV
I = 0
(a) (b)
Ig
(a) (b)
Figure 1.2: (a) Short Circuit Current Condition (b) Open Circuit Voltage Condition
The Shockley equation for diode current is known to be
ID = Isat ·
[
exp
(
VD
nVT
)
− 1
]
, (1.2)
where
Isat = C · T3e−
EgVT is the cell reverse saturation current in Amps
n is the ideality factor
C is a suitable constant in Ampere/ deg K−3
Eg is the energy gap of silicon in electron − Volts
VT = kT/q is the thermal voltage in Volts
k is the Boltzmann’s constant in eV/K
q is the electron charge in Coulombs
T is the junction temperature in Kelvins
The voltage across the diode, VD from Fig. 1.1 is
VD = VPV + RS · IPV . (1.3)
The current through the shunt resistance, (ISH) is given by
ISH =VPV + RS · IPV
RSH. (1.4)
3
Hence Eqn. (1.1) becomes
IPV = Ig − Isat ·
e
VPV + RS · IPV
(nVT) − 1
−
VPV + RS · IPV
RSH. (1.5)
A typical PV panel consists of a number of PV cells connected in series. From
the single PV cell model, a PV panel having N cells can be modeled as shown in
the Fig. 1.3.
N.RS
N.RSHIgVPV
+
-
D1
D2
DN
IPVISH
ID
Figure 1.3: Electrical Equivalent Model of PV panel
At different sun conditions, the short-circuit current Ig varies, which gives
different I-V curves for different solar irradiation conditions. Fig. 1.4 shows the I-
V curve at different irradiation conditions of sun. The maximum solar irradiation
1000 W/m2, the sun condition is said to be 1.0 sun.
0 4.4 8.8 13.2 17.6 21.40
0.6
1.2
1.8
2.4
3.0
Voltage (V)
Curr
ent
(A)
0.9 sun
1 sun
0.7 sun
0.8 sun
0.5 sun
0.6 sun
0.1 sun
0.2 sun0.3 sun
0.4 sun
Figure 1.4: I-V Curves at different sun conditions
4
1.3 Maximum Power Point (MPP)
If the output power is plotted with the output voltage for a given sun con-
dition, a particular combination of voltage and current results in the maximum
power [3]. Fig. 1.5 (a) gives the I-V curve of the panel at 0.8 sun. The correspond-
ing plot of the output power at 0.8 sun is shown in Fig. 1.5 (b).
0 1 4 7 10 13 16 19 220
0.5
1
1.5
2
2.5
Voltage (V)
Curr
ent
(A)
MPP
0.8 sun
(a)
0 3 6 9 12 15 18 210
5
10
15
20
25
30
35
40
45
Voltage (V)
Pow
er
(P
)
MPP0.8 sun
(b)
Figure 1.5: (a) I-V Curve at 0.8 sun (b) P-V Curve at 0.8 sun
It is observed from Fig. 1.5 that the maximum power is 29.18 W. The voltage
corresponding to 29.18 W is 17.1 V. The current corresponding to 17.1 V on the
I-V curve is 1.70 A. Hence, the MPP on the I-V curve is at coordinates (17.1, 1.70).
Observing the location of MPP, it can be inferred that the MPP lies on the knee of
the I-V curve.
1.4 Power Conditioning Unit
Photovoltaics (PV) is one of the emerging solar technologies. As the price of
the PV systems are high, extraction of the maximum available energy is necessary
for early payback. The power conditioning unit converts the DC input power into
5
AC output power and also make the PV system operate at the MPP in order to
maximize the output power.
The PV power conditioning units (PCU) are categorized based on the number
of power stages. The PCU can use a single-stage or a two-stage topology. The
future technology primarily focuses on the two-stage topology, where a DC-DC
converter is connected in between the PV modules and the DC-AC inverter.
1.4.1 Single-Stage PCU
The first generation of the grid-connected PV systems directly connect grid
DC-AC inverter to an PV array as shown in Fig. 1.6 (a). In this configuration,
the inverter is subjected to handle, maximum power point tracking (MPPT), grid
current control and voltage amplification. Although this configuration is simple,
the drawbacks are some drawbacks. One major drawback is that a large number
of PV modules needed to be connected in series to achieve necessary voltage
amplification. In the two-stage configuration, DC-DC converter is connected in
between the PV modules and the DC-AC inverter to provide MPPT and voltage
amplification.
DC
ACPV Panel
Grid
(a)
DC
AC
DC
DCPV Panel
Grid
(b)
Figure 1.6: (a) Single-stage PCU (b) Two-stage PCU
1.4.2 Two-Stage PCU
In order to improve the energy harvesting capabilities and design flexibility,
dedicated converters which perform MPPT for PV panel can be connected in
6
between the PV panel and the inverter as shown in Fig. 1.6 (b). The DC-DC
converter performs MPPT and voltage amplification if necessary. The DC-AC
inverter is then a voltage sourced inverter (VSI) which handles the output current
regulation and DC-link voltage regulation. In this thesis, we focus on the input
capacitance requirement of DC-AC inverter in two-stage PV inverter systems.
1.5 Components of the PCU
In this section the components of a two-stage PCU as shown in Fig. 1.7 are
described.
DC-Link
DC
AC
DC
DC
PV Panel GridMPPT Stage VSI
Figure 1.7: Block Diagram of Two-Stage PV PCU
1.5.1 DC-DC Boost Converter
The role of the DC-DC boost converter is to boost the PV source voltage in
order to extract maximum power from the PV array. Fig. 1.8 shows the circuit
diagram of a DC-DC boost converter.
A DC-DC boost converter consists of an inductor L, a diode D, a controllable
switch Q (a MOSFET or IGBT) , and a filter capacitor C. The switch Q is switched
at a high frequency with a certain duty cycle. During the on-period the voltage
across switch, VSW will be equal to the input DC voltage Vin. When the switch
is OFF the inductor current flows through the diode which makes VSW equal to
7
CVSW
L D
Q
Input Output
Vin Vo
Figure 1.8: DC-DC boost converter
V0. At steady state the average voltage across the inductor must be zero and the
equation will be
Vin · ton + (Vin − Vo) · to f f = 0, (1.6)
where Vin is the input voltage, Vo is the output voltage, ton is the time for which
the switch is ON during one switching period (the ON time) and to f f is the time
for which the switch is OFF during one switching period (the OFF time). Hence,
Eqn. (1.6) can be written as
Vo
Vin=
ton + to f f
to f f, (1.7)
where T = ton + to f f , is the switching period for the switch, and D is the duty
cycle which can be calculated by the ratio of ton and T .
From Eqn. (1.7), it is clear that the output voltage can be boosted by control-
ling the duty cycle of the switch. Thus, a DC-DC boost converter is used to boost
voltage to a level required by the application. However, this voltage is still DC
and most applications require an AC voltage for their operation. Therefore, this
DC voltage levels needs to be converted to an AC voltage using an inverter.
1.5.2 DC-Link
The DC-link in a PCU is an interconnection of single-phase inverter input
port and the boost converter output port. The DC-link comprises of an energy
8
storage component, which decouples the boost converter from the pulsating AC
output power. Single-phase voltage source inverters (VSIs) employ capacitors,
whereas current source inverters (CSIs) use inductors for energy storage purpose.
1.5.3 Inverters
DC-AC converters are called inverters. The function of an inverter is to
change the input DC voltage to an AC output voltage of the desired magnitude
and frequency. Inverters can be three phase or single-phase. The three phase
inverters are mostly used in high power application like, AC motor drives, High
Voltage AC (HVAC) applications, etc. The single-phase inverters are more suited
for low power residential applications. The focus of this thesis is on the single-
phase inverter systems.
S1
S2
S3
S4
Vi
+
-
voa
b
ii
io
Figure 1.9: Single-phase inverter
Fig. 1.9 shows a voltage controlled voltage source single-phase inverter. The
inverter consists of four switches S1, S2, S3 and S4. The switching patterns for
these switches are chosen to produce an AC voltage across the load. To make the
9
system more efficient and to reduce the size of the filter components considerably,
high frequency Pulse Width Modulation (PWM) switching signals are used for
inverter control.
1.6 Literature Review
In a PV system as shown in Fig. 1.7, the DC-link capacitor provides the
necessary power decoupling for single-phase inverter. The electrolytic capacitors
used for power decoupling have high failure rate, the reliability of the PV unit
is adversely affected. High operating temperatures and aging causes these ca-
pacitors to lose their filtering characteristics, thereby increasing the ripple at it
terminals [4].
The idea of employing film capacitors instead of electrolytic type is sug-
gested in [5]. However, film capacitors are large in volume and expensive, which
makes their usage more economical only if the required capacitance for the sys-
tem is significantly reduced. Reduction in the capacitor size will make the unit
highly reliable but this would also result in the increase of double-line frequency
ripple in the DC-link voltage.
The DC-link voltage ripple resulted from the reduction of DC-link capacitor
size causes third harmonic ripples in the AC grid current. Many authors [6–11]
suggested to allow 25% voltage ripple at the DC-link and proposed advanced
closed-loop inverter control methods to minimize the propagation of DC-link rip-
ple to AC side of the inverter.
In a traditional inverter control logic, the sensed DC-link voltage generates
the grid current reference. Therefore a large ripple in the DC-link voltage will
result in a distorted inverter output with low frequency harmonics.
Whereas in one of the new inverter control schemes [11] an estimated DC-
10
link voltage ripple is subtracted from the actual measured voltage and this ripple-
free signal is used to generate the reference current. This approach gives a distor-
tion less grid current.
1.7 Research Motivation
The existing literature [7–11] in terms of DC-link capacitor reduction in
single-phase PV systems, assumes that the PV array voltage is immune to the
large DC-link ripple content. However, a significant amount of the double-line
frequency ripple is imposed in the PV panel current and voltage by the capacitor
reduction. This results in oscillations in the PV output power. In PV applications,
power flow from the panels must be DC. Any variation requires extra operating
headroom and reduces the available average output.
Active filters and ripple port approaches are introduced to reduce the PV
voltage ripple [12,13]. However, these increases the number of components in the
main current path hence reducing reliability and increasing cost. Other methods
try to generate an estimated time varying duty cycle component and added to the
traditional MPPT control duty cycle. However, the control complexity is generally
increased.
Consequently to overcome the stated shortcomings of the reduced DC-link
capacitor power conditioning unit, a different approach with no additional com-
ponents and simplified control scheme is proposed in this research. The control
scheme can be simplified by using a direct duty cycle controlled MPPT technique
which reduces the PV voltage and current ripple.
In this research the state of the art of DC-link capacitor reduction in 1-ph
grid-connected PV systems is investigated. The PV array output power reduction
due to a steady state ripple in the DC-link voltage is minimized.
11
1.8 Thesis Layout
The contents of this thesis have been organized in the following manner:
Chapter 1 provides an introduction about the Photovoltaic (PV) power gen-
eration systems. The characteristics of the PV cells and the electrical equivalent
model of it are described. It also elaborates on the components of the PV power
conditioning unit, like DC-DC boost converter and inverters.
Chapter 2 discuss in greater detail about the necessity of the DC-link capaci-
tor size reduction in PV system. The reasons for failures in electrolytic capacitors
are illustrated. The DC-link capacitor selection criteria and its impact on DC-
link voltage of the PV system operation is discussed. Techniques suggested in
literature to reduce the PV voltage ripple are demonstrated.
Chapter 3 introduces few conventional MPPT techniques. The MPP Locus
Line methods and intricacies involved in it are discussed in detail. The opera-
tional principle of the proposed method and its functionality under large DC-link
voltage ripple is analyzed with mathematical expressions.
Chapter 4 explains the MATLAB Simulink model of the proposed system
used to simulate the control algorithm. Simulation results of the proposed MPPT
method are presented and compared with the Incremental Conductance method.
Chapter 5 discusses the actual hardware implementation. The advantages
of using a DSP micro controller for control of a power conditioning system are
discussed. It also provides specifications of the power conditioning unit used
for experimental tests. Experimental results of the proposed algorithm and the
IncCond method under the test same conditions are shown.
Chapter 6 summarizes the results from the thesis. This chapter also includes
the original contributions of this research and suggestions for future work.
12
CHAPTER 2 DC-LINK CAPACITOR SIZE REDUCTION
This chapter provides a detailed explanation on the role of the DC-link ca-
pacitor in PV power conditioning units (PCU). The problems associated with re-
ducing the capacitor size on the performance of the PV system are discussed.
2.1 Introduction
Voltage source inverters (VSI) are used for grid integration of renewable
sources. These inverters need a large input capacitance to decouple the DC power
from the pulsating AC output power. Electrolytic capacitors are widely used in
VSIs as they offer high capacitance at reasonable cost. Reliability of these elec-
trolytic capacitors is a major concern as they reduce the lifetime of the unit.
With the growing emphasis on reliability and lifetime, many authors are en-
couraging the use of film capacitors in place of electrolytic capacitors. The capac-
itance requirement of the inverters need to be reduced to employ film capacitors
as their cost per unit volume is very high.
2.2 Background
The capacitor size reduction was suggested in the literature for many power
conversion applications like plug-in hybrid electric vehicles (PHEVs), wind en-
ergy units, AC-DC adapters, motor drives and photovoltaic systems.
In reference [14] a reduced DC-link capacitor system was built for an AC-DC
converter, by using a control scheme to overcome the transient voltages and 2nd
harmonic voltage ripple problem.
Authors of [15] proposed a synchronous switching scheme for AC-DC adapters
to reduce the DC-link voltage ripple and enable the use of a film capacitor.
13
An on-board charging circuit for PHEVs is developed in [16] which elimi-
nates the use of large electrolytic capacitors.
In the wind generator power conditioning unit of [17], a DC-link voltage con-
trol loop with a proportional-integral-resonant (PIR) controller is implemented to
reduce the pulsations in the AC power output caused by capacitance reduction.
2.3 Failures in Electrolytic Capacitors
Traditionally in switched mode inverter applications by and large most de-
signers choose electrolytic capacitors for DC-link energy storage. The major ad-
vantage of the lower capacitors is their cost per unit farad. However, these capaci-
tors have high a probability of failure when compared to the other semiconductor
devices used in the converters. Hence, they are major contributors to reduced
life time of the unit. Parameters like temperature, service life and frequency of
electrical quantities will impair the characteristics of the electrolytic capacitors.
Vaporization of electrolyte causes change in some electrical parameters of capac-
itor resulting in wear out.
The Effective Series Resistance (ESR) is utilized to quantify the effect of ex-
ternal factors on the current state of an electrolytic capacitor. ESR is the combined
equivalent resistance of all components like aluminum oxide, electrolyte, spacer
and electrodes. Wear-out of any components would increase the ESR thereby re-
ducing the effective capacitance. ESR is also responsible for the self-heating of
capacitors which in-turn determines the lifetime. Due to high thermal resistivity
of the components the heat dissipation is very low, resulting in high chances of
failure at high temperatures [4].
To employ more reliable type of capacitors, the fundamental function of the
capacitor in a PCU and its selection criteria need to be investigated.
14
2.4 DC-Link Capacitor Selection
In a power conditioning unit, capacitors are used to smooth the DC-link
voltage. The two major factors which influence the DC-link voltage profile of a
PV system are:
1. Fluctuations in PV Output Power.
2. DC-Link Energy Unbalance.
Therefore design of the DC-link capacitor is based on the above two factors.
2.4.1 Fluctuations in PV Output Power
As the PV panel output power constantly fluctuates with the solar irradiance,
the PV maximum power point voltage (VMPP) also varies accordingly. For exam-
ple, in the case of a 40 W BP340 solar panel at full irradiance (1 sun), the MPP
voltage (VMPP) is 17.6 V whereas at 0.5 sun VMPP is 15.3 V. Hence, the average
DC-link voltage which is a function of the PV output power will have fluctua-
tions. The expression for the DC-link voltage fluctuations in terms of fluctuating
PV power from [18] can be written as
∆Vdc, f luct =Tac∆P
CdcVdc, (2.1)
where ∆Vdc, f luct is change in the average value of the DC-link voltage. Cdc, Vdc and
Tac are the DC-link capacitance, voltage and time period of AC-mains respectively.
∆P is the fluctuation in the PV output power.
As shown in Fig. 1.7 , maximum power point tracking is performed by
the boost converter. When there is a change in the irradiance, the maximum
power point tracker (MPPT) slowly sweeps the operating point to the new MPP.
Therefore, perturbation power of the MPPT control algorithm chosen for tracking
would impact the magnitude of these power fluctuations. If an MPPT technique
15
with low perturbation power is chosen then the power fluctuations can be re-
duced.
Alternatively, with a large DC-link capacitor these fluctuations can be min-
imized. It can be seen from Eqn. (2.1) ∆Vdc, f luct is inversely proportional to Cdc.
The DC-link capacitor supplies the instantaneous energy difference caused by the
power fluctuations. But large capacitance designs are undesirable due to relia-
bility issues. Therefore this thesis identifies a need for an alternative solution to
mitigate the PV power fluctuations.
Inverter control algorithms are proposed in literature to overcome the impact
of this PV power fluctuations on the DC-link voltage. In these methods, AC
current injected by the inverter into the grid is regulated to compensate for the
voltage variations. For a positive change in the irradiation on the PV panel the
input power of the inverter would be greater than the output power this increases
the DC-link voltage. The controller senses the DC-link voltage and increases the
injected grid current by adjusting its reference value accordingly. An increase in
the AC output current will reduce the DC-link voltage rise and this stabilizes it
to maintain the power balance.
In more advanced control methods a hysteresis band for DC-link voltage is
defined, which vastly improves the practical stability of the controller [6]. With
the proper implementation of one of these techniques fluctuations in the DC-link
voltage level due to PV panel irradiation variations are eliminated.
Another important criteria for selection of the DC-link capacitor is the steady
state AC ripple in the DC-link voltage due to energy unbalance. This issue is
discussed comprehensively in the next section.
16
DC Source -PV Or
DC-DC ConverterOr
AC-DC Rectifier
1-ϕDC-AC
convertervac(t)
DC-Link
Vdc
iac(t)
P0 pac(t)=P0(1-cos(2t))
Figure 2.1: Typical Single-phase Inverter topology
2.4.2 DC-Link Energy Unbalance
Fig. 2.1 shows that inverter input side DC port is coupled to a DC-DC boost
converter powered by the PV source. The role of the front-end DC-DC converter
in implementing MPP tracking is explained in section 1.4.2 . Inverter output
voltage and current varies sinusoidally with no phase difference especially in
grid-connected case with the help of grid-synchronization and phase-locked loop
(PLL) control.
The power flow in the AC side of the inverter is given by
pac (t) = vac (t)× iac (t) . (2.2)
Sinusoidal voltage and currents are given by
vac (t) = V0 sin (ωt) , (2.3)
iac (t) = I0 sin (ωt − φ) , (2.4)
where I0,V0 are the peak values of the AC current and voltage respectively and φ
is the phase difference between inverter output current and voltage.
By substituting equations (2.3)(2.4) in (2.2) we get
pac (t) =V0 × I0
2(cos (φ)− cos (2ωt − φ)) . (2.5)
17
In grid-connected system the inverter control is designed to achieve unity power
factor i.e, phase difference is close to zero. Then Eqn. 2.5 can be simplified as
pac (t) = P0 − P0 cos (2ωt) , (2.6)
where P0 is the average active power output of the inverter.
O
Pdc(t)
P0
2P0
Figure 2.2: Inverter Output power
In Eqn. (2.6), instantaneous AC power injected into the grid has DC compo-
nent and a double-line frequency time varying component.
From Fig. 2.2, P0 is the average inverter output power which should be
equal to the power from the DC-DC converter or PV source by the law of energy
conservation. Since, the DC-DC converter is at the front end of the inverter,
instantaneous power at the inverter input ports is
pdc (t) = Pdc = P0. (2.7)
Therefore from Equations (2.6) & (2.7) the power unbalance on either side of the
inverter is given by
∆p (t) = pdc (t)− pac (t) = P0 cos (2ωt) . (2.8)
The power difference as in Eqn. (2.8) varies at twice the line-frequency with a
magnitude of ±100% of P0. Therefore, the inverter must provide some means to
supply this time varying power difference for energy conservation. Any energy
18
storing passive component can act as buffering device for this unbalanced power.
0
∆p(t)
P0
0
pdc(t)
P0
O
pac(t)
P0
2P0
+ =
Figure 2.3: PV system Power balance
Traditional approach is to embed an energy storing electrolytic capacitor in
the DC-link as shown in Fig. 2.4. This capacitor stores energy during the first half
cycle of unbalanced power and delivers the stored energy in the next half cycle,
thereby balancing the power flow to the inverter as seen in Fig. 2.2. Therefore,
from Fig. 2.4 the instantaneous power supplied by the capacitor is
pCdc(t) = ∆p (t) = P0 cos (2ωt) . (2.9)
From Eqn. (2.9), with the voltage across the capacitor is constant, current through
it would oscillate in accordance with the unbalanced power. Then the capacitor
DC Source -PV Or
DC-DC Converter
1-ϕDC-AC
convertervac(t)
DC-Link
Vdc
iac(t)
P0 pac(t)=P0(1-cos(2t))
Cdc
ICdc
P0 cos(2t)
Idc +
-
P0(1-cos(2t))
Figure 2.4: Single-phase inverter with DC-link capacitor
19
current is given by
iCdc(t) = ICdc
cos (2ωt) , (2.10)
where ICdc, iCdc
(t) are peak and instantaneous capacitor currents respectively.
The instantaneous voltage across any capacitance is
v (t) =1
C×
∫
iC (t) dt + Vintial. (2.11)
By substituting Eqn. (2.10) in (2.11) we can write
vdc (t) = Vdc + vdcripple (t) = Vdc +1
Cdc×
∫
ICdccos (2ωt) dt. (2.12)
Hence,the expression instantaneous DC-link voltage is
vdc (t) = Vdc + ∆Vdc,ripple sin (2ωt) , (2.13)
where Vdc is average DC-link voltage and Vdc,ripple is peak-peak DC-link voltage
ripple.
From Eqn. (2.13) the derived DC-link voltage has second harmonic voltage
ripple. The magnitude of peak-peak ripple can be obtained from Equations 2.12
and 2.13 as
∆Vdc,ripple =ICdc
2ωCdc=
P0
2ωCdcVdc. (2.14)
The DC-link capacitance required for any amount of voltage ripple can be calcu-
lated by the expression,
Cdc =P0
2ω∆Vdc,rippleVdc. (2.15)
From the above expression, it can be said that if the average DC-link voltage is
increased the capacitance requirement can be reduced. But the capacitance de-
signed for the increased DC-link voltage might not provide the sufficient energy
to meet the PV power balance.
Therefore, an expression for energy storage requirement of the DC-link ca-
pacitance needs to be determined for design purposes. This will demonstrate the
20
role of the capacitor in a more meaningful way. Energy supplied by the capacitor
can be calculated by
Wc =1
2V2
dcCdc =1
2V2
dc ·P0
2ω∆Vdc,rippleVdc
or
Wc =P0
4π f ∆Vdc,ripple%, (2.16)
where
∆Vdc,ripple% =∆Vdc,ripple
Vdc, (2.17)
is the percentage DC-link voltage ripple.
It is evident from Eqn. (2.16) that the energy storage requirement for the
DC-link is directly proportional to the average power and inversely proportional
to percentage DC-link voltage ripple. For example, in a 40 W PV inverter sys-
tem with a DC-link voltage of 30 V, if ±0.5% ripple (0.3 V peak-peak) is allowed
then the capacitor must be capable of storing 5305.16 mJ of energy requiring a
capacitance value of 11789.26 µ F. When ±10% (6 V peak-peak) DC-link voltage
ripple is allowed, energy requirement is only 265.28 mJ and Cdc required is re-
duced by almost 95 % to 589.46 µ F. Similarly for 25 % ripple the capacitance
needed would be around 235.78 µF. Film capacitors can be employed for these
low ratings without any additional cost to the electrolytic capacitor design.
Hence,this thesis will investigate the possibility of reducing the DC-link ca-
pacitance size by allowing the ripple.
2.5 Effect of DC-Link Voltage Ripple on the PV
System
Allowing some DC-link voltage ripple will impose ripple at the PV array
terminals, since instantaneous power at the output and input of the boost con-
21
verter should be the same. Studies have shown that the PV modules are sensitive
to voltage and current ripple. This ripple will not harm the panel cells but the
average power extracted from the panel will be less.
Kajer [19] has stated that instantaneous power oscillates with ripple in the
PV voltage and current. The generated PV output power would have a peak value
of available MPP power. With a high magnitude of the ripple in the PV voltage
and current the average power extracted would be less than the available MPP
power as shown in Fig. 2.5.
0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.210
15
20
25
Vpv
(V
)
0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.225
30
35
P pv (
W)
Time (s)
PMPP
Vavg
Pavg
Figure 2.5: PV array voltage ripple and Power oscillations
The ratio of average power extracted to the maximum available power is
defined as utilization ratio Kpv. This parameter is inversely proportional to the
magnitude of the voltage ripple. The difference of the average power (Pavg) and
PMPP is power loss due to the voltage ripple.
In small capacitance PV system topologies allowing significant amount of
DC-link voltage ripple is inevitable. Therefore, a significant amount of power
loss is witnessed in these designs. The goal of this thesis is to find a solution to
minimize the power loss in PV generation due to PV voltage ripple with reduced
DC-link capacitor. In the next section , other methods proposed in literature
addressing this problem are discussed.
22
2.6 Methods Addressing DC-Link Voltage Ripple
The problem associated with the presence of double-line frequency ripple
in the PV module terminal voltage and currents are explained in the previous
sections. Few solutions are found in the literature addressing issues with DC-link
voltage ripple. A detailed description of different approaches to this problems is
given.
2.6.1 Active Filter Approach
The central idea of this approach is to move out the buffering capacitor from
the main power path. Number of variants of active filters are proposed by the
researchers. An active filtering scheme is implemented for PV topology having
bidirectional double interleaved DC-DC converter [5]. An active clamp circuit
is formed with this additional dump capacitor. This module stores the energy
and then regenerates it back to the DC-link capacitor. This scheme eliminates
the need of a DC-link capacitor in the main power flow path for energy storage.
This active clamp circuit when operated in buck converter mode delivers energy
from dump capacitor to main DC-link capacitor providing a controllable option
to the DC-link voltage. Small DC-link capacitance design is possible with this
technique as the DC-link voltage is controlled by supplying the required energy.
Although this technique solves the problem it requires more advanced circuitry
and involves complicated control schemes for the DC-DC converter which would
raise the price of the unit.
In [20] a current pulsation smoothing parallel active filter (CPSPAF) is pro-
posed to eliminate the low frequency PV current ripple. The active filter part of
the circuit acts as a current source. It generates a current that would make the
average current flowing into the DC-link equal to the PV current. So when the
23
time varying DC-link current is below PV current then the filter circuit behaves
as a boost converter and stores the energy in the filter capacitor. This stored en-
ergy in the filter capacitor is discharged in the interval when DC-link current is
greater than PV current. Since the current drawn from the PV source is constant
the power loss due to the ripple can be eliminated. The filter circuit provides
the necessary energy storage for DC-link power oscillations there by facilitating
the reduction of the capacitor size. This method also has few drawbacks like
additional circuitry and high cost.
In [12] a new type of active filter configuration is proposed where inverter
has additional energy management port along with input DC-port and output
AC-port. With this port the capacitor voltage variation and power oscillations are
directly controlled. That means no control of injected bus current is needed to
maintain required voltage and power variations.
2.6.2 Ripple Reduction Control
In [21] it is stated that if the DC-DC converter supplies only a DC component
Id then the PV current double-line frequency variations can be avoided. This idea
would maintain MPPT efficiency even with double-line frequency ripple on the
DC-link. In this technique the DC-link voltage variation is compensated at the
boost converter in-order to minimize the front end PV current variation. Duty
ratio of the boost converter is modified as
vdc (t)
Vpv=
Vdc + ∆Vdc,ripple sin (2ωt)
Vpv=
1
1 −(
Dmppt + Dvar
) , (2.18)
where Dvar is the current variation cancellation duty ratio and Dmppt is the duty
cycle obtained from the MPPT controller, which is
Dmppt =Vdc − Vpv
Vpv. (2.19)
24
By substituting Eqn. (2.14) and (2.19) in (2.18) Dvar can be written as
Dvar =Vpv
Vdc∆Vdc,ripple sin (2ωt) . (2.20)
Therefore, an estimated value of Dvar containing double-line frequency compo-
MPPT CONTROLLER
Vpv
Ipv
Dmppt
K sin(2ωt)
Vpv
Ipv
Dvar
ΣD
++
Figure 2.6: Block Diagram of Ripple Reduction Control
nent is added to the MPPT duty cycle as shown in Fig. 2.6 to compensate for
the PV current variations. It can be inferred that the presence of double-line fre-
quency component in the duty cycle of the PWM boost converter, the ripple or
variations in the PV current are reduced. Since, PV source is modelled as a current
source the PV voltage profile will follow the current profile. Thus, the PV termi-
nal voltage will not have variations when ripple reduction control is included
to MPPT scheme. Power loss due to ripple is minimized thereby improving the
MPPT efficiency. A similar method is presented in [22] which implements ripple
reduction control duty cycle for boost converter stage but Incremental Conduc-
tance MPPT control is performed at the inverter stage.
These techniques have few drawbacks like a time varying parameter Dvarhas
to be generated by the controller. This would make the control logic highly com-
plex to implement either in an analog or a digital controllers. The average DC-link
voltage (Vdc) required for calculation of Dvar is not constant and any errors in its
approximations can lead to instability or erroneous outcome.
In order to overcome these issues, this thesis proposes a less complex MPPT
technique in which generation of any time varying parameter is not required
25
while implementing the control algorithm in a digital controller. The ripple com-
pensation and power loss reduction are achieved with this method without any
need of additional circuits like active filtering clamping circuits. This control logic
can be applied to a simple one-switch boost converter. Hence, this method im-
proves the reliability of the entire PV unit by limiting the number of switching
devices. A more detailed description of the proposed technique is presented in
the next chapter.
26
CHAPTER 3 PROPOSED METHOD
3.1 Introduction
PV modules have inverse diode characteristics which is non-linear in nature.
Power vs voltage characteristics can be obtained from non-linear current voltage
characteristics. A set of curves can be obtained for different irradiation and tem-
peratures, where maximum of each curve is called maximum power point (MPP)
for that corresponding condition. MPP is tracked by the power conditioning unit
(PCU) which couples the PV array with AC load or the grid. The operating point
of the PV array is the point of intersection of the I-V characteristic curve and the
load line. The closed-loop control PCU trackers, aim to drive the operating point
closer to the maximum power point of the I-V curve at any given condition.
Many MPPT algorithms are suggested in literature, each vary in tracking
efficiency, convergence speed, complexity, number of sensors required and type
of implementation hardware. Few of the popular methods are discussed in the
following sections.
3.2 MPPT Methods
3.2.1 Perturb and Observe Method
The Hill Climbing method requires perturbation in the duty cycle of the
DC-DC converter switch of the PCU. Where as in Perturb and Observation(P&O)
method PV array operating voltage is perturbed continuously [23]. Perturbing the
duty cycle of the DC-DC converter connected to the PV array will in-turn perturb
the array voltage.
From the Power vs Voltage characteristics of a PV array as shown in Fig.
27
MPP dP/dV=0
Figure 3.1: Power vs Voltage curve showing MPP at(
dPdV
)
= 0
3.1 we can say that on the left hand of the curves as the voltage increases power
increases. And on the right side of the curve power decreases with increase in
the voltage. The region of the curves division point is the maximum power point
(MPP). Therefore if with the positive voltage perturbation there is an increase in
the power then the subsequent voltage perturbation should be continued in the
same direction. Where as for the positive voltage perturbation there is a decrease
in the power then in the next iteration voltage perturbation should be negative.
This process repeats periodically until MPP is reached. After the MPP is reached
system oscillates around MPP point as the voltage(Vpv) continues to perturb by
single perturbation voltage size(δV).
3.2.2 Incremental Conductance Method
The incremental conductance (IncCond) method exploits the fact that the
slope of the PV array power curve is zero at MPP, positive on the left of MPP, and
28
negative on the right as seen in Fig. 3.1 [24]. These equations are given by
dP
dV= 0 at MPP, (3.1)
dP
dV> 0 on the left of MPP, (3.2)
dP
dV< 0 on the right of MPP. (3.3)
Since,
dP
dV=
d(IV)
dV= I + V
d(I)
dV∼= I + V
δI
δV, (3.4)
equations (3.1),(3.2) and (3.3) can be written as
δI
δV= −
I
Vat MPP, (3.5)
δI
δV≥ −
I
Von the left of MPP and (3.6)
δI
δV≤ −
I
Von the right of MPP. (3.7)
Thus, MPP is tracked by comparing the instantaneous conductance (I/V) to
the incremental conductance (δI
δV).
3.2.3 Load Voltage and Load Current Maximization
MPPT techniques maximize the power coming out of a PV array. When the
PV array is connected to a PCU, maximizing the PV array power implies the
output power at the load of the PCU also increases. Conversely, maximizing
the output power of the PCU also maximizes the PV array power, assuming a
loss-less PCU [25]. Loads are mostly of voltage source type, current-source type,
resistive type, or a combination of these. The I-V characteristics of these different
loads are shown in Fig. 3.2. It can be inferred that for a voltage-source type load,
the load current Iout should be maximized to reach the maximum power. For a
current-source type load, the load voltage Vout should be maximized [26].
29
Figure 3.2: Different load types 1: Voltage source, 2: Resistive, 3: Combination ofall three and 4: Current source
3.2.4 Fractional Open Circuit Voltage (VOC) and Fractional Short
Circuit Current (Isc)
The relationship between VMPP and VOC of the PV array, under varying tem-
perature levels, has given rise to the fractional VOC method [25]. It is observed
that
VMPP ≈ k1 × VCC , (3.8)
where k1 is constant of proportionality and VMPP is the panel voltage at MPP.
Since k1 is dependent on the characteristics of the PV array being used, VMPP and
VOC for the specific PV array at different insolation and temperature levels has to
be determined beforehand. The factor k1 has been observed to be between 0.71
and 0.78.
Fractional ISC results from the fact that, under varying insolation conditions,
IMPP is approximately linearly related to the Isc of the PV array and is given by
IMPP ≈ k2 × ICC , (3.9)
where k2 is a proportionality constant and IMPP is the panel current at MPP. Just
30
like the fractional VOC technique, k2 has to be determined according to the PV
array that is being used. The constant k2 is generally found to be between 0.78
and 0.92. An additional switch usually is added to the PCU to periodically short
the PV array for measuring ISC.
3.2.5 dP/dI or dP/dV
In this method, the slope
(
dP
dVor
dP
dI
)
of the PV power curve (Fig. 3.2) is
computed and a feedback is provided to the PCU with some control to drive it
to zero, since slope at MPP is zero [27]. In this method, the sign of the slope is
stored from the past few cycles. Based on these signs, a suitable action is taken
and the duty ratio of the PCU is either incremented or decremented to reach the
MPP.
3.3 MPP Locus Line Techniques
It can be observed from the characteristics of the PV array that the maximum
power points of all the I-V curves lie close to a straight line as shown in Fig.
3.3A [28, 29]. Then the idea of tracking MPP for any given condition would just
be operating the PCU on this locus line. The equation of the MPP locus line is
0 4.4 8.8 13.2 17.6 220
0.6
1.2
1.8
2.4
3.0
Voltage (V)
Curr
ent
(A)
0.9 sun
0.7 sun
0.8 sun
0.5 sun
0.3 sun
0.4 sun
0.6 sun
0.2 sun
0.1 sun
1 sun
Figure 3.3: I-V characteristics showing the MPP Locus line
31
given by
V − Req × I − Vth = 0, (3.10)
where 1/Req is the slope of the MPP locus line, and Vth is the intercept on the
voltage axis.
3.3.1 Analytical Proof of MPP Locus
To analyze the theory behind the MPP locus, an equivalent electrical model
for the PV source is defined as shown in Fig. 3.4. This model represents a generic
PV module, composed by N series-connected cells, each of them presenting an
equivalent series resistance RS and shunt resistance RSH . As usual, the current
source Ig represents the photo-generated current, while series-connected diodes
Di are lumped representations of the internal electron-hole recombination pro-
cesses.
N.RS
N.RSHIgVPV
+
-
D1
D2
DN
IPVISH
ID
Figure 3.4: Electrical Equivalent Model of PV Array
The PV module current IPV can be expressed as
IPV = Ig − Isat ·
e
VPV + N · RS · IPV
N · (nVT) − 1
−
VPV + N · RS · IPV
N · RT. (3.11)
32
The shunt resistance RSH being relatively high, the current through it (ISH) is
negligible, then the PV output power is expressed as
PPV = VPV ·
[
Ig − Isat ·
(
eVPV+N·RS·IPV
N·(nVT) − 1
)]
. (3.12)
For the maximization of power, the partial derivative of Eqn. (3.12) with respect
to VPV is made equal to 0. Then the obtained expression is
Ig
Isat+ 1 = e
VMPP+N·RS·IMPPN·(nVT) ·
(
1 +VMPP
N.nVT
)
. (3.13)
Open circuit voltage can derived from Eqn. (3.11) by making IPV as zero and
neglecting the term related to RSH as
VOC ≈ N · nVT · ln
(
Ig
Isat+ 1
)
. (3.14)
Now by substituting Eqn. (3.13) in Eqn. (3.14) and simplifying we obtain
VOC − VMPP ≈ N ·
[
Rs IMPP + nVT · ln
(
VMPP
N · nVT+ 1
)]
. (3.15)
The term N · nVT · ln(
VMPPN·nVT
+ 1)
is assumed constant under all practical condi-
tions and its variations with irradiance is neglected. From the Fig. 3.3 panel I-V
curves of panel it is clear that the change in the open circuit voltage VOC is very
low above a particular sun condition(
I∗g
)
. This also proved by the following
expression derived from Eqn. (3.14),
SVOC ,Ig =dVOC
VOC·
Ig
dIg≈
1
ln(
Ig
Isat+ 1) , (3.16)
poiu where SVOC,Ig is the sensitivity of open-circuit voltage with irradiance.
Now from Eqn. (3.16), the minimum irradiance (I∗g ) above which this sensi-
tivity is less than a negligible threshold value of 5% is calculated. Hence, in the
I-V characteristic curves for the region above the I∗g , open-circuit voltage VOC can
be assumed as constant. Therefore, for the same region from Eqn. (3.15) VMPP
33
and IMPP have a linear relationship. The simplified form this relation is defined
as the MPP locus line
VMPP ≈ −N · Rs IMPP + VOC − VOFF. (3.17)
A more practical way of obtaining the parameters of this expression, is by graph-
ically determining the slope and intercept of the MPP locus line from the offline
measured I-V curves. Then the simplified form of the MPP locus expression is
VMPP = Req · IMPP + Vth, (3.18)
where Req is the inverse slope of the MPP locus line and Vth is the intercept on
the voltage axis.
3.3.2 Approximations of MPP locus methods
An attempt to measure the exactness of the MPP locus line is made in liter-
ature [29] for the verification purpose. The closeness of the MPP locus line to the
actual maximum power point, determines the effectiveness of the locus line. In
the experimental tests, at each irradiance, the power at the locus line operating
point and the actual maximum power are measured. The ratio between these two
values is the effectiveness of the MPP locus line expression. This effectiveness is
sensitive to the terms r and Vth. Fig. 3.5 shows effectiveness curves of the MPP
locus expression for different Rs values 10mΩ, 35mΩ and 50mΩ. In all the cases,
for the irradiance above 0.2 sun, effectiveness is close to unity bellow this value it
decreases reaching a value of 0.9 sun at Ig = 0.25A or 0.075 sun condition.
3.3.3 Other Methods based on the MPP Locus Line
MPPT techniques utilizing the MPP locus of the PV panel are presented
in [28–30]. In [30] the irradiation change is detected by frequently short-circuiting
34
Figure 3.5: Effectiveness of MPP Locus Line Expression for different values of Rs
the PV array for a small duration. This might effect the system stability specially
in the case of grid-connected PV systems. This method assumes short-circuit
current (ISC) is approximately equal to MPP current (IMPP). From the offline
measured I-V curves it is evident that IMPP is always less than ISC. The relation
between the maximum current and short-circuit current is defined as IMPP =
k × ISC, this factor k is not constant and would vary with irradiance. Moreover,
being a single-step method the perturbation power is high for a large change in
the irradiation, this would require a large input capacitor to stabilize the system.
In [29] the proposed control logic has only been tested for a battery charging
application. This technique’s applicability to grid-connected PV system is not
thoroughly investigated. In this scheme, for battery charger circuit acting as a
boost stage, MPPT control loop generates the current reference Ire f to the closed-
loop PI current controller. With the inner PI current-control loop as shown in
Fig. 3.6, the required time varying component of the duty cycle is not generated,
unlike the direct duty-cycle controlled PV system.
The MPPT control stage is cascaded to the PI current control loop which does
the error correction of the PV array current IPV . The generated PWM doesn’t
reflect time variations of the DC-link voltage. It is explained in the following
35
Figure 3.6: PV battery charging scheme with PI Control
sections that in the case of reduced capacitance system, duty-cycle of the PWM
should have a time varying component of twice the line frequency.
3.4 Principle of the Proposed Method
The proposed method tries to overcome the drawbacks of the other MPP
locus methods by eliminating the need of short-circuiting the PV panel and re-
ducing the perturbation power with multiple-steps tracking. A direct duty-cycle
control method is employed instead of PV current or voltage control. The pri-
mary goal of this MPPT control algorithm is to reduce the power loss caused by
the double-line frequency ripple in the PV voltage due to reduction in the DC-link
capacitor. It is worth noting that the proposed method have all the advantages
of the other MPP locus methods like fast tracking, less complexity and topology
independent. The PV panel I-V characteristic curves for different irradiation are
shown in the Fig. 3.3 and the Power vs Voltage curves for the same set of irra-
36
0 4.4 8.8 13.2 17.6 220
9
18
27
36
Voltage (V)
Pow
er
(W
)
(a)
0 4.4 8.8 13.2 17.6 220
0.6
1.2
1.8
2.4
3.0
Voltage (V)
Current
(A
)
0.9 sun
0.7 sun
0.8 sun
0.5 sun
0.3 sun
0.4 sun
0.6 sun
0.2 sun
0.1 sun
1 sun
(b)
Figure 3.7: PV panel characteristics
diance are shown in the Fig. 3.7b. In these curves, for the region above 0.2 sun
condition, all the maximum power points form a straight-line locus. Since the
magnitude of the power output bellow 0.2 sun irradiance is low, the power loss
due to the deviation of the MPP locus line from the actual MPP can be safely
neglected.
In order to minimize the approximation errors in obtaining the MPP locus
line parameters from offline measurements, Power vs Voltages (PV) curves are
plotted from the experiment test results instead of I-V curves. For the flat top
power-voltage curves the accuracy of the locus line is very high. The formulated
expression of the MPP locus would take the same form of the derived Eqn. (3.18)
as
VPV = Req · IPV + Vth. (3.19)
Here as shown in the Fig. 3.3 slope of the line1
Reqis positive for this particular
panel characteristics. The voltage at the intersection of the MPP Locus line and
the voltage axis, termed as Vth is less than the open-circuit voltage.
37
3.4.1 Nature of the Control Scheme
A direct duty cycle control method is chosen for the proposed MPPT con-
trol algorithm. The conventional MPPT control methods have two independent
control, first control loop contains the MPPT algorithm which generates either
voltage reference or current reference, and the second one is usually a propor-
tional (P) or proportional-integral (PI) controller. Non-linear nature of the PV and
unpredictable environmental conditions, results in a non-linear control problem.
Hence, a linear control solution like PI control would be inefficient.
In this thesis, the proposed method with direct duty cycle control is selected.
The PI control loop is eliminated, and the duty cycle is adjusted directly in the
algorithm. Duty cycle control scheme is achieved by utilizing the load line control
approach.
DC
AC
DC
DCPV Panel
Grid
Load seen by the PV module
Figure 3.8: Load at the terminals of PV panel
Load Line Control
For any electrical load, its characteristic curve can be represented on the
source I-V curve as a straight-line passing through origin. The slope of this line
is equal to the magnitude of the load impedance. If a solar panel is directly
connected to an electrical load, the operating point of the unit would be the in-
tersection of the actual load line and the PV array I-V curves. When a power
38
conditioning unit couples the PV panel to the load, the load line is shifted as the
load seen by the PV is different from the actual load as shown in the Fig. 3.8. This
is due to the presence of PCU which boosts the PV voltage to a higher level at
the load terminals. The magnitude of the load line shift or the amount of voltage
0 4.4 8.8 13.2 17.6 220
0.6
1.2
Voltage (V)
Curr
ent
(A)
Shifted Load LinesorLoad Lines for PV panel
MPP
0.5 sun
Actual Load Line
Finaloperatingpoint
Duty cyclecontrol
Initial operatingpoint
Figure 3.9: I-V curves with actual and controlled load line
boost is based on the duty cycle of the boost converter. With the new load line the
operating point (intersection of the controlled load line with I-V curves) would
be different than the one without PCU and so is the output power. In short, the
control logic tries to shift the load line by a margin that it intersects the I-V curves
at the MPP. This shifting of the load line is done by controlling the duty cycle of
the boost converter as shown in the Fig. 3.9.
3.5 MPP Convergence
The process of convergence to the MPP point for the proposed algorithm
is illustrated in Fig. 3.10 and Fig. 3.11. In-order to simplify the description,
the convergence process for an increase in the irradiation and decrease in the
irradiance are explained separately.
39
3.5.1 Step Increment in the Irradiance
0 4.4 8.8 13.2 17.6 220
0.6
1.2
1.8
2.42.6
Voltage (V)
Curr
ent
(A)
2
3
45
5’4’
3’
2’
0.5 Sun
1 Sun
1’
Load Lines
Vth
MPP LocusLine
MPP0.5 sun
MPP1 sun
Figure 3.10: MPPT convergence for a postive change in irradiance
The initial state of the PV is arbitrarily assumed such as the panel is subjected
to an irradiance of 0.5 sun and the system is operating at the point (MPP0.5sun).
In Fig. 3.10, (MPP0.5sun) is the point of intersection of the I-V curve at 0.5 sun
condition and the MPP Locus line.
For a step change in the irradiance from 0.5 sun to 1 sun, the I-V curve is
shifted upwards. With a sudden change in the I-V curve, PV operating point
immediately shifts to a new point 1′. 1′ is the intersection point of the load line
at an initial duty cycle and the new I-V curve. This happens before the controller
starts responding to the change in the sun condition, as the controller has some
computational time delay.
Now the measured values of PV panel current (IPV,1′) and voltages (VPV,1′)
corresponds to the point 1′. The control algorithm is built such a way that the load
line is shifted to a specific point on the MPP Locus line which has same current
of 1′. The voltage coordinate of the new point 2 is calculated by substituting the
(IPV,1′) in the MPP Locus line expression Eqn. (3.19). Thus, VPV,2 can be written
40
as
VPV,2 = Req · IPV,1′ + Vth (3.20)
and
IPV,2 = IPV,1′ . (3.21)
With the new coordinates of point 2 (VPV,2, IPV,2), the duty cycle is updated from
the initial value (D1′) by using the following expression
D2 = 1 −
[
(1 − D1′) ·
√
VPV,2
VPV,1′
]
. (3.22)
The above expression is derived in the next section of the thesis. With the
newly calculated duty cycle the operating point of the PV shifts from 1′ to 2′, as
the load line through 2 intersects the I-V curve at 2′. Now the measured values
of the PV current and voltage would be IPV,2′ and VPV,2′ . It should be noted that
point 2 is a virtual point which is internally calculated by the control algorithm
just to shift the operating point from 1′ to 2′.
This process repeats periodically by moving the operating point along the
I-V curve till the maximum (MPP1sun) of this particular curve is reached, i.e.,
MPP0.5sun → 1′ → 2′ → 3′ → 4′ · · · → MPP1sun. As the control runs in an
iterative fashion, generalized form of Equations (3.20) and (3.22) for kth iteration
can be written as
vPV (k + 1) = Req · iPV (k) + Vth , (3.23)
d (k + 1) = 1 −
[
(1 − d (k)) ·
√
vpv (k + 1)
vpv (k)
]
. (3.24)
Once the MPP point is reached, the calculated voltage would be same as previous
iteration value vpv (k + 1) = vpv (k) and the duty cycle ceases to update.
3.5.2 Step Decrement in the Irradiance
As shown in the Fig. 3.11 for a change in the insolation from 1 sun to 0.5
sun, with the proposed method as explained above the operating point shifts
41
from MPP1sun → 1’→2’→3’. . .→ MPP0.5sun. It can be noticed that the MPP con-
vergence is quick for the descent in irradiance than compared to the increment
case. As for any I-V curve of PV, MPP current (IMPP) is usually closer to short-
circuit current (ISC).
0 4.4 8.8 13.2 17.6 220
0.6
1.2
1.8
2.42.6
Voltage (V)
Curr
ent
(A)
1’
0.5 sun3’
MPP0.5
2’
MPP1
Load Lines
MPP Locus Line
32
1 sun
Figure 3.11: MPPT convergence for a negative change in irradiance
3.6 Functional Description
In this section the procedure for determining the duty cycle from the calcu-
lated PV voltage reference is illustrated.
3.6.1 Determination of Duty Cycle
The duty cycle of the PWM to DC-DC boost converter can be expressed
similar to the transformer turns ratio. That is
VDC
VPV=
IPV
IDC=
1
1 − D. (3.25)
By rearranging the above expression we can write
1
(1 − D)2=
VDC
VPV×
IPV
IDC. (3.26)
42
Therefore duty cycle is
D = 1 −
√
VPV × IDC
VDC × IPV. (3.27)
The discrete form of the duty cycle in kth iteration for a continuous control loop
is given by
d(k) = 1 −
√
vpv(k)× idc(k)
vdc(k)× ipv(k). (3.28)
The new duty cycle d (k + 1) to be calculated during kth iteration based on the
reference PV voltage vpv (k + 1) generated is
d (k + 1) = 1 −
√
vpv(k + 1)× idc(k)
vdc(k)× ipv(k). (3.29)
By substituting (3.28) in the above expression we get
d (k + 1) = 1 −
[
(1 − d (k)) ·
√
vpv (k + 1)
vpv (k)
]
. (3.30)
Finally,
d (k + 1) = 1 −
[
(1 − d (k)) ·
√
Req · ipv (k) + Vth
vpv (k)
]
. (3.31)
The above expression is used to obtain the desired duty cycle of the subsequent
iteration. Based on the above analytical proof the flow chart for the proposed
control method is developed as shown in the Fig. 3.12.
3.7 Functional Evaluation of the Proposed Method
The central focus of the thesis is to reduce the power loss induced by the DC-
link capacitor size reduction. This capacitance reduction causes DC-link voltage
ripple and subsequently the PV voltage ripple. In this section, the operational
effectiveness of the proposed method compared to IncCond method in reducing
the PV voltage ripple is discussed. Duty cycle time variations are analyzed to
prove this.
43
Start
( ) ( )( ) ( )( )
Update the duty cycle
11 1 1 pv
pv
v kd k d k
v k
+ + = − − ⋅
( ) ( )Calculate the PV reference voltage
1pv eq pv thv k R i k V+ = × +
Initialize
d(0), ,eq thR V
Sense v and ipv pv
Figure 3.12: Flowchart of the proposed method
This research tries to investigate the case of the boost converter when in its
input and output voltages have time-variations. The required duty cycle for the
boost converter for two cases, first when PV voltage ripple is allowed next when
the PV voltage ripple is eliminated.
3.7.1 Duty Cycle with PV voltage ripple
The duty cycle profile for a system having both DC-link and PV voltage
ripple is estimated by the following analysis. From Eqn. (2.13) the DC-link voltage
for a reduced capacitor system would be
vdc (t) = Vdc + ∆vdc,ripple sin (2ωt) . (3.32)
44
Based on the discussion in the chapter 2, the PV voltage profile matches with the
DC-link voltage. Therefore PV voltage can be expressed as
vpv (t) = Vpv + ∆vpv,ripple sin (2ωt) . (3.33)
From the above expression it is evident that PV voltage contains a fundamental
component and second harmonic ripple. Then the duty cycle would be
d (t) = 1 −vpv (t)
vdc (t). (3.34)
By substituting Equations (3.32) and (3.33) in (3.34) we get
d (t) = 1 −Vpv + ∆vpv,ripple sin (2ωt)
Vdc + ∆Vdc,ripple sin (2ωt). (3.35)
A simplified form of the duty cycle in terms of percentage ripple is
d (t) =Davg +
(
∆vdc,ripple% − ∆vpv,ripple%)
sin (2ωt)
1 + ∆Vdc,ripple% sin (2ωt), (3.36)
where,
Davg = 1 − VdcVpv
is the average duty cycle,
∆Vdc,ripple% is the percentage peak-peak ripple of DC-link voltage,
∆Vpv,ripple% is the percentage peak-peak ripple of PV voltage.
The above expression if further simplified
d (t) =Davg +
(
1 −∆vpv,ripple%
∆vdc,ripple%
)
∆vdc,ripple% sin (2ωt)
1 + ∆vdc,ripple% sin (2ωt). (3.37)
Then
d (t) = Davg ·1 + ∆vdc,ripple% sin (2ωt)
1 + ∆vdc,ripple% sin (2ωt). (3.38)
Therefore the duty cycle obtained for the system with both DC-link voltage and
PV voltage ripple is
d (t) = Davg. (3.39)
In other words, if the duty cycle generated by the MPPT control algorithm is
constant in steady state with respect to irradiance, then the DC-link voltage would
induce a ripple in PV voltage.
45
3.7.2 Duty Cycle without PV voltage ripple
The duty cycle in this case from Eqn. 3.34 can be written as
d (t) = 1 −Vpv
Vdc + ∆vdc,ripple sin (2ωt). (3.40)
The simplified form of the expression is
d (t) =1 −
Vpv
Vdc+ ∆vdc,ripple sin (2ωt)
1 + ∆vdc,ripple sin (2ωt). (3.41)
Then,
d (t) =(
Davg + ∆vdc,ripple sin(2ωt))
·(
1 − ∆vdc,ripple sin(2ωt))
. (3.42)
Finally,
d (t) = Davg +(
1 − Davg
)
∆vdc,ripple sin (2ωt) . (3.43)
Hence, if the PV voltage is ripple-free even with the presence of DC-link voltage
ripple, then a time varying component proportional to the magnitude of DC-link
voltage ripple is induced in the duty cycle. Conversely, if the duty cycle generated
has a double-line frequency ripple component the ripple in the PV voltage can be
eliminated.
3.8 Ripple Compensation by the Proposed Method
By digital implementation of the proposed algorithm, the duty cycle gener-
ated would be as per Eqn. (3.29). In this expression the time variations in the PV
voltage would be canceled out by the current variations. Hence, the duty cycle is
solely a function of the DC-link voltage. The time domain expression for the duty
cycle can be obtained by solving discrete Eqn. (3.31). The derived duty cycle
d (t) = F [vdc(t)] , (3.44)
46
is a function of DC-link voltage ripple magnitude. Thus, with the proposed algo-
rithm by allowing a ripple in the DC-link voltage, the duty cycle generated will
have an equivalent time varying component. As explained in the Section 3.6.2 ,
this ripple component in the duty cycle would reduce the PV voltage ripple and
thereby the power loss associated with it.
47
CHAPTER 4 SIMULATION RESULTS
This chapter describes the simulation of the PV system with proposed MPPT
algorithm. The configuration of the simulated system is discussed in detail. In
the simulation studies, IncCond MPPT method is used for comparison purpose.
4.1 System Design
The logic presented in the flowchart in Fig. 3.12 was simulated with the
help of MATLAB Simulink. The circuit shown in the Fig. 4.1 was simulated
using SimPowerSystem toolbox in Simulink and the operation of the proposed
algorithm is verified. The solar cell module as per the electrical model defined in
Fig. 3.4 was built in Simulink to simulate the exact behavior of a PV array. Both
the proposed MPPT control algorithm and Incremental Conductance Algorithm
(IncCond) for comparison purpose were implemented using Stateflow toolbox. A
Vg
Ig
Ipv
Inverter Controller
FilterInverterBoost Stage DC-Link PV Array
Ig
Ppv
Grid
Ipv
Vpv
Vdc
MPPT ControllerVpv
Vg
Cpv Cdc
S1
S2
S3
S4
S
Duty Cycle
PWM
Figure 4.1: Circuit Diagram of the proposed system
48
PWM Generator block, which can generate pulse width modulated (PWM)signals
with a variable duty cycle was built by using Simscape toolbox. The PV voltage
and current are sensed and used by the MPPT control algorithm to calculate the
duty cycle for boost converter. The Simulink model is as shown in the Fig. 4.3.
Multiple subsystems are used for the purpose of verification. The irradiation
condition was changed using the irradiance block. The irradiance value of 1000
W/m2 defines a sun condition of 1 sun whereas irradiation value of 500 W/m2 is
the value for 0.5 sun.
The specifications of the simulated PV module are shown in the Table 4.1.
The simulated PV module has 36 cells in series in which each cell gives an open
circuit voltage of 0.6 V and a short circuit current of 2.3 A at 1 sun condition.
Therefore, 36 such cells connected in series will give an open circuit voltage (VOC)
of 21.8 V. The Fig. shows 4.2 the I-V curves of the 40W PV module designed.
Table 4.1: Photovoltaic Panel Specifications
PV panel Nominal Power rating 40 W
Voltage at Max Power 17.3 V
Current at Max Power 2.31 A
Short-circuit current 2.54 A
Open-Circuit Voltage 21.8 A
For each irradiation the PV array voltage is swept from VOC to 0 V and the cor-
responding currents are plotted against the voltage. The set of these curves for
different irradiation form the PV array I-V characteristics. The equation of the
MPP Locus Line can be obtained from these I-V curves and is given by
V = 1.5245× I + 14.5934. (4.1)
The coefficient of I in the above expression is inverse of the slope of the locus line
and the constant term is threshold voltage Vth. The designed power conversion
49
0 4 8 12 16 20 230
0.5
1
1.5
2
2.5
Voltage (V)
Cur
rent
(A
)
Vth
=14.593 V
Slope = 0.65594
Figure 4.2: I-V Characteristics of the simulated PV panel
unit contains a DC-DC boost converter, single-phase voltage source inverter and
an LCL filter. The specifications of all these modules are shown in the table 4.2.
Table 4.2: Power Condition Unit Specifications
Boost Converter Switching Frequency 100 KHz
Inverter Switching Frequency 10 KHz
Input Capacitance Cpv 180µF
DC-Link Capacitance Cdc 288-1500µF
Boost Inductor Lboost 100 µFH
Filter Inductance L f 1, L f 2 100µH,100µH
Filter Capacitance C f 3 µF
Stateflow supports modeling of complex control flows by transitions between
defined hierarchical states. The event-triggered modeling environment of state-
flow, helps it to operate exactly similar to a digital controller. The proposed
algorithm implemented in Stateflow generates duty cycle for the PWM Generator
block. This block shown in Fig. 4.3(b) produce the required switching signal for
the MOSFET switch of the boost converter. The switching frequency of the boost
50
converter is 100 KHz. The input PV capacitance of the boost converter is 180µF
which designed based on switching frequency ripple.
The time-interval between the each iterative loop of the MPPT control algo-
rithm defines the speed of the method and inverse of this parameter is termed
as MPPT frequency. For the simulated system, the MPPT frequency is chosen
as 50 KHz i.e., half of the switching frequency. The inverter was controlled by
the sinusoidal pulse-width modulation (SPWM) scheme with a 10 KHz switching
frequency.
4.2 Simulation Results
Simulations were initially carried out for the full capacitance case. In order
to validate the proposed method, the results were compared to IncCond method.
The results concerning the performance of proposed method are shown in Fig.
4.5. The performance of any MPPT method is tested for a step change input of
irradiance.
Next the simulations was performed with a reduced capacitance system and
the operation of proposed algorithm and IncCond method are analyzed. This
method retains the concept of MPP locus method and thereby carries all the ad-
vantages of the other MPP Locus methods proposed in the literature. Therefore,
the load variation tests and tests involving different variants of DC-DC converters
and other typical tests conducted for an MPPT method are out of scope of this
thesis.
The DC-link capacitor is designed based on the analysis presented in section
2.3.2 . In Case 1 of the simulated system, the allowed DC-link voltage ripple
is limited to 3.73 %. Whereas in Case 2, the allowed DC-link ripple voltage is
extended to 25 % of the average value. The simulation results are provided for
51
DC−Link Capacitor
b) MPPT Control Algorithm− State Flow Module
a) Single−phase Two−stage PV system
powergui
Continuous
PWM Generator
PV Array GridInverter
Duty_Cycle
PWMVpv
Ipv
Vpv
Vpv
Vdc
Duty_Cycle
Ipv
Irradiance FilterBoost Converter
Vpv
Ipv
D
Fig
ure
4.3:P
rop
osed
Sy
stemIm
plem
entatio
nin
Sim
ulin
k
52
these two cases. Figures 4.4 through 4.7, show the waveforms at the output of the
converter blocks in the Power Conditioning Unit for the two cases.
4.2.1 Case 1 - Large Capacitance Design
IncCond Method
When a DC-link capacitor of 1500 µF is employed in the simulation, a DC-
link voltage ripple of 3.73% or 1.12 V peak to peak at 120 Hz is witnessed in Fig.
4.4 (a). This magnitude of ripple is justified by the derived analytical expression
Eqn. (2.15). This 1.12 V ripple in the DC-link voltage enforces a 0.5 V ripple
in the PV voltage as in Fig. 4.4 (b). The PV voltage percentage ripple of 2.5 %
is quite less than the 8.0 % limit. Hence, the power extracted doesn’t have any
loss and it is evident from the Fig. 4.4 (c) showing the instantaneous PV power.
For 0.5 sun the power extracted is 16.35 W whereas for 1 sun it is 38 W. These
values match with the theoretical MPP powers calculated from the simulated PV
I-V curves. Duty cycle calculated by the IncCond method is shown in the Fig. 4.4
(d). It can be seen that once the MPP is reached the duty cycle oscillates by its
step-increment parameter (∆V). In-short, for a large capacitor design with the
incremental conductance algorithm, MPP is tracked perfectly for a step change in
the irradiation.
Proposed Method
The proposed MPPT algorithm is tested for the system with a capacitor of
1500 µF. It can be seen form the Fig. 4.5 (a) that the DC-link voltage has the
same 3.73% ripple at 120 Hz . The PV voltage ripple is little less than 5% with
the proposed method Fig. 4.5 (b). The power extracted for the 0.5 sun is 16.35
W and 38 W for 1 sun condition as shown in Fig. 4.5 (c). The instantaneous
duty cycle is used to depict the fastness of the proposed MPP Locus method. In
53
0.2 0.25 0.3 0.35 0.40
50
Vdc
(V
)
(a)
0.2 0.25 0.3 0.35 0.40
10
20
Vpv
(V
)
(b)
0.2 0.25 0.3 0.35 0.4
20
30
40
P pv (
W)
(c)
0.2 0.25 0.3 0.35 0.40
0.5
Dut
yCyc
le
(d)Time(s)
0.5 sun
0.5 sun 1 sun
0.5 sun
1 sun
1 sun0.5 sun 16.35 W
1 sun 1.12 V pk-pk ripple
38 W
T=0.045 s
Figure 4.4: IncCond Method for Case 1: Transient response for step change inirradiance from 0.5 → 1 sun
Fig. 4.5 (d), duty cycle reaches a steady state value in 0.025 secs. Whereas for the
IncCond method the tracking time is 0.045 secs as shown in the Fig. 4.4 (d). To
summarize, for a large capacitance PV system, the proposed algorithm offers fast
tracking without any compromise on MPPT efficiency.
4.2.2 Case 2- Reduced Capacitance Design
In this case both IncCond and the proposed algorithm results are illustrated
for the reduced DC-link capacitor design. As per the theory presented in section
54
0.2 0.25 0.3 0.35 0.40
2040
Vdc
(V)
(a)
0.2 0.25 0.3 0.35 0.40
1020
Vpv
(V
)
(b)
0.2 0.25 0.3 0.35 0.4
203040
P pv (
W)
(c)
0.2 0.25 0.3 0.35 0.40
0.5
Dut
yCyc
le
(d)Time(sec)
1 sun
0.5 sun
0.5 sun
0.5 sun
0.5 sun
1 sun
1 sun38 W
1.12 V pk-pk ripple
16.35 W
T=0.025 s
1 sun
Figure 4.5: Proposed Method for Case 1: Transient response for step change inirradiance from 0.5 → 1 sun
2.3.2, the DC-link voltage ripple is inversely proportional to the capacitor size.
The capacitance value for 25 % voltage ripple is calculated as 288.14 µF from the
Eqn. (2.15).
Incremental Conductance Method
From Fig. 4.6 (a) we can notice a 10 V peak-peak ripple which is 25% of
the 40V voltage level. This large DC-link voltage ripple imposes a 5 V peak-
peak ripple in the PV voltage as shown in Fig. 4.6 (b). An equivalent amount
of current ripple is also induced in PV panel current. This can be noticed in the
55
instantaneous PV output power waveform, Fig. 4.6 (b). Due to the presence of
steady state oscillations in the panel power 4.5 (c), the average power extracted is
less then the practical maximum power. The PV output power obtained for 0.5
sun irradiation is 13.81 W and 29.24 W for 1 sun. Hence, for this case IncCond
0.2 0.25 0.3 0.35 0.40
153045
Vdc
(V)
(a)
0.2 0.25 0.3 0.35 0.40
10
20
Vpv
(V
)
(b)
0.2 0.25 0.3 0.35 0.40
153045
P pv (
W)
(c)
0.2 0.25 0.3 0.35 0.40
0.5
Dut
yCyc
le
(d)Time(s)
0.5 sun
0.5 sun
1 sun
1 sun
∆D
1 sun
25 % ripple
5 V pk-pk ripple
0.5 sun
0.5 sun
Figure 4.6: IncCond Method for Case 2: Transient response for step change inirradiance from 0.5 → 1 sun
method results in a power loss of 15.53 % for 0.5 sun and 23.17 % for 1sun.
Proposed Method
In this case, the proposed MPPT algorithm is tested for the system with a
capacitance of 288.14µF. Therefore, for the same amount of ripple as of previous
56
0.2 0.25 0.3 0.35 0.40
20
40
Vdc
(V
)(a)
0.2 0.25 0.3 0.35 0.40
10
20
Vpv
(V
)
(b)
0.2 0.25 0.3 0.35 0.40
2040
P pv (
W)
(c)
0.2 0.25 0.3 0.35 0.40
0.5
Dut
yCyc
le
(d) Time (sec)
0.5 sun
0.5 sun
1 sun0.5 sun
38 W
16.35 W0.5 sun1 sun
1 sun1 V pk-pk ripple
10 V or 25 % pk-pk ripple1 sun
Figure 4.7: Proposed Method for Case 2: Transient response for step change inirradiance from 0.5 → 1 sun
one, shown in Fig. 4.7 (a), the PV voltage , the PV output power and the duty
cycle of the proposed algorithm were recorded. From 4.7 (b) it is evident that
ripple in the PV voltage is negligibly low. Similarly PV panel current is ripple
free, which can be estimated from the instantaneous power waveform of Fig. 4.7
(c). From the Ppv waveform, the power extracted is 16.35 W for 0.5 sun and after
a step-change in the irradiance the power output is 38.06 W.
The duty cycle calculated by the proposed algorithm is plotted against the
time in Fig. 4.7 (d). The generated duty cycle follows the variations in the DC-
link voltage. Mathematical analysis presented in section 3.7.3 is justified with
57
this result. Hence, the oscillations in the PV output power are eliminated thereby
reducing the power loss. The following table compares the extracted power by
both the MPPT control algorithms discussed above.
Table 4.3: PV Power Extracted by Proposed method and IncCond method forReduced Capacitor case
IncCond Method Proposed Method
Irradiance(W/m2)
TheoreticalMaximumPower(PMPP(W))
ExtractedPower(
Ppv(W))
PowerLoss %
ExtractedPower(
Ppv(W))
PowerLoss %
200 4.69 4.39 6.42% 4.67 0.38%
300 8.37 7.60 9.26% 8.33 0.54%
400 12.30 10.70 13.03% 12.28 0.18%
500 16.38 13.81 15.71% 16.35 0.21%
600 20.58 16.94 17.69% 20.53 0.24%
700 24.87 20.04 19.41% 24.81 0.23%
800 29.23 23.15 20.80% 29.18 0.17%
900 33.65 26.22 22.09% 33.60 0.16%
1000 38.13 29.24 23.32% 38.06 0.19%
From Table 4.3 it is can be said that the power loss due to DC-link voltage
ripple is more prominent at high irradiance conditions than at for low irradiance.
Power loss with the IncCond Method is above 20% for sun conditions greater than
0.9, whereas the power loss with the proposed method is less than 0.5 % for all
the sun conditions.
58
CHAPTER 5 EXPERIMENTAL RESULTS
PCUs are very important in any power related applications. For any system
to give an output that is suitable for the load, a PCU is needed. Over the last few
decades the control of PCUs has gone through a significant change. The system
becomes more and more sophisticated with advancements of control techniques
using digital methods. The system becomes cheap and small with these tech-
niques. Amongst all the control techniques, micro-controllers revolutionized the
world of PCUs. Micro-controllers are used for implementing complex algorithms
and mathematical calculations. A number of high power PCUs can be controlled
with the help of a single micro-controller. Amongst these, Digital Signal Process-
ing (DSP) micro-controllers are gaining popularity in control of PCUs because of
their capability to handle large amount of data.
This chapter gives a detailed description of the use of DSP micro-controller
for implementing the objective of this thesis. The hardware setup is described.
TMS320F28035 sits on TI’s Solar Explorers Kit and forms its control part. The
actual implementation for a conventional PV system has been carried out and the
results have been presented and compared.
5.1 Use of DSP Micro-controllers for PCUs
The use of DSP micro-controllers has moved from support to the existing
main control system to being the actual control system. Power electronics ap-
plications require more advanced features and functionality which need to be
incorporated in control systems in order to reduce their size and cost. DSP micro-
controllers allows automotive and industrial motor drives control to be advanced
and cost effective. Other advantages of DSP include higher speed to handle high
frequency inputs. PCUs require advanced PWM based control and complicated
59
algorithms. There is a need for precise and reliable control with provisions for
protecting critical parts of the system in case of faults. Digital signal processors
(DSP) play an important role for implementing such control methods since their
operating speeds are very high which ensure fast response times to faults. Also
being reprogrammable, changes to the control can easily be made in case any
changes to the control part of the system need to be made.
Advantages of DSP processor power control over analog methods are
• Precision
• High Reliability
• High Speeds
• Ease of implementation of Multiplication and Square root
• Low cost and size
5.2 TMS320F28035
TMS320F28035 is a high performance 32-bit DSP microcontroller used for
high end applications. Some of the features of TMS320F28035 are
1. High-Efficiency 32-Bit CPU
2. 60-MHz Device
3. Three 32-Bit CPU Timers
4. Enhanced Control Peripherals like Enhanced Pulse Width Modulator (ePWM),
Analog-to-Digital Converter (ADC), Comparator
5. Harvard Bus Architecture
60
6. Watchdog Timer Module
7. Serial Port Peripherals like SCI, SPI, I2C bus, eCAN, etc.
8. Advanced emulation features like real time debug via hardware and break-
point functions.
5.3 Development Platform-Code Composer Studio
(CCS)
TI’s Code Composer Studio (CCS) is an Integrated Development Environ-
ment (IDE). It is used for the development of all the phases: coding the micro-
controller, editor in C, linker, assembler, interface to load the program on the
microcontroller as well as debugger. It also has advanced features such as real
time data exchange.
CCS provides a friendly environment for managing files and projects. Var-
ious library files have been provided with definitions for standardized functions
and with initializations and other standard routines for different modules. CCS
comes with an editor, a compiler, an assembler and a linker. The source files
can be in assembly or C. CCS provides support tools like watch windows, break
points and probe points, single stepping through the code, real time monitoring
tools, memory watch, etc. The variety of graphical data formats allows us to the
real time capabilities supported by CCS. Not just the graphical displays, all the
debug windows (watch windows and memory windows) can be continuously
refreshed in real time. This power to look into your application in real time,
while your system is running, is invaluable. This provides the system designer
an opportunity to optimize his/her system for the real world.
61
5.4 TI’s Solar Explorer Kit
TI solar explorer Kit is developed to emulate a PV panel and Power con-
ditioning unit. It provides a flexible and low voltage platform to evaluate the
TMS320F28035 microcontroller device for solar power application.
Figure 5.1: Solar Explorer Kit Overview
Fig. 5.1 gives a block diagram of different stages present on the Solar Ex-
plorer kit to process power from the solar panel. The input to the solar explorer
kit is a 20V DC power supply which powers the controller and the supporting
circuitry. A PV emulator power stage is integrated on the board along with other
stages that are needed to process power from the panel. The control of the PV
panel is kept separate from the control of the other stages.
Thus, the board uses two C2000 controllers, a dedicated Piccolo-A device
(TMS320F28027) is present on the base board and is used to control the PV emu-
lator stage. The other stages such as, DC-DC Boost and DC-AC and DC-DC Sepic
are controlled by a single C2000 device using a control-card that can be placed in
62
the DIMM100 control card slot on the EVM board. Any of C2000 device with a
compatible control card can be used for this operation.
5.4.1 Power Stages on the Kit
Fig. 5.2 shows the location of the different power stages blocks present on
the board.
PV EMULATOR
BOOST CONVERTER1-PH INVERTER
DC-LINK CAPACITOR
TMS320F28035 CONTROL CARD
Figure 5.2: Detailed layout of Solar Explorer Kit
• Boost DC-DC converter with MPPT: This block accepts DC input, which
can be from the PV panel and boost it. This block has the necessary input
sensing to implement MPPT.
• Inverter Single-phase: DC-AC Macro accepts a DC voltage and uses a full
bridge single-phase inverter to generate a sine wave. The output filter, filters
high frequencies, thus generating a smooth sine wave at the output.
• Sync Buck Boost DC-DC: This converter accepts DC input from the DC
Power Entry (20V typical) and uses it to generate the PV panel emulator
output. The module senses the output voltage and current, which makes
emulation of the panel’s V vs I characteristics possible.
63
DC POWER SUPPLY
OSCILLOSCOPE
SOLAR EXPLORER KIT
CODE COMPOSER STUDIO
AUTO TRANSFORMER
MULTIPLIER CKT
Figure 5.3: Experimental Setup
5.5 Experimental Setup
The laboratory setup for the experiment includes the solar explorer kit con-
nected to the computer by USB JTAG and an AC source for grid synchronization
as shown in Fig. 5.3. A synchronous buck boost stage is used to realize the PV
panel. The MPP Locus Line expression of the emulated panel is obtained from its
Power vs Voltage characteristics.
The equation for this locus line is calculated as
PPV = 1.9675 · VPV − 0.06378. (5.1)
Since the MPPT control module senses voltage and current, Eqn. (5.1) in terms of
IPV and VPV is given by
IPV · VPV = 1.9675 · VPV − 0.06378, (5.2)
hence,
VPV =0.06378
(1.9675− IPV). (5.3)
The flow chart of the proposed MPPT algorithm shown in the Fig. 3.12 is updated
for the new MPP Locus line Eqn. 5.3.
The code for the algorithm is written in c++ language using CCS IDE. The
experimental results are carried out for the scenarios similar to the simulation
64
tests. Both proposed algorithm and IncCond method are programmed in IQ
Math format with a global Q value of 24. In order to perform the square root
inloved in the flowchart IQsqrt function is used. The IQ Math functions utilizes
the preloaded IQMath lookup tables in the bootROM.
To emulate the step change of irradiance, the light command to the PV em-
ulator is changed in the watch window in real time.
5.6 Discussions Based on Experimental Results
After the hardware was setup as described in the previous section, and the
DSP controller was loaded with the proposed control algorithm from Composer
Studio, the experiment was carried out and results were obtained. Figures 5.4
through 5.7 furnish the results of the hardware implementation.
5.6.1 Case 1- Large Capacitance Design
IncCond Method
The DC-link capacitor for this case is chosen as 3200 µF. The operation of
IncCond control method is tested using the experimental setup for comparison
with the proposed algorithm.
Fig. 5.4 shows the waveforms at the output of the PV emulator module of
the solar explorer kit. For a step change in the irradiation from 0.5 sun to 1 sun,
the PV voltage (VPV), current (IPV) and instantaneous power (PPV) are shown in
the Fig. 5.4.
It can be noticed that the PV voltage (VPV) and power (PPV) are ripple free
for this case. Hence, the IncCond control operates efficiently and extracts maxi-
mum power available. For 0.5 sun, the measured PV power PPV is 16.15 W and
65
Vpv
Ipv
Ppv
0.5 sun 1 sun
T=48 m s
16.15 W
38.722 W
1.90 A
1.85 A
20.38 V
8.73 V
Figure 5.4: IncCond for Case 1 : PV panel voltage, current and power waveformsfor a Step Change in Irradiance
for 1 sun it is 38.72 W. These values match with the theoretical maximum powers
PMPP for respective irradiance as shown in the simulation results section 4.2.1.
Proposed Method
The proposed control algorithm is tested for the same DC-link capacitor de-
sign as mentioned in the above section. The transient response for a step change
in the irradiance is observed from the test results.
Fig. 5.4 shows the tracking of the new maximum power (PMPP) by proposed
control algorithm. The power extracted from PV source at both the sun conditions
(16.23 W at 0.5 sun and 38.81 W at 1 sun) is approximately close to power obtained
by the IncCond method. From Fig. 5.4 it can be seen that the tracking time delay
for this case is 19 ms. Where as for the IncCond method the tracking time is 48
66
Vpv
Ipv
Ppv
0.5 sun 1 sun
T=19 m s
16.23 W
38.81 W
1.86 A1.84 A
20.46 V
8.78 V
Figure 5.5: Proposed Method for Case 1 : PV panel voltage, current and powerwaveforms for a Step Change in Irradiance
ms which is the twice the proposed method. The tracking time values obtained
from simulation for both the algorithms are 25 ms and 45 ms respectively. This
justifies the fact that MPP locus line based methods will converge quickly than
the traditional methods like IncCond.
5.6.2 Case 2 - Reduced Capacitance Design
IncCond Method
A 22 µF capacitor is connected at the DC-link for the reduced capacitor de-
sign of PCU. In order to have a proper comparison with simulation results, the
capacitor size is chosen such that the DC-link voltage ripple is 25% of its average
value.
67
vac
Vdc=30 V ∆Vdc,ripple=7.5 V
VPV=18.75 V
IPV=1.57 A
∆Vpv,ripple=3.5 V
1 Sun 29.43 W
Figure 5.6: InCond for Case 2 : Inverter Output voltage, PV panel voltage, currentand power waveforms
Fig. 5.6 shows the waveforms at the output of the PV emulator module of
the solar explorer kit. An irradiation of 1.0 sun is set for the PV emulator and
the measured inverter output AC voltage (Vac), DC-link voltage (Vdc), PV panel
voltage (VPV) and current (IPV) are shown in the Fig. 5.4.
It is evident from the Fig. 5.4 that the PCU with the reduced capacitor in-
duces 7.5 V peak-peak ripple in the DC-link voltage. The frequency of this ripple
is twice the frequency of Vac i.e., 2 × 60 = 120Hz . An equivalent amount of the
ripple is imposed in the PV panel voltage and current . The magnitude PV voltage
ripple is measured as 3.5 V peak-peak and PV current ripple is 0.6 A peak-peak.
The instantaneous power extracted from the PV panel would also oscillate. The
average power extracted in this case is 29.43 W which is less than the actual max-
imum power (38.72 W ) for 1 sun. The measured average power is identical to the
68
result obtained from the simulations. Therefore, when IncCond method is used
for MPPT for the reduced capacitor system , the power loss is measured as 24%.
Proposed Method
For the same DC-link capacitor design of 22 µF the proposed control algo-
rithm is tested. The PV panel voltage and currents are ripple free even when
there is 25% peak-peak ripple in the DC-link voltage as shown in the Fig. 5.7.
Therefore, the PV panel output power would be a constant DC. The resulting
average power with the proposed control algorithm is measured as 37.98 W, it is
approximately close the actual maximum power for 1 sun.
vac
Vdc ∆Vdc,ripple=7.5 V
VPV
IPV
= 20.32 V
= 1.87 A 1 sun 37.98 W
Figure 5.7: Proposed Method for Case 2 : Inverter Output voltage, PV panelvoltage, current and power waveforms
The results obtain in this section corroborate with the simulation results.
Any disparities found are due to the variations in the testing conditions.
69
CHAPTER 6 CONCLUSIONS AND FUTURE WORK
6.1 Conclusions
This research investigated the operation of the PV power conditioning unit(PCU)
with reduced capacitor. In the single-phase PCU reducing the decoupling capac-
itance would induce oscillations in the PV panel power. The extracted average
output power by the traditional MPPT techniques is reduced due to these oscilla-
tions.
To address this problem, a MPPT technique based on MPP locus line has
been presented. The proposed algorithm retains the major advantages of MPP
locus line techniques like fast tracking and low complexity. In addition, this
method generates a time varying duty cycle for the boost converter to mitigate
the oscillations in the PV panel power.
An accurate PV array model is defined and the MPP locus line concept is
analytically proved for this model. A summary of mathematical analysis pertain-
ing to duty cycle time variations is presented to justify the effectiveness of the
proposed method in mitigating the PV voltage ripple. Simulated results for the
proposed algorithm and IncCond method are compared in terms of the tracking
time and power reduction. It is found that the proposed method tracks the MPP
at a faster rate than the IncCond method. The oscillations in the PV panel power
as seen in the case of IncCond method are mitigated by the proposed method.
Also, during practical implementation, we observe that the performance of
proposed method corroborates with the simulation results. Experimental results
have shown that the IncCond control method is subjected to a 20.0 % power
loss due to capacitor reduction. Whereas with the proposed method the true
maximum power is extracted from the PV panel.
70
Hence, the proposed MPPT algorithm can contribute majorly in improving
the reliability of the PV systems by reducing the DC-link capacitance requirement.
6.2 Future Work
In the section 4.2.2 it is described that the DC-link capacitor is reduced to a
value such that 25% voltage ripple is allowed in the DC-link. With the proposed
algorithm it is proved that the power loss caused by this 25% DC-link ripple can
be mitigated. From the simulation results it is observed that the DC-link voltage
ripple can be further increased with the proposed algorithm without any power
loss. Hence, an analysis is required to find the upper limit of the amount of the
ripple the converters in the power condition unit can handle without any stress
on the semiconductor switches.
To determine the upper limit of the DC-link voltage ripple, dynamic stability
of the proposed MPPT control algorithm has to be evaluated at different magni-
tudes of DC-link voltage ripple. State-space modeling of all the converters and
the control schemes involved are required for this stability analysis. The stabil-
ity limits of the system in terms of percentage voltage ripple can be determined
with this analysis. Transient behaviors of the proposed PV system can also be
examined for various operating conditions. Hence, with this stability analysis the
performance of the PV system under large DC-link voltage ripple can be realized
more effectively.
71
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