A Modular Programmable Cmos Analog Fuzzy Controller Chip ...RODR´IGUEZ-V AZQUEZ´ et al.: A MODULAR...

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 3, MARCH 1999 251

A Modular Programmable CMOS AnalogFuzzy Controller Chip

Angel Rodrıguez-Vazquez,Fellow, IEEE,Rafael Navas, Manuel Delgado-Restituto,Member, IEEE,and Fernando Vidal-Verdú

Abstract—We present a highly modular fuzzy inference analogCMOS chip architecture with on-chip digital programmability.This chip consists of the interconnection of parameterized in-stances of two different kind of blocks, namelylabel blocks andrule blocks. The architecture realizes a lattice partition of theuniverse of discourse, which at the hardware level means thatthe fuzzy labels associated to every input (realized by the labelblocks) are shared among the rule blocks. This reduces the areaand power consumption and is the key point for chip modularity.The proposed architecture is demonstrated through a 16-rule two-input CMOS 1-��m prototype which features an operation speedof 2.5 Mflips (2.5�� 106 fuzzy inferences per second) with 8.6 mWpower consumption. Core area occupation of this prototype is ofonly 1.6 mm2 including the digital control and memory circuitryused for programmability. Because of the architecture modularitythe number of inputs and rules can be increased with any hardlydesign effort.

Index Terms—Analog IC design, function approximation, fuzzyhardware.

I. INTRODUCTION

FUZZY controllers are used to map amultidimensionalinput signal onto a scalar output

in accordance to a well-definednonlinear relationship [1],

(1)

In control applications the inputs are usually calledfacts,the output action, and the mapping lawsurface response.For instance, a fuzzy controller for a washing machine mustunivocally set the water level (action) as a nonlinear function(surface response) of the clothes’ mass, the water impurity,and the time differential of impurity (facts) [2].

Fuzzy controllers employ the procedure offuzzy logic infer-ence[1] to construct the surface response. Some characteristicfeatures of this procedure are as follows [3], [4].

• The surface response, which is aglobal model predictingthe system behavior for any input, is obtained as acomposition oflocal functions, each one predicting thisbehavior only for inputs comprised in a limited region ofthe input space.

Manuscript received July 31, 1997; revised April 30, 1998. This work wassupported in part by the Spanish C.I.C.Y.T under Contract TIC96-1392-C02-02 (SIVA).

A. Rodrıguez-Vazquez and M. Delgado-Restituto are with the Instituto deMicroelectronica de Sevilla, Centro Nacional de Microelectronica-C.S.I.C.,Endificio CICA-CNM, Avda. Reina Mercedes s/n, 41012-Sevilla, Spain.

R. Navas and F. Vidal-Verdu are with Dto. de Electronica, Universidad deMalaga, Complejo Tecnologico, Campus de Teatinos, Malaga, Spain.

Publisher Item Identifier S 1057-7130(99)01776-0.

• These local functions representinsights on the systemoperation, and are described through inferencerules ofthe type

where are calledfuzzy labels, and the consequentaction assigns values to depending on the outcome ofthe combination of the antecedent clause statements.

• The validity of the statements “IF is ” is con-tinuously graded from 0 to 1; the actual grade of eachstatement is calculated by evaluating a nonlinearmem-bership function which is different from zero onlyinside a subinterval of the whole interval.

Because the statements involved in the fuzzy rules are innatural language, for instance “if the temperature is low,” thismodeling technique is very well suited to capture and emulatehuman expertise. On the other hand, the continuous gradingguaranteesgeneralizationof the local pieces of knowledge andhence, smooth surface responses. Finally, any change whichaffects only a limited region of the input space can be easilyincorporated to the global model by just modifying the affectedlocal functions—transparencyproperty [3].

There are many fuzzy controller applications where theinputs and the output areanalog signals [1], [2]. The hard-ware required for these applications can be realized in twoalternative ways. One employs analog circuitry only at A/Dand D/A conversion interfaces, while the fuzzy processing isrealized in digital domain by either general-purpose processorsor dedicated ASIC’s [5]–[8]. The other realizes the fuzzyprocessing itself in the analog domain, and employs the digitalcircuitry for programmabilityand reconfigurability [9]. Thispaper contributes to the latter approach. Generally speaking,this approach is expected to feature larger operation speed,lower power consumption and smaller area occupation thanthe other [10], [11]. These expectations are confirmed by thetechniques presented in this paper, which fully exploit thefunctional capabilities of the MOS transistor (MOST) to real-ize the fuzzy operators with very simple circuitry. An inherentdisadvantage of analog fuzzy controllers is limited precision.However, it can be overcame through proper modeling of theerror sources and the use of sound circuit design techniques[10]–[12].

Circuit blocks and design techniques for CMOS analogfuzzy controllers have been reported elsewhere [13]–[17].

1057–7130/99$10.00 1999 IEEE

252 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 3, MARCH 1999

Some of them have been demonstrated through actualmono-lithic circuits, a fraction of which include programmability[15]–[17]. However, although precision is a weak point ofthe analog approach, most previous contributions do notconsider the accuracy issue during the design phase. Theiroutput signal may hence become largely erroneous. Theseerrors can be attenuated by post-fabrication tuning of somecritical parameters, guided by learning processes [18]. But theerrors must still remain bounded for convergence. Our chiparchitecture includes design equations to guarantee accurateoperation within prescribed error margins. Consequently, itcan be programmed in robust and transparent way.

The demonstration chip in this paper implements morerules than previous analog monolithic controllers and featuresmuch smaller values, namely: 470 ns8.6 mW (with 16 rules) versus 570 ns 44 mW (with 9rules) [16], and 160 ns 550 mW (with 13 rules) [17]. Pro-grammability is also a quality of our chip, which incorporateson-chip memories for serial digital programming of the ruleconsequents, and allows external analog programming of themembership functions. This is advantageous as compared to[16], where the consequents values are learned using softwaremodels of the controller and are stored on-chip with no furtherchange possible. Finally, the modular organization around twohigh level building blocks easily identified from the user anddesigner point of view, renders our chip architecture feasiblefor silicon compilation.

II. CHIP ARCHITECTURE

The chip realizes a type of fuzzy inference where the ruleconsequents are constant values

(2)

These values are calledsingletons. As compared to thegeneral case where the consequents include fuzzy labels [1],this type of fuzzy inference requires much less complexhardware [9], and, thus, less silicon area and less electricalpower. Besides, it increases the transparency of the rulesand, thus, eases the incorporation of programmability. Onthe other hand, different studies show that singleton fuzzycontrollers areuniversal approximators, i.e., they are capableto approximate any surface response by properly choosing therules and singletons [3], [4].

The set of membership functions constitutes theelementary nonlinearities from which the surface response ofa fuzzy controller is built. Fig. 1(a) shows a typical mem-bership function shape [4]—described by three parameters:

measured as the length of the interval definedby the the central point ofthis interval; and the absolute value of the functionslope at the crossover points.

For a complete controller description, the surface responseformula has to be generated from these elementary nonlin-earities. Fig. 1(b) illustrates the building procedure for aone-dimension, four-rules controller. Here, each rule involvesonly a fuzzy label, “IF is THEN ” whose validity

(a)

(b)

(c)

Fig. 1. (a) One-dimensional membership function shape; (b) illustratingfunction approximation through singleton fuzzy controllers; and (c)two-dimensional membership function.

is evaluated by using the corresponding membership functionIf the actual input is at the center of the interval

for the th membership function, then and theoutput is given by the value of theth singletonAt any point different from the centers of the membershipfunction intervals, the output does not coincide with any ofthe singletons but it is interpolated by using the followingformula:

(3)

where .1 In this way a global responsecurve is built from the local data represented by the singletons,as Fig. 1(b) illustrates.

In the general multidimensional case, the surface responseis interpolated from the singletons by using multidimensionalmembership functions

(4)

1This normalization precludes the output to take a value larger than thelargest singleton at any point.

RODRIGUEZ-VAZQUEZ et al.: A MODULAR PROGRAMMABLE CMOS ANALOG FUZZY CONTROLLER CHIP 253

(a) (b)

Fig. 2. (a) Controller chip architecture and (b) interconnection of label andrule blocks in the 1�m CMOS prototype.

where the function is evaluated by choosing themin-imum2 among the values of the unidimensional membershipfunctions associated to theth rule

(5)

Fig. 1(c) illustrates the build-up procedure and final shape ofa two-dimensional membership function.

The fuzzy controller chip architecture of Fig. 2 realizes(4) for a system with inputs, fuzzy labels per inputand rules. The architecture is composed of theinterconnection of blocks of two different types, namely:labeland rule. Each fuzzy label, say (the th fuzzy label ofthe th input), has an associated label block which evaluatesthe corresponding membership function and generates

replicas of the result. These replicas are processedin the “min inp” sub-blocks of the label blocks to make afirst step toward the realization of the minimum. Each ruleblocks combines inputs coming from the label blocksto: first, realize the second step of the minimum operation;second, evaluate the function and, third, multiply thisfunction by its associated singleton to obtain Thefinal aggregation leading to (4) is performed at the outputnode.

2This is theAND operator used in our chip. Other operators could be usedas well [1]–[4].

(a) (b) (c)

Fig. 3. Examples of different types of input space partitions.

Fig. 2(b) illustrates the interconnection of label and ruleblocks for a system with two inputs and four fuzzy labels perinput, as it is the case for the CMOS prototype presented inSection VI of this paper. Each box in the grid corresponds toa rule, has an associated singleton value, and is defined bytwo labels, one per input. Each label block is shared by fourdifferent rules. Because of this membership function sharing,the architecture of Fig. 2(a) can only generatelattice partitions[see Fig. 3(a)];tree [Fig. 3(b)] andscatter[Fig. 3(c)] partitions[4] are not allowed.

Generally speaking lattice partitions have the potential dis-advantages ofcourse of dimensionality(the number of rulesneeded to perform a good approximation may become pro-hibitively large for large number of inputs) andinappropriategeneralization(the partition granularity needed to approximatethe function in a region of the input space may be inappropriatein other region). However, these potential disadvantages arenot really significant for the type of problems which analogfuzzy controllers are intended for (medium-to-low complexityproblems with low number of inputs and low number of rules).In this scenario, the architecture of Fig. 2 features significantpros for hardware implementation, namely:

• Area and power consumption required for the implemen-tation of the rules antecedents are smaller than in the caseof scatter and/or tree partitions. This is because the repli-cation operation is much less area- and power-demandingthan the membership function evaluation itself.

• The whole architecture is highly modular and can be madeto grow in very simple manner. Consequently, it is verywell suited for design automation.3

• Programmability can be easily incorporated.

Inputs to the chip are voltages for easier interfacing. On theother hand, the minimum and the normalization operations arerealized in current domain because this requires much simplercircuitry that their voltage domain counterparts [19]. Thus, theinputs to the membership function circuits are voltages, whiletheir outputs are currents. However, as already mentioned, thelabel blocks do not directly deliver the membership functioncurrents to the rule blocks; these currents are nonlinearlypreprocessed to produce intermediate output voltages. Thissimplifies the realization of the minimum operation in therule block. Besides, transmitting these voltages (instead of theoriginal currents) from the label to the rule blocks largely sim-

3Highly complex controllers with prohibitive aggregated errors may resulthowever for large input and label count, due to the course of dimensionalityof lattice partitions [3].


(a)

(b)

Fig. 4. Concepts for the realization of a transconductance membershipfunction by current shaping: (a) blobal shapping in current-mode [20] and(b) partial shaping in current-mode [23].

plifies the interblock routing as these latter blocks have onlyone input node (instead of if currents were transmitted).

III. L ABEL BLOCK

Each label block is driven by a component of theinput voltage vector to, first, obtain a membership functioncurrent and, second, generate replicas of avoltage which is a nonlinear function of this current—apreprocessing step for the realization of the minimum operatorin the rule blocks. This section describes first the membershipfunction circuitry, then the complete minimum circuitry and,finally, outlines some major design considerations to reducesystematic errors in these circuits.

A. Membership Function Circuitry

A few alternative realizations of the pseudo-trapezoidalfunction shape of Fig. 1(a) have been reported in literature[15], [21]–[23]. One, see Fig. 4(a), consists of a cascadeof a linearized transconductor, to convert the input voltageinto a current, and a current-mode nonlinear block to realizethe pseudo-trapezoidal shape [20]; this latter block can berealized by using the techniques proposed in [15], [21], [22]. Adrawback of this implementation is the extra area occupationand power consumption of the linearization circuitry. Also,because the transconductor cannot be linearized in the wholeinput range, some of this range is wasted.

Fig. 4(b) employs a slightly different strategy [23]. It usestwo quasi-linear transconductance amplifiers to, at a firststep, obtain monotone increasing and decreasing, respectively,currents around the crossover points; then, at a second step,these currents are first clipped and then aggregated in currentdomain. This strategy shares the drawbacks associated tolinearization. However, as compared to Fig. 4(a), it has theadvantage that the centers and widths of the membershipfunctions are controlled through voltages applied to high-inputimpedance nodes, which requires a simpler control circuitryand yields smaller loading errors in the application of thecontrol signal.

The membership function circuit used in our chip (see theshaded region at the left in Fig. 5) approximates the shapeof Fig. 1(a) by using the nonlinear dc characteristics of aCMOS differential pair. This strategy is based on the work byFattaruso and Meyer on CMOS function approximation [24],and was proposed for analog fuzzy design in [25]. Analysisof this circuit assuming equal differential pairs and using thesquare-law MOS transistor characteristics [26] obtains

(6)

whereis the large signal transconductance factor of

the transistors in the differential pairs,4 and we assume thatthe membership function width is large enough to allow theoutput current reaching the logic unit value at the center.

This membership function circuit shares the advantages ofFig. 4(b) regarding control of the centers and widths throughvoltages applied to high input impedance terminals

(7)

On the other hand, the slope at the crossover pointsiscontrolled by the large signal transconductance of the MOStransistor5

(8)

The main advantage of this membership function circuitis that it does not require any linearization circuitry—whyto linearize if the whole behavior is nonlinear? Thus, itfeatures minimum area occupation and power consumption,and full usage of the transconductor input dynamic range.On the other hand, it has been shown that the shape in (6)can actually realize the universal approximation feature, evenwhen parasitics (systematic, as well as random) are taken intoaccount [18].

Considerations about the main nonidealities that influencethe membership function circuitry, and the design strategiesadopted to reduce their influence, are presented in subsequentsections. However, because they are influenced by the pre-processing circuitry used for the minimum operation, we willdescribe this circuitry first.

B. Minimum Circuitry

As mentioned in Section II, the minimum operation isrealized in three steps: two in the label blocks and other in the

4We assume that the positive and negative input transistors are equal.5Using the bias current to control the slope is not convenient because the

bias current set the logical value “1.”


Fig. 5. The label block.

rule block. However, for clarity, these three steps are describedas a whole in this section.

The whole operation of the minimum circuit is to select-and-propagate the minimum among a set ofinput currents

However, for convenience, we do not directly selectthe minimum among the input currents, but the maximumamong theirfuzzy complements

(9)

where the current level corresponds to the logic “1.” Thisis based on the De Morgan’s law [39]

(10)

and takes advantage of the larger simplicity of the current-mode maximum circuitry [27].

Fig. 6(b) shows conceptual circuits to evaluate the fuzzycomplements by KCL, for positive (entering to) and negative(leaving from) currents. Regarding the maximum circuit itself,several alternatives appear which have to be evaluated bearingin mind the following major architectural features:

• Neither constraints nor penalties should be imposed to thenumber of inputs since it coincides with the number ofcontroller inputs.

• The inter-block routing should be the smallest possiblefor increased modularity

These considerations lead us to discard realizations withcomplexity [28]. Realizations based on sequential bi-

nary selection trees [29] are also discarded because, althoughthey have complexity, their implementation requires

circuit layers, and causes the errors and delays tobe accumulated proportionally to the number of inputs. Themaximum circuit used in our chip [see Fig. 6(a)] is based on

the winner-take-all circuit by Lazzaro [30] and was proposedin [25]. Its steady-state circuit operation is simple: the bottomtransistor driving the maximum current will force the commonvoltage by means of its associated top transistor, whilethe remaining bottom transistors are driven into ohmic regionto comply with their input currents and, consequently, theirassociated top transistors are cutoff. Then, provided the outputtransistor works in saturation region, its current coincides withthe maximum one. When the maximum current is switchedfrom one input terminal to another, a transient takes placewhere the difference between the new and the old maximumcurrent is integrated in the latter terminal, thus driving thistransistor into a conducting state and, eventually, changingthe value of the common voltage

This circuit exhibits the architectural features mentionedabove: 1) it has complexity; 2) the different inputs shareonly the node This latter feature allows us to partition thecircuit as Fig. 6(a) shows, so that the rule block has only oneinput. Another current-mode maximum circuit based also onLazzaro’s was proposed in [31] and used in [14]. It connectsthe output transistor as a diode, removes the current source

and connects the drains of the top transistors toa common node which is the output node. Thus, the inputsshare two nodes instead of one. Besides, the removal of thecurrent makes the resolution of this circuit dependent of theoutput current level and, specifically, small for large currents[27]. Finally, because the output node load increases with theinput count, this circuit performs poorer than Fig. 6(a) whenthe number of inputs increases.

Let us now describe the realization of the two first steps forthe minimum in the label block. The first (complementation)is realized by KCL at the input node of the right-top currentmirror in Fig. 5. Its input current is where the current

is added to preclude the transistors entering in subthresh-old, where the operation speed would become significantlydegraded. Note, on the other hand, that this current mirror has


(a) (b)

Fig. 6. Circuitry for the minimum computation: (a) maximum circuit and(b) complement implementation.

output branches to generate the membership functionoutput replicas for the different rules.The second step is realized also in the label block and consistsof the generation of a set of intermediate voltages asnonlinear functions of the currents Each of thesevoltages is generated in the right-bottom shaded area of Fig.5 by a two transistor circuit (see also Fig. 6(a); for properoperation of this two transistor circuit, some artifact mustbe added to discharge the node—provided by the currentsource included in the rule block).

The next step for the minimum operation is realized in therule block (bear in mind, Fig. 2(a), that this block has oneinput and one output). To that purpose the set of voltages

for the membership function values associated tothe th rule are routed and tied together at the input nodeof the rule block [see the left-hand part of Fig. 6(a)]. Thus, acollective computation is performed at this common node suchthat the maximum among the set of voltages prevails. Fromthis maximum voltage the corresponding maximum current

is generated by the transistor inFig. 6(a). According to (10) this corresponds to the fuzzycomplement of the multidimensional membership valueshifted by

C. Design Considerations in the Label Block

A thorough analysis of the static (systematic and random)and dynamic errors of Fig. 5, Fig. 6(a) and other label blockcircuits is found in [27]. This section summarizes some mainresults regarding systematic errors due to the finite output

resistance of the MOST’s6 which are relevant to designpurposes. Random errors are covered for the whole controllerin Section V.

1) Membership Function Circuit:A first considerationrefers to the common-mode input range of the differentialamplifiers of Fig. 5. It is calculated by constraining thetransistors to beON and operate in saturation region

(11)

where is the limiting voltage of the currentis the large signal transconductance of the input nMOST’s,

is the corresponding threshold voltage, is thetransconductance of the top pMOST’s, and is thecorresponding threshold voltage. A strategy to improve thecommon-mode range is using bias current circuits with thesmallest possible value of such as that attached to Fig.5 where

(12)

Biasing of the current mirror that generates is then carriedout by the circuit at the left of Fig. 5, where is a referencecurrent and the geometry of is obtained from

(13)

where is the large-signal transconductance density ofthe nMOST and is its zero-bias threshold voltage.Typical input range values are around 3.25 V by followingthis approach with a 1-m CMOS standard technology and5-V supply voltage.

Another error source is dc voltage mismatching betweenthe drains of the input transistors (nodes andin Fig. 5) which might cause offset and distortion of themembership output current for finite MOST Early voltages.However, because these two nodes are both of low-impedancetype, the voltage excursions are largely attenuated by thetransconductance of the pMOST’s and the error is, hence,negligible.

The last error is due to dc voltage mismatching between theinput and output nodes of the pMOS current mirror drivingthe minimum input cell,

(14)

where is the equivalent Early voltage of the pMOST’s.This error can be attenuated by proper setting of the biasvoltage of the cascode transistor For optimumattenuation, this voltage should be different for different inputvalues. However, system-level considerations [27] show thatit suffices to obtain the largest possible error attenuation at the

6They will be modeled through an equivalent Early voltageVA which is aquasi-linear function of the channel length [26].


crossover points. The corresponding voltage is calculated toannul the following expression of the absolute current error:

(15)

where

and we assume (as it happens in practice) that all pMOS signaltransistors in Fig. 5 are equal

is the zero-bias threshold voltage ofthe pMOST and and are technological parameters[26] which account for the influence of the substrate on thethreshold voltage. This optimum voltage can be generated bythe circuit at the right in Fig. 5, where we assume that the twodiode-connected transistors have the same aspect ratio,

(16)

and is a reference current. This choice reduces therelative error in (14) to around 0.5%—negligible at the systemlevel.

2) Static and Dynamic Errors in the Maximum Circuit Op-eration: Two major features related to the dc operation arethe discrimination (the circuit ability to distinguish two closeinput values), and the error due to dc voltage mismatchingbetween the input node sinking the maximum current and thedrain of the output transistor. The discrimination of Fig. 6(a)is calculated as [27]

(17)

where is the minimum current increment that can bedetected by the circuit, and is the equivalent Earlyvoltage of the bottom MOST. This equation shows that the dis-crimination improves for decreasing, increasing and

increasing. The 1-m CMOS controller demonstratorin this paper obtains values as small as 8 nA, for inputcurrents around 10 A, with A, and transistorssizes m and m.

On the other hand, the current gain error due to input–outputdc voltage mismatching is given by

(18)

where we have assumed equal Early voltages for the input andoutput transistors. Calculation of this error for Fig. 6(a) and a

(a) (b)

Fig. 7. Circuitry for the minimum computation: (a) adaptive bias circuit and(b) fixed bias circuit.

maximum current level obtains

(19)

where

and

and we assume This expression showsthat can be chosen to annul the error for a given currentlevel. Because the compensation value depends on the current,the adaptive biasing stage of Fig. 7(a) [27] can be used toobtain varying with the current level. In the 1-mCMOS technology used in the paper’s prototype, this adaptivebiasing obtains errors as low as 0.3% for input currents upto 20 A—a precision larger than needed for most practicalfuzzy logic applications. In practice a simpler biasing stage[see Fig. 7(b)] providing a constant value is enough.This voltage can be obtained by making in (19)for corresponding to the middle of the range. The size of

in Fig. 7(b) is then determined by

(20)

where is the large-signal transconductance density of thepMOST.

Another strategy to attenuate this error is by adding cascodetransistors [see Fig. 8(b)] to equalize both drain voltagesin (18). However, this slows down the transient followingan interterminal switching of the maximum input current.This transient has two phases: during the first the voltage

remains quasi-constant while the voltage at the newwinning input terminal is builtup (henceforth calledswitchingtransient); during the second phase the voltage is updatedto conform to the new current (propagation transient). Differ-ences between Fig. 8(a) and (b) arises mostly at the switchingtransient and can be assessed by comparing the time constants


(a)

(b)

Fig. 8. Circuitry for the minimum computation—small signal models ofinput unit cells: (a) noncascode and (b) cascode.

of the first-order models attached to the figures,

(21)

Assuming equal transistor sizes so that and becausewe obtain —the reason leading

us to discard cascode input transistors.Besides of dynamic aspects involved in the switching

process, we have to take into account that the dynamicresponse of these implementations depend on the numberof inputs, since the parasitic capacitance at the common gateincreases. Possible solutions for a high number of inputs areusing bias currents and trees with complemented pMOS andnMOS circuits [32].

IV. RULE BLOCK

The th rule block is intended to: 1) calculate the currentand 2) generate an output current given by

(22)

and these currents are then routed to a common node toimplement (4) through KCL.

There are three main approaches for the analog implemen-tation of (22): 1) using an extension of Mead [33] follower-aggregation circuit with weighting capability [16], [37]; 2)using weighting-plus-division circuits [14], [22], [35] [36];and 3) using normalization-plus-weighting circuits [9], [25],[28]. The first uses an elegant circuit concept, see Fig. 9(a),to implement a nonlinear version of (4) with voltage output.However, because of the feedback, its transient response is not

optimum; also, because a large signal current is appliedat the transconductance amplifier bias terminals, the linearoperation range and the transient response, are largely nonho-mogeneous over the universe of discourse; finally, additionalMDAC’s are required to incorporate digital programmabilityof the singletons. Fig. 9(b) and (c) shows the concepts ofthe other two approaches. Both permit transparent digitalprogrammability of the singletons. However, different reasonslead us to using the normalization-plus-weighting approach.First, the weighting-plus-division approach requires replicationof the input currents and wide-range linear current-modedividers, while the normalization can be realized through acollective computation circuit with only two transistors perinput; the chosen approach results, hence, in simpler circuits.Second, because the transmission path for the numerator andthe denominator of (4) are not the same in Fig. 9(b) thisapproach is more sensitive to mismatching. Third, the transientresponse of Fig. 9(b) is largely-dependent on the signal level.Fourth, there is no simple way to compensate for the errors inthe divider—the only way is using very accurate dividers.

Fig. 10 shows the schematics of the rule block where fourdifferent operations are realized: first, the current isgenerated as explained in Section III-B; second, this current iscomplemented and shifted to obtain third, acollective computation is carried out by all the rule blocks(they share the global nodes and to realizethe normalization operation; fourth, the resulting current isweighted by a digitally controlled current mirror to obtain theshifted version of the th rule output current.

A. Normalization Circuitry

Fig. 11 shows the CMOS normalizer circuit used in ourchip based on a translinear BJT circuit by Gilbert [34]. As adifference to the normalizers used in [9], [28], Fig. 11 does notinvolve any global feedback loop and, hence, features muchfaster dynamic response. Note that Fig. 11 can be split intocells, one per each input–output pair, plus a little commoncircuitry consisting of the transistor and the currentsource Fig. 10 exploits this modularity by incorporatingone of these cells at each rule block.

Assuming that the transistors operate in strong inversion,where the BJT translinear principle does not hold, the circuitis found to realize the following nonlinear transformation:

(23)

where the function is

(24)


(a) (b)

(c)

Fig. 9. Singleton defuzzification strategies: (a) follower–aggregation; (b) weighting-plus-division; and (c) normalization-plus-weighting.

Fig. 10. Rule block.

and

(25)

The offset current is added to improve the dynamicbehavior. Note from Fig. 10 that it is related to the bias currentsin the rule antecedent by Thus, itcan be introduced by just increasing the currentwithoutadditional area cost, although it will be preserved in figuresand equations to gain clarity.

The circuit in Fig. 11 exhibits the following features:1) the sum of all output currents is constant and equal to

2) for each input, the input-output transformation is

a soft monotonic one, i.e, the higher an input current, thehigher the corresponding output current. Thus, the relativestrengths of the different rule antecedents are preserved atthe outputs—as required for defuzzification [1]–[4]. Hence,although this circuit does not realize the ideal normalizationoperation, it keeps the essential features needed for defuzzifi-cation; nonlinearity is not problematic because the whole con-troller chip is highly nonlinear. Actually, system-level analysisshows that, despite this nonlinearity, the normalization-plus-weighting defuzzification approach features smaller deviationsfrom the linear interpolation than the ideal weighting-plus-division structure [27].


Fig. 11. Normalization circuit schematics.

B. Design Considerations in the Normalization Circuit

A first consideration refers to the input range of the nor-malization circuit when embedded into Fig. 10. Consider firstthe common-mode range, where all input currents are equal.If they increase, transistors evolve toward the ohmicregion; on the other hand, if they decrease, the transistors usedin the current source evolve toward the ohmic region.Thus, the common-mode input range is given by

(26)

where is the limiting voltage for the current sourceand we have assumed that the threshold voltages of top

and bottom transistors are approximatelyequal, because their sources are at similar voltage. The bot-tom limit in (26) is valid whenever

otherwise the real condition limit is zero.The wide range cascode current mirror enclosed in Fig. 10allows us to obtain a good common mode range (given by

as well as goodprecision.

Consider now the differential range; if one input currentincreases while the others are kept constants, the top tran-sistor for the changing current will eventually drive all thecurrent and the other top transistors will be cut-off. Thedifferential range is given by,

(27)

where we have considered that the set of fuzzy rules isconsistent[39], i.e., when an input is maximum the remainingare zero.

There are three main sources of systematic errors in Fig.10: the finite impedance of the dc voltage mismatchingamong output nodes of the circuit core (transistors and

in Fig. 11), and the dc voltage mismatching betweeninput and output nodes of the output pMOS mirrors. The

(a)

(b)

Fig. 12. (a) Singleton weighting concept and (b) controller output node.

adopted cascode realization of makes the first negligible.On the other hand, because the top transistors are connectedto low-impedance nodes, the second error is largely attenuatedby the transconductances of the pMOST’s used at these nodes.Concerning the third error source, it can be minimized byinserting cascode transistors, as Fig. 10 shows. The error isthen given by

(28)

which is minimized by proper choice of Again, aparticular signal value has to be selected to guide the choiceof Because most output branches drive a current value

such current level defines a good choice. Thus,is obtained from (28) for and and it isgenerated in similar as already explained for Fig. 7(b).

With regard to the dynamic response, analysis recommendsto scale the width of as well as the value ofproportionally to the number of normalizer inputs, i.e., rulesin the controller, in order to preserve the dynamic response asthe complexity increases.

C. Singleton Weighting and Output Layer

Fig. 10 employs a digitally-controlled current-mirror [rep-resented at the conceptual level in Fig. 12(a)] to implementa programmable singleton value As compared to analog-programmed current mirrors [38], [40], the digital approachis preferred because it is more robust and accurate, compat-ible with standard memory circuits and directly controllablethrough conventional computers.

Regarding the mirror circuitry itself, and because the nor-malization circuit output stage does not impose major rangelimitations, a stacked (self-biased) cascode structure is usedto minimize errors due to dc mismatching. On the other hand,parallel-connected unit transistors are used to realize the binaryweighting and, thus, reduce systematic errors caused by the


lack of symmetry. The bias current depicted with dashed linesin Fig. 12(a) is added to reduce speed degradations due to theincrease of the parasitic capacitance for large singleton values.

After singleton weighting the rule block outputs are wiredup to the output node where a current isadded to remove the offset and, thus, obtain (4).

V. GLOBAL CONSIDERATIONS

A. Dependence on Temperature

Changes of the controller transfer function with temperatureare basically due to the temperature dependence of the large-signal transconductance densities and the zero biasthreshold voltages Thus, those building blocks whoseinput–output relation is not affected by these parametersdo not contribute to output changes when the temperaturevaries. This is the case of the minimum and the singleton-weighting circuits, where temperature-dependence cancellationis based on the same principles as for current mirrors. Thenormalization circuit does not contribute either becauseappears at the numerator and the denominator in (23) and (24).The membership function circuit is the only whose transferfunction [given by (6)] depends on temperature. However, theelectrical values of the logical zero and one are not affected,provided the current reference is temperature-independent,because these values are associated to logical states of thetransistors in the differential pairs. On the other hand, thewidth and center defined in (7) do neither depend on nor

The only parameter which is affected by temperaturechanges is the membership function slopeIts dependencecan be expressed through parameterwhose maximum value is given by

(29)

at the crossover points. From a global point of view, this meansthat the slope of the generated function between interpolationpoints changes with temperature, as Fig. 13(a) illustrates for acontroller with four rules. Thus, the interpolation smoothnesschanges with temperature, but the interpolation points are notaffected if membership functions are wide enough to saturatein the whole temperature range. Fig. 13(b) shows the differenceof the values provided by Fig. 13(a) for every input value. Notethat the difference is minimum in the interpolation points (forinput values 1.75, 2.25, 2.75, and 3.25 V). Note also that suchdifference is always below 0.75% of the full output range forthe temperature changing from 0–

B. Power Estimation

Let us consider a controller with inputs, rules, andfuzzy labels whose maximum singleton value in

the associated rule base is The maximum static powerconsumption is calculated as:

(30)

(a) (b)

Fig. 13. Illustrating dependence on temperature.

where and the currents and are definedin Figs. 5, 6, and 10.

C. Mismatching Errors

Random variations of the transistor parameters andcan be modeled as normal distributions whose mean values

are the nominal parameter values. For close and small enoughtransistors the variances depend mostly on the device area [12]

(31)

where and are the transistor channel width and length,and and are technology-dependent.

Based on (31), we can obtain expressions for the errorsin the fuzzy controller blocks. The detailed explanation ofthese errors is beyond the scope of this paper; thus, only thoseresulting in important design equations will be outlined.

Consider the membership function circuit first. Analysisshows that the most significant error corresponds to the casewhere the rule output is maximum [27]. The variance of thecomplement of the membership function current (its meanvalue is is given by,

(32)

where we assume that the pMOST’s and ’s areequal, and cascode transistors mismatching is not computedbecause their influence is negligible as compared to signaltransistors. This expression includes the errors due to the


nMOS transistors (parameters and of the currentmirror used to provide in Fig. 5.7

The error at the rule output is calculated by adding theerror caused by the minimum circuit to the previous one. Thevariance for the worst case (only one antecedent active in therule and nonsharing of the membership function circuits) is

(33)

and the corresponding mean value is The bracketedterms correspond to the maximum circuit; the others to thecomplement and membership function circuits. The mismatchis smaller for any other case, although the expression ofthe variance is difficult to obtain because of correlationsbetween variables. Parameters and in (33) corre-spond to the large signal transconductance value and the zerobias threshold voltage respectively, of the noncascode outputpMOS transistor in a current mirror that provides in Fig. 5.

The errors due to the normalization circuit are characterizedby the following approximate variance expression

(34)

where the mean value of is given by (23)

(35)

and is given by (33) for a maximum rule antecedentoutput current.

The approximation used to calculate (34) consists of ne-glecting the mismatching in those normalizer inputs othersthan the th. These terms contribute only around 3% of thevariance for the 16 rules CMOS prototype in this paper,

7This mirror was omitted there in behalf of clarity and because its designis not critical for other performance parameters.

(a) (b)

Fig. 14. Illustration of programmability: (a) chip pin-out and (b) example ofan uniform lattice partition programming.

and their contribution decreases as the rule count increases.This highlights an interesting feature of Fig. 11 which is notshared by other approaches to the normalization operation;namely, the mismatching errors of the different rules are nearlyindependent. Thus, they are not mixed in the output node andmanifest as offsets (easy to correct) at the points were the ruleoutputs are maximum (the most significant to design purposes).

The global error at the rule block output includes also theinfluence of the weighting circuit

(36)

where is given by (34), and and refers to thenoncascode input transistor in the weighting circuit [see Fig.12(a)]. The first term at the right in (35) corresponds to theerror transmitted by the weighting circuit from previous stages,while the second term corresponds to the error introduced byitself. Note that the latter decreases when the singleton valuegrows.

While residual systematic errors may be filtered out by thenormalizer [27], the only way to attenuate the random errorsis solving the design equations (31)–(36) to obtain propertransistor sizes, which is more conveniently performed withthe help of an iterative optimizer.

D. Programmability

Fig. 14(a) shows the pin-out of the prototype presentedin this paper. PinsXiej (forand as well as “sing” and “CLK” are dedicatedto programming. The desired lattice partition is programmedby means of analog voltages atXiej inputs, as illustratedin Fig. 14(b). Note that they are easily identified once thepartition is decided [an uniform partition is shown in Fig.14(b) for the sake of clarity, but any other lattice partitioncan be generated]. These voltages coincide with those at thecrossover points in (7) that define the center and width of themembership functions. Such voltages are generated externallyin the prototype of the paper using variable resistors, as theinset in Fig. 14 illustrates. On the other hand, the controlleroutput at the interpolation points (core of the fuzzy sets in thepartition) is serially programmed by digital signals at inputs“sing” and “CLK.” Singletons associated to each fuzzy set inthe partition are the digital words in


(a)

(b)

Fig. 15. (a) Chip microphotograph and (b) internal architecture.

TABLE ITRANSISTOR SIZES (W=L) IN �m/�m IN THE PROTOTYPE

the singleton weighting circuit inside the rule block of Fig.10. In the prototype of the paper, the singletons are encodedin digital words of 4 bits and stored on-chip in a static RAM.

VI. EXPERIMENTAL RESULTS

Fig. 15(a) shows the microphotograph of a chip that per-forms the processing tasks involved in (4) and Fig. 2(a). It isa lattice controller with two inputs and four labels per input[see Fig. 2(b)]. Thus, eight label blocks, four per chip input, areneeded, as well as sixteen rule blocks. The label blocks outputsare connected to inputs of rule blocks through a “ring bus.”Bias circuitry, as well as one diode connected transistor andone current mirror, which complete the normalization circuitin Fig. 11, are implemented in the “biasing box.” Table I showthe most relevant transistor sizes in this chip.

Digital values to program the output current mirror andhence the singleton values are stored in a “shift register”which is the chip internal memory element and is serially pro-grammed through two pads. Apart from digital programmabil-ity of the singleton values, width and location of membership

(a) (b)

(c)

Fig. 16. (a) and (b) Controller output for two different sets of singleton values:(c) and sections from (b) at maximum local points.

functions are also analogically programmable by setting thevoltages and [see (7) and Fig. 5].

Fig. 16(a) and (b) shows two output surfaces generated bythe chip. The bias signals are V, V,

A, A, A, A,and A, while the voltages are fixed to obtaina uniform lattice partition of the input space. The circuit wasloaded with a constant voltage source of 2.5 V and a currentsource to remove the offset introduced in the normalizationcircuit. Singletons are set to decimal values 1 and 15 inFig. 16(a), which highlights the locality of the fuzzy basisfunctions, while Fig. 16(b) illustrates an exemplary surfaceobtained with different singleton values. Finally, Fig. 16(c)depicts a set of sections from Fig. 16(b) which show theoutput when it reaches their local maximum values, thus thesingleton values.

Maximum circuit delay is 471 ns (90% of the full scaleoutput current) for a step input. For this test, all the singletonsin the controller had the decimal value 1, except one ofthem which was set to the maximum value 15. Under theseconditions, one input was forced to remain constant, while theother input changes following a pulse. As a consequence, theoutput changes from the minimum value to the maximum oneand vice-versa. The maximum power consumption measuredin the previous experiment was 8.6 mW. With respect tothe resolution, it is around 6.5%. The latter was obtainedthrough Monte Carlo simulations (30 iterations) which takeinto account parameter mismatching among transistors, with

as error figure. Finally, input voltage range isover 3.25 V and the area of the chip without pads is 1.6 mmIt is possible to achieve faster designs by introducing biascurrents at input and output branches of the current mirror


TABLE IICMOS ANALOG IMPLEMENTATIONS OF FUZZY CONTROLLERS

that replicates membership function output, and in the outputmirror that implements singleton weighting. It is also possibleto achieve a higher precision by inserting the chip in a learningloop with a computer and using the hardware-compatiblelearning algorithms presented in [18].

For comparison purposes, Table II shows data from threecontinuous-time analog CMOS monolithic controllers thatimplement similar algorithm as the paper’s prototype. Otherreported implementations are difficult to compare because theyare not monolithic and/or differ from the presented prototypein some important aspect. On the other hand, although [16] and[17] report examples of the controllers in a wider context, theyprovide data enough to make the comparisons. Because theprototypes are realized using different technologies no absoluteconclusions can be drawn from the comparison. However,and bearing this in mind, Table II shows that the proposedprototype features much smallerDelay Power,while theirremaining features are competitive. Finally, it is the only onethat reports results of the resolution under random fluctuationsof the technological parameters—an issue which affects theother controller features because it defines many tradeoffsduring the design cycle.

VII. CONCLUSIONS

A highly modular fuzzy controller chip has been proposed.The design methodology is based on two high-level buildingblocks, thelabel and therule blocks, which are respectivelyidentified with the antecedent labels and the consequent offuzzy inference rules. These blocks are prepared to be readilyconnected for the realization of lattice fuzzy partitions. Wepropose circuit implementation for these high-level blocks andpresent detailed discussions concerning their practical design.The results from a prototype of 16 rules, 2 inputs, and 1 outputare shown in Table II and compared with other proposals.They demonstrate that the approach provides very good resultsfor medium-to-low complexity controllers, as those usuallyimplemented with analog techniques. Further improvementsshould face the error aggregation at collective computationnodes as well as the degradation of theDelay Powerwhenthe complexity increases. Current work of the authors takes

advantage from the building blocks of this paper to buildcontrollers of higher complexity using mixed-signal circuits.Automatic tuning or learning rules are also used to increasethe complexity while maintaining theDelay Powerand theprecision.

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[35] T. Miki, H. Matsumoto, K. Ohto, and T. Yamakawa, “Silicon implemen-tation for a novel high-speed fuzzy inference engine: Mega-flips analogfuzzy processor,”J. Intell. Fuzzy Syst., vol. 1, no. 1, pp. 27–42, 1993.

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[39] L.-X. Wang, A Course in Fuzzy Systems and Control. EnglewoodCliffs, NJ: Prentice Hall, 1997.

[40] A. Rodrıguez-Vazquez, S. Espejo, R. Dom´ınguez-Castro, and J. L.Huertas, “Current mode techniques for the implementation of continuousand discrete-time cellular neural networks,”IEEE Trans. Circuits Syst.II , vol. 40, pp. 132–146, Mar. 1993.

Angel Rodrıguez-Vazquez (M’80–SM’95–F’96), for photograph and biog-raphy, see this issue, p. 230.

Rafael Navas-Gonzalezreceived the degree of Licenciado en Ciencias Fısicas(Branch of Electronics) from the University of Granada, Spain, in 1987.From 1988–1993, he worked as a Design Engineer in the microelectronicsgroup of the R&D department of Fujitsu España S.A. During this period,he participated in several ASIC’s specification and design projects. In 1993he joined the University of Málaga, Spain, where he is currently teachingand making research toward the Ph.D. degree. His research activity focusesin specification and design of integrated circuits to implement fuzzy andneuro-fuzzy controllers using analog and mixed signal techniques and theirapplications.

Manuel Delgado-Restituto (M’96) received theBachelor’s degree in physics-electronics in 1988,and the Ph.D. degree in physics-microelectronics in1996, both from the University of Seville, Spain.

Since 1990, he has been working at the Instituteof Microelectronics of Sevill—Centro Nacional deMicroelectronica (IMSE-CNM), where he is cur-rently a member of the research staff. His researchinterests include analog and mixed-signal integratedcircuit design for nonlinear signal processing usingneuro-fuzzy controllers and chaotic circuits. He is

also interested in the design of integrated wireless transceivers.

Fernando Vidal-Verdu received the degree of Licenciado en Ciencias Fısicas(Branc of Electronics) from the University of Seville, Spain, in 1988. FromSeptember 1988 to April 1991, he worked at the Department of Electronicsand Electromagnetism of the University of Seville, in a project supported byFujitsu-Espana S.A. In May of 1991 he joined the University of Malaga as aProfesor Ayudante and got the Ph.D. degree in March 1996 with a dissertationon the design of VLSI fuzzy and neuro-fuzzy controllers using analog andmixed signal techniques. His current research activity focuses on looking forapplications and building experimental demonstrators for analog or mixed-signal based neuro-fuzzy controllers as well as the design of these controllers.He is also interested in adaptive algorithms for hardware implementations andin the design of low-power analog circuits.

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