IRE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

A New Digital Computer System for CommercialData Processing*

J. A. BRUSTMAN,t FELLOW, IRE

Summary-A computer system, the RCA 501, has been de- Attached to the computer are from one to eight mag-signed to meet the needs of commercial data processing. netic tape stations and an on-line high-speed printer.The equipment utilizes transistors as active elements, fer- For the preparation of paper tape, the system is sup-rite cores for high-speed memory, magnetic tape as primarybulk and working store, and built-in and programmable ac- plemented by a Tapewriter and Tapewriter-Verifier.curacy control. Input-output equipment includes paper tape A much larger system is shown in Fig. l(b). The(in), card (in and out), and line printer (out). high-speed memory may be increased to 262,144 char-

The language of the computer system exploits variable- acters, which is equivalent to 1,835,008 bits. Theword and variable-message-length for efficiency. The in- number of tape stations associated with the computerstruction complement is designed to facilitate the program- may be increased to 63. Also shown are off-line inputming of data-processing tasks, taking advantage of thevariable word and message and of built-in simultaneous and output devices associated with the system, tooperation provisions. perform the functions of transcribing both ways be-

The system is adaptable in size to small and large ap- tween magnetic tape and cards and printing informa-plications. tion prepared on magnetic tape. A random access file

can be added to the system.

INTRODUCTION

The RCA 501 is a new electronic data-processing TAPEWRITER(S)isystem of intermediate and large scale. The system TVPEWRIER1is flexible and has been designed to handle commercialdata-processing applications. READER cC>P ) *H

The RCA 501 has the following features:1) True variable data organization. 2nRALqOTEO_

HIGH SPEED MEMORY

2) Expandable random access core memory; up to TAPSELECTING-A

262,144 alphabetic-numeric characters. J3) High data transfer rate to and from magnetic

tape; 33,333 characters per second. PRINTER STATION

4) Directly addressable magnetic tape stations; TO 8 TAPE STATIONSup to 63 in number. (a)

5) Simultaneous operations; READ-WRITE, READ-COMPUTE, WRITE-COMPUTE.

6) Built-in accuracy controls. TAPEWRITERIS) CANS READERCAEDITOR

7) Great programming flexibility to minimize cost I_TAPEWRITER ___ AP

of application. VERIFIERISI STATION

All devices comprising the 501 system employ tran- MONITOR PRINTER

sistors. Tubes are not used. The only exceptions CON W/PUNCH

are some indicators. __ROGR_SQCNTROL_A typical small installation of a 501 system is lAP ___'TRG,

shown in Fig. 1(a). The central computer comprises " ACCESS FILE

a program control unit, a high-speed memory, a tape PRINTER UPTO12RANDOMrselecting unit, a console, a paper tape reader, and a

ELECTROMECHANICAL TAPE SELECTING-B TAPE SELECTING-8 TRANSCRIBING

monitor printer with an associated paper tape punch. PRINTER 11 TO TAPES IITO TAPES"I CARDPUNH

*Received by the PGIE, December 1, 1959;,revised manu-i TOTALOPOPTO TTP SAIN

script received, June 7, 1960. This paper is based on atalk given at the 1959 Industrial Electronics Symp., (b)Pittsburgh, Pa., September 30-O0ctober 1, 1959.

tRCA, Camden, N. Jw Fig. 1-RCA 501 systems. (a) Small. (b) Large.

2

A NEW DIGITAL COMPUTER SYSTEM FOR COMMERCIAL DATA PROCESSING

CODE AND WORD STRUCTURE <0 JOHN D. SMITH * 216 MAINSTREET 0 COLUMBUS, OHIO...

The code used in the 501 system includes all alpha- (a)numeric characters, certain punctuation marks, andspecial symbols used for machine control. Each char-acter is expressed by six information bits (compactly OpCode Address Modifier Addressrepresented by 2 octal digits) and one parity bit. An 0 AAA N BBB

eighth bit is recorded with each character on the mag- 16 720003 10 400000netic tape for timing.

In the RCA system, one or more related characters (b)specify a particular piece of information called an Fig. 2-Formats. (a) Message. (b) Instruction."item. " An item may be a numerical quantity, aname, a street address, or stock number, and may becomposed of both letters and numbers. A number of alh. uei nomto ite eilyo nprlecomposed obohlte anf in groups of four characters. A two-address instruc-related items are grouped into a "message. tion code, shown in Fig. 2(b), is employed. The first

A typical 501 message is shown in Fig. 2(a). A character (0) specifies the operation. The next threecomplete message consists of a start symbol, one or characters specify the first address (A address). Themore related items, each preceded by an item separa- fifth character (N) is used for automatic modificationtor symbol, and finally, an end message symbol. A of the A and B address. The remaining three charac-message may be as short as five or six characters, ormay contain many hundreds or thousands of characters. .otersspecifyeheseonad ( ddss)The content of the registers specified byr N iS addedData storage in the RCA 501 system incorporates to either one or both of the addresses A and B. Thetrue variable item length. Variable data organizationpermits processing of data in their natural form and dressiand themderuas thefs. themd-avoids~~~~~~~~ ~arirr.etitosan dtn rcdrs dress and the modifier as the final address. The modi-

Davoisarbitorar resatritovandabe eitimlengthproc ted . fication of the address does not alter the original in-Data stored in a true variable item length systemdo not have the limitations imposed by fixed or fixed struction stored in the memory.

A complete instruction, then, is made up of eight501 characters. The instructions, however, are codedthe ability to address each character location individ- in octal notation. Since the octal equivalent of a 501

ually, permit the length of any item in any message to character consists of two octal digits, a coded in-be in strict accordance with that item's actual charac- struction contains 16 octal digits. An example of anter count. This allows for total variability of item instruction expressed in octal notation is shown inand message length, but does not preclude the use of the lower part of Fig. 2(b).fixed or fixed variable lengths when the programmerfinds this expedient. The variable item length system, Computerhowever, requires the recording of one control symbolper item. The computer (see Fig. 1) consists of the following

With a given tape density (number of characters sections:packed per inch) and a given tape speed (number of the program control unitinches per second) a specific business file requires the high-speed memory or core memoryless tape length and can be read or recorded in less the tape selector and buffer unit-Atime when true variable item length is utilized. the console

In addition to the message construction, a block the monitor printerconstruction of characters is permissible for certain the paper tape reader.operations. Programs are written in block form. Ihe program control unit contains the arithmetic

A file consists of any number of related information and control elements, as well as the circuitry for in-units, in message or block format; it may consist of terpretation and execution of instructions.several tape reels or any part of one tape. A file is The high-speed memory is a random access, mag-terminated by END FILE (EF) symbol. netic core device which provides storage and work

area for data, as well as programs. The memory isINSTRUCT1ON FORMAT available in increments of 16,384 character locations

and may be exrpanded to 262,144 character locations.The computer in the 501 System is a general-pur- Each location is individually addressable and can

pose, stored program digital computer which handles store any one of the 64 501 characters. Four charac-

3

IRE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

ters in parallel are addressed, brought into the Memory sertion, program testing, "one-shot" programs, in-Register, and regenerated in their original location sertion of periodically changing constants, and inin one 15-ysec cycle. small systems, for data input.

The computer console contains the control and in- The monitor printer is an on-line device, similar todicating devices necessary for the operation and main- an electric typewriter, that prints on paper stock fromtenance of the computer. information received directly from the computer's

The tape selecting and buffer unit-A provides the memory. It operates at a rate of 10 characters percircuitry for communication with the tape stations. second. A seven-hole paper tape punch is associated

The unit-A permits connection of one to eight tape with the device.stations. The number of tape stations directly con- Fig. 3 is a block diagram of the computer. Thetrolled by the computer may be increased to as many high-speed memory, including memory address registeras 63 by connecting a tape selection unit-B to each and memory register, are shown on the left side of theof the unit-A tape trunk lines. The magnetic tape re- figure.cording and reading rate is 33,333 characters per As can be seen, simultaneous access to four char-second. acters is provided. This decreases instruction sta-

The paper tape reader accepts seven-hole punched ticizing time and data transfers. No data length re-paper tape and operates at the rate of 1000 characters strictions result from this arrangement, since allper second. This unit is used for initial program in- character locations are individually addressable. A

REGISTER REGISTER ABREGISTER S

UALIT ~~~~~~~~~~~~REGISTER

REGISTER RGSE

MO 41ADDRESSING ARR L RR

REGISTERIREGISTERRE READ 1 WT >

L~~J BUFFERS _ADDRESS BUS~~ADDE

MEMORY SEPARATORGSR D BUS

4 -m

I _ I REGISTER READ & WRITE~ ~~~~~~~~EGITE

CX C. BUFER I ADDESREENRAIO

4L~~~~~~~~~

A NEW DIGITAL COMPUTER SYSTEM FOR COMMERCIAL DATA PROCESSING

group of four adjacent and simultaneously addressable The N register, associated with the most signifi-characters is called a "tetrad." cant character of the data bus, stores the modifier (N).

The data bus provides the four-character pathway SW and SR store the reference number of the outputbetween the core memory and the interchange. The (WRITE) and input (READ) devices, respectively, andinterchange provides the switching of the single- provide the clock pulses for the WRITE and READcharacter bus to any of the four data bus lines. operation.

The arithmetic unit includes registers, each of one- Operations can be executed either in the normal orcharacter capacity, and an adder circuit. During an the simultaneous mode. Simultaneity is defined asarithmetic operation, the L (left) register stores one coincident execution of two instructions, both or onecharacter of one operand and the R (right) register of which must be an input or output instruction.stores one character of the other operand. Individual All instructions are initiated and may be performednumbers enter the left and right registers from the in the normal mode, but only potentially simultaneoussingle character bus. Depending upon the specific operations may be performed in a simultaneous mode.process, they are complemented or not complemented If the simultaneous mode is free, transfer from thebefore the addition process takes place. The result normal to the simultaneous mode will take place byof decimal arithmetic is converted to the excess three transferring the content of the NO register to the SOcode and then passes through the adder output register. register, and the content of the A register to the SThe parity bit is stored in the adder output register. register. Ihis transfer is automatic.An arithmetic operation is immediately followed by an Simultaneous operation within the computer is madeoperation on the complemented numbers. The two re- possible by the low duty-cycle of the high-speed mem-sults are compared by the comparator while the result ory during execution of most of the input-output in-is returned to the single character bus. The arithmetic structions. The majority of the time required for theunit can also be controlled to perform, in addition to execution of a tape instruction, for example, is useddecimal arithmetic, logic add, logic multiply, and in moving the tape. The high-speed memory is involvedbinary add with carry. The arithmetic processes are for only a very small fraction of that time. If properlyperformed on a character-by-character basis, thus ac- controlled, therefore, the memory is available for othercommodating variable operands and results without functions while it is waiting for the tape to be ad-restriction. vanced. In order to accomplish this with a minimum

The address bus is shown in the upper half of Fig. 3. of buffering and additional hardware, an interruptionAll registers have access to these bus lines, thus technique is employed. That is, the sequence of in-permitting a high degree of freedom in storing data structions being executed simultaneously with theand address information. Registers are used in place tape function is automatically interrupted when theof address counters. A simplified binary bus adder is memory must receive or transmit information in con-used to modify the contents of any of the registers nection with the tape operation.associated with the memory address bus. Character Ihe computer has two READ buffers and two WRITElocations can be addressed in either ascending or de- buffers; each has a capacity of four characters. Onescending modes. The address bus-data bus separator character from tape is clocked into the first READserves as a switch between the data bus and the ad- buffer in 30 ,tsec, and the buffer is filled in 120 ,tsec.dress bus. The entire contents shift into the second READ buffer

The A address and the B address of an instruction and then are transferred in parallel, in one statusare stored in the A and B registers, respectively. The level (15 ixsec) into an HSM tetrad. The 30-gsecT register acts as a third register when needed in con- clocking of characters from tape to buffer continuesjunction with the A and B registers, and on occasion uninterrupted until the READ instruction has beenas internal counter. IThe P register acts as program completed.counter and temporarily stores the high-speed memory During 105 yIsec of the 120-fisec buffer-fillingaddress of the next instruction to be executed. The time, the computer is free to execute another instruc-S register holds the address of the high-speed memory tion or instructions. The number of instructions thatlocation to be affected by the instruction in the si- can be executed simultaneously with any one READmultaneous mode. instruction depends upon the number of characters to be

The A-B equality circuit is used for comparing the read in. Execution of these instructions is interruptednumeric content of the two registers. This enables only for the 15-,visec transfer time.the computer to end a given instruction when the par- Thnese same factors apply to WRITE operations,ticular sector has been processed. except that the 15-yisec interruption occurs with tetrad

5

IRE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

transfer from the HSM to the WRITE buffer and the 1) input-output;computer is free during seven-eighths (105 itsec) of 2) data-handling;the time. 3) arithmetic;

The execution of a program is controlled by status 4) decision and control.levels. Status level is a term applied to a basic period The input-output instructions enable the computerof 15-gsec duration, during which certain paths open to communicate with the on-line peripheral devicesover which information can travel. Status level and (magnetic tape stations, paper tape reader, monitormemory regeneration cycle are of the same time in- printer and paper tape punch, on-line printer). Theyterval and closely related; however, status level and perform the functions of positioning or searchingmemory cycle are not synonymous. tapes, bringing data from an input medium into the

Instructions are executed by an integral number of computer, or sending data from the computer to anstatus levels arranged in a certain order. During an output medium.instruction, status levels may be repeated any number Most of the 12 input-output instructions are po-of times and arranged in any sequence. Each status tentially simultaneous (PS); i.e., they can be executedlevel contains six time pulses, each 2Y% lisec in in the Simultaneous Mode, so that operational timeduration. for these instructions can overlap that of other

The computer operates under the direction of 47 instructions.basic, wired-in two-address instructions (Table I). The data-handling instructions are nonarithmeticThese instructions may be classified into four general instructions for manipulation of data stored in the high-categories: speed memory. The 13 instructions included in this

TABLE I

LIST OF INSTRUCTIONS

Input-Output Instructions Arithmetic Instructions

Operation Code Instruction Name Operation Code Instruction Name

02 Print . .41 Binary add .

03 Paper advance 42 Binary subtract.04 Linear READ reverse 43 Sector compare.05 Block READ reverse . . 44 Three-character add.06 Unwind n symbols 45 Three-character subtract ....11 Single sector WRITE 46 Logical OR .

12 Linear WRITE 47 Logical AND .

13 Multiple sector WRITE 51 Decimal add.14 Linear READ forward.

5 Decimal act

15 Block READ forward 52 Decimal subtract .16 Rewind n symbols 53 Decimal multiply.17 Rewind to BTC 54 Decimal divide.

Data-Handling Instructions

21 Item transfer ................... Decision and Control Instructions

22 One-character transfer .24 Sne-ct ractrtransferby.chaac61 Conditional transfer of control24 Sector transfer by character...25 Three-character transfer .62 Sense simultaneous mode26 Sector transfer by tetrad 63 Tape sense.27 Random distribute 65 Sense simultaneous gate.31 Locate nth symbol in sector.32 Zero suppress 66 Tally .

33 Justify right 71 Transfer control.34 Sector clear by character 72 Set register .

35 Sector compress--retain redundant 73 Store register .ISS's.

36 Sector clear by tetrad 75............... Control simultaneous gate .37 Sector compress-delete redundant 76 Stop.

ISS's.77............. Return after interrupt.

6

A NEW DIGITAL COMPUTER SYSTEM FOR COMMERCIAL DATA PROCESSING

group permit operation control by symbol or by ad- Example (LRF)dress, and transfer of data with or without editing. Instruction: 14 116726 00 060000

The arithmetic instructions include the four-decimalarithmetic instructions, five binary instructions and two Tape (on Tape Station 06):instructions to alter the bit configuration of an operand. _

The decimal instructions operate in accordance > <@TUBE-Z460159.95> <OTwith arithmetic rules and are designed to handle op- - _

erands of unequal anr.Read-write head is < Read-write head iserands of unequal and practically unlimited length. in this gap before Direction of in this gap after

They employ the computer's ability to recognize con- instruction Tape Movement instructiontrol symbols, so that the arithmetic process, in effect,is performed with alignment of the least significant HSM before Instruction is executed:digits and is terminated when the item separator sym-bol (ISS) or a space character to the left of the longer (23 24 25 26 27 30 31 32 33 34 35 36 37)operand is encountered. Thus, the need for the pro- (A B C D E F G H I J K L Mgrammer to preposition operands, by shifting, is largely (A)eliminated, since proper alignment will be achievedeven if one (or both) of the operands as addressed

40 41 42 43 44 45 46 47 5 1 52 53 54contains a series of spaces to the right of the sign. 7J

The binary instructions handle operands of equal )N 0 P QI R S T U V W X Y Z)but unlimited length. Here, length is not defined bythe presence of a control symbol, but by address HSM after Instruction:specification. Alignment of the operands must beprogrammed, since it is not automatically performed 2 24 25 26 27 30 31 32 33 34 35 36 37)as in the decimal instructions. A < * T U B E - Z 4 6 0 I(

The decision and control instructions include sevendecision and control instructions which influence thesequence of operation. Four of these are conditional; 1 567 4 41 42 43- 44 4 47 50 SI 52 53that is, they choose a path according to PRI settings, 5 9 9 5 > - - V W X Y Zthe kind of instruction currently in the simultaneous (A).mode, the state of the simultaneous gates, or the statusof a designated tape station. Two of the seven are Final register contents:unconditional commands, and one enables the com- (A), or (S), = 116745puter to execute the same subroutine any designated (B), = 060000 (unless the instruction is concludednumber of times. in the Simultaneous Mode).

Two instructions enable the programmer to address Time:registers directly; one instruction controls the Si- 3.575 + (.03 x 18) = 4.115 ms.multaneous Gates; and one stops Computer operation.

The execution of a simple input-output instruction Fig. 4-Execution of LINEAR READ FORWARD instruction.is shown in Fig. 4. Instruction 14 (LINEAR READFORWARD) brings one complete message from mag- EM are generated automatically to fill out the remain-netic or punched paper tape into the high-speed memory. ing characters in the four character groups.

14-instruction: LINEAR READ FORWARD At the completion of the transfer the A Register116726-specifies the memory tetrad location holds the high-speed memory address of the location

which is to receive the beginning of containing the EM symbol.the message The process of a decimal addition (Fig. 5) is as fol-

00-indicates no address modification lows. The initial contents of the A register, specifying060000-(B ) specifies the tape station trunk the rightmost character, are transferred to the T regis-B2, B 3-are ignored. ter, which is used thereafter to place the sum in the

During the transfer, a check is performed to verify high-speed memory. Next a search is made in eachthat the first character is an SM. The SM and the operand for the rightmost nonspace, nonminus charac-three characters following it are admitted into the ter. The contents of the A register are decreased byREAD buffer, and then transferred into the high-speed one with each location search in the augend; the con-memory, four characters in parallel. The spaces after tents of the B register are decreased by one with each

7

IRE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Examples (DA) feature is facilitated by the availability of static andInstruction: 51 001016 00 000524 dynamic registers which are under the programmers'

HSM before Instruction is executed: control. Beginning and end addresses of variableZ2<lo 11 12 131F4 15 length messages are located by the use of static reg-0010

l (*1 2 1- - - l isters. Any items within the message may be located(A), by use of the instruction LOCATE nTH SYMBOL.

2021 22 2324) Relative reference can be made to a series of con-0005 jL9I 1 2I i9 - secutive items by using final contents of the dynamic

(B) registers. When processing reference files using theHSM after Instruction: simultaneous tape instructions, it may be desirable to

(1o 1 12 13 14 Is 16 use alternate areas for reading and writing. The abilityL01) LX I I'X to alternate data areas in this fashion evolves to the

(A). (T)f simple problem of transposing the contents of two of

( (20 21 22 231 24 \ the static registers. In this way, extensive modifica-0003 | * ~ 9 9 | - 5tions or duplications are avoided.

(B), Programs can be written relative to a fixed point byTime: utilizing static registers. In order to transfer ad-

(15 x4) + (45x2) + 90 240 ps. dressing of programs, it is necessary only to relocatePRP is set. the program in the memory and change the setting inInstruction: 51 003031 00 012540 the register. Programs can also be written completely

HSM before Instruction is executed: self-relative to the computer. The programmed instruc-25 26 27130 31 tions are set up so that they are relative to a programl3 4 6 6 register, the contents of which hold the high-speed

(A)* memory location of the next instruction to be executed.F 34 35 36 37 4 This is accomplished by the P register. Programs

[~) 'L 7iiI*5 written in this manner can operate without modification(B) from any portion of the memory.

HSM after Instruction:

25 26 27 30 3 1 INPUT-OUTPUT EQUIPMENT

(T). (A). The efficiency of a data-processing system dependsm 3 35 36 37 to a great extent on the design parameters of the input

L02 'uzizLTh and output devices. A variety of input and output de-(B), vices can be provided for the 501 system with high-

Time: speed capabilities.(15x0) + (45x0) + (30x2) +90 150i,s.PRP is set. Magnetic Tape Station

Fig. 5-Execution of DECIMAL ADD instruction.Magnetic tape is the basic data storage medium in

location search in the addend. The search is con- the RCA 501 system. Magnetic tape is used for long-cluded when the addressed character is neither a term storage and intermediate working storage.space nor a minus sign. Te magnetic tape station operates fully automati-

The sign of the sum is then placed in the high-speed cally under the control of the computer or any othermemory location specified by the contents of the T user equipment at a read and write rate of 33,333 char-register. The contents of the T register are then de- acters per second. The recording medium is 3/4-inch-creased by one and the addition process takes place. wide Mylar base tape. Two 101%-inch reels are mounted

The time required to execute a specific instruction on each tape station-a full reel and a take-up reel.is dependent upon the type of operation and the lengths The capacity of a reel is 2400 feet of tape. The de-of the operands. sign of the tape station facilitates rapid manual change

of reels.PROGRAMMING FEATURES The tape station can be instructed to move the tape

in forward or reverse direction. The tape speed isThe 501 computer has provisions for automatic 100 ips, which results in a packing density of 333.33

relative addressing of both programs and data. This characters to the inch. The method of recording char-

8

A NEW DIGITAL COMPUTER SYSTEM FOR COMMERCIAL DATA PROCESSING

acters is unique. The six information bits, the paritybit, and the timing bit are redundantly recorded on 16channels. Each bit is recorded in two separate anddistinct locations. The two recorded dipoles ex-

pressing the same bit are separated by approximatelyhalf the tape width. The track width is 0.020 inch andthe guard band is 0.025 inch. Fig. 6 illustrates thepattern which results from recording on the tape. Dur-ing the reading process, the output from each of thetwo half bits is added in phase by virtue of internalconnections in the magnetic head. Therefore, the lossof either half bit in any given information channel mayresult in a reduction of the signal, but not in the lossof the character bit.

The recording on the magnetic tape is of the biased Fig. 7-Tape transport mechanism.pulsed return-to-bias type. A dc erase field precedesthe recording gap by approximately 1/10 inch. containing approximately 15 feet of magnetic tape

The gaps between messages are 0.34 inch. To as- balanced on a spring support. A proportional controlsure uniform pulse packing on tape, 3.5 sec must elapse is derived by sensing the weight of the tape in thebetween the tape START command and write-out of the bins.first character. The READ-WRITE switch time is less The tape remains essentially in a tensionless con-than 10 ILsec. dition throughout the tape path, except at the two

Eight information lines provide the WRITE signals points near the tape reels. At these points, tension isfrom the user equipment. A WRITE clock signal as- introduced to assure smooth winding and unwinding ofsures precise clocking of all eight channels. A volt- the tape.age drop derived from the 50-ma recording current in Three actuators constructed along loudspeaker voiceeach channel is fed to a parity checking unit. The coil principles provide rapid starting and stopping ofoutput from the parity checker is returned to the user the magnetic tape. To move the tape in either direc-equipment in the form of an echo check signal. A tion, one of the two pressure rollers is pressed againstmissing echo will result in an alarm. the proper capstan. A third actuator provides the power

The READ signal is fed to an eight-bit register via for rapid stopping of the magnetic tape. This brakea pulse transformer and amplifier. After 83 ,Isec, the action is accomplished by momentarily clamping thesignal is clocked out to the user equipment. The tape between the brake shoe and the highly-polishedregisters are reset after an additional 314 psec. surface of the magnetic head.

Fig. 7 shows the tape transport mechanism. A In addition to the data signals, the tape station re-unique servo system is used for maintaining a buffer ceives the following commands from the user equip-tape storage between the head assembly and the tape ment: WRITE-READ, FORWARD-REVERSE, and RUN-reels. This tape buffer consists of a bin-type reservoir STOP.

Each of these paired signals is fumished as a volt-age level to the tape station and is echoed by the tape

TAPE TRACKNOS. 16 15 14 13 12 11 10 9I 7 6 5 4 3 2, station also m the form of a level.

CHANNEL P 2' 2' 2' T 2' 2' r P 2' 2' 2' T r 2' r A 200-jtsec, rewind pulse automatically initiates a

rewind of the tape without further instructions from theA

= _- - =- =user equipment.., _= __ I_ = =_ wE The tape stations. in tum, furnish the following

< __-| _ _ < signals:.= =-=- |-=-==_- - . BTC: (Beginning of Tape Contact). This

o_- = _ _ | _ = _ _ omeans that the magnetic tape is po--==- =_ I_ _ =_sitioned properly. The signal is de-

z ______I______ * rived from a transparent section at_____I -----

the beginning of the tape.ETW: (End of Tape Warning). This signals

NOTE: -0110COIMAT.W Yrn to the user equipment that the end

Fig. 6-Recording on magnetic tape. of the magnetic tape is approaching

9

IRE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

(5 feet) and no additional messages When the card reader is connected to the card editor,should be recorded on the tape. the information recorded on magnetic tape is in 501

OPERABLE: This signal indicates that the equip- code. A plugboard associated with the card editor per-ment is in operating position, i.e., mits the deletion of characters, insertion of new char-power on, capstan on, servo bal- acters, complete rearrangement in the sequence of theanced, and unit in remote operation. characters, and card column splitting.

FLAW: Defective areas in the magnetic tape To assure high accuracy in the transcription ofcan be marked by painting the back data, the card reader is provided with two sensingof the tape with a highly-reflective stations, each equipped with 80 sensing brushes. Thepaint. Areas so marked will be two sensing brushes are separated by a distance equalsensed by a photocell and recording to the distance between adjacent rows on a card.will be halted temporarily while Fig. 8 is a block diagram of the card reader. Thepassing over this area. information sensed by each of the 80 brushes is fed to

a shift register. The sequence of operation is asRandom Access File follows.

Card row 1 is first transferred to shift register 1.The random access storage device available with After the card has advanced by one card row, a second

the 501 system consists of magnetic drum units manu- set of brushes will read the information and store it in'factured by the Laboratory for Electronics, Boston, shift register 2. At the same time, the information inMass. The complete random access file consists of shift register 1 is transferred to register 3, and a shortthe file control unit and the random access storage time later brush set Number 1 will store in shift regis-drums. One file control unit can be connected to each ter Number 1 the information contained in the secondof the computer tape trunks. card row.

Each storage drum contains 300 tracks, and each A timing disk associated with the card feed mecha-track is capable of storing 5000 alpha-numeric charac- nism generates a clock signal which, in turn, advancesters. Therefore, each storage drum has a capacity of a counter from 1 to 12, corresponding to the 12 card1Y-million characters. rows. The binary output of this counter, together with

The drum cabinet contains, besides the storage the two information bits, parity and timing, are re-drum, the track switching relays and the READ-WRITE corded on a magnetic tape. Thus, each punched cardamplifier. Mercury-wetted contact high-speed relays is recorded in the form of 12 short blocks on a magneticare used as switching elements. The file control unit tape.contains the electronic circuitry which provides the In case of a detected error, all registers will locklogic and control functions and drum selection relays. and the card in process is diverted to the reject hopper.

The modes of operation of the random access file The bits 20 and 21, transmitted last, are stored in theare similar to those of the tape stations. However, the 81st position in the shift registers 2 and 3.programmer must exercise slightly greater care in the A much more efficient recording is accomplished byconstruction of the messages in order to stay within the use of the card editor. In this case, the outputthe storage capacity of the selected track, from the card reader is fed to the card editor.

Simultaneous operation between the computer andtwo random access files is possible, provided eachfile is connected to a separate file control unit. G_AE

-- ~~~~~~~ourPUT HOPPER

Card Transcriber,

The function of the card transcriber is to transcribe 80OSAAGES84.STGE ,C

data from 80-column punched cards onto magnetic tape. 0 LIES 2a, OR

The transcription rate is 400 cards per minute. The SHIT EGIS ERROR DETECTION

equipment consists of two units, the card reader and EKALthe card editor. AMP EIGICOTROL

The card reader provides for low-cost off-line tran- =scribing of punched cards to magnetic tape. However, fMwDS ocLAOl IEETRtapes produced by this method require editing and trans- TArPE STDTIOW COE"TROL! ,",lation into the 501 code by the computer. Fig. 8-Card reader.

10

A NEW DIGITAL COMPUTER SYSTEM FOR COMMERCIAL DATA PROCESSING

Card Editor while the second is being punched, and the third isbeing checked. The sequence of operation is as

The card editor receives the coded characters from follows.the card reader and stores the complete data of one During the READ cycle, one section of the tem-card in its core memory. A plugboard in this unit per- porary storage is erased. Then the tape is started, amits the deletion of characters, the insertion of ad- complete message is transferred to the temporary stor-ditional characters, the rearranging in sequence of the age, and the tape is stopped. At the end of the cycle,characters, and a splitting of card columns. The in- the storage sector containing the message is switchedformation from the card and the inserted data can be to the punch channels.expanded to a message length of up to 128 characters. During the punch cycle, information is read from

the temporary storage into the coder. The output of theTranscribing Card Punch coder has 12 channels which correspond to the 12 rows

on the punched card. The electronic commutator as-The transcribing card punch permits transcription of sociated with the coder is synchronized with the card

data from magnetic tape to punched characters in 80- advance.column accounting machine cards at a rate of 150 From the selected commutation channel, the serialcards per minute. data are sent to the shift register which converts the

The device consists of two sections: the electronic information from serial to parallel form. All bits of in-circuitry, including the power supply, and the mechani- formation associated with the particular card row arecal punch. read out simultaneously through the plugboard to am-

The transcribing card punch receives data from a plifiers which drive the 80 punch magnets. This processmagnetic tape station at a rate of 33.3-thousand char- is repeated 12 times. After punching the last cardacters per second. The messages must be of fixed row, the card advances to the check station.field format. All control symbols, such as SM, IS, and During the check cycle, the card is read one row atEM contained in the original message are eliminated a time by 80 wire brushes, and the information is re-during translation and do not create blank columns. A layed through the plugboard into a second shift regis-plugboard permits data rearrangement and character ter. This second shift register converts the informationinsertion. from parallel to serial form. Its output is routed to a

A block diagram of the TCP is shown in Fig. 9. single-channel comparator. In the meantime, the tem-During the transcription process, three cards are proc- porary storage section containing the original informa-essed at one time. One is being read from the tape tion has been switched from the punch channel to

the check channel. The information in the storageis translated again by a second coder. A second 12-

TAPE O(LELECS ALARM channel commutator routes the correct channel to theREADER PRtE |CHC|ALM

comparator, which checks this output with the informa-tion read from the brushes.

The verification of the punched data assures a highdegree of accuracy. In addition, the sequence of SM,

CODE CODERCODtIn~ 7COER °EM symbols is monitored and the input information isc| l , O checked for parity prior to translation.

ONE CARD ROW SELECTRONIC ONE CARD ROWi|(SERIAL) COMlMUTATORS (SERtAL) PI ALR

SITRGISTER SHIFT REGISTER ATH g - p e rnei 1t:< ~ ~~~~~~High-Speed Printer

31 12 ~~~~~~~~~heprinter is a high-speed device capable of on-)=~~~~~~~~~~~line printing at the rate of ten lines per second. Each

_ ~~~~~~~~~linecontains 120 charac.ter positions. Thus, the print-SOLENOID DRIVERS] ing rate is 1200 characters per second. Printing is

, r ~~~~~~~~~doneon a sprocket-driven fanfold, or continuous web

nnn E n n 1 1 ~~~~paper; multileafed forms can be utilized for carbon

LX LX< < LX LJ ~~~~~~Printing is done "on the fly" (see Fig. 10). The_________ PUNCHES BRUSHED print cylinder, a shaft carrying 120 print wheels, ro-

Fig. 9-Transcribing card punch. tates continuously at 900 rpm. Below the rotating

11

IRE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

print cylinder are 120 hammers. Each hammer is ac- Electromechanical Printertuated individually by a solenoid. When a solenoid isenergized, it propels the corresponding hammer upward, The electromechanical printer consists of the high-thereby momentarily pushing the paper and print ribbon speed electromechanical unit coupled with an elec-against the rotating print wheel. The time of contact tronic unit which contains the logic and control cir-of the hammer with the paper is less than 100 psec. cuitry for off-line operation.One line is printed during one print wheel operation. Information is read from the magnetic tape into a

The operation of the electronic circuitry which con- printer memory at the normal tape speed of 33.3-thou-trols the printing is directly related to the rotation of sand characters per second.the print rotation. Control symbols arriving from the magnetic tape

Information to be printed is processed on a charac- may be instructed by a plugboard to initiate such paperter-by-character basis. Characters read from the HSM motion as single line shift, multiple line shift, verticalof the computer are compared, four bits at a time, with tab, and page change. The control symbol item separa-the code of the character to be printed next. Each tor placed between items on the tape can be used to

initiate horizontal tabulation. Sixteen horizontal tabsare available on the plugboard. They may be set to

CODE E cause tabbing to any of the 120 print positions. TheTIM INGCOMPUTER DISC tab counter and plugboard can also be used to eliminate>PRINT CYLINDER ( groups of characters which are not to be printed.

The operation of the device is as follows. TheHIGH SPEEDR SOLENOIDS characters stored on the magnetic tape are transferredt120 from magnetic tape via an information register and en-coded before entering the memory. The memory con-

I30 30 I30 sists of a magnetic core array, 120 columns wide andI t ILi"tsIS0IFT,tIB ISNER1WiFTREGIST6ft 51 positions deep. Each of the 51 positions corre-

spond to a specific alphabetic or numeric character. ACOMPARATOR character is stored by energizing a single core per

column. A column counter permits printing of an item-7r-

PAPERMVACE I to start at any selected column.I IMECMNISM IJ Readout is accomplished by the readout core drivers.

iCONTROLSIGNALS I I The stored characters are read out in the same orderCONTROL SIGNALS GENERATOR as the characters engraved on the print cylinder appearLOCC CONTROL

in the print position. The print speed is dependentupon the information to be printed.

Fig. 10-High-speed printer. The print cycle is completed when the last charac-ter is read from the printer memory. If only numericinformation is to be printed, the print speed is 1200

four-character comparison consumes 15 ,usec. Thus, lines per minute, since less than half a revolution isthe search of all 120 characters requires 450 IIsec. required to print numeric information.The total processing time available for all 120 charac-ters, up to the firing of the hammers, is 900 /Isec. Theshift register is advanced for each comparison, and a CIRCUIT ELEMENTS AND CONSTRUCTIONone is stored for each character match. The 120 out-puts of the shift register feed the 120 solenoid drivers; The basic circuit which was chosen for the logic51 such character comparisons are made during each element in the design of the 501 equipment is therevolution of the print cylinder. After the last com- "Sheffer Stroke" or NOR circuit (Fig. 11). This circuitparison, the paper is advanced to the specified line. configuration provides not only the gating function,The paper motion time is approximately 30 msec for a but also the signal amplification and level standardiza-single line shift. For multiline paper advance, a paper tion as well. The circuit has proven a very powerfulspeed of 50 lines per second is reached when advanc- logical element, since a large number of stages may being the paper by three or more lines. A perforated paper directly cascaded to synthesize any logical array. Thetape loop associated with the equipment and advanced circuit shown provides a logic gain of five and theby the same paper feed mechanism provides for verti- delay per stage for a single load is approximately 0.1cal format control. tLsec.

12

A NEW DIGITAL COMPUTER SYSTEM FOR COMMERCIAL DATA PROCESSING

+13V +8.5V Fans on the bottom of each cabinet cool the circuit1O+PI .,8K components.

+ 6A5V 2N5K +Sn3The various equipment items in the 501 system con-3vL1O,.,t 2 IL83 ov tain the following numbers of transistors.

24._3KK1.8K.-. Tape station 581

A B= AS+ _19.5V On-line printer 942A B OUT Electromechanical printer 3518OO OR / Card transcriber 3077O 1 1 ° 4 Transcribing card punch 2400I 0 1 AND 2* / File control unit 27001 I0*2 Computer (including HSM 32468

characters) 13,797IUhT LOAD

Fig. 11-Basic transistor circuit for RCA 501

Individual circuit modules are packaged on smallprinted boards (Fig. 12). Up to 12 modules may be as-sembled on a larger board. A special lock-in receptaclewas constructed to assure high-contact pressure andreliable operation

The plug-in units are assembled in cabinets as il-lustrated in Fig. 13. The size of this cabinet is ap-proximately 44 inches wide, 14 inches deep, and 68inches high. Each cabinet has space for 572 plug-inunits. Cable connectors between cabinets provide forrapid assembly and disassembly of the equipment.

Fig. 13-Cabinets for RCA 501.

ACCURACY CONTROL

Several types of equipment checks are performed inthe system. Included in these checks are characterparity, arithmetic operation followed by a compare,tape data format control, dual recording on magnetictape, and echoed signals from the tape station for re-corded signals as well as command instructions. Adetected error will initiate automatically a repetition

Fig. 12-Plug-in modules for RCA 501. of the last cycle.

13