IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. I , JANUARY 1994 63

A New Technique for Forming a Shallow Link Base in a Double Polysilicon Bipolar Transistor

J. D. Hayden, Senior Member, IEEE, J. D. Bumett, J. R. Pfiester, Senior Member, IEE, and M.P. Woo

Abstract-A new technique is presented for forming a shallow link base in a double polysilicon bipolar transistor. This method is easily integrated into an advanced BiCMOS process, making use of a disposable polysilicon spacer technology for MOSFET LDD formation. This new scheme allows independent optimization of active and link base regions while providing improvements in base-emitter breakdown and resistance to bipolar hot carrier degradation.

polysilicon

Fig. 1. Cross-section of double polysilicon bipolar transistor with the new link base. I. INTRODUCTION

AST, high-density SRAM circuits have relied upon CMOS-basd B~CMOS processes to meet speed and

packing density requirements [I]. Historically, a single polysilicon bipolar transistor has provided adequate device performance. Recently a double polysilicon bipolar transistor has been proposed for the 4 Mb generation of fast SRAM products in order to provide improved bipolar performance and increased circuit speed [ 2 ] . F~~ B~CMOS applications, one disadvantage of a double po~ysi~icon bipolar is reduced base-emitter breakdown voltage, BVEBOr and resistance to hot carrier degradation. A link region between the active and extrinsic base areas can help improve the tradeoff between base resistance, Rg , and base-emitter breakdown voltage, BVEBO. For a double polysilicon bipolar transistor, however, this typically requires a considerable increase in process complexity. In one example, a link is formed by out-diffusion from a permanent BSG (boro-silicate glass) spacer [3]. This may pose reliability cOncemS in a BiCMOS flow if the Same

diffuses during subsequent heat cycles. The merging of bipolar and CMOS transistors in a BiCMOS

technology has provided the opportunity of applying MOSFET device design techniques to bipolar transistors and vice versa.

used for LDD in advanced CMOS processes in order to reduce the lateral diffusion of the LDD regions and to lower junction leakage [41. Also, researchers have proposed using the

PMOS threshold voltage 151, [6] . In the present work, a new technique is presented for

forming an ultra-shallow link base in a double polysilicon bipolar This relatively simple technique is easily

integrated into an advanced BiCMOS process. This new tech- nique makes use of the diffusion of boron from a disposable PolYsilicon spacer, though a thin thermal oxide layer to the underlying silicon. A very shallow link base is thus formed, allowing independent optimization of the active and link base regions. This improves the trade-off between base-emitter breakdown and base resistance and results in enhanced bipolar performance. It is also anticipated that the shallower link base will lower the emitter-base capacitance CBE. Fig. 1 is a ~ A ~ m a t i c C~oss-section of the Proposed structure.

F

11. FABRICATION PROCESS

This work is based on a 0.5 pm CMOS-based BiCMOS technology with a double polysilicon bipolar transistor [ 2 ] . This process employs self-aligned complementary buried layers and twin wells. Framed-mask poly buffered LOCOS

and buried channel PMOS transistors are formed with a 150 i% gate oxide to give long-channel MOSFET behavior to effective lengths ( L E F F ) as short as 0*35 and

N- and p- LDD regions are formed

reduced lateral under diffusion and improved diode leakage. The process at 'Ontact and two levels Of

metallization. The process features three levels of polysilicon:

the second defines the bipolar emitter, a self-aligned contact landing pad, and a local interconnect; and the third forms a tera Ohm load resistor in the bit

In this experiment, a link base is formed as depicted in Fig. 2. After the first polysilicon layer is doped, a thick dielectric cap is deposited to provide isolation between first and second polysilicon layers. The CMOS gate and bipolar extrinsic base stacks are patterned and etched and an oxidation is performed to reoxidize the gate sidewalls and grow a thin screen oxide of approximately 100 i% on exposed single crystal silicon.

spacers are used for MOSFET LDD formation and the boron (FMPBL) provides i7i. ''Iface

pm

In particular, disposable polysilicon spacers have recently h e n with a polysilicon 'pacer process i4i to Provide

tungsten

diffusion of boron though a thin thermal oxide for setting the the first forms the gates and extrinsic base;

Manuscript received March 20, 1993; revised August 30, 1993. The review

The authors are with Advanced Products Research and Development

IEEE Log Number 92 13694.

of this paper was arranged by Associate Editor K. Shenai.

Laboratory, Motorola, Inc., Austin, TX 78721.

0018-9383/94$04.00 0 1994 IEEE

64 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 1, JANUARY 1994

process sequence (a) g m t d b m n .t.c* Pmt-nbw and .tell. Pow luox

+ + + + + + + + + +-4i-iT++ + + + + + + + +

(e) -08 otch. Ihk ban a n d

(d) r t i v o ban hphntatbn

. . . . . . . . e . . . . . . . 4

Fig. 3. SEM photomicrograph of double polysilicon bipolar transistor with the new link base. The disposable polysilicon spacers have been completely removed and replaced with dielectric spacers.

The emitter polysilicon is deposited, implanted with arsenic, pattemed, and annealed with an RTA step (20 s at 1050OC) to break up the interfacial oxide and provide low emitter resistance. The remainder of the process is conventional.

This new technique for forming an ultrashallow link base relies heavily on recent findings that the diffusion or "penetra- tion" of boron through a thin oxide is enhanced in the presence of fluorine, as in the case of a BF2 implant [8]. It has also been observed that under certain process conditions, boron penetration is a very repeatable and well-controlled process that results in a shallow exponential dopant profile in the underlying silicon. In such cases, the boron flux is dominated by diffusion across the thin oxide and is controlled by oxide thickness and thermal cycle 191. Consistent results, wafer-to- wafer and lot-to-lot have been observed when such a process

on.

Fig. 2. Process sequence for forming the newlink base, integrated into a CMOS-based BiCMOS flow with disposable polysilicon spacers.

A thick sacrificial polysilicon layer is then deposited and implanted with boron difluoride, BF 2 at a dose and energy of 1 . 1015 - 1 . 10l6 and 20-30 keV, respectively. Photoresist can be used to block the implant from the MOSFET areas. A short RTA step at 105OOC for 10 s distributes dopants throughout the polysilicon layer. Polysilicon spacers are then anisotropically etched, stopping on the thin screen oxide. A longer diffusion step (15-60 min at 900°C> drives boron from the spacers through the thin thermal oxide and into the underlying silicon, forming the link base. The active base and the CMOS source/drain implants are performed, aligned to the spacer edge. The link and active base regions are thus self-aligned to the extrinsic base and to each other. After stripping the polysilicon spacers, selectively to the underlying oxide, the LDD implants are performed. An interpoly dielectric is next deposited and the emitter opening is pattemed and etched. This forms permanent dielectric spacers, to provide isolation between extrinsic base and emitter polysilicon layers.

has been used. In the present work, comparisons are made between the new

link base and either (a) the case of no BF2 link implant or (b) the conventional process [2] where active and link regions are merged by implanting the active base after removal of the polysilicon spacers.

111. RESULTS AND DISCUSSION

Double polysilicon bipolar transistors were fabricated using the new link base process. Fig. 3 is an SEM cross-section of a completed bipolar transistor, demonstrating that the disposable polysilicon spacers are completely removed and subsequently replaced with permanent oxide spacers to provide dielectric isolation between extrinsic base and emitter polysilicon layers. Transistors formed with the new link base exhibit excellent transistor characteristics. Fig. 4 is a Gummel plot of a 0.4 x 1.2 pm2 double polysilicon bipolar transistor, displaying ideal characteristics with a slope of 60 mV/decade to below 0.10 pA/pm2 of emitter area.

To verify that the link base was formed by diffusion from the disposable spacers, wafers were fabricated which did not

HAYDEN et al.: TECHNIQUE FOR FORMING A LINK BASE POLYSILICON BIPOLAR TRANSISTOR 65

VBE (v)

Fig. 4. Gummel plot of 0.4 x 1.2 pm2 double polysilicon bipolar transistor with the new linkbase. Ideal bipolar characteristics are observed to below 0.1 pA/pm2 of collector current.

-with link base - -without link base lod

0.2 0.4 0.6 0.8 1.0 1.2 VBE W)

Fig. 5. Gummel plots of 0.4 x 1.2 pm2 double polysilicon bipolar transistors with and without the new link base. High base resistance results when the link base implant is not performed.

receive the BF2 implant but which otherwise were processed equivalently. Fig. 5 shows that these wafers exhibit very high base resistance and strong evidence of collector-emitter punchthrough. The high Rg is associated with a poor link between active and extrinsic base regions. The silicon surface undemeath the dielectric spacers is depleted, resulting in a high base resistance and potentially a high recombination current in the emitter-base depletion region.

Insufficient link base doping has been shown to result in low collector-emitter punchthrough, B V ~ E S [ 101. This is further confirmed in Fig. 6, which displays the effect on BVCES of not performing the link base implant. Here, there is insufficient charge in the base of the parasitic lateral bipolar transistor to prevent depletion of the link region.

Process (PEPPER [I 11) and device (PISCES-2B [ 121) sim- ulations were performed to further understand the collector- emitter punchthrough behavior. The diffusion coefficients for boron through thermal oxide in the presence of fluorine were based on earlier work [9]. Fig. 7 is a cross-section of the bipolar transistor, displaying contours of electric potential. The figure compares bipolar transistors formed using the

10-2

1 o4

,lo4 9 >lo4

- - - - - - - - - I I I

8 0

I I

I I

I I n

l o . l o F 71 I 1 - - -without link base

0 4 8 12 16 20 VCE (v)

Fig. 6. Collector-emitter punchthrough characteristics for double polysilicon bipolar transistors with and without the new link base. The new link base prevents collector-emitter punchthrough caused by depletion of the link region.

conventional process (a), formed without any link base implant (b), and formed with the new link base (c). This figure demonstrates that the doping in the new link base is sufficient to prevent lateral collector-emitter punchthrough. The link base region is entirely depleted in the transistors which did not receive the link base implant.

The new link base lowers the electric field at the emitter- base junction edge relative to the conventional process in which the active and link base regions are merged by perform- ing the active base implant after polysilicon spacer removal. This reduction in lateral electric field is manifested as a large increase in base-emitter breakdown voltage, BVEBO, as is demonstrated in Fig. 8. Measurements have also shown that for a given value of base resistance, the new link base can increase the base-emitter breakdown voltage by as much as 4 v.

The decrease in electric field at the emitter-base junction edge reduces the generation of hot carriers, which in tum lowers the level of hot carrier degradation. Fig. 9 presents the result of reverse emitter-base bias stressing. After IO00 s at 6 V, the bipolar transistor with the new link base fail\; to exhibit any hot carrier degradation while the conventional bipolar transistor displays a 300 fold increase in nonideal base current, AIB.

The new link base modifies the behavior of current gain as emitter area is scaled. This is illustrated in Fig. 10 where normalized current gain is plotted as a function of emitter periphery-to-area ratio. The shallower link reduces the impor- tance of the parasitic lateral bipolar transistor at the emitter edge, modifying the conventional narrow emitter effect [ 131. In a conventional double polysilicon bipolar transistor, lateral encroachment of dopant from the extrinsic base increases the base Gummel number of the parasitic lateral bipolar transistor, resulting in a decrease in gain as emitter area is scaled and the emitter periphery-to-area ratio increases. With the new link, the base Gummel number for the parasitic lateral bipolar transistor is reduced sufficiently to cause an increase in bipolar gain as emitter area is scaled.

If the link base implant is blocked from the CMOS areas, the characteristics of the MOSFET transistors remain unaffected.

66

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. I , JANUARY 1994

Emitter tJ I 1

Collector a. conventional approach

Collector

b. without link base Emitter Base

Collector

c. with new link base Fig. 7. PISCES-ZB simulations of a double polysilicon bipolar transistor showing potential contours at \,E = 5 V and \BE = 0 V for the three cases described in the text. Contour lines included for every 0.25 V increment in potential. (a) Link region formed in the conventional fashion (is., active and link base regions merged), a relatively deep link region results. (b) Without the link base implant, insufficient doping in the link base region allows premature collector-emitter punchthrough. (c) With the new link base, the doping in the new link prevents collectoremitter punchthrough.

On the other hand, the new link base process can also be used to form the boron LDD region in a PMOS transistor. By forming the p- LDD region using diffusion rather than the conventional approach of low energy implantation, a considerable reduction in the depth of the boron dopant profile can be achieved. This results in a decrease in boron lateral diffusion and hence AL. This is demonstrated in Fig. 11 which is a plot of electrical channel length as a function of poly gate length. Additionally, a reduction in gate-induced drain leakage current (GIDL) [14], [15] is observed, as is shown in Fig. 12. A modification in the surface concentra- tion under the gate edge would be sufficient to give rise to the observed effect. If the link base dopant is allowed

10-2 4

I- - -conventional approach1

' 1 ' 1 " ' 1 0 3 6 9 12 15

VEB (VI

Fig. 8. Emitter-base breakdown characteristics for double polysilicon bipolar transistors with the new link base versus the conventional approach where active and link base regions are merged by implanting simultaneously. The new link base lowers the lateral electric field at the emitter-base junction edge.

stress time (s) Fig. 9. Results of bipolar hot carrier stress for double polysilicon bipolar transistors with the new link base versus the conventional approach. Degra- dation in base current as a function of stress time for a reverse emitter-base stress of 6 V. Forward characteristics monitored at \ B E = 0.60 V.

1.4

>

0 2 4 6 8 Emitter Periphery-to-Area Ratio

Fig. 10. Normalized transistor gain as a function of emitter periphery-to-area ratio for double polysilicon bipolar transistors with the new link base versus the conventional approach. The gain( 3 ) has been normalized to that measured for the standard0.8 x 2.4pm2 device ( . 3 , ) .

to slightly compensate the n- LDD region in the NMOS device, the lateral under-diffusion or AL is slightly reduced.

HAYDEN er al.: TECHNIQUE FOR FORMING A LINK BASE POLYSILICON BIPOLAR TRANSISTOR 67

/a0- U

0 . 0 4 0.0 0.2 0.4 0.6 0.8 1.0

poly gate length (Fm)

10

10

10

10

10

10

Fig. 11. Electrical channel length as a function OfpolY gate length for PMOS transistors with the conventional LDD versus the new LDD formed with boron penetration.

~ i ~ , 13. Subthreshold tum-on characteristlcs for 25/0.5 p m NMOS tran- sistors with and the l i d base counterdoping the n.region, with the counterdoping, lower gate-induced drain leakage current and a smaller A L result.

= .- .l- I I 10 -I% I I .-

- - 10-1 LJ p i I 10-’J I I I I I 1

2.0 1.0 0.0 -1.0 -2.0 v= (VI

Fig. 12. Subthreshold tum-on characteristics for 25/2 p m PMOS transistors with the conventional LDD versus the new LDD formed with boron pene- tration. Lower gate-induced drain leakage current results with the new LDD formation.

The vertical electric field at the gate edge is also lowered resulting in a small decrease in the gate-induced-drain leakage current (GIDL). Both of these trends can be seen in Fig. 13.

IV. CONCLUSIONS

A new technique for forming a shallow link base in a double polysilicon bipolar transistor has been demonstrated. This simple technique is easily integrated into a BiCMOS process and provides improvements in emitter-base breakdown and resistance to bipolar hot carrier degradation.

ACKNOWLEDGMENT

The authors would like to thank H. Kirsch, C . Lage, R.Sivan, and L. Parrillo for their support and guidance throughout this project.

REFERENCES

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131 M. Sugiyama, H. Takemura, C. Ogawa, T. Tashiro, T. Morikawa, and M. Nakamae, “A 40 GHz ff Si bipolar transistor LSI technology,” IEDM Tec.h. Digest. pp. 221-224, 1989.

[4] L. C. Pamllo, J. R. Pfiester, J.-H. Lin, E. 0. Travis, and R. D. Sivan, “An advanced 0.5 jtm CMOS disposable LDD spacer technology,” in 1989 Symp. on VLSI Technology. p. 31.

[SI Y. Toyoshima, T. Eguchi, H. Hayashida, and K. Hashimoto, “Novel shallow counter doping process and high performance buried channel pMOSFET using boron diffusion through oxide,” in 1991 Symp. on VLSI Technology, pp. 11 1-1 12.

161 J . R. Pfiester, J. D. Hayden, H. C. Kirsch, H.-H. Tseng, and U. Ravaioli, “An ultra-shallow buried-channel PMOST using boron penetration,” IEEE Trans. Electron Devices. vol. 40, p. 207, 1993.

[7] B.-Y. Nguyen, P. Tobin, M. Lien, M. Woo, J. k i s s , and J. D. Hayden, “Framed mask poly-buffered LOCOS isolation for submicron VLSI technology,” in ECS Spring 1990 Meet. Extended Abstracts, vol. 90-1, p. 614.

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68 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41. NO. 1, JANUARY 1994

James D. Hayden (S‘81-M’83-SM’91) received the B.S. degree in engineering physics from the University of Colorado, and the M.S.E.E. degree from the University of Arizona.

Mr. Hayden worked as an RF Test Engineer at Bell Aerospace from 1981 to 1983. In 1983 he joined Advanced Micro Devices as a Modeling Engineer, where he developed circuit simulation models for EPROM and EEPROM products. From 1985 to 1986 he worked at NCr Microelectronics in Colorado Springs, CO, where he had device design

responsibilities in the development of a l p m CMOS process. In 1987 he worked as a Device Physicist at INMOS Corp. Since May 1988, he has been with Motorola’s Advanced Products Research and Development Laboratories. His duties have included bipolar and MOS device design and SRAM bit cell development for 0.50pm and 0.35pm BiCMOS processes. He is now a section manager of 0.25pm BiCMOS SRAM technology development. He has authored or coauthored more than 35 papers and holds 15 US patents.

Mr. Hayden is a member of the Technical Staff and a Distinguished Innovator at Motorola.

J. D. Burnett, for a photograph and biography see IEEE Trans. on Elecrron Devices, vol. 40, no. 6, p. 1121, June 1993.

James R. Bester, for a photograph and biography see IEEE Trans. on Electron Devices, vol. 40, no. 1, p. 207, Jan. 1993.

M. P. Woo, for a photograph and biography see IEEE Trans. on Electron Devices, vol. 39, no. 7, July 1992.