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A Novel PWM Technique for MMCs with High Frequency Link and Natural Capacitor Balancing for Grid-Interfacing of Renewables

Prince Kumar1, Abhijit Kshirsagar2, Daniel Opila3, Ned Mohan4

1,2,4University of Minnesota Twin Cities, Department of Electrical Engineering, Minnesota, MN, USA 3United States Naval Academy, Department of Electrical and Computer Engineering, Annapolis, MD, USA

Email: kumar367@umn.edu

Abstract— This paper presents a new pulse width modulation (PWM) technique for a high-frequency link Modular Multilevel Converter topology for grid-integrated renewables. The topology generates a multilevel output voltage with low harmonic distortion, increased reliability, and design flexibility due to the modular nature of the converter. A central full-bridge converter is connected to multiple High Frequency Link modules via high frequency transformers. Each module produces its own isolated DC voltage, and modules are inserted or bypassed to synthesize large AC voltages. The proposed PWM technique equalizes module utilization without increasing losses, and retains inherent capacitor voltage balancing. Simulation results using SIMULINK models show that the proposed modulation scheme results in better performance than conventional schemes such as level-shifted carrier PWM, phase-shifted carrier PWM, hybrid schemes or nearest-level modulation.

Keywords— Modular Multilevel Converter; Full-Bridge Converter; Full-Bridge Rectifier; High Frequency Transformer; Pulse Width Modulation

I. INTRODUCTION Rapid development in power electronics has allowed greater use of renewables and has reduced our dependence on fossil fuels. Renewable sources such as photovoltaics (PVs) are connected to the grid via so-called grid-interactive inverters [1]. Conventionally, PV or wind plants are connected to the grid via three phase inverters, filters, and line frequency transformers[2, 3]. Although this system is well tested, robust and reliable, it suffers from many shortcomings. The inverters are usually two-level inverters, which need bulky line frequency transformers and filters. Also, since most collection voltages for utility-scale generation are 34.5 kV or higher, a line frequency step-up transformer is used which is often large and heavy. Multilevel converters with high frequency transformers have the potential to overcome many of these drawbacks. Modular multilevel converter (MMC) have a scalable, modular structure due to the use of several identical submodules which can be easily replaced in case of failures, resulting in very low maintenance time [4-7], and has been used in several other applications [8-12].

The modular topology in [10] replaces the traditional 60Hz transformer with multiple compact, lightweight, high frequency transformers. It produces multi-level output voltages, following the sinusoidal waveform, which leads to lower THD. This topology can generate high voltage output suitable for direct connection to a 34.5kV collection grid. Since the power and voltage stresses are distributed across submodules of the multilevel converter, lower rated

components can be used to achieve the desired high voltage and power levels.

Previous work on modulation schemes for this high-frequency link MMC include a level-shifted carrier-based approach [10], which is computationally simple but results in vastly unequal stresses in different modules of the MMC. Alternatively, phase-shifted PWM can equalize module stresses, but results in much higher switching losses. This paper proposes a modified PWM technique based on the level-shifted carrier approach, which equalizes the module stresses without increasing switching losses.

II. POWER CIRCUIT TOPOLOGY The circuit topology of the modular multilevel converter is

shown in figures 1-3. The DC output from a PV, wind or storage system is connected to the Primary H-Bridge converter (Fig. 1), which produces a high frequency AC square wave. The H-Bridge is switched such that output AC voltage has a constant frequency of 20 kHz at a duty ratio of 50%. This high frequency AC is the input for the primary side of the high frequency transformer of each HFL-submodule (Fig. 2). The secondary of each transformer is connected to a diode rectifier, which is connected to a DC capacitor. The DC capacitor acts as the constant voltage source for a full-bridge converter. The outputs of all HFL-submodules are connected in series (Fig. 3) to generate a multilevel voltage output. Each output phase consists of a string of series connected HFL-submodules. Thus, this topology has one primary H-Bridge converter and multiple identical cascaded modules.

Figure 1: Primary H-Bridge Converter

Figure 2: High Frequency Link (HFL) Sub-modules

Figure 3: MMC module connection

Fig. 4 shows the voltage on the HF bus, which is generated by the single, central primary H-Bridge. Gate signals are given to each submodule such that the phase voltage follows the desired sinusoidal waveform. Greater the number of submodules, smaller will be the magnitude of the steps in the output voltage and hence the output voltage will more closely follow the desired sinusoidal waveform. This reduces the harmonic content of the voltage waveform and thus reduces the filter requirement. There is a design tradeoff between the cost of additional modules and the reduction in harmonics. The results shown in this paper are for four HFL submodules per leg. As a result, the output voltage has nine distinct voltage levels (including zero) as shown in Fig. 5.

Figure 4: H-bridge theoretical voltage

Figure 5: Ideal MMC phase voltage

III. MMC MODULATION The most commonly used PWM schemes for MMCs are

based on sinusoidal pulse width modulation (SPWM). In SPWM for MMCs, multiple triangular carrier signals are compared with a sinusoidal waveform (the reference signal) to generate gate pulses. Each module is associated with two carriers. When the reference signal is greater than the both carriers, the module output is +Vc (Q1 and Q2’ on). When the reference signal is less than the both carriers, the module

output is –Vc (Q2 and Q1’ on), and is 0 otherwise (Q1 and Q2 on; or Q1’ and Q2’ on). In general, PWM schemes for MMCs use phase-shifted carriers, level-shifted carriers, or a combination of both (hybrid scheme). This paper presents a new PWM technique and compares it with level-shifted PWM [13], phase-shifted PWM [14], and a hybrid of level and phase-shifted PWM [15]. Existing PWM schemes are reviewed below.

A. Nearest Level Modulation(NLM) In NLM, gate pulses are given sequentially to modules to

generate an output voltage level closest to the desired voltage level (Fig. 6). Although this scheme requires the least computation and has the lowest switching loss as modules only switch N-1 times per half cycle, some modules are stressed much more than others over the fundamental cycle. This can result in accelerated aging, localized heating and premature failure of these modules. This also results in a large capacitor ripple. The simulation results for NLM modulation scheme is as shown in Fig. 7.

Figure 6: Nearest Level Modulation

Figure 7: Simulation results for NLM for MMC (a) submodule capacitor voltage ripple (top trace), A-phase pole voltage (middle trace) and phase current (bottom trace) (b) A-phase pole voltage (top trace), capacitor voltage ripple SM1-SM4 (Lower four traces)

B. Level Shifted PWM In level-shifted PWM [13], several level-shifted carrier

signals are compared with a reference signal to generate gate signals for every sub-module (Fig. 8). This results in an average output voltage that is much closer to the desired

voltage compared to NLM, although with higher switching loss. It can be seen that only one module switches at a time at a desired frequency fSW while the remaining modules do not switch. As in NLM, submodules in level-shifted PWM have unequal stresses.

Figure 8: Level Shifted Modulation

C. Phase Shifted PWM In phase-shifted PWM [14], carrier signals have the same

amplitude and level, but are phase-shifted, such that they are equally spaced in one switching period (Fig. 9). This scheme results in equal stress on all submodules and generates extremely low harmonics even with a low number of submodules. However, all the modules in phase-shifted PWM switch throughout the fundamental cycle, leading to higher switching losses.

Figure 9: Phase Shifted Modulation

D. Hybrid PWM Hybrid modulation schemes [15] use a combination of

level and phase-shifted carriers. Carriers are divided into groups. Carriers within groups are at the same level, and each group is level-shifted. Carriers within each group are phase- shifted from each other. Fig. 10 shows hybrid PWM with two groups of four carriers each. Hybrid PWM provides a trade-off between level and phase-shifted PWM in terms of loss, capacitor ripple, and equalization of module stress.

Figure 10: Hybrid modulation

IV. PROPOSED PWM SCHEME In the proposed PWM scheme, level-shifted carriers are

used, but carriers are re-assigned to modules after every quarter Figure 11: Proposed Level Shifted Modulation

cycle to equalize module stresses without increasing switching loss. This ensures that the module which is turned ‘on’ first in the fundamental period is turned off first, in a “FIFO” approach. Gate signal reassignment is as shown in Fig. 11. Since all the carriers are phase-aligned, this can be done without causing the output voltage to glitch.

V. RESULTS Table I shows the simulation parameters used to determine

the capacitor voltage ripple. It should be noted that capacitor voltage ripple for a modulation technique depends on various parameters, like capacitance value, arm inductance, number of submodules in a leg. The effect of different PWM techniques on the MMC with respect to output voltage, capacitor ripple, harmonics and losses are discussed in the following subsections.

TABLE I. Simulation Parameters

Parameter Values No. of Submodules per leg 4 Transformer frequency 20kHz Transformer turns ratio 1:1 Duty Cycle 50% Output frequency 60Hz 3-Phase output power 1.36kW Submodule Capacitance 2.2mF Arm Inductance 10mH Input Voltage 50V HFL Vmod 50V PWM Carrier frequency 10 kHz

Figure 12: Simulation results for PWM schemes for the MMC showing submodule capacitor voltage ripple (top trace), A-phase pole voltage (middle trace) and phase current (bottom trace): (a) Proposed PWM scheme (b) Level shifted PWM

Figure 14: Simulation results for PWM schemes for the MMC showing submodule A-phase pole voltage (top trace), capacitor voltage ripple SM1-SM4 (Lower four trace respectively): (a) Proposed PWM scheme (b) Level shifted PWM

Figure 16: Output Voltage FFT Analysis 100k Hz window

Figure 13: Simulation results for PWM schemes for the MMC showing submodule capacitor voltage ripple (top trace), A-phase pole voltage (middle trace) and phase current (bottom trace): (a) Phase shifted PWM (b) Hybrid PWM

Figure 15: Simulation results for PWM schemes for the MMC showing submodule A-phase pole voltage (top trace), capacitor voltage ripple SM1-SM4 (Lower four trace respectively): (a) Phase shifted PWM (b) Hybrid PWM

A. Output Voltage and Current Fig. 12-13 show the capacitor voltage Vc for the sub-modules, output voltage Vout, and the current Iout for phase A in the proposed PWM scheme, level-shifted, phase-shifted, and hybrid PWM.

B. Capacitor Voltage Fig. 14-15 show the DC-link capacitor voltage of phase A for all submodules (SM) for different modulation types. The voltage ripple for phase-shifted PWM is minimum while that of the Modified level-shifted or level-shifted PWM is maximum.

Table II: Losses for different PWM technique

PWM Technique Semiconductor Loss over all submodules (W)

NML 50 Level Shifted 70 Phase Shifted 210

Hybrid 130 Proposed Level Shifted 70

Table III: Summary of different PWM technique

PWM Technique

Semiconductor Loss(W)

Capacitor Ripple (mV)

Module Utilization

NLM 50 55 Unequal Level Shifted 70 60 Unequal Phase Shifted 210 30 Equal

Hybrid 130 50 Unequal Proposed

Level Shifted 70 60 Equal

C. Harmonics and FFT analysis Fig. 16 shows the FFT analysis for the output voltage with different PWM techniques. The phase-shifted PWM technique has the lowest subharmonic content of all the PWM techniques discussed here.

D. Switching Losses The two components of the losses in the switch are turn-on loss and switching loss. Conduction loss is independent of the PWM techniques while switching loss depends greatly on the selected PWM technique. The switching loss is observed to be the highest in phase-Shifted PWM followed by hybrid PWM technique and the least in level-Shifted and modified level-shifted PWM. A loss analysis is done using SIMULINK as described previously [16] and the obtained losses are shown in the table II. The model consists of IGBT and Diode losses. IGBTs losses includes switching and conduction loss, while diodes losses consist of reverse recovery and conduction loss. The obtained losses are the sum of all the losses incurred in the switches of the submodules of MMC. The losses incurred in primary converter is not considered in the analysis as it is equal in all PWM techniques and is mainly due to conduction loss of switches. The total output power of the three-phase converter in the simulation was 1.36 kW.

VI. CONCLUSION This paper presents a new PWM scheme for a high-

frequency link MMC converter for the grid integration of PV and wind. The proposed PWM technique has equal module

stress with low switching losses, thereby including the benefits of both level-shifted and phase-shifted techniques. Detailed analysis of the various PWM techniques is summarized in table III. This also includes a comparison of switching losses and capacitor ripple with analytical models SIMULINK simulation.

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