A PARALLEL-SERIES TWO BRIDGE DC/DC CONVERTER FOR PV …

A PARALLEL-SERIES TWO BRIDGE DC/DC CONVERTER FOR

PV POWER CONDITIONING SYSTEMS USED IN HYBRID

RENEWABLE ENERGY SYSTEMS

by

Amish Ansuman SERVANSING

A thesis submitted to the Department of Electrical and Computer Engineering

In conformity with the requirements for

the degree of Masters of Applied Science

Queen’s University

Kingston, Ontario, Canada

(April, 2012)

Copyright ©Amish Ansuman Servansing, 2012

ii

Abstract

This thesis presents a parallel-series two-bridge DC/DC converter topology with the ability to

operate with ZVS over a wide input and load range. The intended application is power

conditioning systems (PCS) of photovoltaic (PV) arrays used in hybrid renewable energy system

architectures. The proposed topology provides two degrees of freedom which allows the PV-PCS

to regulate the DC-link voltage, while tracking the maximum power point (MPP) of the PV array.

This topology distributes the main power into two bridges and the phase-shift between the two

bridges and provides another degree of freedom for the PCS to track the MPP. The proposed

topology is also able to achieve soft-switching over a wide range. The power conditioning system

shows a modular structure to efficiently transfer the power to the load as the main power is

divided between two bridges. In addition, the proposed control scheme provides complete

decoupling between the input side controller from the output side controller in order to perform

MPPT and regulate the the DC-link voltage simultaneously. A 2kW Experimental prototype has

been provided to validate the feasibility and performance of the converter. Experimental results

prove that the converter is able to regulate the DC-link voltage and track the maximum power

extracted from the PV array simultaneously.

iii

Acknowledgements

I wish first of all to thank my supervisor Dr. Praveen Jain, Director of ePOWER, the Queen’s

Centre for Energy and Power Electronics Research. I am also deeply grateful to Dr. Majid

Pahlevaninezhad for his sound advice, constructive discussions and enduring friendship during

the course of my project. I also wish to recognise the continuous support and affection of my

parents, sister and childhood friend, who always encouraged me to give the best of myself.

Finally, I would like to acknowledge the precious financial support from NSERC and the

Department of Electrical and Computer Engineering at Queen’s University which was available

to me through Dr. Praveen Jain.

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Table of Contents

Abstract ............................................................................................................................................ ii

Acknowledgements ......................................................................................................................... iii

Chapter 1 Introduction to Hybrid Distributed Generation Systems ................................................. 1

1.1 General Introduction .............................................................................................................. 1

1.2 HDGS in an Urban and Remote or Rural Areas .................................................................... 2

1.3 HDGS Requirements and System Configurations ................................................................. 3

1.3.1 Centralized and Distributed Schemes ............................................................................. 4

1.3.2 Grid Connected and Stand-Alone Systems ..................................................................... 6

1.3.3 HDGS System Arrangements ......................................................................................... 7

1.3.3.1 Common DC-Bus Configuration ............................................................................. 7

1.3.3.2 Common AC-Bus Configuration ............................................................................. 9

1.3.3.3 Hybrid-Coupled System Configuration ................................................................. 11

1.4 Proposed Architecture of Hybrid-Coupled System ............................................................. 11

1.5 Power Generation Technologies and Energy Storage Devices for HDGS .......................... 14

1.6 Incentives for HRES and the Energy Demand in the ICT Sector ........................................ 14

1.7 Objectives and Scope ........................................................................................................... 15

1.8 Chapter Summary ................................................................................................................ 17

Chapter 2 Photovoltaic Power Conditioning Systems ................................................................... 19

2.1 Motivation for Photovoltaic Power ...................................................................................... 19

2.2 Photovoltaic Cell Theory ..................................................................................................... 20

2.3 Photovoltaic Characteristics ................................................................................................. 21

2.4 PV Power Conditioning System Configurations and Requirements .................................... 29

2.5 Literature Review................................................................................................................. 31

2.6 Chapter Summary ................................................................................................................ 38

Chapter 3 Proposed 2-Bridge Series-Parallel Topology ................................................................ 39

3.1 Introduction .......................................................................................................................... 39

3.2 Circuit Description ............................................................................................................... 39

3.3 Operating Principle .............................................................................................................. 40

3.4 Steady State Analysis ........................................................................................................... 43

3.4.1 Mode 1: to≤t<t1 ............................................................................................................. 46

3.4.2 Mode 2: t1≤t<t2 ............................................................................................................. 48

3.4.3 Mode 3: t2≤t<t3 ............................................................................................................. 50

v

3.4.4 Mode 4: t3≤t<t4 ............................................................................................................. 50

3.4.5 Mode 5: t4≤t<t5 ............................................................................................................. 53

3.4.6 Mode6: t5≤t<t6 .............................................................................................................. 55

3.4.7 Mode 7: t6≤t<t7 ............................................................................................................. 57

3.4.8 Mode 8: t7≤t<t8 ............................................................................................................. 59

3.4.9 Mode 9: t8≤t<t9 ............................................................................................................. 61

3.4.10 Mode 10: t9≤t<t10 ........................................................................................................ 63

3.5 Design Considerations ......................................................................................................... 65

3.5.1 Selection of Turns Ratio and Leakage Inductance ........................................................ 65

3.5.2 Selection of Snubber Capacitors ................................................................................... 66

3.5.3 Determining the Dead-Time ......................................................................................... 67

3.6 Extension of ZVS to LegB2 .................................................................................................. 68

3.6.1 Selection of Auxiliary Inductance ................................................................................. 68

3.6.2 Selection of the Voltage Divider Capacitors ................................................................. 70

3.7 Simulation Results ............................................................................................................... 71

3.7.1 Verification of Circuit Operation .................................................................................. 72

3.7.2 Verification of ZVS ...................................................................................................... 75

3.8 Experimental Results ........................................................................................................... 77

3.8.1 Prototype Specifications ............................................................................................... 77

3.8.2 Prototype Components .................................................................................................. 78

3.8.3 Key Operational Experimental Waveforms .................................................................. 79

3.8.4 Verification of ZVS ...................................................................................................... 82

3.9 Features of Proposed Converter ........................................................................................... 85

3.10 Chapter Summary .............................................................................................................. 87

Chapter 4 Non-Linear Control Scheme ......................................................................................... 88

4.1 Introduction .......................................................................................................................... 88

4.2 Output Controller Design ..................................................................................................... 88

4.2.1 Ouput Voltage Loop State-Space Model ...................................................................... 88

4.2.2 Ouput Voltage Loop Transfer Function ........................................................................ 96

4.2.3 Output Voltage Loop Compensator Design .................................................................. 97

4.2.4 Digital Implementation of Output Controller ............................................................... 99

4.3 Linearized Input State-Space Model .................................................................................. 100

4.3.1 Linearized Input Transfer Function ............................................................................ 106

4.3.2 Input Coupled Factors ................................................................................................. 107

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4.3.3 Input Voltage Loop Compensator Design................................................................... 108

4.4 Non-Linear Controller Design ........................................................................................... 110

4.4.1 Non-Linear Input Model ............................................................................................. 110

4.4.2 Input-Side Decoupling Factors ................................................................................... 110

4.5 Overall Non-Linear Control Scheme Digital Implementation ........................................... 113

4.6 Simulation Results ............................................................................................................. 114

4.7 Experimental Results ......................................................................................................... 116

4.8 Chapter Summary .............................................................................................................. 119

Chapter 5 Conclusions ................................................................................................................. 120

5.1 Summary ............................................................................................................................ 120

5.2 Contributions ..................................................................................................................... 121

5.2.1 Major Contributions .................................................................................................... 121

5.2.2 Minor Contributions .................................................................................................... 122

5.3 Suggestion for Future Work ............................................................................................... 122

References .................................................................................................................................... 123

Appendix A PV Characteristics Curve Generator ....................................................................... 127

Appendix B Input and Output Transfer Function Script .............................................................. 130

Appendix C PSIM Converter Schematic ..................................................................................... 132

vii

List of Figures

Figure 1.3.1: Centralized Power Conditioning System .................................................................... 5

Figure 1.3.2: Distributed Power Conditioning System .................................................................... 6

Figure 1.3.3: Schematic of Common DC-Bus Systems ................................................................... 8

Figure 1.3.4: Schematic of Common PFAC-Bus Approach ............................................................ 9

Figure 1.3.5: Schematic of Common HFAC-Bus Configuration ................................................... 10

Figure 1.3.6: Schematic of Hybrid-Coupled System ..................................................................... 11

Figure 1.4.1: Existing Hybrid Coupled HDGS Architecture ......................................................... 12

Figure 1.4.2: Proposed Hybrid-Coupled HDGS Architecture ....................................................... 13

Figure 2.2.1: Cross-sectional view of photovoltaic cell ................................................................. 21

Figure 2.3.1: PV Cell Equivalent Circuit Model ........................................................................... 22

Figure 2.3.2: I-V Characteristic Curve at STC .............................................................................. 24

Figure 2.3.3: P-V Characteristic Curve at STC ............................................................................. 25

Figure 2.3.4: I-V Characteristics for different Irradiance Levels ................................................... 26

Figure 2.3.5: P-V Characteristics for different Irradiance Levels .................................................. 27

Figure 2.3.6: I-V Characteristics at different Temperatures .......................................................... 28

Figure 2.3.7: P-V Characteristics at different Temperatures ......................................................... 29

Figure 2.5.1: Conventional PSM-FB Topology ............................................................................. 31

Figure 2.5.2: Ideal Waveforms of Conventional PSM-FB ............................................................ 32

Figure 2.5.3: Two-Bridge ZVS PSM-FB Converter ...................................................................... 34

Figure 2.5.4: Hybrid PSM-FB Converter ...................................................................................... 35

Figure 2.5.5: HPMC with Current-Doubler Rectifier .................................................................... 36

Figure 2.5.6: HPMC with Center-Tapped Rectifier ....................................................................... 37

Figure 3.2.1: Proposed Converter Schematic ................................................................................. 40

Figure 3.3.1: Block Diagram Representation of the Proposed Topology ...................................... 41

Figure 3.3.2: Non-bounded Operational Waveforms ..................................................................... 42

Figure 3.4.1: Ideal Waveforms of Proprosed Converter ................................................................ 45

Figure 3.4.2: Equivalent Circuit for Mode 1 (t0≤t≤t1) ................................................................... 47

Figure 3.4.3: Equivalent Circuit for Mode 2 (t1 ≤ t ≤ t2) ............................................................... 49





viii



Figure 3.4.10: Equivalent Circuit for Mode 9 (t8 ≤ t ≤ t9) ............................................................. 62

Figure 3.4.11: Equivalent Circuit for Mode 10 (t9 ≤ t ≤ t10) .......................................................... 64

Figure 3.5.1: Snubber Capacitors of a Leg .................................................................................... 66

Figure 3.6.1: Auxiliary Network Schematic .................................................................................. 68

Figure 3.6.2: Auxiliary Inductor Voltage and Current Waveforms ............................................... 69

Figure 3.7.1: Simulated Waveforms: 50% Load, Vin = 380 V (200 V/div, 27 A/div) .................. 73

Figure 3.7.2: Simulated Waveforms: 100% Load, Vin = 300V (200V/div, 27A/div) ................... 74

Figure 3.7.3: Simulated Waveforms: Leading and Lagging Legs ZVS, 50% Load, Vin = 380V

(200V/div, 27A/div) ....................................................................................................................... 75


(200V/div, 27A/div) ....................................................................................................................... 76

Figure 3.8.1: Experimental Waveforms 95% load, Vin = 380V .................................................... 79

Figure 3.8.2: Experimental Waveforms at 55% load and Vin = 300V ........................................... 80

Figure 3.8.3: Experimental Waveforms at 55% load and Vin = 300V ........................................... 81

Figure 3.8.4: Experimental Waveforms at 100% load and Vin = 300V ......................................... 82

Figure 3.8.5: Experimental Waveforms at Iaux = 5A, Vin = 380V ............................................... 83

Figure 3.8.6: Experimental Waveforms at 100% load and Vin = 300V (Rising Edges) ................ 84

Figure 3.8.7: Experimental Waveforms at 100% load and Vin = 300V (Falling Edges) ............... 85

Figure 4.2.1: Block diagram of proposed converter ...................................................................... 89

Figure 4.2.2: Rectifier voltage waveform ...................................................................................... 90

Figure 4.2.3: Equivalent output circuit for time interval TA and TC ............................................. 91

Figure 4.2.4: Equivalent output circuit for time interval TB .......................................................... 92

Figure 4.2.5: Equivalent output circuit for time interval TD .......................................................... 93

Figure 4.2.6: Output transfer function bode plot ........................................................................... 97

Figure 4.2.7: Output closed loop bode plot .................................................................................... 98

Figure 4.2.8: Output Controller Block Diagram ............................................................................ 99

Figure 4.3.1: Key waveforms for input controller ....................................................................... 101

Figure 4.3.2: Equivalent input circuit for time interval TA and TC ............................................. 102

Figure 4.3.3: Equivalent input circuit for time interval TB .......................................................... 103

Figure 4.3.4: Input transfer function bode plot ............................................................................ 107

Figure 4.3.5: Input closed loop bode plot .................................................................................... 109

Figure 4.4.1: Input Controller Block Diagram ............................................................................. 111

ix

Figure 4.4.2: MPPT Algorithm Flowchart ................................................................................... 112

Figure 4.5.1: Simultaneous MPPT and Output Voltage Control Scheme .................................... 113

Figure 4.6.1: Load Step Change from 80% to 100% ................................................................... 115

Figure 4.6.2: Load Step Change from 100% to 80% ................................................................... 116

Figure 4.7.1: Experimental waveforms of Vpv from Voc to Vmpp ............................................ 117

Figure 4.7.2: Experimental waveforms of Ipv from Isc to Impp ................................................. 118

Figure 4.7.3: Experimental waveforms of Ipv from Isc to Impp ................................................. 119

x

List of Tables

Table I: Simulation Model Parameters .......................................................................................... 71

Table II: Experimental Prototype Specifications ........................................................................... 77

Table III: Experimental Prototype Components ............................................................................ 78

xi

List of Acronyms

GHG Greenhouse Gas Emissions

DG Distributed Generation

HDGS Hybrid Distributed Generation Systems

MPPT Maximum Power Point Tracking

PV Photovoltaic

SAA Stand-Alone

GC Grid-Connected

UPS Uninterruptible Power Supply

PFAC Power Frequency AC

HFAC High Frequency AC

HRES Hybrid Renewable Energy System

MT Microturbine

FIT Feed-in Tariff

ICT Information and Communications Technology

OPA Ontario Power Authority

STC Standard Test Conditions

MPP Maximum Power Point

ZVS Zero Voltage Switching

PSM-FB Phase Shift Modulated Full-Bridge

SOFC Solid Oxide Fuel Cell

HPMC Hybrid Phase Modulated Full-Bridge Converter

CCM Continuous Conduction Mode

DOF Degree of Freedom

xii

Nomenclature

𝑡𝑑 Dead-time between MOSFET gate signals

𝐿𝐴𝑢𝑥 Auxiliary inductance (H)

𝐶𝑠𝑏 Snubber capacitance (F)

𝑁𝑠 𝑁𝑝⁄ Transformer turns ratio

𝐿𝑙𝑘 Leakage inductance (H)

𝐿𝑠 Transformer series inductance (H)

𝐶𝑎 Auxiliary capacitance (F)

𝐿𝑓 Output filter inductance (H)

𝐶𝑓 Output filter capacitance (F)

𝑓𝑠 Switching frequency (Hz)

𝑇𝑠 Switching period (s)

𝑖𝑝𝑘 Peak primary current (A)

𝑖𝑝𝑘_𝑎𝑢𝑥 Peak auxiliary inductor current (A)

𝑉𝑖𝑛 Input DC voltage (V)

𝑉𝑜𝑢𝑡 Output DC-Link voltage (V)

𝑃𝑜 Output power (W)

𝑖𝑝𝑟𝑖 Primary voltage of the transformer

𝑣𝑠𝑒𝑐 Secondary voltage of the transformer (V)

𝜙 Phase-shift between leading and lagging leg pulses

𝜓𝐵𝐵 Phase-shift between leading and lagging bridges

1

Chapter 1

Introduction to Hybrid Distributed Generation Systems

1.1 General Introduction

As the global demand for energy continually increases, oil reserves are being depleted and

greenhouse gas emissions (GHG) are rising. Consequently, there is an important need for

alternative and renewable energy generation projects. Traditionally, large, remote centralized

power plants use nuclear, coal, oil or hydro to generate electricity. These plants are generally

large, complex and require high maintenance. They are also detrimental to the environment as

they contribute substantially to GHG emissions. The utility companies responsible for the

distribution of the electricity are the ones located closer to the end-users in densely populated

areas. This traditional generation and distribution model is archaic and lacks reliability,

efficiency, and security. These are paramount characteristics when a city’s entire population often

depends on a single provider. Smaller Distributed Generations (DG) solutions provide a better

alternative for power quality and energy management. They are able to perform voltage

regulation, protection, control tasks with a higher reliability compared to their centralized

counterpart.

U.S. distributors are expected to operate with at least 99.9% reliability and are permitted a

cumulative total of 8 hours of power outage per year [1]. However, this margin is unacceptable

for critical loads such as airports, hospitals, military applications and telecommunications central

offices or data centers which have critical service level agreements. Smaller DG systems such as

hybrid distributed generation systems (HDGS) are located closer to the end-users and can run as

sustainable backup power solution with the grid. This new system harnesses energy from

2

multiple sources and also provides storage capabilities. Not only does this solution prove to be a

cost-effective and efficient alternative but also improves the entire system capacity, security and

reliability. Losses due to transmission will decrease as fewer high voltage power lines are needed

over long distances and unused energy can be sold back to the grid. Harnessing energy from

various sources, however, can prove challenging as the system requires a certain level of

coordination. In some cases, complex supervisory control schemes are needed to maximize the

sustainability of the entire system. The key requirements for the hardware design of such systems

are adequate technology selection and generation unit sizing. A robust control scheme is also

needed in order to ensure optimal operation of the hardware in order to achieve high reliability

and efficiency [2], [3], [4].

1.2 HDGS in an Urban and Remote or Rural Areas

Estimates show that approximately 1.5 billion people around the world do not have access to

electricity [5], [6]. 21% of the world’s population which is mostly concentrated in Africa and

southern Asia are “energy poor” [7]. They face problems such as lighting their premises, cooking,

heating and access to medical facilities. Up to 85% of the “energy poor” population lives in rural

areas or in isolated communities. Extending the grid in those remote areas is very expensive and

unfeasible. Some areas are not very accessible and the cost of fuel transportation would be very

high and unaffordable by the community [8], [9]. The selection of a hybrid distributed generation

system could provide a low cost sustainable energy infrastructure compared to the installation

cost associated with the extension of the grid in rural and remote areas. This system would be

attractive due to its relatively low maintenance and operation cost [10]. The implementation of

such a system could provide strictly clean energy from renewable sources, although alternative

low polluting energy sources could also be used.

3

Estimates show that almost 79% of the world’s population is concentrated in cities. Cities already

rely on the power grid heavily and use centralized distribution to power many essential

institutions necessary for a society. There are numerous accounts where the distribution was

interrupted due to grid faults or poor maintenance of generation and distribution infrastructures.

This in turn caused the paralysis of manufacturing plants, commerce, transportation systems and

critical infrastructures such as telecommunication systems as well as hospitals [11], [12]. The

obvious solution to increase capacity would be to build a new generation plant. The price of land

in densely populated urban areas, however, is generally very expensive and the construction of

new power generation plants in cities is often contested [13]. The integration of residential scale

hybrid renewable energy distributed generation systems [14] or similar larger scale systems

installed on top of buildings and factories could be a possible alternative [15]. Such systems could

be low in complexity consisting of several roof-top solar panels and a battery for storage in

residential case. In a larger scale system, the addition of a wind turbine and fuel cells to the

already existing solar panels could increase the capacity further. These systems should not only

be flexible but also scalable and modular. This would facilitate the integration of more energy

sources or storage devices to the existing infrastructure. The peak load requirements, as a result,

would be lowered with little or no ecological impact [16].

1.3 HDGS Requirements and System Configurations

Due to the uncontrollable nature of some renewable energy sources, a choice of diversified multi-

source generation configurations and storage devices are required to ensure reliability and

effectiveness of sustainable autonomous hybrid distributed generation systems. For instance,

many remote cellular base stations that are too far away from the grid were supplied by diesel

generators [17]. These generators require maintenance and refueling which is relatively expensive

4

and unsustainable. New green solutions have emerged and HDGS are slowly being implemented

to supply these base transceiver stations. Such solutions could be expanded to supply in

electricity to houses, schools and hospitals in remote locations. They could also be extended to

military and critical emergency response equipment in the event of natural disasters where the

grid is inaccessible.

1.3.1 Centralized and Distributed Schemes

There are generally two schemes for such hybrid systems: distributed and centralized. The

primary objective of the centralized, system (shown in Figure 1.3.1), is to endure continuous

operations of the system rather than supplying specific critical loads. In these configurations, one

large converter or inverter is used to perform all the necessary power processing from every

source to supply all the loads. This method is currently used in large scale applications, which

require 3-phase input. Its lower initial cost, little and easy maintenance and low operation costs

make the central approach attractive [18], [19]. This approach, however, bears severe limitations,

such as power losses due to a centralized Maximum Power Point Tracking (MPPT) scheme and

the lack of flexibility as each one is custom designed for a specific capacity. The quality of power

supplied or injected is also low due to the presence of higher current harmonics [20]. Although,

the entire system could fail due to the failure of the central converter, redundant converters could

be introduced as a backup alternative [21]. This would in turn increase the overall cost and

complexity of the system.

5

PV

PV

PV

Centralized Power Conditioning

SystemDC/AC Inverter

UtilityGrid/ACLoad(s)

Figure 1.3.1: Centralized Power Conditioning System

The distributed configuration in such hybrid systems is shown in Figure 1.3.2. The input

Photovoltaic (PV) blocks can represent either a single solar panel or a string of panels. In this

scheme a few separate power conditioning converters operate in parallel to supply the critical

loads which exhibit increased reliability due to redundancy and increased flexibility due to

modularity. The modular characteristic of the implementation allows for an easier upgrade when

higher capacity is required. Due to each power processing unit’s quick dynamic response, fast and

precise load sharing between the units is mandatory. Such implementations could require the use

of complicated control schemes and would add complexity to the system.

6

PVDC/AC

InverterModule

PVDC/AC

InverterModule

PVDC/AC

InverterModule

Utility Grid/AC

Load(s)

AC Bus

Figure 1.3.2: Distributed Power Conditioning System

1.3.2 Grid Connected and Stand-Alone Systems

Hybrid distributed generation systems can be implemented distinctively as stand-alone, grid-

connected or hybrid mode systems. Stand-Alone (SA) systems are generally used in remote areas

as an alternative to the grid or as backup power solutions. SA systems require power conditioning

units and supervisory control dependent on the system’s arrangement and the load requirements.

Grid-Connected (GC) systems can be used for harvesting energy and requires a connection to the

grid. This second arrangement generally requires additional power conditioning stages and a

more complex control scheme to ensure that the system injects high quality current and is

synchronized with the grid, while complying with the regional standards. The third configuration

features an additional capability where the system can both supply a load and inject current in the

grid simultaneously. This arrangement requires even more complex control strategies as it not

only needs to fulfill the individual requirements of the SA and GC configurations but should also

7

be able to transition between the different modes without compromising the system’s

effectiveness. Transitioning between the different modes of operation should be quick and precise

in order to ensure an uninterruptible operation of the system similar to an Uninterruptible Power

Supply (UPS). The fluctuation in voltage and current could affect the quality of the current

injected or cause instability in the system [22], [23]. Transitions in such systems should be

seamless to reduce any harmonics that could arise due these sudden changes.

1.3.3 HDGS System Arrangements

HDG systems are comprised of several energy sources that differ in their behavior and it is

therefore necessary to have a well-defined framework that can provide a few procedures for

arranging the energy sources, interfacing the power conditioning units and connecting the loads in

order to form an integrated scheme [24], [25]. A few common integrated schemes are briefly

outlined below.

1.3.3.1 Common DC-Bus Configuration

The common DC-Bus configuration, shown in Figure 1.3.3 below, allows all the energy sources

to be connected to a common DC-Bus through adequate power processing units. Some DC-

sources can be connected directly to the DC-Bus if their output matches the regulation

requirements required by the bus. If the system has DC-loads, they can be directly interfaced to

the DC-Bus or through DC/DC converters to achieve appropriate regulation. In addition, the

system can be interfaced to a utility grid or supply AC-loads through the use of bidirectional

inverters which will perform the required power conditioning. The advantage of this modular

configuration is that no synchronization is required between the energy sources and the DC-Bus

when they are integrated to the system. The supervisory control for such systems needs to have a

fast dynamic response and therefore needs to perform power-sharing and regulate the output

8

quickly and precisely. This is an important requirement as any disturbances in the system could to

affect the other power conditioning units. Instability in the system could also cause the loss of

output regulation which in turn could affect the DC-loads. In the event that the inverter fails the

system will not be able to supply power to the AC-loads in the system. One solution could be to

use several inverters with lower power ratings which could be connected in parallel. An

additional inverter could also be used for redundancy. This solution would, however, increase the

cost of the system and would require supplementary supervisory control.

DC/DCPCS

DC/DCPCS

Bidirectional DC/DC

Converter

DCLoads

DC/AC Inverter

ACLoads

AC Bus

60/50HzUtilityGrid

DC Bus

PV

PV ArrayDC Energy

Source

Wind Turbines

DC Generator

Source

Storage Device

DC Energy Sink/Source

Figure 1.3.3: Schematic of Common DC-Bus Systems

9

1.3.3.2 Common AC-Bus Configuration

The common AC-Bus configurations can be further divided into two distinct sub-categories: the

common PFAC-bus and HFAC-bus configurations. The first method has a common Power

Frequency AC (PFAC) bus (shown in Figure 1.3.4). All sources can be either connected to the

PFAC-bus directly or through their respective power conditioning unit. The utility grid can also

be directly interfaced to the bus as well as PFAC-loads. DC-loads can also be interfaced through

an AC/DC rectifier which is at the expense of adding an additional power converter. This

arrangement is more reliable as any malfunctioning energy sources can be isolated from the rest

of the system without impacting any of the other energy sources. This system is not only modular

but it is also suitable for grid connection as the output is standardized and complies with the

region’s standards. Such systems require more complex control schemes as they have to perform

power factor and harmonic distortion correction.

DC/ACPCS

AC/ACPCS

Bidirectional Converter

PFAC Bus

ACLoads

PV

PV ArrayDC Energy

Source

Wind Turbines

AC Energy Source

Storage Device


AC/DCPCS

60/50HzUtilityGrid

DCLoads

Figure 1.3.4: Schematic of Common PFAC-Bus Approach

10

The second approach (generally used in space station applications), has a High Frequency AC

(HFAC) bus (shown in Figure 1.3.5) where all the energy sources can be connected either directly

or through their respective power conditioning unit. HFAC loads could be directly interfaced to

the bus whereas DC-loads have to be interfaced through an AC/DC rectifier. Such systems have

higher overall efficiency and higher order harmonics can be easily filtered at higher frequencies.

The higher frequency operation of the system, as a result, allows a reduction in the physical size

and weight of harmonic filters and magnetics used compared to the ones used in the PFAC

approach. This system, however, requires custom built magnetic components and a custom EMI

filter design due to the high frequency operation. Such a system requires a more complex control

compared to the scheme used in its common DC-BUS counterpart. The overall cost of such a

system is higher than its PFAC counterpart [26].

DC/ACPCS

PCS

BidirectionalConverter

PV

PV ArrayDC Energy

Source

Micro Turbines

HFAC Energy Source

Storage Device


HFAC Bus

HFACLoads

AC/DCPCS

DC Bus

DCLoads

DC/ACInverter

PFAC Bus

PFACLoads

60/50HzUtilityGrid

Figure 1.3.5: Schematic of Common HFAC-Bus Configuration

11

1.3.3.3 Hybrid-Coupled System Configuration

The hybrid-coupled system, shown in Figure 1.3.6 below is a more flexible and modular design

compared to the common DC-bus and common AC-bus configurations. The diverse energy

sources can be connected to either a DC-bus directly (or through a power conditioning unit if

necessary) and also to a PFAC-bus directly (or through an adequate power processing unit instead

of being connected to a single bus). This implementation is cost-effective, more efficient and

more reliable than its counterparts. The supervisory control and energy management schemes,

however, are more involved compared to the previously outlined configurations.

AC/ACConverter

DCLoads

DC/AC Inverter(s)

DC Bus PFAC Bus

PFACLoads

60/50HzUtilityGrid

PFAC Energy Sources

DC/DCPCS

DC/DCPCS

Bidirectional DC/DC

Converter

PV

PV ArrayDC Energy

Source

Wind Turbines

DC Energy Source

Storage Device


Figure 1.3.6: Schematic of Hybrid-Coupled System

1.4 Proposed Architecture of Hybrid-Coupled System

Existing hybrid-coupled distributed generation system are configured such that the DC-DC PCS

which are connected to the DC-bus track the MPPT of the PV array or the wind turbines (shown

in Figure 1.4.1). The DC-AC PCS is responsible of reducing the fluctuations that may occur on

the DC-BUS, regulates the quality of the current injected into the grid and ensures

12

synchronization with the grid (shown in Figure 1.4.1). The system also requires coordination and

management which is provided by the supervisory control.

AC/ACConverter

DCLoads

DC/AC Inverter(s)

DC Bus PFAC Bus

PFACLoads

60/50HzUtilityGrid

PFAC Energy Sources

DC/DCPCS

DC/DCPCS

Bidirectional DC/DC Converter

PV

PV ArrayDC

Energy Source

Wind Turbines

AC Energy Source

Storage Device


MPPT

MPPT

IPVVPV

IgenVgen

Σ +-

H11(s)

Σ +-

Vmpp

Vmpp

H21(s)

Σ H12(s)

H22(s)

Vbus

Vref

Σ igrid

ig*

Figure 1.4.1: Existing Hybrid Coupled HDGS Architecture

This system configuration however bears limitations. The performance of the DC-AC converters

deteriorate as they have to operate with a wide input voltage range and low bandwidth. The

system cannot supply the critical DC-loads if the DC-AC converters were not operational. The

DC-loads are also considered as an additional disturbance on the DC-bus and could cause

instability in the system as the DC-AC inverters cannot provide fast transient responses. The

supervisory control must then take on an additional burden to ensure the stability in the event the

inverters would fail.

13

The new proposed hybrid-coupled system configuration shown in Figure 1.4.2 could overcome

those limitations. The upstream DC-DC converters would be responsible of tracking the MPP and

regulate the DC-bus voltage. This would enable the DC-bus voltage to be regulated such that the

DC-AC converters can operate with a lower input voltage range and the DC-loads to have a

regulated input voltage. This would improve the performance of the DC-AC PCS. The fast

transient response required by the DC-loads can now also be met, therefore improving the system

stability and decreasing the supervisory control complexity.

AC/ACConverter

DCLoads

DC/AC Inverter(s)

DC Bus PFAC Bus

PFACLoads

60/50HzUtilityGrid

PFAC Energy Sources

DC/DCPCS

DC/DCPCS

Bidirectional DC/DC

Converter

PV

PV ArrayDC

Energy Source

Wind Turbines

AC Energy Source

Storage Device


H22(s)

Σ

igrid

igref

MPPTIPV

VPV Σ +-

H11(s)Vmpp

Σ

H13(s)

Vref

Mod

Vbus

MPPTIgen

VgenΣ +

-H21(s)

Vmpp

Σ

H23(s)

Vref

Mod

Vbus

Figure 1.4.2: Proposed Hybrid-Coupled HDGS Architecture

14

1.5 Power Generation Technologies and Energy Storage Devices for HDGS

There are a several suitable sources for smaller hybrid DG systems: fuel cell, micro-hydro,

microturbine (MT), biomass, geothermal, tides, wave generator and clean alternative or

renewable energy. Hybrid Renewable Energy Systems are a subcategory of HDGS which harness

energy strictly from renewable energy sources. Wind and solar energy are the most prominent

renewable sources in HRES. The synergy of different sources, (for example a hybrid combine

cycle system consisting of a fuel cell and a MT), can help the overall system in increasing its

overall system efficiency and performance compared to the case where sources operate

independently [27], [28].

Energy storage devices are a key design aspect of HDGS as they can enhance the performance of

the overall system by ensuring backup power. They can be classified in two categories: access-

oriented storage and capacity oriented technologies. Access-oriented storage technologies, such

as batteries, flywheels and supercapacitors are generally used for powering critical loads which

require fast transient responses. Fuel cells and compressed air energy storage are examples of

capacity-oriented storage devices that are used for long term energy storage requiring low

transient responses.

1.6 Incentives for HRES and the Energy Demand in the ICT Sector

Harnessing energy from multiple renewable energy sources not only is key to decarbonisation but

can also reduce a consumer’s electricity bill. Federal governments, around the world, have put in

place several programs catering to residential-scale, small-business and large renewable energy

developers. Such financially incentivized programs allow developers to feed the electricity

harvested to the grid at competitive prices. Although, the initial startup investment is required by

the developers, the payback period is short.

15

The energy consumption growth in the Information and Communications Technology (ICT)

sector is particularly prominent. Delivering power to critical loads first and second providing a

high reliable uninterruptible supply are the two major challenges in energizing this sector. Due to

increasing energy demands and financial incentives, many ICT companies are looking into

sustainable and green power generation and backup solutions. This provides an opportunity to

implement new cost-effective approaches and technologies using hybrid distributed generation

systems. Harnessing power from alternative and renewable energy sources is, therefore a

prevalent solution in alleviating the present energy demand and supply issue of this sector. HRES

have already started to become a popular solution as it offers flexibility in harvesting energy from

solar panels, wind turbines and fuel cells all at once, as well as providing energy storage as a

backup and to feed electricity in to the grid. A hybrid renewable energy system, with a hybrid-

coupled configuration would be a suitable solution for such systems as it would offer great

flexibility and scalability. The raw power provided by renewable energy sources, however, have

to be conditioned rapidly and efficiently in order to power sensitive loads in the ICT sector and to

be able to inject high quality current into the grid.

1.7 Objectives and Scope

The first objective of this thesis is to make apparent the need for DG solutions in the form of

hybrid distributed generation systems. The benefits of such systems in both an urban and rural

setting are discussed. Several system configurations along with their inherent advantages and

disadvantages are then outlined. A new suitable system architecture for powering critical loads is

presented. The power generation technologies and the type of storage devices currently being

used are also stated. Finally, the financial and environmental incentives for HDGS are highlighted

16

and the energy demand in the ICT sector is identified and a possible solution in the form of a

Hybrid Renewable Energy System is proposed. These topics are presented in Chapter 1.

The second objective is to focus on the DC-DC power conditioning converter required to

interface the PV energy source to the HRES implementation. After examining the characteristics

of PV systems, the necessary requirements for the DC-DC converter are drawn. A literature

review of selected works follows the requirements in order to evaluate previous solutions and

their benefits and limitations. These topics are reviewed in Chapter 2.

The third objective is to propose a new 2-bridge parallel-series DC/DC converter topology with

the ability to operate with ZVS over a wide input and load range. The converter’s principle of

operation is explained and an interval-by-interval piecewise equivalent steady-state circuit

analysis is performed to derive the modes of operation. A design guideline for the converter

follows the analysis. Finally, simulation and experimental results performed on a prototype are

shown to verify and validate the design. These topics are discussed in Chapter 3.

Finally, the fourth objective is to propose a controller for the new 2-bridge parallel-series

connected DC/DC converter that will simultaneously perform maximum power point tracking

(MPPT) and regulate the output dc-link voltage. The state-space equations of the converter are

derived in order to characterize the pertaining dynamics and design an adequate non-linear

controller. The digital implementation of the chosen non-linear control scheme on a DSP is

outlined. Lastly, simulation results and experimental results are presented to verify and validate

the design. These topics are presented in Chapter 4.

The thesis limits its scope to, determining the need for distributed generation solutions in the ICT

sector, the steady-state analysis, simulation and experimental verification of the proposed 2-

bridge full bridge phase shift series-parallel connected DC-DC converter with emphasis on the

17

design, verification and digital implementation of a new proposed controller simultaneously

performing MPPT and regulating the output DC-link voltage.

The analysis and design procedures presented in this thesis can be used for any general DC/DC

application at any voltage and power level, however, the focus and intended application is a

power conditioning system interfacing a PV array with MPP voltage input range of 300-380V.

The converter’s rated DC output voltage is 400V and its output power capability is 4kW with an

operational frequency of 100 kHz.

1.8 Chapter Summary

The performance of DG system is often assessed by drawing comparisons to traditional power

generation solutions. When, compared to traditional solutions, emphasis is often place upon the

reliability and capacity of DG systems due to the intermittent nature of the source of energy.

Firstly, DG systems can be multi-source which improves their reliability compared to single-

source configurations and secondly, the traditional alternative energies are also not entirely

reliable. A smaller HRES comprising of smaller sources provides a higher reliability and safety

than a centralized system with fewer large sources which is consequently prone to a greater rate

and duration of failures. This chapter therefore introduces the adequacy and need for HDGS

solutions. The potential benefits of such systems in remote or rural and urban settings were also

discussed. Harnessing energy in such systems can prove challenging as highly efficient power

conditioning and complex control schemes are required. Therefore, after specifying the system

requirements critical to the design, the need for proper technology selection to ensure optimal

performance through the presentation of several system configurations was outlined. The

incentives for these solutions were highlighted and the energy demand was also identified.

Finally, the objectives were listed and the scope of the thesis was defined.

18

The benefits and incentives of implementing DG systems, the accessibility of the sun as a free

source of energy and the alarming need to reduce our carbon footprint are ultimately the driving

factors for the continual growth of the PV market in the future years. One of the most essential

part to ensure its success will be to condition and control this power in the most efficient and

cost-effective manner, which is the focus of this thesis.

19

Chapter 2

Photovoltaic Power Conditioning Systems

2.1 Motivation for Photovoltaic Power

Solar energy, in particular, is a clean and promising energy source which is being harvested

widely in many developed countries such as Australia, Japan, USA, France and Canada amongst

others. The local cumulative photovoltaic (PV) capacity in Canada has more than tripled within a

year, from 2009 to 2010 and Canada’s PV sales have also more than doubled in 2010 compared

to 2009 [29]. Ontario is the province which is driving the country’s PV market growth by offering

several stimulating incentives by the means of an attractive Feed-in Tariff program from its local

power authority. The Ontario Power Authority (OPA) Feed-in Tariff program is divided in two

categories: the FIT Program for projects larger than 10kW and the micro-FIT Program which

targets energy projects less than 10kW such as small business and residential installations. The

rates offered under the programs are presently between 0.44 and 0.71 CAD per kWh for

generating 10kW and above and between 0.64 and 0.82 CAD per kWh for less than 10kW [30].

The current average indicative household retail electricity price is currently of 0.72 CAD [29] and

with the FIT program the cost savings of this a household could amount on average to 0.10 CAD

per kWh. Furthermore, PV arrays are a popular option due to their quiet operation and flexible

size as well as little to no maintenance needs and lack of wear because of very few moving parts.

Therefore, investing in a PV energy conversion system would lead to cost savings and contribute

to increase the overall electricity generation capacity without harming the environment.

20

2.2 Photovoltaic Cell Theory

Light is made up of packets of energy proportional to their frequency called photons. There are

specific materials which exhibit the photoelectric effect that causes them to release electrons due

to the energy given off by photons when light is incident on them. A photovoltaic cell converts

the energy from light directly into electricity in a one-step process commonly known as the

photovoltaic effect. The principle of the photoelectric effect forms the basis for the photovoltaic

effect.

Figure 2.2.1 below shows the cross-section of a solar cell. The transparent conducting coating is

used to collect the light from the sun and protect the cells from environmental degradation. The

anti-reflective coating is used to ensures that most of the light is absorbed needed to output useful

electric work. The heart of the cell is made up of n-type and p-type extrinsic semiconductor

material that are brought into contact. The n-type dope material is an electron donor and the p-

type material containing minority carriers is an acceptor. When the two come into contact an

electric field is formed, however the electron and hole pairing only occurs at the junction to form

a barrier. The combination exhibits properties similar to that of a diode where the junction

prevents the electrons from flowing from the n-side to the p-side, allowing it to only flow from

the p-side to the n-side [31]. Therefore when light is incident on the PV cell, the energy from the

photons breaks the electron-hole pairs, thereafter, the electron is channeled through an external

path. When the PV cell is externally connected to a load, the flow of electrons provides current to

output electrical work. The Ohmic contact provides the conductive contact such that an external

circuit can be connected. The substrate is the material on which all the other layers are deposited.

21

Anti-reflective Coating

Transparent Conducting

Coating

Junction between n-type and p-type material

Substrate

Ohmic Contact

n-type layer from first semiconductor material

p-type layer from second semiconductor material

Figure 2.2.1: Cross-sectional view of photovoltaic cell

2.3 Photovoltaic Characteristics

PV panel manufacturers provide I-V characteristics and often P-V characteristics and main

parameters under standard test conditions (STC). STC is equivalent to having 1000W/m2 of

irradiance, a cell temperature of 25°C and air mass of 1.5. However, the panel does not always

operate at STC and therefore its I-V characteristics vary in a non-linear manner due to the

behavior of the solar cells.

Figure 2.3.1 below shows an ideal and practical equivalent circuit used to model a solar cell

which is known as the one diode model as treated in literature, [32], [33], [34], [35], used to

model a solar cell. A PV cell can be modeled as a DC current source in parallel with a diode and

parasitic resistances. In practice, due to the resistance of contacts and through leakage currents

from the device power is dissipated from the cell. This power loss is equivalently modeled by a

22

parasitic resistance in series Rs and a shunt resistance Rsh. Equation (2.1) and (2.2) below

mathematically characterizes the ideal and practical equivalent circuit model respectively.

iph

id

Rsh

Rs

+vd-

+vc-

icIdeal PV Cell

Practical PV Cell

Figure 2.3.1: PV Cell Equivalent Circuit Model

𝐼𝑐 = 𝐼𝑝ℎ − 𝐼𝑑 = 𝐼𝑝ℎ − 𝐼𝑜�𝑒−𝑞𝑉𝑐 𝑛𝑘𝑇⁄ − 1�

(2.1)

𝐼𝑐 = 𝐼𝑝ℎ − 𝐼𝑜�𝑒−𝑞(𝑉𝑐+𝐼𝑐𝑅𝑠) 𝑛𝑘𝑇⁄ − 1� −𝑉𝑐 + 𝐼𝑐𝑅𝑠𝑅𝑠ℎ

(2.2)

Ic – is the PV cell output current being delivered to the load

Iph – is the photocurrent generated which depends on the light intensity or irradiance

Io – is the dark saturation current of the diode

Id – is the diode current

Vc – is the output voltage of the PV cell

23

q – is the electron charge 1.60217646 ×10-19 C

k – is the Boltzman constant 1.3806503 × 10-23 J/K

T – is the temperature of the p-n junction in Kelvin

n – is the ideality constant of the diode

Rs – is the equivalent series resistance of the PV cell

Rsh – is the equivalent parallel resistance of the PV cell

The output characteristics of a solar cell and invariably that of a panel are affected by irradiation

and the operating temperature as shown in (2.1) and (2.2) above.

Figure 2.3.2 and Figure 2.3.3 below respectively show the I-V plot and P-V curve of a PV panel

at STC generated using this above discussed practical equivalent mathematical model. The

Matlab script used to generate the curves is shown in Appendix A.

24

Figure 2.3.2: I-V Characteristic Curve at STC

From the two plots shown in Figure 2.3.2 above and Figure 2.3.3 below, five key electrical

parameters listed below are of relevance when designing power conditioning systems.

Isc – The short circuit current is the maximum current provided by the PV panel when it is

short-circuit.

Voc – The open circuit voltage is the maximum voltage provided by the PV panel when no

external load is connected across its output terminals.

MPP – The maximum power point (Pmax) that occurs at the knee point of the I-V characteristic

curve is the maximum power that the cell can produce.

0 5 10 15 200

1

2

3

4

5

6

7

8

9

Voltage (V)

Cur

rent

(A)

I-V Characteristics of Solar Panel

S=1000W/m2

T=25oC

Isc

Voc VMPP

IMPP MPP

25

Vmpp – is the voltage at the maximum power point

Impp – is the current at the maximum power point

Figure 2.3.3: P-V Characteristic Curve at STC

However, PV panels do not always operate at STC as changes in the operating temperature and

irradiance levels are inevitable. These two parameters impact the most the performance of the

panel. Figure 2.3.4 and Figure 2.3.5 below illustrate how the I-V and P-V characteristic vary with

irradiance.

0 5 10 15 200

10

20

30

40

50

60

70

80

90

100

110S=1000W/m2

Voltage (V)

Pow

er (W

)

P-V Characteristics of Solar PanelT=25oC

MPP

VMPP

26

Figure 2.3.4: I-V Characteristics for different Irradiance Levels

As Figure 2.3.4 above shows, changes in irradiance levels cause slight voltage variations in the

PV panel. The panel’s current is directly proportional to the irradiation, or to Iph, the photocurrent

as shown in Equation (2.1) and (2.2). The maximum power point decreases due to lower

irradiance levels as shown in Figure 2.3.5 below.

0 2 4 6 8 10 12 14 16 18 200

1

2

3

4

5

6

7

8

9

Voltage (V)

Cur

rent

(A)


S=1000W/m2

S=800W/m2

S=500W/m2

S=200W/m2

1000W/m2

800W/m2

500W/m2

200W/m2

27

Figure 2.3.5: P-V Characteristics for different Irradiance Levels

Figure 2.3.6 shows how changes in operating temperature impact the PV panel’s PV

characteristics. Figure 2.3.7 below shows how changes in operating temperature impact the P-V

characteristics.

0 2 4 6 8 10 12 14 16 18 200

20

40

60

80

100S=1000W/m2

Voltage (V)

Pow

er (W

)

P-V Characteristics of Solar Panel

S=800W/m2

S=500W/m2

S=200W/m2

1000W/m2

800W/m2

500W/m2

200W/m2

28

Figure 2.3.6: I-V Characteristics at different Temperatures

Figure 2.3.6 above, shows that the short circuit current increases slightly with temperature.

However, the temperature dependence of the PV panel’s voltage is noticeable. The open circuit

voltage decreases with increasing operating temperature. The maximum power point decreases

when the temperature increases as shown in Figure 2.3.7 below.

0 5 10 15 20 250

1

2

3

4

5

6

7

Voltage (V)

Cur

rent

(A)


S=800W/m2

T = 18oCT = 25oCT = 30oCT = 40oC

29

Figure 2.3.7: P-V Characteristics at different Temperatures

2.4 PV Power Conditioning System Configurations and Requirements

PV panels and array cannot be efficiently interfaced to critical DC-loads directly due to their non-

linear I-V characteristics. Additionally, in a grid-connected system it is necessary to provide a

power conditioning stage to connect PV arrays to the utility grid. The hybrid renewable

distributed generation system configuration outlined and chosen for the study in the ICT sector, in

Chapter 1, interfaces both critical DC-loads and the utility grid.

PV power conditioning systems need to fulfill three key requirements [36], they have been

outlined below.

0 5 10 15 20 250

20

40

60

80

100

S=800W/m2

Voltage (V)

Pow

er (W

)P-V Characteristics of Solar Panel

T = 18oCT = 25oCT = 30oCT = 40oC

30

1. Invert the DC voltage into the AC standard voltage of the region

2. Step-up or boost the voltage, if the PV array voltage is lower than the grid voltage

3. Provide a sinusoidal output voltage or current output or both

Maximum power point tracking is one more key additional requirement that the power

conditioning stage should perform in order to maximize the efficiency of the overall system [37].

To this, aim a single stage or two-stage conversion approach can be implemented as discusses in

section 1.4 of Chapter 1. The most common configuration nowadays is the two cascade stages as

it offers an additional controllable variable required in the operation of a grid-connected PV

system compared to its single-stage counterpart [38]. This additional degree of freedom is the

duty cycle of the dc-ac inverter which is used to control the dc-link voltage between the two

stages and the current injected in the grid. The first stage is a dc-dc converter responsible for

maximum power point tracking and possibly voltage amplification. The second stage is a dc-ac

converter which feeds a sinusoidal current to the grid. Isolation is also a key requirement for such

systems in North America [39]. The galvanic isolation could be provided by a line frequency

transformer at the output of the dc-ac converter or a high-frequency transformer which is part of

the dc-dc converter. The former option requires an expensive and bulky transformer. Hence, the

preferred option is a smaller sized high-frequency transformer that provides the required isolation

and voltage amplification [40].

However, in the ICT sector, critical DC-loads such as a battery bank, in addition to the utility grid

are connected to the system. These loads need additional converters that provide them a regulated

output voltage that increases the complexity and the overall cost of the system. Therefore the

purpose of the research presented in this thesis focuses on the design of a novel topology and a

31

new non-linear control scheme for the first stage, an isolated dc-dc converter that will

simultaneously perform MPPT and regulate the output dc-link voltage.

2.5 Literature Review

The zero voltage-switching (ZVS) phase-shift modulated full-bridge (PSM-FB) presented in [41]

is the converter of choice for dc-dc converters above a few hundred watts [42]. This topology will

form the basis of the converters discussed in the literature review and the proposed converter. The

conventional PSM-FB converter topology and its ideal waveforms are shown in Figure 2.5.1 and

Figure 2.5.2 respectively below.

Vin

S1

S2

S3

S4

+Vout

-Co

Lo

Lk

T1

ipri+

vpri

-

Figure 2.5.1: Conventional PSM-FB Topology

32

t

vpri

ipri

Figure 2.5.2: Ideal Waveforms of Conventional PSM-FB

This converter consists of four Mosfet switches forming an H-bridge, a transformer, an output

rectifier bridge and an output filter. This circuit makes use of the leakage inductance included as

parasitic in the transformer and the Mosfet’s intrinsic capacitance and diode to achieve soft-

switching at a constant switching frequency. However, soft-switching can only be achieved if the

energy in the leakage inductance is sufficient to discharge the capacitance between the drain to

source of the Mosfet switches. The Mosfet switches which transition during the freewheeling

period lose ZVS at low load conditions.

The converter presented in [43], shown in Figure 2.5.3 is used for power conditioning for solid

oxide fuel cell (SOFC) applications. This topology consists of two identical full-bridge sections

connected in parallel at the input and output. Each bridge is forced to process half the output

power by being operated at the same switching frequency and with the same leg–to–leg phase

shift. In addition, auxiliary circuits comprised of two external inductors and two dc-blocking

33

capacitors are connected at the midpoint between the two bridges. Since ZVS in the conventional

bridges can only be achieved if the energy in the inductance is sufficient to discharge the

capacitance between the drain to source of the Mosfet switches, these auxiliary circuits provide

the difference to maintain soft-switching. The phase-shift between the two bridges is introduced

as a new controllable variable that allows the adjustment of the peak current necessary through

the auxiliary inductors to achieve ZVS down to no load. Therefore, this power converter is able to

overcome the loss of ZVS at low load by using an adaptive storage system at the expense of

additional external passive components.

34

Vin

S1 S2

S4 S3

S5 S6

S8 S7

Lo1

Lo2

Co

T1

T2

Lext_BLext_A

Cext_BCext_A

Lk

Lk

+Vout

-

Figure 2.5.3: Two-Bridge ZVS PSM-FB Converter

The hybrid phase shift modulated full-bridge converter (HPMC) [44], shown in Figure 2.5.4

below, is suitable for applications where the input voltage varies widely and a regulated output is

required. This topology is composed of an uncontrolled half-bridge section comprising Mosfet

35

switch TA+ and TA- and a transformer T1 and of a controlled PSM-FB comprising of Mosfet

switches TA+, TA-, TB+, TB- and transformer T2. The transformers outputs are connected in series

at the secondary. The key to operate this circuit suitably and regulate the output against line and

load variation while maintaining ZVS for the entire load range lies in the careful transformer

design. The range of variations in the voltage input and output are the determining factor in

choosing the turns ration for the two transformers. T1’s turn ratio is selected such that at the

maximum line voltage, its secondary voltage is equal to the required output voltage. The phase

shift of the controlled section is set to zero at maximum input voltage and so that it does not

contribute to the output voltage. However, as the input voltage decreases the voltage across T1

drops proportionally. As a result the phase shift of the controlled FB-PSM increases to contribute

to the output voltage by causing the secondary voltages of the two transformers to add vectorially

providing the balance needed to regulate the output. Hence, the turns ratio of T2 is chosen such

that it can provide the difference of the output for the full input voltage range.

+Vin-

+Vout

-

TA+

TA-

TB+

TB-

Lo

T1 T2

Figure 2.5.4: Hybrid PSM-FB Converter

36

This circuit provides ZVS from full load to no load for a wide input voltage range with an

additional transformer. Furthermore, this configuration’s waveforms exhibit near-ideal filter

waveforms which reduce both the input and the output filter requirement.

The converter presented in [45], shown in Figure 2.5.5 is also an HPMC. This converter is

composed of an uncontrolled full-bridge section comprising of Mosfet switches S1, S2, S3, S4 and

transformer T1 and of a controlled full-bridge section constituting of Mosfet switches S3, S4, S5,

S6 and transformer T2. The converter achieves ZVS for a wide load and line range in a similar

manner as explained in [44].

Vin

S1

S2

S3

S4

S5

S6

L2

L1

T1

T2

C

R

- Vout +

Figure 2.5.5: HPMC with Current-Doubler Rectifier

The improvement in the topology is the Current Doubler rectifying technique used instead of its

center-tapped rectifier counterpart, shown in Figure 2.5.6. Two identical inductors L1 and L2

which are connected in parallel across the two transformers’ secondary windings carry half of the

average load current. One of the advantages of this circuit is that ZVS can be achieved right down

to extremely low loads with a much lower peak magnetizing current and leakage inductance

compared to its counterpart.

37

Vin

+Vout

-

S1

S2

S3

S4

S5

S6

T1

T2

Lext

Lext

L

C

Figure 2.5.6: HPMC with Center-Tapped Rectifier

The above discussed topologies can, however, only regulate the output voltage or control the

MPPT and provide ZVS but cannot do all three simultaneously. To this, aim a new 2-bridge

parallel-series DC/DC converter topology, with the ability to operate with ZVS over a wide input

voltage and load range while ensuring MPPT control and output voltage regulation

simultaneously has been developed and presented in Chapter 3.

38

2.6 Chapter Summary

PV technology is presently a means for clean electricity co-generation. It is and will remain a

necessity for future sustainable energy supply systems in many countries. Not only governments

are offering substantial market introduction programs in regards to PV systems but a considerable

amount of money is being invested in research and development as well by the private sector. PV

energy conversions systems meet key requirements for sustainable energy production. There are

neither harmful emissions or generation of pollutants during operation nor any production of

noise. Solar energy conversion is a one-step process which avoids thermodynamic or mechanical

processes required in conventional energy production methods. The absence of moving parts, low

maintenance requirements and high modularity also make this technology attractive.

The characteristics of PV panels and arrays are non-linear and therefore, require PCS to perform

the necessary energy conversion. These units have to optimize the operation of the entire PV

system. They need to operate efficiently and ensuring that the panels operate at their maximum

power point while complying with all the standards set by the region.

In the previous section of this chapter, a few power converter topologies used for power

processing have been reviewed and the potential benefits of developing a new power topology for

the first stage DC/DC converter in PV-PCS have been outlined.

39

Chapter 3

Proposed 2-Bridge Series-Parallel Topology

3.1 Introduction

A new dual-bridge parallel-series DC/DC converter topology, with two degrees of freedom

(DOF), for use as a first-stage DC/DC converter in PV-PCS is proposed in this chapter. This

converter can track the MPP while simultaneously ensuring output voltage regulation. It can also

achieve ZVS over a wide input voltage and load range.

The converter topology is described and an analysis of the steady-state operation of the circuit is

given. The extension of ZVS using passive auxiliary circuits is also discussed. Steady-state

simulation results are presented to verify the design and operation of the proposed converter.

Experimental results obtained from a 300V-380 V, 2 kW prototype operated at 100 kHz validate

the design. The benefits of the proposed topology are also outlined.

3.2 Circuit Description

The proposed converter is shown in Figure 3.2.1. The primary side of the power train consists of

two traditional full-bridge choppers connected across the primary windings of their respective

transformers. LegA1 is made up of two MOSFET switches, S11 and S21. LegB1 consists of

switches S31 and S41. Similarly, LegA2 is made up of switches S12 and S22, while LegB2 consists

of switches S32 and S42. The secondary windings of the two transformers are connected in series

across a full-bridge rectifier to an output filter and load. All MOSFET switches and the two

transformers are identical. Silicon carbide diodes are used in the output rectifier. The auxiliary

circuit, explained in Section IV, consists of an auxiliary inductor, Laux, and two auxiliary voltage

divider capacitances, Ca1 and Ca2.

40

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

CPV

+

-vsec

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

+

-vpri2

Ca1

Ca2

Laux

T1

T2

DR1

DR2 DR3

DR4

+

-VPV

Vout

+

-

to bus

ipri2

ipri1

Figure 3.2.1: Proposed Converter Schematic

3.3 Operating Principle

The two full-bridge inverters (shown in Figure 3.3.1) in the proposed converter are operated at

the same switching frequency, fs.

41

PV BRIDGE 1

BRIDGE 2

Figure 3.3.1: Block Diagram Representation of the Proposed Topology

The leg-to-leg phase shift, ɸ, is used to regulate the output voltage and is bounded as follows:

0° ≤ 𝜙 ≤ 180° (3.1)

An additional control variable, ψBB, the bridge-to-bridge phase shift, is introduced for the

proposed converter topology. It is bounded such that:

𝜓𝐵𝐵 ≤ 𝜙 (3.2)

𝜙 + 𝜓𝐵𝐵 ≤ 𝑇𝑠2

(3.3)

These boundary conditions are necessary in order to be able to track the maximum power from

the PV array while simultaneously outputting a regulated DC voltage at the DC-link.

�𝜙

𝜙 𝝍𝑩𝑩 1st DOF 2nd DOF

42

If the operating conditions were such that:

𝜓𝐵𝐵 ≥ 𝜙 (3.4)

𝜙 + 𝜓𝐵𝐵 ≥ 𝑇𝑠2

(3.5)

the average voltage of the rectified secondary voltage across the transformer windings would be

lower than the output voltage required. This can be observed from the waveform showing the

addition of the voltages across the windings of each transformer in Figure 3.3.2.

vpri1

ΨBB

ɸ

Ts/2vpri2

vpri1+vpri2

t

t

t

Figure 3.3.2: Non-bounded Operational Waveforms

The novel feature of this converter topology is the introduction of an additional degree of

freedom the bridge-to-bridge phase shift, ψBB. The MPPT can be controlled with ψBB,while

simultaneously regulating the output voltage with ɸ. The bridge-to-bridge phase shift, ψBB, and

43

the auxiliary circuit also allows current to circulate at the primary of the transformers, enabling

eight switches to achieve ZVS across a wide input voltage and load range.

ɸ and ψBB, however, are coupled as they both alter the converter’s operating point. The new non-

linear control scheme presented in Chapter 4 explains the control strategy for the converter and

introduces the necessary decoupling terms which are required in the control loops.

3.4 Steady State Analysis

The steady-state modes of operation of the proposed converter are presented in this section. The

transformer voltage and current equations for each interval as well as the output filter inductor

current have been derived. A general analysis is given where the initial conditions for each mode

are symbolically expressed. The initial conditions for each time interval can, however, be derived

by parameterizing the previous time interval. The following assumptions have been made when

performing the steady-state analysis:

The steady-state operating conditions of the converter are defined below:

- operating in continuous conduction mode (CCM)

- drawing a nominal current, Impp, from the PV array at STC

- input voltage, Vmpp, is nominal (STC) and ripple free

- output nominal voltage, Vout

- delivering the power, Pmpp, to a constant load

The phase modulated gating signals of switch S11 and S21 are leading the gating signals

of switch S31 and S41 by a phase shift angle, ɸ, determined by the controller to regulate

the output voltage. The leg-to-leg phase shift angle, ɸ, is fixed in steady-state operation.

The phase modulated gating signals of switch S11 and S21 are leading the gating signals

of switch S12 and S22 by a phase shift angle, ψBB, which is determined by the control

44

circuit to track the MPP. Similarly, the gating signals of S31 and S41 are leading the

gating signals of switch S32 and S42 by the same phase shift angle, ψBB. The bridge-to-

bridge phase shift angle, ψBB, is fixed in steady-state operation.

The switching frequency is constant and fixed at fs.

All the components in the circuit are ideal and lossless. MOSFET switches and diodes

have zero resistance when they are turned on and infinite resistance when they are off.

The other devices and wires have zero conduction loss.

The dead-time, td, is non-zero and identical for all legs.

All the drain-to-source capacitances are equal

The two DC blocking capacitors are sufficiently large such that they act as AC short

circuits

The waveforms, shown in Figure 3.4.1, illustrate the steady-state operation of the converter

taking into consideration the above assumptions.

The converter has twenty unique switching intervals, or modes, from t0 to t0 + Ts and they have

been explained below. The equivalent circuit for each interval follows the equations

characterizing the intervals. The modes of operation between t10 = t0 + Ts/2 to t0 + Ts have been

omitted to avoid repetition, as they are similar to the nine modes described below from t0 to t10,

which is equal to t0 + Ts/2.

45

vg11

vpri1

vg31

vLauxiLaux

vg12

vg32

t0 t1 t2 t7 t8t3 t4t5t6 t9 t10 t11 t12 t17 t18t13t14t15t16 t19 Ts

ɸ

ɸ

ΨBB

td

Ts/2

vpri2

ipri1,2

vpri1+ vpri2

vsec

tttt

t

t

t

t

t

t

Figure 3.4.1: Ideal Waveforms of Proprosed Converter

46

3.4.1 Mode 1: to≤t<t1

In this mode, the diode in the first bridge, D11, turns on and switch S41 remains on from the

previous mode. As a result, the first primary voltage, Vpri1, is clamped to zero. S22 and S42 remain

on from the previous mode. A negative voltage, –Vin, is impressed across the second bridge’s

primary windings and the reflected secondary voltage is –Vin(Ns/Np). This causes the slope of the

negative primary currents to change during this energy transfer mode. This mode is characterized

by the following equations:

𝑣𝑟𝑒𝑐𝑡(𝑡) =𝑁𝑠𝑁𝑝

∙ 𝑉𝑖𝑛

(3.6)

𝑉𝐿𝑓(𝑡) = 𝑉𝑟𝑒𝑐𝑡(𝑡) − 𝑉𝑜 =𝑁𝑠𝑁𝑝

∙ 𝑉𝑖𝑛 − 𝑉𝑜

(3.7)

𝑖𝐿𝑓(𝑡) = 𝐼(𝑡0+) +1𝐿𝑓� 𝑣𝐿𝑓(𝑡)𝑑𝑡𝑡

𝑡0

(3.8)

𝑖𝐿𝑓(𝑡) = 𝐼5 +1𝐿𝑓� �

𝑁𝑠𝑁𝑝

∙ 𝑉𝑖𝑛 − 𝑉𝑜�𝑑𝑡𝑡

𝑡0

(3.9)

𝑖𝐿𝑓(𝑡) = 𝐼5 +�𝑁𝑠𝑁𝑝

∙ 𝑉𝑖𝑛 − 𝑉𝑜�

𝐿𝑓∙ (𝑡 − 𝑡0)

(3.10)

where Vlf is the voltage across the output filter inductor and I5 is the initial condition of the filter

current during this mode.

47

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Ca1

Laux

Ca2

Figure 3.4.2: Equivalent Circuit for Mode 1 (t0≤t≤t1)

48

3.4.2 Mode 2: t1≤t<t2

At time t1, switch S22 turns off and the drain-to-source capacitor C22 charges up to the input

voltage, Vin, which results in the rise of the voltage across the primary windings of transformer

T2 to rise from -Vin to zero. The primary voltage of transformer T1 remains at zero. . Diode D11

in the first bridge and switches S41 and S42 in the second bridge remain on from the previous

interval. The drain-to-source capacitor C12 discharges across the transformer’s primary leakage

inductance and this causes the inductor current’s slope to change again. The following equations

characterize the inductor current in this mode:

𝑣𝑟𝑒𝑐𝑡(𝑡) =−𝐼6

2 ∙ 𝐶𝑑𝑠∙ (𝑡 − 𝑡1)

(3.11)

𝑣𝐿𝑓(𝑡) = 𝑣𝑟𝑒𝑐𝑡 − 𝑉𝑜 =−𝐼6

2 ∙ 𝐶𝑑𝑠∙ (𝑡 − 𝑡1)

(3.12)

𝑖𝐿𝑓(𝑡) = 𝐼6 −𝐼6

2 ∙ 𝐶𝑑𝑠 ∙ 𝐿𝑓∙ (𝑡 − 𝑡1)2 −

𝑉𝑜𝐿𝑓∙ (𝑡 − 𝑡1)

(3.13)

49

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Laux

Ca1

Ca2

Figure 3.4.3: Equivalent Circuit for Mode 2 (t1 ≤ t ≤ t2)

50

3.4.3 Mode 3: t2≤t<t3

Switches S41, S42 and diode, D11 remain on from the previous mode and at t2, diode, D12 turns on.

In this mode, the voltage across the primary windings of transformer T1 and T2 remain zero. The

reflected secondary voltage is also zero. The following equations characterize the change in slope

of the primary current during this mode:

𝑣𝑟𝑒𝑐𝑡(𝑡) = 0 (3.14)

𝑣𝐿𝑓(𝑡) = −𝑉𝑜

(3.15)

𝑖𝐿𝑓(𝑡) = 𝐼7 −𝑉𝑜𝐿𝑓

(𝑡 − 𝑡2)

(3.16)

3.4.4 Mode 4: t3≤t<t4

During this interval, diodes D11 and D12 and switch S42 remain on from the previous interval. At

time t3, switch S41 turns off and the drain-to-source capacitor C41 charges to Vin while capacitor

C31 discharges across the leakage inductance. This causes the voltage across the windings of

transformer, T1 primary to rise from zero to Vin to zero while the primary voltage of transformer,

T2 remains at zero. The secondary voltage remains at zero. The following equations characterize

this interval:

𝑣𝑟𝑒𝑐𝑡(𝑡) = 0 (3.17)

𝑣𝑝𝑟𝑖1(𝑡) + 𝑣𝑝𝑟𝑖2(𝑡) =

𝑁𝑠𝑁𝑝

∙ 𝐼8

2 ∙ 𝐶𝑑𝑠(𝑡 − 𝑡3)

(3.18)

51


(3.19)

𝑖𝐿𝑓(𝑡) = 𝐼8 −𝑉𝑜𝐿𝑓∙ (𝑡 − 𝑡3)

(3.20)

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Ca1

Ca2

Laux


52

RL

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Ca1

Ca2

Laux


53

3.4.5 Mode 5: t4≤t<t5

At time t5, diode D31 turns on and switch, S42 , D11 and D12 are the power devices that remain on

from the previous mode. The voltage across the primary windings of transformer T1, Vpri1,

remains at +Vin and the voltage across the second bridge’s transformer primary windings remains

clamped at zero. The voltage across the second bridge’s transformer primary windings remains

clamped at zero. The secondary voltage also remains at zero and the output inductor current starts

to freewheel through the output rectifier diodes. the leakage inductor current increases from –I9 to

zero. The following equations characterize this mode:

𝑣𝑟𝑒𝑐𝑡(𝑡) = 0

(3.21)

𝑣𝑝𝑟𝑖1(𝑡) + 𝑣𝑝𝑟𝑖2(𝑡) = 𝑉𝑖𝑛

(3.22)

𝑖𝑝𝑟𝑖1,2(𝑡) =𝑁𝑠𝑁𝑝

∙ 𝐼9 +2 ∙ 𝑉𝑖𝑛𝐿𝑙𝑘

(𝑡 − 𝑡4)

(3.23)


(3.24)

𝑖𝐿𝑓(𝑡) = 𝐼9 −𝑉𝑜𝐿𝑓∙ (𝑡 − 𝑡4)

(3.25)

54

RL

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Ca1

Ca2

Laux


55

3.4.6 Mode6: t5≤t<t6

At time t5, switch S11, S31 and S12 turn on with ZVS. Switch S42 remains on despite the primary

currents reverse polarity and increase from zero to a positive value I1. When the auxiliary current

is added to the leakage current, the positive resultant current is the drain-to-source current of

switch S42. The voltage across the first bridge’s transformer primary windings, Vpri1, remains at

+Vin and the voltage across the second bridge’s transformer primary windings remains clamped

at zero. The secondary voltage also remains at zero and the output inductor current continues to

freewheel through the output rectifier diodes. The following equations characterize this mode:

𝑣𝑟𝑒𝑐𝑡(𝑡) = 0 (3.26)

𝑣𝑝𝑟𝑖1(𝑡) + 𝑣𝑝𝑟𝑖2(𝑡) = 𝑉𝑖𝑛

(3.27)

𝑖𝑝𝑟𝑖1,2(𝑡) =2 ∙ 𝑉𝑖𝑛𝐿𝑙𝑘

(𝑡 − 𝑡5)

(3.28)

𝑣𝐿𝑓(𝑡) = −𝑉𝑜𝐿𝑓

(𝑡 − 𝑡5)

(3.29)

𝑖𝐿𝑓(𝑡) = 𝐼10 −𝑉𝑜𝐿𝑓∙ (𝑡 − 𝑡5)

(3.30)

Where 𝐼10 = 𝐼𝑜𝑢𝑡 (Output Average Current)

56

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Laux

Ca1

Ca2


57

3.4.7 Mode 7: t6≤t<t7

During this interval, switches S11, S31, S12 and S42 are the power devices that remain on from the

previous mode. The voltage across the first bridge’s transformer primary windings, Vpri1, remains

at +Vin and the voltage across the second bridge’s transformer primary windings remains

clamped at zero. However, the voltage across the secondary voltage is no longer zero but

+Ns/Np(Vin) as the output inductor current no longer freewheels through the output rectifier

diodes in this energy transfer mode. The output rectifier diodes DR1 and DR3 are now forward

biased. This is due to the primary current through the leakage inductance increasing to the

reflected output inductor current. The following equations characterize this mode:


𝑉𝑖𝑛

(3.31)

𝑣𝐿𝑓(𝑡) =𝑁𝑠𝑁𝑝

𝑉𝑖𝑛 − 𝑉𝑜

(3.32)

𝑖𝐿𝑓(𝑡) = 𝐼1 +

𝑁𝑠𝑁𝑝


𝐿𝑓∙ (𝑡 − 𝑡6)

(3.33)

58

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Laux

Ca1

Ca2


59

3.4.8 Mode 8: t7≤t<t8

Switches S11, S31, S12 remain on from the previous mode. At time t6, switch S42 turns off and the

drain-to-source capacitance C42 charges to Vin. This causes the voltage across the transformer’s

primary windings in the second bridge to rise from zero to Vin while the voltage across the

transformer’s primary windings in the first bridge remains at Vin. Capacitor C32 also discharges

during the dead-time as the resultant current from the addition of the leakage current and the

auxiliary inductance current is negative. The voltage across the secondary windings rises from

+Vin(Ns/Np) to 2Vin(Ns/Np). The slope of the primary current through the leakage inductance

changes as the converter enters a new energy transfer mode. The following equations characterize

this interval:


𝑉𝑖𝑛 +𝐼2

2 ∙ 𝐶𝑑𝑠(𝑡 − 𝑡7)

(3.34)


𝑉𝑖𝑛 +𝐼2

2 ∙ 𝐶𝑑𝑠(𝑡 − 𝑡7) − 𝑉𝑜

(3.35)

𝑖𝐿𝑓(𝑡) = 𝐼2 +

𝑁𝑠𝑁𝑝


𝐿𝑓∙ (𝑡 − 𝑡7) +

𝐼22 ∙ 𝐿𝑓𝐶𝑑𝑠

(𝑡 − 𝑡7)2

(3.36)

60

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Laux

Ca1

Ca2


61

3.4.9 Mode 9: t8≤t<t9

Switches S11, S31 and S12 are the power devices that remain on from the previous interval. At

time t8, diode D32 (shown in blue in Figure 3.4.10) turns on and carries the drain to source current

for the duration the resultant current (sum of leakage and auxiliary inductor current) remains

negative. This is shown in the equivalent circuit for this mode. Switch S32 (shown in black in

Figure 3.4.10) turns on with ZVS shortly after when the leakage current becomes dominant

enough to cause the resultant current to commutate and become positive. Diode D32 and switch

S32 do not conduct at the same time. The voltage across both transformer primary windings is Vin

and the reflected voltage at the secondary windings is 2(Ns/Np)Vin. The current increases with a

steeper positive slope during this energy transfer mode. The following equations characterize this

mode of operation:

𝑣𝑟𝑒𝑐𝑡(𝑡) = 2�𝑁𝑠𝑁𝑝�𝑉𝑖𝑛

(3.37)

𝑣𝐿𝑓(𝑡) = 2�𝑁𝑠𝑁𝑝�𝑉𝑖𝑛 − 𝑉𝑜

(3.38)

𝑖𝐿𝑓(𝑡) = 𝐼3 +2 �𝑁𝑠𝑁𝑝

�𝑉𝑖𝑛 − 𝑉𝑜

𝐿𝑓∙ (𝑡 − 𝑡8)

(3.39)

62

RL

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-

vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Laux

Ca1

Ca2


63

3.4.10 Mode 10: t9≤t<t10

At time t9, Switch S11 turns off and the drain-to-source capacitor C11 charges to Vin. Capacitor

C21 discharges through the leakage inductance and in turn, the voltage across the primary

windings of transformer, T1 falls from Vin to zero. The voltage across the second bridge’s

transformer primary remains at Vin. The primary current through the leakage inductance increases

with a positive slope while the reflected secondary voltage falls from 2Vin(Ns/Np) to Vin(Ns/Np)

as the converter enters a new energy transfer mode. The following equations characterize this

interval:


𝑉𝑖𝑛 −𝐼4

2 ∙ 𝐶𝑑𝑠(𝑡 − 𝑡9)

(3.40)


𝑉𝑖𝑛 −𝐼4

2 ∙ 𝐶𝑑𝑠(𝑡 − 𝑡9) − 𝑉𝑜

(3.41)

𝑖𝐿𝑓(𝑡) = 𝐼4 +

𝑁𝑠𝑁𝑝


𝐿𝑓∙ (𝑡 − 𝑡9) +

𝐼42 ∙ 𝐿𝑓𝐶𝑑𝑠

(𝑡 − 𝑡9)2

(3.42)

64

S11

S21

S41

S31

S12

S22

S42

S32

Llk1

Llk2

Lf

Cf

+

-vpri1

vpri2

+

-vPV CPV

+

-vsec

+

-

RL

D11 C11 C41 D41

D21 C21 C31 D31

D12 C12

D22 C22

C42 D42

C32 D32

Laux

Ca1

Ca2


65

3.5 Design Considerations

The main requirement of this power supply is to regulate the output voltage for a wide input

voltage and load range with high efficiency. The secondary requirement is to maintain a

reasonable profile and size for the intended application.

The following specifications for the power supply are required in order to begin the design

process:

Vin – Input Voltage Range

Vout – Output Voltage

IL – Load Current

fs – Switching Frequency

3.5.1 Selection of Turns Ratio and Leakage Inductance

A few key parameters need to be carefully designed in order to achieve efficient power

conversion. The first step in the design procedure is to choose a maximum primary duty cycle, D,

such that the turns ratio of the transformer, Ns/Np, can be maximized according to the equation

below:

𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛𝑁𝑠𝑁𝑝

𝐷𝑒

(3.43)

where De is the effective duty cycle of the voltage across the secondary windings of the

transformers, characterized as follows:

𝐷𝑒 = 𝐷 − ∆𝐷 (3.44)

ΔD is the duty cycle loss and it is expressed as follows:

66

∆𝐷 =

𝑁𝑠𝑁𝑝𝑉𝑖𝑛

2𝑓𝑠𝐿𝑙𝑘

�2𝐼𝐿 −𝑉𝑜𝑢𝑡

2𝑓𝑠𝐿𝑓(1 − 𝐷)�

(3.45)

Once the turns ratio, Ns/Np, has been calculated, the second step is to calculate the required

leakage inductance, Llk, needed to discharge the drain-to-source capacitors before the switches

start conducting, which ensures ZVS. The required leakage inductance is calculated as follows:

𝐿𝑙𝑘 =𝑉𝑖𝑛∆𝐷

2 𝑁𝑠𝑁𝑝𝑓𝑠𝐼𝐿

(3.46)

3.5.2 Selection of Snubber Capacitors

The third step is the selection of the snubber capacitors, Csb, shown in Figure 3.5.1, to achieve

ZVS at turn-off, thus eliminating switching losses. ZVS at turn-off is obtained by delaying the

rise time of the drain to source voltage, Vds.

SADA

Csb

SB DBCsb

Llk

Figure 3.5.1: Snubber Capacitors of a Leg

67

The snubber capacitors charge the fastest when the input voltage is at the minimum and the load

current is at the maximum. The following equation helps in selecting the snubber capacitor

values:

𝐶𝑠𝑏 =𝐼𝑝𝑘𝑡𝑑𝑉𝑖𝑛

(3.47)

where Ipk is the transformer primary peak current and td is the dead-time.

The leakage inductance, Llk, needs to store enough energy to ensure that the snubber capacitors

can be discharged and achieve ZVS at turn-on. The condition below expresses the

aforementioned and further restricts the selection of the snubber capacitors, Csb.

12𝐿𝑙𝑘𝐼𝑝𝑘2 ≥

43

(𝐶𝑠𝑏)𝑉𝑖𝑛2

(3.48)

3.5.3 Determining the Dead-Time

The final step is to determine the required dead-time necessary to discharge the capacitors in

order to achieve ZVS at turn-on. The minimum length for the dead-time should be restricted such

that it ends before the primary current crosses zero. This would then prevent the discharged

snubber capacitors from charging again and causing the loss of ZVS at turn on. The preceding is

characterized by the condition below:

𝑡𝑑 ≥2𝜋4�𝐿𝑙𝑘(2𝐶𝑠𝑏)

(3.49)

68

3.6 Extension of ZVS to LegB2

The switches of Leg B2 do not turn on with ZVS and this causes switching losses. MOSFET

switch S22 does not turn on with ZVS as the transformer’s primary current, Ip2, is positive and

similarly, S42 turns on when Ip2 is negative. Therefore, the drain-to-source capacitance of the

MOSFET switches cannot discharge and, as a result, the drain-to-source diode cannot turn on

prior to the switch turn-on as per the regular ZVS mechanism.

An auxiliary circuit can be designed to provide the reactive power required for the ZVS of LegB2.

This would help eliminate all switching losses, reduce EMI and facilitate heat management of the

circuit but at the expense of additional components. The auxiliary circuit, shown in Figure 3.6.1,

consists of two identical voltage divider capacitors, Ca1 and Ca2, and an auxiliary inductor, Laux.

Ca1

Ca2

Laux

S42D42

C42

S32 D32C32

Llk2

Figure 3.6.1: Auxiliary Network Schematic

3.6.1 Selection of Auxiliary Inductance

In order to achieve ZVS at turn-on, the snubber capacitors need to be completely discharged in

the dead-time, td. The current needed to discharge them will be provided by the auxiliary

69

network. The waveforms shown in Figure 3.6.2 depict the voltage and current of the auxiliary

inductor and help with providing a general guideline to select the auxiliary inductance.

+Vin/2

-Vin/2

+Ipk_aux

-Ipk_aux

Ts/2 - td

iLaux

vLaux

t

Figure 3.6.2: Auxiliary Inductor Voltage and Current Waveforms

The current discharging the snubber capacitors, Idischarge, for LegB2 is the sum of the auxiliary

inductor current and the transformer primary current:

𝐼𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 = 2𝐶𝑠𝑏𝑉𝑖𝑛𝑡𝑑

(3.50)

The required auxiliary inductor peak current required can be determined as follows:

𝐼𝑝𝑘_𝑎𝑢𝑥 = 𝐼𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 − 𝐼𝑝𝑘

(3.51)

where Ipk is the peak current through the primary windings of the transformer.

The energy balance condition can be expressed as:

12𝐿𝑙𝑘�𝐼𝑝𝑘 + 𝐼𝐿𝑎𝑢𝑥� ≥

12

(2𝐶𝑠𝑏)𝑉𝑖𝑛2

(3.52)

70

The auxiliary inductor can be derived as follows:

𝑉𝐿𝑎𝑢𝑥 = 𝐿𝑎𝑢𝑥𝑑𝑖𝐿𝑎𝑢𝑥𝑑𝑡

(3.53)

where VLaux = Vin/2, diL = 2Ipk_aux and dt = Ts/2 - td

Therefore, the auxiliary inductor is:

𝐿𝑎𝑢𝑥 =𝑉𝑖𝑛

4𝐼𝑝𝑘_𝑎𝑢𝑥�𝑇𝑠2− 𝑡𝑑�

(3.54)

3.6.2 Selection of the Voltage Divider Capacitors

The identical voltage divider capacitors, Ca1 and Ca2, which are part of the auxiliary circuit, need

to hold the DC voltage with very little ripple. The permitted voltage ripple on the auxiliary

capacitors will be restricted to 1% of the input voltage. The following equation will serve as a

guideline for their selection:

𝑖𝐶𝑎1,2 = 𝐶𝑎1,2𝑑𝑉𝐶𝑎1,2

𝑑𝑡

(3.55)

where dVCa1,2 = 0.1Vin, dt = 1/(2fs) and iCa1,2 = Ipk_aux

𝐶𝑎1,2 =50𝑉𝑖𝑛𝑓𝑠

𝐼𝑝𝑘_𝑎𝑢𝑥

(3.56)

The peak current can be solved using Equation (3.53), where dt = 1/(2fs):

𝐼𝑝𝑘_𝑎𝑢𝑥 =𝑉𝑖𝑛

8𝐿𝑎𝑢𝑥𝑓𝑠

(3.57)

Substituting Equation (3.56) into Equation (3.57) yields:

71

𝐶𝑎1,2 =25

4𝐿𝑎𝑢𝑥𝑓𝑠2

(3.58)

3.7 Simulation Results

A simulated model of the converter was built using PSIM simulation software to verify the

operation of the circuit. The circuit parameters have been summarized in Table I. A PI controller

was used which provided a reasonably fast response to load and line changes. The phase shift

between the two FBs was fixed. The converter schematic is shown in Appendix C.

Table I

Simulation Model Parameters

Symbol Parameter Value

Po Output Power 2 kW

Vin Input Voltage 300-380 V

Vo Output Voltage 400 V

fs Switching frequency 100 kHz

Ns/Np Transformer turns ratio 22:18

Llk1, 2 Transformer Leakage

Inductance 6.5 μH

Laux Auxiliary Inductance 25 μH

Csb Snubber Capacitors 1.1 nF

Ca1, 2 Auxiliary Capacitance 20 μF

Lf Output Filter Inductance 540 μH

Cf Output Filter Capacitance 33 μF

td Dead-time 220 ns

72

3.7.1 Verification of Circuit Operation

Figure 3.7.1 shows the simulated waveforms of the converter when it is operated at the maximum

line voltage, Vin = 380 V, and at 50% nominal load.

The waveform labels are described below:

VP1 – Voltage across primary transformer windings of FB1

Ilk1 – Current through primary transformer windings of FB1

VP2 – Voltage across primary transformer windings of FB2

Ilk2 – Current through primary transformer windings of FB2

Vrect – Rectified Secondary Voltage

Vaux – Auxiliary Inductor Voltage

Iaux – Auxiliary Inductor Current

73

Figure 3.7.1: Simulated Waveforms: 50% Load, Vin = 380 V (200 V/div, 27 A/div)

Figure 3.7.2 shows the simulated waveforms of the converter when it is operated at the minimum

line voltage, Vin = 300 V, and at full load. The waveform labels have been described above.

0

-400

400VP1 Ilk1*15

0

-400

400VP2 Ilk2*15

0400800

Vrect

0

-400

400Vaux Iaux*15

0.01083 0.010835 0.01084 0.010845Time (s)

0

-400

400Ilk1*15 Ilk2*15 Iaux*15

(V) (A)

(A) (V)

(A) (V)

(A)

(V)

(A) (A)

74

Figure 3.7.2: Simulated Waveforms: 100% Load, Vin = 300V (200V/div, 27A/div)

0-200-400

200400

VP1 Ilk1*15

0-200-400

200400

VP2 Ilk2*15

0200400600800

Vrect

0-200-400

200400

Vaux Iaux*15

0.03575 0.035755 0.03576 0.035765Time (s)

0-400

400Ilk1*15 Ilk2*15 Iaux*15

(V) (A)

(V) (A)

(V) (A)

(V)

(A) (A) (A)

75

3.7.2 Verification of ZVS

Figure 3.7.3 shows that the converter can operate with full ZVS at the maximum line voltage, Vin

= 380 V, and at 50% load. The waveform labels are described below.

Vds – Drain-to-source voltage of the MOSFET switch

I(SXX) - Drain-to-source current of the MOSFET switch

GXX – The PWM gating signal of the MOSFET switch


(200V/div, 27A/div)

0

-200

200

400

Vds11 I(S11)*15 G11*100

0

-200

-400

200

400Vds31 I(S31)*15 G31*100

0

-200

-400

200

400Vds12 I(S12)*15 G12*100

0.010628 0.01063 0.010632 0.010634 0.010636Time (s)

0-200-400

200400

Vds32 I(S32)*15 G32*100

(V) (A) (A)

(V) (A) (A)

(V) (A) (A)

(V) (A) (A)

76

Figure 3.7.4 shows that the converter can operate with full ZVS at the maximum line voltage, Vin

= 380 V, and at 50% load. The waveform labels have been described above.


(200V/div, 27A/div)

0

-200

200

400

Vds11 I(S11)*15 G11*100

0-200-400

200400

Vds31 I(S31)*15 G31*100

0-200-400

200400

Vds12 I(S12)*15 G12*100

0.012358 0.01236 0.012362 0.012364 0.012366Time (s)

0-200-400

200400

Vds32 I(S32)*15 G32*100

(V) (A) (A)

(V) (A) (A)

(V) (A) (A)

(V) (A) (A)

77

3.8 Experimental Results

A 2 kW laboratory prototype of the proposed converter topology was built using the

specifications listed in Table II. The list components used for the experimental hardware are

summarized in Table III. A LeCroy Wavepro 7000 oscilloscope was used to capture all the

results. A high voltage differential probe, ADP305, and a current probe, CP150, were used to

obtain the experimental waveforms.

3.8.1 Prototype Specifications

Table II

Experimental Prototype Specifications

Symbol Parameter Value

Vin Input Voltage 300-350 V

Vout Output Voltage 400 V

Pout Output Power 2 kW

Csb Snubber Capacitor 1.1 nF

Ns:Np Transformer Turns Ratio 22:18

Llk1,2 External Leakage Inductance 10 μH

Ls Transformer Series Inductance 2.2 μH

Laux Auxiliary Inductance 45 μH

Lf Output Filter Inductance 540 μH

Cf Output Filter Capacitor 33 μF

fs Switching Frequency 100 kHz

td Dead-time 220 ns

78

3.8.2 Prototype Components

Table III

Experimental Prototype Components

Component Manufacturer Part Number

MOSFET Drivers IXYS IXDD614YI

MOSFET Switches S11 - S42

Vishay IRFPS40N50LPBF

Rectifier Diodes DR1 - DR4

Cree C4D05120A

Transformers Core Ferroxcube ETD59/31/22-3F3

Transformers Bobbin Ferroxcube CPH-ETD59-1S-24P

Output Capacitor Cf

Vishay A_515D336M450FR6AE3

Output Inductors Lf

CoilWS CWS-1HF11361 x 2

Auxiliary Capacitors Ca1,2

Epcos B32676E4206K

Auxiliary Inductor Core Ferroxcube PQ32/20-3F3

Auxiliary Inductor Bobbin Ferroxcube CPV-PQ32/20-1S-12P-Z

External Leakage Inductance Core Ferroxcube PQ32/20-3F3

External Leakage Inductance Bobbin Ferroxcube CPV-PQ32/20-1S-12P-Z

79

3.8.3 Key Operational Experimental Waveforms

Figure 3.8.1 shows the voltage across the primary windings of the transformers, the secondary

voltage and the primary current through the transformers at 95% load and Vin = 380V.

Figure 3.8.1: Experimental Waveforms 95% load, Vin = 380V

2.5A/div 400V/div

400V/div

400V/div

Vsec

Vpri1 Vpri2

Ip1, 2

80

Figure 3.8.2 and Figure 3.8.3 shows the voltage across the primary windings of the transformers,

the secondary voltage and the primary current through the transformers at 55% load and Vin =

300V.

Figure 3.8.2: Experimental Waveforms at 55% load and Vin = 300V

2.5A/div

250V/div

200V/div

250V/div

Vsec

Vpri1

Vpri2 Ip1, 2

81


Figure 3.8.4 shows the voltage across the primary windings of the transformers, the secondary

voltage and the primary current through the transformers at 100% load and Vin = 300 V.

2.5A/div

120V/div

200V/div

120V/div

Vsec Vpri1 Vpri2

Ip1, 2

82


3.8.4 Verification of ZVS

The following waveforms were obtained after adding the auxiliary inductance and the two

voltage divider capacitances to the circuit.

Figure 3.8.5 shows the voltage across the primary windings of the transformers and the auxiliary

inductor current at 5A and Vin = 380V. The rising and falling edges of the primary voltage

waveforms are constant which demonstrates turn on and turn off of all the switches under ZVS.

3A/div

125V/div

600V/div

125V/div

Vsec

Vpri1 Vpri2

Ip1, 2

83

Figure 3.8.5: Experimental Waveforms at Iaux = 5A, Vin = 380V

Figure 3.8.6 shows the voltage across the primary windings of the transformers, the primary

current through the transformers and the auxiliary inductor current at 100% load and Vin = 300V.

The bottom half of the figure is an enlarged view of the rising edges of the two primary voltages

and the primary current. The rising edge of the primary voltage waveforms are constant which

demonstrates turn on and turn off of all the switches under ZVS.

Vpri1 Vpri2

Iaux

ZVS Turn OFF Bridge 1

ZVS Turn ON Bridge 1



10A/div

400V/div 400V/div

84

Figure 3.8.6: Experimental Waveforms at 100% load and Vin = 300V (Rising Edges)

Figure 3.8.7 shows the voltage across the primary windings of the transformers, the primary

current through the transformers and the auxiliary inductor current at 100% load and Vin = 300V.

The bottom half of the figure is an enlarged view of the falling edges of the two primary voltages

and the primary current. The falling edge of the primary voltage waveforms are constant which

demonstrates turn on and turn off of all the switches under ZVS.

Vpri1 Vpri2

Iaux Ip1,2



10A/div 300V/div

5A/div 300V/div

85

Figure 3.8.7: Experimental Waveforms at 100% load and Vin = 300V (Falling Edges)

3.9 Features of Proposed Converter

The targeted application for the proposed topology is PV-PCS. The benefits of the converter are

listed below:

- Two degrees of freedom

The converter topology is configured in such a way that a second degree of freedom has

been introduced in addition to the existing one, the leg-to-leg phase shift. The two phase-

shifts will allow for simultaneous control of MPPT and output voltage regulation.

Vpri1 Vpri2 Iaux

Ip1,2



10A/div 300V/div

5A/div 300V/div

86

- Wide ZVS range of operation

The bridge-to-bridge phase shift allows current to circulate between the primary windings

of bridge 1 and bridge 2. This circulating current helps bridge 1 to achieve a wider range

of operation under ZVS as there is more energy stored in the leakage inductance to

discharge the drain to source capacitors. ZVS operation of the converter helps eliminate

switching losses.

- Wide line and line range operation

The converter can operate with a wide line voltage range of 300V – 380V. The converter

has been designed to operate up to 4kW.

- Voltage step-up and galvanic isolation

The transformers of the converter step-up the voltage as required for PV-PCS and

therefore, no boost stage is required. Galvanic isolation between the input and the output

is also provided by the transformers.

- Load sharing between two bridges

In the proposed topology, the two bridges process the main power. This reduces the

stress on power devices at the primary. The high switching frequency of the converter

also decreases the size of the filter components.

87

3.10 Chapter Summary

A new dual-bridge parallel-series DC/DC converter topology for use as a first stage DC/DC

converter in PV-PCS has been described in this chapter. The operating principles of the converter

were outlined and the steady-state analysis was presented. A design guideline was provided and

the design equations for the key circuit parameters were derived. Simulation results for a 4 kW

system verified the steady-state operation and ZVS of the circuit. Experimental results obtained

from a 2 kW lab prototype validated the performance of the proposed converter.

88

Chapter 4

Non-Linear Control Scheme

4.1 Introduction

The novel converter proposed in Chapter 3 for use in PV-PCS application needs to track the MPP

while simultaneously ensuring output voltage regulation. This requires therefore, a new robust

controller which will allow this simultaneous operation over a wide input voltage and load range.

This chapter describes the design and implementation of this novel non-linear controller.

The output voltage and output control variable relationship is identified and compensated in the

first section. The linear and non-linear input voltage and input control variable relationships are

also identified. The third section covers the identification of the input voltage and output control

variable, the derivation of the decoupling terms in order to implement the new non-linear control

strategy. This section is concluded by the input compensator design and the outline of the MPPT

algorithm. Finally, in the fourth section, the simulation results verify the design, the digital

implementation of the controller is outlined and the experimental results are shown to validate the

design.

4.2 Output Controller Design

4.2.1 Ouput Voltage Loop State-Space Model

The dynamics of the converter’s output is characterized by deriving the state space equations

pertaining to the output filter inductor and capacitor. The voltage of the output filter inductor and

the current of the output capacitor are defined as the state vector for each circuit state. The input

variable vector comprises of the input voltage in this case, although the control variables could

also be included. The next step is to define the state and input matrices.

89

�⃑�1 = �𝑣𝐿

𝑖𝑐�

(4.1)

𝑢�⃑ 1 = [𝑣𝑖𝑛]

(4.2)

Bridge 1

Bridge 2

+Vin-

iPV

+Vout

-

io

iin

Cf

Lf

+ vL -

+vrect

-

C1

iin2

iin1

+VPV

-

Figure 4.2.1: Block diagram of proposed converter

The input voltage of the converter’s output filter (shown in Figure 4.2.1) is the rectified voltage

across the secondary windings of the transformer. The output filter inductor of the converter is

very large compared to the leakage inductances and the dead-time is very small compared to the

switching period. This simplifies the analysis as the freewheeling mode and the dead time can be

ignored. The MOSFET rise-time and fall-time are considerably smaller than the switching period

90

and are therefore ignored and omitted from the analysis. The rectifier voltage (shown in Figure

4.2.2) is therefore assumed to be the rectified addition of the primary voltages reflected at the

secondary. k is the transformer turns ratio Ns/Np.

t0 t1 t2 t3

vpri1

ψBB

ɸ

Ts/2

kVin

2kVin

Vin

Vin

t4

vpri2

vrect

t

t

t

Figure 4.2.2: Rectifier voltage waveform

There are four time interval pertaining to the rectified voltage waveform:

𝑇𝐴 = 𝑡1 − 𝑡0 =𝜓𝐵𝐵2𝜋

𝑇𝑠

(4.3)

91

𝑇𝐵 = 𝑡2 − 𝑡1 =𝜙 − 𝜓𝐵𝐵

2𝜋𝑇𝑠

(4.4)

𝑇𝑐 = 𝑡3 − 𝑡2 =𝜓𝐵𝐵2𝜋

𝑇𝑠

(4.5)

𝑇𝐷 = 𝑡4 − 𝑡3 =𝑇𝑠2−

(𝜙 + 𝜓𝐵𝐵)2𝜋

𝑇𝑠

(4.6)

There are three distinct time intervals TA, TB and TD as TA is identical to TC. The equivalent

circuit for time interval TA and TC is shown in Figure 4.2.3. The differential equations

characterizing this interval are derived and from which the state matrix and input matrix is

defined.

kVin

Lf

Cf RL

+ VL -iL

+Vc-

Figure 4.2.3: Equivalent output circuit for time interval TA and TC

𝑑𝑖𝐿𝑑𝑡

=1𝐿𝑓

(𝑘𝑣𝑖𝑛 − 𝑣𝑐)

(4.7)

92

𝑑𝑣𝑐𝑑𝑡

=1𝐶𝑓�𝑖𝐿 −

𝑣𝑐𝑅𝐿�

(4.8)

𝐴1��⃑ = 𝐴3��⃑ =

⎣⎢⎢⎢⎡ 0 −

1𝐿𝑓

1𝐶𝑓

−1

𝐶𝑓𝑅𝐿⎦⎥⎥⎥⎤

(4.9)

𝐵1��⃑ = 𝐵3��⃑ = �𝑘𝐿𝑓0�

(4.10)

The equivalent circuit for time interval TB is shown in Figure 4.2.4. The differential equations


defined.

2kVin

Lf

Cf RL+Vc-

iL

Figure 4.2.4: Equivalent output circuit for time interval TB

93


=1𝐿𝑓

(2𝑘𝑣𝑖𝑛 − 𝑣𝑐)

(4.11)



𝑣𝑐𝑅𝐿�

(4.12)

𝐴2��⃑ =

⎣⎢⎢⎢⎡ 0 −

1𝐿𝑓

1𝐶𝑓

−1


(4.13)

𝐵2��⃑ = �2𝑘𝐿𝑓0�

(4.14)

The equivalent circuit for time interval TD is shown in Figure 4.2.5. The differential equations


defined.

Lf

Cf RL+Vc-

iL

Figure 4.2.5: Equivalent output circuit for time interval TD

94


=1𝐿𝑓

(2𝑘𝑣𝑖𝑛 − 𝑣𝑐)

(4.15)



𝑣𝑐𝑅𝐿�

(4.16)

𝐴4��⃑ =

⎣⎢⎢⎢⎡ 0 −

1𝐿𝑓

1𝐶𝑓

−1


(4.17)

𝐵4��⃑ = �0

0�

(4.18)

In order to find the general state space representation the state variable need to be averaged over

the half the switching period as this is the period of the rectified voltage which is the input of the

output filter.

�̇�1 = 𝐴�⃑�1 + 𝐵�⃑ 𝑢�⃑ 1

(4.19)

When the averaging is carried out the result is as follows:

�̇�1 = ��𝜓𝐵𝐵𝜋�𝐴1��⃑ + �

𝜙 − 𝜓𝐵𝐵𝜋

�𝐴2��⃑ + �𝜓𝐵𝐵𝜋�𝐴3��⃑ + �1 −

(𝜙 − 𝜓𝐵𝐵)𝜋

�𝐴4��⃑ � �⃑�1

+ ��𝜓𝐵𝐵𝜋�𝐵1��⃑ + �

𝜙 − 𝜓𝐵𝐵𝜋

�𝐵2��⃑ + �𝜓𝐵𝐵𝜋�𝐵3��⃑ + �1 −

(𝜙 + 𝜓𝐵𝐵)𝜋

�𝐵4��⃑ � 𝑢�⃑ 1

(4.20)

95

A small AC perturbation is introduced before finding the output voltage to the output control

variable transfer function. The small perturbations are represented by “~”.

�⃑�1 = �⃑�1 + 𝑥�1

(4.21)

𝑢�⃑ 1 = 𝑈��⃑ 1 + 𝑢�1

(4.22)

�̇�1 + �̇�1 = ��𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋�𝐴1��⃑ + �

𝜙 + 𝜙� − 𝜓𝐵𝐵 − 𝜓�𝐵𝐵𝜋

�𝐴2��⃑ + �𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋�𝐴3��⃑

+ �1 −�𝜙 + 𝜙� + 𝜓𝐵𝐵 + 𝜓�𝐵𝐵�

𝜋�𝐴4��⃑ � ��⃑�1 + 𝑥�1�

+ ��𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋�𝐵1��⃑ + �

𝜙 + 𝜙� − 𝜓𝐵𝐵 − 𝜓�𝐵𝐵𝜋

�𝐵2��⃑ + �𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋�𝐵3��⃑

+ �1 −�𝜙 + 𝜙� + 𝜓𝐵𝐵 + 𝜓�𝐵𝐵�

𝜋�𝐵4��⃑ � �𝑈��⃑ 1 + 𝑢�1�

(4.23)

After simplifying the equations and isolating the small signal components,

�̇�1 = 𝐴𝑥�1 + �2𝜋𝐵�⃑ 1 +

(𝜙 − 𝜓𝐵𝐵)𝜋

𝐵�⃑ 2� 𝑢�1 + �2𝜋𝐵�⃑ 1𝑈��⃑ 1 −

1𝜋𝐵�⃑ 2𝑈��⃑ 1� 𝜓�𝐵𝐵 + �

1𝜋𝐵�⃑ 2𝑈��⃑ 1� 𝜙�

(4.24)

where,

𝐴 = 𝐴1 = 𝐴2 = 𝐴3 = 𝐴4

96

4.2.2 Ouput Voltage Loop Transfer Function

The transfer functions of the state variable to the output control variable are

𝑇�⃑𝑂𝐿1(𝑠) =𝑥�1(𝑠)𝜙�(𝑠)

�𝑢�1=0, 𝜓�𝐵𝐵=0

=1𝜋

(𝑠𝐼 − 𝐴)−1𝐵�⃑ 2𝑈��⃑ 1

(4.25)

The second order transfer function of the output voltage to the control variable is the second entry

in the 𝑇�⃑𝑂𝐿1(𝑠) matrix,

𝑇𝑂𝐿1,21(𝑠) =𝑣�𝑐(𝑠)𝜙�(𝑠)

=2𝑘𝑅𝐿𝑉𝑖𝑛

𝜋��𝐿𝑓𝐶𝑓𝑅𝐿�𝑠2 + 𝑠𝐿𝑓 + 𝑅𝐿�

(4.26)

The Matlab script used to generate the output transfer function is shown in Appendix B.

The bode plot of the open loop transfer function is shown in Figure 4.2.6.

97

Figure 4.2.6: Output transfer function bode plot

4.2.3 Output Voltage Loop Compensator Design

The open-loop dc-dc converter cannot regulate the output voltage to a set reference due to

changes in the input operating point. A compensator is required for closed loop operation to reject

any disturbance that may arise. The gain margin and phase margin are measures of stability for a

feedback system although often only the phase margin is considered [46], [47], [48]. The target

phase margin of 40° – 90° is generally desirable in a feedback design as a tradeoff between loop

stability and settling time in the transient response when working with second order systems [49],

[50].

0

20

40

60

80

Mag

nitu

de (d

B)

103

104

105

-180

-135

-90

-45

0

Phas

e (d

eg)

Magnitude and Phase Plot of the Output Transfer Function

Frequency (rad/s)

98

The poles and zeros of the compensator should be places in such a way that the phase margin at

the crossover frequency, 𝜔𝑐. The magnitude and phase plot of the compensated system is shown

in Figure 4.2.7.

Figure 4.2.7: Output closed loop bode plot

A second order compensator was designed for the output voltage control loop. The phase margin

of the closed loop system is 94°. The compensator’s equation is shown below.

𝐻1(𝑠) = 0.61 + 5 × 10−4𝑠

𝑠(1 + 1.3 × 10−5𝑠)

(4.27)

-200

-150

-100

-50

0

50

Mag

nitu

de (d

B)

Closed Loop Output Magnitude and Phase Plots

Frequency (rad/s)10

110

210

310

410

510

610

7-270

-180

-90

0

Phas

e (d

eg)

99

4.2.4 Digital Implementation of Output Controller

The output controller has been implemented digitally on a Texas Instruments DSP,

TMS320F28335. The bilinear transform shown below was used to convert the compensator to the

z-domain. The block diagram representation of the control loop has been shown in Figure 4.2.8.

𝐻1(𝑧) = 𝐻1(𝑠)|𝑠=2𝑇𝑠

𝑧−1𝑧+1

(4.28)

Bridge 1

Bridge 2

+VPV

-

iPV

+Vout

-

io

Vout[n]

Vref

A/DΣ - +

+-Phase

Modulator

S11 S21 S31 S41

Verror[n]b01

b11Σ +

-

ɸ

Z-1

b21 Z-1

+

+Σ a11Z-1

a21Z-1

+

-

-

Figure 4.2.8: Output Controller Block Diagram

100

4.3 Linearized Input State-Space Model

The dynamics of the converter’s input is characterized by deriving the state space equations

pertaining to the input capacitor and the leakage inductance of the converter. The input capacitor

voltage of the converter and input current to the bridges (shown in Figure 4.2.1) are defined as the

state vector for each circuit state. The input variable vector comprises of the output voltage and

the PV current in this case, although the control variables could also be included. Similarly, the

next step is to define the state and input matrices.

�⃑�2 = �𝑣𝑖𝑛

𝑖𝑖𝑛�

(4.29)

𝑢�⃑ 2 = �𝑣𝑜𝑢𝑡

𝑖𝑃𝑉�

(4.30)

The input voltage of the converter is the PV array’s voltage, Vin across the input capacitor, C1

and the input current of the capacitor is the difference between the current supplied by the PV

array and the input current to the bridges. The relationship between the input voltage and the

input current is assumed to be linear in this analysis. The input current to the bridges is the sum of

the individual input current to each bridge (shown in Figure 4.2.1). The output filter inductor of

the converter is very large compared to the leakage inductances and the dead-time is very small

compared to the switching period. This simplifies the analysis as the freewheeling mode and the

dead time can be ignored. The MOSFET rise-time and fall-time are considerably smaller than the

switching period and are therefore ignored. The key waveforms for this analysis are shown in

Figure 4.3.1.

101

t0 t1 t2 t3

vpri1

ψBB

ɸ

Ts/2

Vin

2Vin

Vin

Vin

iin1

iin2

vpri2

vpri1+vpri2

t

t

t

t

t

Figure 4.3.1: Key waveforms for input controller

There are three time intervals that are of relevance in the analysis:

𝑇𝐴 = 𝑡1 − 𝑡0 =𝜓𝐵𝐵2𝜋

𝑇𝑠

(4.31)

102

𝑇𝐵 = 𝑡2 − 𝑡1 =𝜙 − 𝜓𝐵𝐵

2𝜋𝑇𝑠

(4.32)

𝑇𝑐 = 𝑡3 − 𝑡2 =𝜓𝐵𝐵2𝜋

𝑇𝑠

(4.33)

There are two distinct time intervals TA and TB as TA is identical to TC. The equivalent circuit for

time interval TA and TC is shown in Figure 4.3.2. The differential equations characterizing this

interval are derived and from which the state matrix and input matrix is defined.

kVin

Leq

C1 -Vout/k

iin

ic

ipv

Figure 4.3.2: Equivalent input circuit for time interval TA and TC

𝑑𝑖𝑖𝑛𝑑𝑡

=1𝐿𝑒𝑞

�𝑣𝑖𝑛 −𝑣𝑜𝑢𝑡𝑘�

(4.34)

𝑑𝑣𝑖𝑛𝑑𝑡

=1𝐶1

(𝑖𝑃𝑉 − 𝑖𝑖𝑛)

(4.35)

where, 𝐿𝑒𝑞 = 𝐿𝑙𝑘 + 𝐿𝑓𝑘2

and 𝑘 = 𝑁𝑠𝑁𝑝

103

𝐴1 = 𝐴3 =

⎣⎢⎢⎢⎡

1𝐿𝑒𝑞

0

0 −1𝐶1⎦⎥⎥⎥⎤

(4.36)

𝐵�⃑ 1 = 𝐵�⃑ 3 =

⎣⎢⎢⎢⎡−

1𝑘𝐿𝑒𝑞

0

01𝐶1⎦⎥⎥⎥⎤

(4.37)

The equivalent circuit for time interval TB is shown in Figure 4.3.3. The differential equations


defined.

2kVin

Leq

C1 -Vout/k

iin

ic

ipv

Figure 4.3.3: Equivalent input circuit for time interval TB

𝑑𝑖𝑖𝑛𝑑𝑡

=1𝐿𝑒𝑞

�2𝑣𝑖𝑛 −𝑣𝑜𝑢𝑡𝑘�

(4.38)

104

𝑑𝑣𝑖𝑛𝑑𝑡

=1𝐶1


(4.39)

𝐴2 =

⎣⎢⎢⎢⎡

2𝐿𝑒𝑞

0

0 −1𝐶1⎦⎥⎥⎥⎤

(4.40)

𝐵�⃑ 2 =

⎣⎢⎢⎢⎡−

1𝑘𝐿𝑒𝑞

0

01𝐶1⎦⎥⎥⎥⎤

(4.41)

In order to find the general state space representation the state variable need to be averaged over

the half the switching period as this is the period of the input current.

�̇�2 = 𝐴�⃑�2 + 𝐵�⃑ 𝑢�⃑ 2

(4.42)

When the averaging is carried out the result is as follows:

�̇�2 = �𝜓𝐵𝐵𝜋

𝐴1 +(𝜙 − 𝜓𝐵𝐵)

𝜋𝐴2 +

𝜓𝐵𝐵𝜋

𝐴3� �⃑�2 + �𝜓𝐵𝐵𝜋

𝐵�⃑ 1 +(𝜙 − 𝜓𝐵𝐵)

𝜋𝐵�⃑ 2 +

𝜓𝐵𝐵𝜋

𝐵�⃑ 3� 𝑢�⃑ 2

(4.43)

A small AC perturbation is introduced before finding the output voltage to the output control

variable transfer function. The small perturbations are represented by “~”.

105

�⃑�2 = �⃑�2 + 𝑥�2

(4.44)

𝑢�⃑ 2 = 𝑈��⃑ 2 + 𝑢�2

(4.45)

�̇�2 + �̇�2 = ��𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋 �𝐴1��⃑ + �𝜙 + 𝜙� − 𝜓𝐵𝐵 − 𝜓�𝐵𝐵

𝜋 �𝐴2��⃑ + �𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋 �𝐴3��⃑ � ��⃑�2 + 𝑥�2�

+ ��𝜓𝐵𝐵 +𝜓�𝐵𝐵

𝜋 �𝐵1��⃑ + �𝜙 + 𝜙� − 𝜓𝐵𝐵 − 𝜓�𝐵𝐵

𝜋 �𝐵2��⃑ + �𝜓𝐵𝐵 + 𝜓�𝐵𝐵

𝜋 �𝐵3��⃑ � �𝑈��⃑ 2

+ 𝑢�2�

(4.46)

After simplifying the equations and isolating the small signal components,

�̇�2 = �𝜓𝐵𝐵𝜋

�𝐴1 + 𝐴3� +(𝜙 − 𝜓𝐵𝐵)

𝜋𝐴2� �̇�2 + �

1𝜋�𝐴1 + 𝐴3 − 𝐴2��⃑�2�𝜓�𝐵𝐵 + �

1𝜋𝐴2� 𝜙�

+ �𝜓𝐵𝐵𝜋

�𝐵�⃑ 1 + 𝐵�⃑ 3� +(𝜙 − 𝜓𝐵𝐵)

𝜋𝐵�⃑ 2� �̇�2 + �

1𝜋�𝐵�⃑ 1 + 𝐵�⃑ 3 − 𝐵�⃑ 2�𝑈��⃑ 2�𝜓�𝐵𝐵

+ �1𝜋𝐵�⃑ 2� 𝜙�

(4.47)

106

4.3.1 Linearized Input Transfer Function

The transfer functions of the state variable to the input control variable are:

𝑇�⃑𝑂𝐿2(𝑠) =𝑥�2(𝑠)𝜓�𝐵𝐵(𝑠)

�𝑢�2=0, 𝜙�=0

= (𝑠𝐼 − 𝐴𝑎𝑣𝑔)−1 �1𝜋�𝐴1 + 𝐴3 − 𝐴2��⃑�2 +

1𝜋�𝐵�⃑ 1 + 𝐵�⃑ 3 − 𝐵�⃑ 2�𝑈��⃑ 2�

(4.48)

where, 𝐴𝑎𝑣𝑔 = 𝜓𝐵𝐵𝜋�𝐴1 + 𝐴3� + (𝜙−𝜓𝐵𝐵)

𝜋𝐴2

As the input voltage has been considered to The transfer function of the output voltage to the

control variable is the first entry in the 𝑇�⃑𝑂𝐿2(𝑠) matrix,

𝑇�⃑𝑂𝐿2,11(𝑠) =𝑣�𝑖𝑛(𝑠)𝜓�𝐵𝐵(𝑠)

=𝑉𝑜𝑢𝑡�𝑘2𝐿𝑙𝑘 + 𝐿𝑓�

�𝑘𝐿𝑙𝑘 +𝐿𝑓𝑘 � ��𝜋𝐿𝑓 + 𝜋𝑘2𝐿𝑙𝑘�𝑠 + 2𝑘2𝜙�

(4.49)

The Matlab script used to generate the output transfer function is shown in Appendix B.

The bode plot of the open loop transfer function is shown in Figure 4.3.4.

107

Figure 4.3.4: Input transfer function bode plot

4.3.2 Input Coupled Factors

The input control variable is coupled with the output control variable as the term 𝜙 is present in

the open loop input transfer function. In order to simultaneously control the MPPT and the output

factors relating the input voltage to the output control variable need to be derived and decoupled

from the input voltage control loop as shown in the non-linear approach. The transfer functions

of the state variable to the output control variable when the input voltage is considered to be

constant are:

85

90

95

100

105

110M

agni

tude

(dB

)

100 101-91

-90.5

-90

-89.5

-89

Phas

e (d

eg)

Magnitude and Phase Plot of the Input Transfer Function

Frequency (rad/s)

108

𝑇�⃑𝑂𝐿2(𝑠) =𝑥�2(𝑠)𝜙�(𝑠)

�𝑢�2=0, 𝜓�𝐵𝐵=0

= (𝑠𝐼 − 𝐴𝑎𝑣𝑔)−1 �1𝜋�𝐴2�⃑�2� +

1𝜋�𝐵�⃑ 2𝑈��⃑ 2��

(4.50)

The relation between the input and output control variable characterized by Equation (4.41)

below which corresponds to the first entry of the matrix.

𝑇�⃑𝑂𝐿2,11(𝑠) =𝑣�𝑖𝑛(𝑠)𝜙�(𝑠)

=

�𝑘2𝐿𝑙𝑘 + 𝐿𝑓��2𝑉𝑖𝑛

𝐿𝑙𝑘 +𝐿𝑓𝑘2

− 𝑉𝑜𝑢𝑡𝑘2𝐿𝑙𝑘 +

𝐿𝑓𝑘

�

�𝜋𝐿𝑓 + 𝜋𝑘2𝐿𝑙𝑘�𝑠 − 2𝜙𝑘2

(4.51)

The compensator design in this case would require linearization around a few operating points

which is challenging as the input voltage varies widely and the input current and voltage have a

non-linear relationship. Therefore, it is preferable to derive the non-linear input state-space model

and identify the necessary decoupling factors to be able to simultaneously control the output

voltage and MPPT.

4.3.3 Input Voltage Loop Compensator Design

The open-loop dc-dc converter cannot track the maximum power point voltage. A maximum

power point tracking algorithm needs to be used to this end. This voltage will then serve as the

input reference to the input voltage loop. A commonly used MPPT algorithm, perturb and

observe, has been implemented to find the maximum power point. The flowchart in Figure 4.4.2

outlines the algorithm.

A compensator is also required for closed loop operation of the system. Similarly, the closed loop

feedback system needs a phase boost at the crossover frequency, 𝜔𝑐. The magnitude and phase

plot of the compensated system is shown in Figure 4.3.5.

109

Figure 4.3.5: Input closed loop bode plot

Similarly, a second order compensator was designed for the output voltage control loop. The

phase margin of the closed loop system is 40°. The compensator’s equation is shown below.

𝐻2(𝑠) = 251 + 0.02𝑠

𝑠(1 + 1.315 × 10−5𝑠)

(4.52)

-100

-50

0

50

100

150M

agni

tude

(dB

)

Closed Loop Input Magnitude and Phase Plots

Frequency (rad/s)100 102 104 106

-180

-135

-90

Phas

e (d

eg)

110

4.4 Non-Linear Controller Design

4.4.1 Non-Linear Input Model

The input capacitor voltage was considered to be constant in the linearized model and as a result

the dynamics around it was fixed. This is shown by the first order transfer function derived and

shown by Equation (4.49). The ouput control variable is present in this transfer function and has

to be restricted within certain operating points or else the stability of the system will be

compromised. The PV current in this analysis, is however, defined as a non-linear function of the

PV voltage. The differential equations characterizing this model are shown below.

⎩⎪⎪⎪⎨

⎪⎪⎪⎧𝑑𝑖𝑖𝑛𝑑𝑡

=2𝑉𝑖𝑛

𝐿𝑓𝑘2 + 𝐿𝑙𝑘

�2𝜙 + 𝜓

𝜋� −

2𝑉𝑜𝑢𝑡𝑘

𝐿𝑓𝑘2 + 𝐿𝑙𝑘

�𝜙𝜋�

𝑑𝑉𝑃𝑉𝑑𝑡

=1𝐶1


𝑖𝑃𝑉 = 𝑓(𝑉𝑃𝑉)

(4.53)

4.4.2 Input-Side Decoupling Factors

The input to output decoupling factors can be derived from the differential equations,

𝜓𝐵𝐵,𝑑𝑒𝑐𝑜𝑢𝑝(𝑠) = 𝜙(𝑠)�𝑉𝑜𝑢𝑡𝑘𝑉𝑖𝑛

− 2�

(4.54)

These terms need to be added to the input voltage control loop in order to decouple the input

voltage from the output control variable such that MPPT and output voltage regulation can be

achieved simultaneously. This ensures the stability of the loop is independent of the output

111

operating point. The input controller does no longer needs to be linearized around any operating

points as it is fully decoupled from the output. This input controller has been implemented

digitally on the same DSP mentioned above. The MPPT algorithm and the input compensator

were also implemented digitally. The block diagram representation of the control loop has been

shown in Figure 4.4.1 and the MPPT algorithm used is shown in Figure 4.4.2.

Bridge 1

Bridge 2

+VPV

-

iPV

+Vout

-

io

Vpv[n]

Vmpp

Verror[n]Σ b02

b12Z-1 Σ Σ -+

+

-+-

PhaseModulator

S42S32S22S12

ψBB

A/DA/DMPPT

A/D

ipv[n]b22Z-1

+ a12Z-1

a22Z-1

-

Figure 4.4.1: Input Controller Block Diagram

112

START

Next Samplen = n + 1

P[n] - P[n-1] > 0

Measure VPV[n] and IPV[n]

Calculate Instantaneous Power

P[n]= VPV[n] x IPV[n]

Measure VPV[n] and IPV[n]

Calculate Instantaneous Power

P[n]= VPV[n] x IPV[n]

VPV[n]-VPV[n-1] > 0

Vref[n] =Vref[n-1] - C

Vref[n] =Vref[n-1] + C

VPV[n]-VPV[n-1] < 0

Vref[n] =Vref[n-1] - C

RETURN

P[n] - P[n-1] = 0YES

NO

YES NO

YES NO YES NO

Figure 4.4.2: MPPT Algorithm Flowchart

113

4.5 Overall Non-Linear Control Scheme Digital Implementation

The overall control scheme comprising of the two control loops have been implemented

simultaneously on the same DSP and the decoupling factors have been added to the input side as

shown in Figure 4.5.1.

Bridge 1

Bridge 1

+VPV

-

iPV

+Vout

-

io

Vpv[n]

Vmpp

Verror[n]Σ b0

b1Z-1 Σ Σ -+

+

-

+-Phase

Modulator

S42S32S22S12

ψBB

A/DA/DMPPT

A/D

ipv[n]b1Z-1

+ a1Z-1

a1Z-1

-

Vout[n]

Vref

A/DΣ -

++-

Verror[n]b0

b1Σ +

-

ɸ

Z-1

b1 Z-1

+

+Σ b1Z-1

b1Z-1

+

-

-

Σ +

+

PhaseModulator

S11 S21 S31 S41

Ψ*BB

kVin

Vout 2

Figure 4.5.1: Simultaneous MPPT and Output Voltage Control Scheme

114

4.6 Simulation Results

A simulated model of the converter was built using PSIM simulation software to verify the

operation of the circuit. The solar panel and array provided in the renewable energy toolbox of

PSIM was used as input. The circuit parameters have been summarized in Table I in Chapter 3.

The above designed input and output compensators were used in their respective control loops.

The leg-to-leg phase shift, 𝜙 which is determined by the output voltage control loop was

employed for output voltage regulation and the bridge-to-bridge phase shift, 𝜓𝐵𝐵, which is

determined by the input voltage loop was used to track the MPP.

Figure 4.6.1shows the simulation waveforms when a load step change from 80% to 100% was

made at 85ms. The maximum power point has increased from 3200W to 4000W and the

controller tracked the change in the maximum power point voltage from 320V to 350V and has

maintained the output voltage regulated at 400V. The settling time for the maximum power point

voltage was 19ms.

Figure 4.6.2 shows the simulation waveforms when a load step change from 100% to 80% was

made at 85ms. The maximum power point has increased from 4000W to 3200W and the

controller tracked the change in the maximum power point voltage from 350V to 320V and has

maintained the output voltage regulated at 400V. The settling time for the maximum power point

voltage was 40ms.

115

Figure 4.6.1: Load Step Change from 80% to 100%

3.2K3.6K

4KPmppt

0200400

Vpv_array

0

10

Ipv_array

0200400600

Vdc_Link

048

I_RL

0.06 0.08 0.1 0.12Time (s)

020004000

Vpv_array*Ipv_array Vdc_Link*I_RL

(W)

(V)

(V)

(A)

(A)

(W) (W)

116

Figure 4.6.2: Load Step Change from 100% to 80%

4.7 Experimental Results

The existing experimental setup described in Chapter 3 was used along with the addition of a

Solar Array Simulator (SAS), Agilent Technologies E4360A to emulate a solar array.

020004000

Pmppt

200400600

Vpv_array

05

1015

Ipv_array

0200400600

Vdc_Link

048

I_RL

0.06 0.08 0.1 0.12 0.14Time (s)

0K2K4K

Vpv_array*Ipv_array Vdc_Link*I_RL

(W)

(V)

(V)

(A)

(A)

(W) (W)

117

Figure 4.7.1: Experimental waveforms of Vpv from Voc to Vmpp

Figure 4.7.1 shows the experimental waveforms when the converter’s input voltage starts at the

open circuit voltage, 𝑉𝑜𝑐 and when the controller is turned on the feedback loop tracks the

maximum power point voltage such that the converter starts drawing the maximum power point

current from the PV array.

5A/div

200V/div

Vpv

Ipv

Vpri1 Ip1,2

118

Figure 4.7.2: Experimental waveforms of Ipv from Isc to Impp

Figure 4.7.2 and Figure 4.7.3 shows the experimental waveforms when the converter’s input

current starts at the short circuit current, 𝐼𝑠𝑐 and when the controller is turned on the feedback

loop tracks the maximum power point voltage such that the converter starts drawing the

maximum power point current from the PV array.

2.5A/div

75V/div

Ipv

Vpv

119

Figure 4.7.3: Experimental waveforms of Ipv from Isc to Impp

4.8 Chapter Summary

A new non-linear control scheme has been designed for the proposed dual-bridge parallel-series

DC/DC converter presented in Chapter 3. The output and input controller design procedure has

been explained. The non-linear state-space model of the input was given. The necessary

decoupling factors were thereafter, derived and added to the input voltage control loop. This

allowed the converter to simultaneously track MPP and regulate the output voltage. The

simulation results performed in PSIM have verified the concept. The experimental results

obtained from the prototype have validated the concept.

75V/div

Vpri2

Vpv

Ip1,2

Vpri1

120

Chapter 5

Conclusions

5.1 Summary

HDGS systems and the use of renewable energies are vital to reach a more sustainable energy

path. The use of non-renewable energy such as coal and petroleum will continue to contribute to

GHG emissions and become more expensive as the supplies diminish and demand increases. The

leading prospect for a clean, reliable and abundant DG source are renewable energies such as

PVs.

The research presented in this thesis focuses had four objectives as outlined in Chapter 1:

1. Identify the need for DG solutions in the form of hybrid distributed generation systems

and highlight their potential benefits

2. Evaluate the DC-DC PV-PCS requirements and review existing soltions

3. Propose a new 2-bridge parallel-series DC/DC converter topology with the ability to

operate with ZVS over a wide input and load range

4. Propose a non-linear controller for the proposed converter in order to simultaneously

perform MPPT and regulate the output dc-link voltage

Chapter 1 has identified the need for DG solutions in an urban and rural setting. The different

configurations of HDGS have been outlined as well as their advantages and limitations. A new

architecture for hybrid-coupled HDGS, more suitable for powering critical loads has been

proposed. The target application for the research has been established as the ICT sector.

Chapter 2 has highlited the incentives and benefits of PVs. It was established as a suitable source

for the application. The PV-PCS requirements were specified after examining the characteristics

121

of the source. A few existing power conditioning system were reviewed and it was concluded that

a new DC-DC converter encompassing simultaneous MPPT and output regulation was required.

In Chapter 3, the new parallel-series converter topology was described and analyzed. This

topology only requires a minimal number of auxiliary components to achieve ZVS for a wide

load and line range without adding complexity to the design. The converter operation was

verified through simulation results. Experimental results validated the operation and showed that

the converter could achieve ZVS over a wide input voltage and load range.

Chapter 4 presented a linear model of the input and ouput dynamics of the proposed converter.

The coupling between input voltage and ouput control variable was described. The non-linear

model of the input was, therefore given which lead to the derivation of the necessary decoupling

terms for the new scheme. The overall digital implementation of the control scheme was outlined.

The simultaneous MPPT and output voltage regulation were verified by the simulation results and

validated by the experimental results.

The four objectives outlined in Chapter 1 have been met respectively in each of the four chapters.

5.2 Contributions

5.2.1 Major Contributions

• A new ZVS full-bridge topology for PV-PCS has been proposed, described and analyzed

• A new degree of freedom has been introduced in addition to existing leg-to-leg phase

shift

• Design of non-linear control scheme for simultaneous MPPT control and output voltage

regulation

• Digital Implementation of proposed control scheme

122

5.2.2 Minor Contributions

• State-space model of the output converter dynamics

• Linearized state-space model of the input dynamics

• Proposed a new architecture for hybrid-coupled HDGS

5.3 Suggestion for Future Work

The areas in this thesis that can improve upon the work done are:

• Redesign the magnetics such that all the primary and secondary windings could be on one

core

• Implement an adaptive energy storage scheme to achieve ZVS over the load and line

range

• Design a custom IC to provide a complete and integrated control solution for the

proposed topology

• The proposed system performance could be compared to a reference topology in DG

applications

123

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127

Appendix A

PV Characteristics Curve Generator

% M-File Generating Solar Panels/Array Characterictic Curves % %%%%%%%%%%%%%%%%%%% by Amish A. SERVANSING %%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%% DATE: JAN 11, 2012 %%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%% Queen's University , 2012 %%%%%%%%%%%%%%%% %PV Module Specifications: A=1.72; %Ideality factor q=1.6e-19; %Charge of an electron [Coulomb] k=1.380658e-23; %Boltzmann constant [J/K] Eg=1.1; %Band gap energy [eV] Ior=19.9693e-6; %Reverse saturation current at Tr [A] Iscr=3.3; %Short circuit current generated at Tr [A] ki=1.7e-3; %Temperature coefficient of short circuit current[A/K] ns=40; %Number of cells connected in series np=2; %Number of cells connected in parallel Rs=5e-5; %Internal series resistance of a cell [Ohm] Rp=5e5; %Internal parallel resistance of a cell [Ohm] Tr=301.18; %Reference temperature [K] %Initialisation of the parameters for I-V characteristic calculation: V=0; %Initially, I=Isc -> V=0 Vinc=0.01; %Voltage increment Es=0.01; %Relative error tolerance Er=5000; %1st relative error value loop=0; %Initial number of loops %Additional parameters initialisation: NOCT=44; %Typical NOCT [C] G=0.8; %Insolation G [kW/m^2] Ta=313.15; %ambient temperature Ta [K] %Cell temperature: Tc=((NOCT-20)*G/0.8)+(Ta); %Reverse saturation current for Tr: Is=(Ior*((Tc)/Tr)^3)*exp(((q*Eg)/(k*A))*((1/Tr)-(1/Tc))); %Short circuit current:

128

Isc=(Iscr+ki*(Tc+273.15-Tr))*G; %Equivalent shunt resistance: Rsht=(np/ns)*Rp; %Equivalent series resistance: Rst=(ns/np)*Rs; %Calculating P to make F1 subscript indices real and positive%integers P=q/(A*k*Tc); It=np*Isc; I=Isc; %Initialise I=Isc when V=0: Vval=V; %Set of voltage values Ival=Isc*np; %Set of current values while(I>0) %I=0 -> V=Voc, calculating V for all values ofIsc>I>0 %Using Newton-Raphson algorithm for calculating I while(abs(Er)>Es) %While absolute relative approximate error %bigger than specified error tolerance loop=loop+1; %Increase loop count F1=(I)*(1+(Rst/Rsht))-It+(np*Is*exp(P*((V/ns)+I*Rst))+(V/(ns*Rsht))); Fdash=(1+(Rst/Rsht))+np*P*Rs*Is*exp(P*((V/ns)+I*Rst)); Inext=I-(F1/Fdash); %Next value of I for the next loop Er=((Inext-I)/Inext)*100; %New error value to be compared to Es I=Inext; %Set I to be the new value of I if(I<0) %Only allowing I values to be positive I=0; %End algorithm when I<0 break; end; if(loop==50000) %End calculations after 50 000 break; end; end; Ival=[Ival,I]; %Obtain the set of I values Er =1000; %Reset the error value for the algorithm to work if (I ==0) Vval=[Vval,V]; %After I=0, obtain the set of V values

129

break; else Vval=[Vval,V]; %If Isc>I>0, continue calculating V V=V+Vinc; end; end P = [Ival.*Vval]; %Calculate the power values M=max(P) %Find the maximum power %Plot the I-V Characteristic Curve figure(1); plot(Vval,Ival); xlabel('Voltage (V)','FontSize',16); ylabel('Current (A)','FontSize',16); %title('\bf{I-V Characteristics of Solar Panel}','FontSize',24) %text(8,1,{'S=800W/m^2';'T=18{ô}{C}'}, 'Fontsize',16); text(8,1,'{T=40{ô}{C}}', 'Fontsize',16); %text(8,1,'{S=1000W/m^2}','FontSize',16); %text(0.5,6.8,'{800W/m^2}') %text(0.5,6,'{500W/m^2}') %text(0.5,4.8,'{200W/m^2}') grid; hold on; %Plot the P-V Characterisctic Curve figure(2); plot(Vval,Ival.*Vval); %text(15,80,{'S=800W/m^2';'T=18{ô}{C}'}, 'Fontsize',16); text(8,1,'{T=40{ô}{C}}', 'Fontsize',16); %text(15,90,'\bf{S=1000W/}{m^2}','FontSize',16) xlabel('Voltage (V)','FontSize',16); ylabel('Power (W)','FontSize',16); title('\bf{P-V Characteristics of Solar Panel}','FontSize',24) grid; hold on;

130

Appendix B

Input and Output Transfer Function Script

% M-File Generating State Space Equations of proposed Topology % %%%%%%%%%%%%%%%%%% by Amish A. SERVANSING %%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%% DATE: FEB 13, 2012 %%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%% Queen's University 2012 %%%%%%%%%%%%%%%%%%%%% clear all clc %%%%%%%%%%%% Input Side Transfer Fuctions %%%%%%%%%%% %Defining the symbols and Leq: syms Iin Vin C1 Leq Lf Llk Vo Ipv Phi Psi k s PI Leq = Llk + (Lf/k^2) %Defining state and input matrix A1 = [1/Leq 0; 0 (-1/C1)] A2 = [2/Leq 0; 0 (-1/C1)] A3 = A1 B1 = [-1/(k*Leq) 0; 0 1/C1] B2 = B1 B3 = B1 %Defining state vector and input vector X = [Vin;Iin] U = [Vo ;Ipv] %Simplifying to find small-signal relationships P1 = (1/PI)*((A1+A3-A2)*X) P2 = (1/PI)*((B1+B3-B2)*U) P = P1+P2 Q = (1/PI)*((A2*X)+(B2*U)) %Finding Aaverage Aavg = ((Psi)/PI)*(A1+A3) + ((Phi-Psi)/PI)*A2 %Determining input transfer function matrices sI = [s 0; 0 s] (inv(sI-Aavg))*P inv(sI-Aavg))*Q %Substituting in the circuit parameters C1 = 30e-6; Llk = 6.5e-6; Lf = 540e-6; k=22/18; Vin = 350; Vo = 400; Phi= 0; PI = pi;

131

%%%%%%%%% Output Side Transfer Fuctions %%%%%%%%%%% %Defining the symbols: syms Cf Lf Vc RL Vin IL Phi Psi k s PI %Defining state and input matrix A1= [0 -1/Lf ; 1/Cf -1/(Cf*RL)] A2 = A1; A3 = A1; A4 = A1; B1 = [k/Lf ; 0] B2 = [(2*k)/Lf ; 0] B3 = B1 B4 = [0; 0] %Defining state vector and input vector X = [IL Vc] U = [Vin] %Finding Aaverage Aavg = A1; %Determining input transfer function matrices sI = [s 0; 0 s] (inv(sI-Aavg))*((1/PI)*B2*U) %Substituting in the circuit parameters Cf = 33e-6; Lf = 540e-6; Vin = 350; k = 22/18; RL = 40;PI = pi;

132

Appendix C

PSIM Converter Schematic

S11

S21

S41

S31

S22

S42

S32

270uLf2

33uCf

160RLA

Ilk1

VP1

VP2

AIlk2

Vsec

VVin1

VVin2

VdcSenseVdc

Vdc

Vds11

Vds31

Vds12

Vds32

G21

G22

G31

G32

G41

G42

AIin1

AIin2

Iin

AIbridge

C1120u

AI_RL

380

Vs1

Vs2

AIsec12u

Lk1

12uLk2

A B

AB

VVlk2

VVlk1

VVlf

VA1

VB1

VA2

VB2

Vds22

Vds42

Vds41

Vds21

Lf1270u

PI

4

A BCBA

VcompVtriDmax CDDmax AB

D

A B

A B

A B

0.8u

0.8u

0.8u

0.8uG12

G22

G32G42

A BBridge2Bridge1

G11

G21

G31

G41

G12

G22

G32

G42

G11_1

G21_1

G31_1

G41_1

G12_1

G22_1

G32_1

G42_1

Bridge1

Bridge2

20uC12

45uLaux

1 AIaux

Vrect

V

10uC13

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