TEXAS INSTRUMENTSEPC – Sept’06
A Practical Introduction toDigital Power Supply Design
Hui Tan (谭徽)TI, Shanghai
TEXAS INSTRUMENTSEPC – Sept’06
C2000: Digital Controller for DPS (20 minutes)• PWM considerations (frequency and resolution)• ADC consideration (sampling rate and resolution)• CPU utilization• Interrupt overhead• MIPS flexibility• Power stage control (multiple topology support)
Software development approach (20 minutes)• Code efficiency and execution time• Modularity• Re-use•“ Analog friendly” approach
Development environment and software (10 minutes) • Incremental build and software visibility• Code Composer Studio -IDE• Real-time debug capabilities
Agenda
TEXAS INSTRUMENTSEPC – Sept’06
TMS320C2000™Digital Signal Controllers
TEXAS INSTRUMENTSEPC – Sept’06
Perf
orm
ance
Integration
FutureDevelopmentSamplingProduction
DeviceF2812
C/R2812F2811
C/R2811F2810
C2810
HigherPerformance
C281xTM
• 150 MIPS• 128-256 KB• 12.5 MSPS ADC
C280xTM
• 100 MIPS• 32-256 KB• 150ps PWM• 7 pin-compatible
devices
F2801 F2808
F2809
DPS
C240xTM
• 40 MIPS• 16-64 KB• 10-bit ADC
10 DevicesLF/C240xA
F = FlashC = Custom ROMR = RAM only
C2000TM Roadmap
LowerCost
C2801 C2802
F2802 F2806
F2801-60 F2802-60
3Q06 Production
F28015 F28016
TEXAS INSTRUMENTSEPC – Sept’06
Typical Control System on a Chip
CPU (DSP/uC/RISC)
+Memory
(FLASH/ROM,RAM)
ADC
Quad Decoder
Capture
i.e. V
i.e. Encoder
i.e. Hall Sensor
CommsCAN
UARTSPIIICIIS
FlexRayUSB
EMAC
RXTX
Control Loop(i.e. PID/IIR)
PWM(‘DAC’ function)
i.e. BuckConverter
TEXAS INSTRUMENTSEPC – Sept’06
High Resolution PWM (HRPWM)
PWM Period
Device Clock(i.e. 100MHz)
Regular PWM Step(i.e. 10ns)
HRPWM Micro Step(~150ps)
HRPWM Technology Breaks A Clock Cycle
Into Smaller Steps Called Micro Steps
(Step Size ~= 150ps)
ms ms ms ms ms ms
Calibration Logic
Background Calibration Logic
Tracks The Number Of Micro Steps
Per Clock To AccountFor Variations CausedBy Temp/Volt/Process
TEXAS INSTRUMENTSEPC – Sept’06
HRPWM: Enabler For Digital Power Supplies
HRPWM Enabled – Stable OutputRegular (10nS) PWM – Not Stable ‘Hunting’
Buck DC/DC Converter
HRPWMonly found on
F280x Devices!!
TEXAS INSTRUMENTSEPC – Sept’06
Execution time analysis (1 of 2)
MIPS = 100 MIPS = 150PWM CPU CPU # loops PWM CPU CPU # loops(KHz) (cycles) overhead (KHz) (cycles) overhead125 800 5.1% 29.2 125 1200 3.4% 44.6250 400 10.3% 13.8 250 600 6.8% 21.5500 200 20.5% 6.1 500 300 13.7% 10.0750 133 30.8% 3.6 750 200 20.5% 6.1
1000 100 41.0% 2.3 1000 150 27.3% 4.2
MSPS = 3 MSPS = 6.25 MSPS = 12PWM # Channels PWM # Channels PWM # Channels(KHz) (KHz) (KHz)125 24 125 50 125 96250 12 250 25 250 48500 6 500 13 500 24750 4 750 8 750 161000 3 1000 6 1000 12
CPU utilization -# Loops vs PWM freq.
ADC utilization -# Channels ( “Loops”) vs PWM freq.
TEXAS INSTRUMENTSEPC – Sept’06
Execution time analysis (2 of 2)
CPU loading -PWM freq. vs CPU%
loops = 1 loops = 2 loops = 3 loops = 4PWM CPU BG BG CPU BG BG CPU BG BG CPU BG BG(KHz) load (MIPS) (KHz) load (MIPS) (KHz) load (MIPS) (KHz) load (MIPS) (KHz)125 5.6% 142 94 7.8% 138 92 9.9% 135 90 12.1% 132 88250 11.2% 133 89 15.5% 127 85 19.8% 120 80 24.2% 114 76500 22.3% 117 78 31.0% 104 69 39.7% 91 60 48.3% 78 52750 33.5% 100 67 46.5% 80 54 59.5% 61 41 72.5% 41 28
1000 44.7% 83 55 62.0% 57 38 79.3% 31 21 96.7% 5 3
CPU = 100 MIPS, BG code = 1500 instructionsloops = 1 loops = 2 loops = 3 loops = 4
PWM CPU BG BG CPU BG BG CPU BG BG CPU BG BG(KHz) load (MIPS) (KHz) load (MIPS) (KHz) load (MIPS) (KHz) load (MIPS) (KHz)125 8.4% 92 61 11.6% 88 59 14.9% 85 57 18.1% 82 55250 16.8% 83 56 23.3% 77 51 29.8% 70 47 36.3% 64 43500 33.5% 67 44 46.5% 54 36 59.5% 41 27 72.5% 28 18750 50.3% 50 33 69.8% 30 20 89.3% 11 7 108.8% -9 -6
1000 67.0% 33 22 93.0% 7 5 119.0% -19 -13 145.0% -45 -30
CPU = 150 MIPS, BG code = 1500 instructions
TEXAS INSTRUMENTSEPC – Sept’06
Power Topology support
Multiple channel DC-DC buck converter/s
EPWM1A
Vin1 Vout1
EPWM2A
EPWM3A
EPWM4A
Vin2
Vin3
Vin4
Vout2
Vout3
Vout4
Buck #1
Buck #2
Buck #3
Buck #4
Target§ DC-DC power supplies§ Distributed power systems§ UPS
How Many Channels?
Frequency pairs8Indep. frequency5
9501
TEXAS INSTRUMENTSEPC – Sept’06
Power Topology support
Multi-phase Interleaved DC-DC converter
Target§ DC/DC systems§ High efficiency§ High power
How Many Phases ?
External. D’Band5Internal. D’Band3
9501
TEXAS INSTRUMENTSEPC – Sept’06
Power Topology support
Phase Shifted Full-bridge DC-DC converterwith Zero Voltage Switching
Target§ AC/DC Rectifiers§ DC/DC systems§ High efficiency§ High power
19501
How Many Converters ?
TEXAS INSTRUMENTSEPC – Sept’06
Fault Management support
TEXAS INSTRUMENTSEPC – Sept’06
A Practical Introduction toDigital Power Supply
Design
Part-II
TEXAS INSTRUMENTSEPC – Sept’06
Modularity, re-useefficiency……
Software
TEXAS INSTRUMENTSEPC – Sept’06
Defining “GOOD” Software
q Modularity – blocks with well defined inputs / outputs
(“cause and effect”)
q Multiple instantiation of same module or function
q De-lineation (separation) between code and device peripherals
or target h/w i.e. use of peripheral (h/w) drivers
q Re-useable / Re-targetable (maximize return on investment)
q Efficient & high performance – code execution in min. time
q Easy to use / read / interpret / debug / modify ….. i.e. friendly!
TEXAS INSTRUMENTSEPC – Sept’06
Exploring Ideas / Methods1. System Framework
§ Good choice for addressing many power systems (even complex ones)§ Simple to use and understand§ Efficient (incurs only 1 ISR context save/restore)§ Deterministic (all events synchronous and submultiples of ISR freq.)§ High degree of visibility during debug and development
Back-ground loop (BG)• C / C++, large code, complex, feature rich, key customer differentiator• System intelligence / personality, heavy in “if then else”
Interrupt Service Routine (ISR) – Main control loop•“ lean and mean” in-line assembly (ASM) results in a very small footprint.• Typically “Math function” type code (very few “if then else” branches or loops)• Once developed, changes very little. Low maintenance burden.
1 of 4
TEXAS INSTRUMENTSEPC – Sept’06
Exploring Ideas / Methods
2. In-line assembly ISRHow complex ?
How much code development ?How much maintenance burden ?How wasteful on memory ?
Number of Instruction (or cycles) words
3. ASM Macros – great for modularity !Modern compilers support:ØMacro parameter passingØMacro variable & lable substitution
Benefits:Ø No call/return overhead (save 8 cycles/call)Ø Can easily build self contained modules (modular!)Ø Supports multiple instantiationØ Supports “Re-entrancy”Ø Re-useable
PWM(KHz) 100 150200 500 750250 400 600300 333 500350 286 429400 250 375500 200 300
MIPS
PWM(KHz) 100 150200 2.0% 1.3%250 2.5% 1.7%300 3.0% 2.0%350 3.5% 2.3%400 4.0% 2.7%500 5.0% 3.3%
MIPS
% impact per 10 instructions
2 of 4
Fear facto
r !
TEXAS INSTRUMENTSEPC – Sept’06
3 of 4
Module example 2• Single In / Single out• Configurable• m, b, Constant ?
or Variable ?• No History• Multiple Instantiation?
f(x) = mx+ b
Out = m.In+ b
Module example 3• Single In / Single out• Non-Configurable• History• Multiple Instantiation?
In OutBoxCarAvg
X(n)X(n-1)X(n-2)X(n-3)
f(x) = ( xn + xn-1+ xn-2 + xn-3 ) / 4
Exploring Ideas / Methods4. Modularity
TEXAS INSTRUMENTSEPC – Sept’06
5. Module “connectivity”
Exploring Ideas / Methods 4 of 4
// pointer & Net declarationsInt *In1A, *In1B, *Out1, *In2A,...Int Net1, Net2, Net3, Net4,...
// “connect” the modulesIn1A=&Net1; In1B=&Net2; Out1=&Net5;In2A=&Net3; Out2=&Net6;In3A=&Net4; Out3=&Net7;In4A=&Net5; In4B=&Net6; In4C=&Net7; Out4=&Net8;In5A=&Net7; Out5=&Net9;
; Execute the code
f1f2f3f4f5
Initialization time (“C”) Run time (ASM macros)
TEXAS INSTRUMENTSEPC – Sept’06
Module TypesPeripheral Independent Peripheral Dependent &
Application Configurable
“Peripheral Drivers”
TEXAS INSTRUMENTSEPC – Sept’06
Why use Peripheral Drivers ?Depends on:• PWM frequency• System clock frequency
Depends on:• # ADC bits (10 / 12 ?)• Unipolar, Bipolar ?• Offset ?
CPU dependency only:• Math / algorithms• Per-Unit math (0-100%)• Independent of Hardware
TEXAS INSTRUMENTSEPC – Sept’06
Digital PWM -101
countsKHzMHz
ffT
PWM
SYSCLKPWM 1000
100100
===(Note: Units = # sysclksor “counts”)
Compare = Duty x Periode.g. 30% x 1000 = 300 counts
à Q15 x Q0 = Q15 (32 bit format: SSII IIII IIIIIIIII.FFF FFFF FFFFFFFF )à Q0 (16 bit format: SIII IIII IIIIIIII )
TEXAS INSTRUMENTSEPC – Sept’06
Digital Power Modules – some examplesDescr. # Cycles Descr. # Cycles
Controller,2 pole / 2 zero
Biquaddigitalfilter
Inversesquarefunction
PFCCurrentCommandfunction
Slew rateLimiterfunction
PFC over-voltagemonitor
PFC 2-phaseInterleavedPWMs/w driver
Zero VoltageSwitched Full BridgePWMs/w driver
Analog / Digital conv.Sequencers/w driver
Multi-phase3InterleavedPWMs/w driver
36
46
78
30
17
25
14
26
57
15
Symbol Symbol
TEXAS INSTRUMENTSEPC – Sept’06
28xx AC/DC Rectifier – Reference design
• 1000W / 48 V• F2810 DSP based• 2 Phase PFC-IL• Phase shifted ZVS-FB• 200 KHz PWM (DC/DC)• 100 KHz PWM (PFC)
AA
TEXAS INSTRUMENTSEPC – Sept’06
PFC (2PHIL) Software control flow
TEXAS INSTRUMENTSEPC – Sept’06
DC-DC (ZVSFB) Software control flow
TEXAS INSTRUMENTSEPC – Sept’06
CPU Bandwidth utilizationFW_Isr
ADCSEQ2_DRVCNTL_2P2Z(1)CNTL_2P2Z(2)ZVSFB_DRV
ADCSEQ1_DRVFILT_2P2Z
AC_LINE_RECT
Context Save
Every ISR call
Int AckContext restore
Return
200 KHz
50 KHz 50 KHz 50 KHz 50 KHz
Time Slice mgr
PFC_OVPPFC_ICMD
CNTL_2P2Z(4)PFC2PHIL_DRV
TS1BOXCAR_AVG(1)BOXCAR_AVG(2)
PFC_ISHAREExecPS(1:50)
CNTL_2P2Z(3)
TS2
PFC_OVPPFC_ICMD
CNTL_2P2Z(4)PFC2PHIL_DRV
TS3
FILT_BIQUADINV_SQR
TS4
MIPS = 100 # inst / uS = 100 PWM(KHz) = 200# TS = 4 # inst / time slice = 500 PWM(bits) = 9.0
S. rate = 200 Sampling period = 5.0
ISR Rate Function / Activity # Cyc Tot. Cyc. StatsAll 200KHzContext Save / Restore 32 292 %Util
200KHzISR Call / Return / Ack 24 58%200KHzTime slice Mgmt 12200KHz ADCSEQ2_DRV 14200KHz CNTL_2P2Z 1 (V loop) 36200KHz CNTL_2P2Z 2 ( I loop) 36200KHz I_FOLD_BACK 25200KHz ZVSFB_DRV 14200KHz ADCSEQ1_DRV 57200KHz FILT_2P2Z 35200KHz AC_LINE_RECT 7
TS1 100KHz PFC_OVP 25 117 %Util100KHz PFC_ICMD 30 82%100KHz CNTL_2P2Z 4 (I loop) 36 #Cyc. Rem.100KHz PFC2PHIL_DRV 26 91
TS2 50KHz BOXCAR_AVG 1 42 145 %Util50KHz BOXCAR_AVG 2 42 87%100 Hz PFC_ISHARE 15 #Cyc. Rem.50KHz Execution Pre-scaler(1:50) 10 631KHz CNTL_2P2Z 3 (V loop) 36
TS3 100KHz PFC_OVP 25 117 %Util100KHz PFC_ICMD 30 82%100KHz CNTL_2P2Z 4 (I loop) 36 #Cyc. Rem.100KHz PFC2PHIL_DRV 26 91
TS4 50KHz FILT_BIQUAD 46 124 %Util50KHz INV_SQR 78 83%
#Cyc. Rem.84
BG Function / Activity # inst. Tot.Cyc. StatsComms + Supervisory 400 434 + Soft-Start + Other ?SLEW_LIMIT 1 17SLEW_LIMIT 2 17
87%12.629.0 34.4
% ISR utilization = Spare ISR MIPS =
BG loop rate (KHz) / (uS) =
TEXAS INSTRUMENTSEPC – Sept’06
Exploring execution limits / scenariosPFC-2phase IL / DCDC-ZVSFB
PFC-1phase / DCDC-ZVSFB (i.e. with PFC current share removed)
MIPS = 100
S. Rate CPU util. CPU spare BG Rate(KHz) (%) (MIPS) (KHz)175 69% 31.2 71.9200 79% 21.4 49.3225 88% 11.6 26.7250 98% 1.8 4.0300 118% -17.9 -41.2350 138% -37.6 -86.5
MIPS = 150
S. Rate CPU util.CPU spare BG Rate(KHz) (%) (MIPS) (KHz)175 46% 81.2 187.2200 52% 71.4 164.5225 59% 61.6 141.9250 66% 51.8 119.2300 79% 32.1 74.0350 92% 12.5 28.7
MIPS = 100
S. Rate CPU util. CPU spare BG Rate(KHz) (%) (MIPS) (KHz)175 76% 23.5 54.2200 87% 12.6 29.0225 98% 1.7 3.9250 109% -9.3 -21.3275 120% -20.2 -46.5300 131% -31.1 -71.7
MIPS = 150
S. Rate CPU util.CPU spare BG Rate(KHz) (%) (MIPS) (KHz)175 51% 73.5 169.4200 58% 62.6 144.2225 66% 51.7 119.1250 73% 40.8 93.9275 80% 29.8 68.7300 87% 18.9 43.5
TEXAS INSTRUMENTSEPC – Sept’06
Analog “look and feel” 1 of 2
PFC stage shownAt bootup.
• Full control during start-up / boot-up, very deterministic• Module “connections” are dynamically configurable• Multiple start-up or re-start scenarios possible (safe, diagnostic, fast, power limited,…)• Also invaluable during development and debug
TEXAS INSTRUMENTSEPC – Sept’06
Analog “look and feel” 2 of 2
Incremental System Start-up (2)• Closed loop Voltage control mode• Check Boost voltage feedback• Check open loop PFC current.
TEXAS INSTRUMENTSEPC – Sept’06
Incremental build,Visibility, IDE, Real-time Debug ……
Code development
TEXAS INSTRUMENTSEPC – Sept’06
System Commissioning – Incremental BuildIB1: Validate Interrupt gen., PWM drivers, and pseudo DAC utility
ZVSFB_phase
Watch Window
ZVSFB_llegdb
ZVSFB_rlegdb
PFC2PHIL_duty
xxxx
Watch Window
xxxx
xxxx
EV
HW
phase
llegdb
rlegdb
PWM1
PWM2
PWM7
PWM8
ZVSFB
DRV
ZVSFB_phase
ZVSFB_llegdb
ZVSFB_rlegdb
EV
HW
Duty
T2PWM
T4PWM
PFC2PHILDRV
Adj
PFC2PHIL_duty
SinGenT1
FreqGain OutOffset
RampGen
FreqGain OutOffset
PWMDACDRV
EV
HW
PWM10
PWM12
In1
In2
1 of 3
TEXAS INSTRUMENTSEPC – Sept’06
IB2: Open loop test with feedback meas. via ADC driver
System Commissioning – Incremental Build 2 of 3
TEXAS INSTRUMENTSEPC – Sept’06
IB3: Closed loop operation with watch window and DAC visibility
System Commissioning – Incremental Build 3 of 3
TEXAS INSTRUMENTSEPC – Sept’06
Code Composer Studio -IDE
TEXAS INSTRUMENTSEPC – Sept’06
Real-Time debug 1 of 2
TEXAS INSTRUMENTSEPC – Sept’06
Real-Time debug 2 of 2
q RTDebugis a Non-intrusive debug scheme supportedvia on-chip H/W (utilizes spare / dead cycles in CPU buses)
q Allows user full interaction while application runs un-disturbed (at speed)
q Can interrogate / modify any memory, register, variable, ..etcq Supports Single step / Break point in back-ground code
while ISR (time critical loops + PWM) continues to run at speed.q Clock / cycle profiling allows time critical code analysis.
TEXAS INSTRUMENTSEPC – Sept’06
……. The End
TEXAS INSTRUMENTSEPC – Sept’06
Spare
TEXAS INSTRUMENTSEPC – Sept’06
Q-Math 101Fixed point format – S I . F (Sign / Integer . Fraction)
-8 < N < +7.99999 …SIII. FFFF FFFFFFFFQ12
-32,768 < N < +32,767SIII IIII IIIIIIIIQ0
-4 < N < +3.99999 …SII.F FFFF FFFFFFFFQ13
-2 < N < +1.99999 …SI.FF FFFF FFFFFFFFQ14
-1 < N < +0.99999 …S.FFF FFFF FFFFFFFFQ15
Qnx Qm= Qn+m, e.g. Q15 x Q14 = Q29SSI.F FFFF FFFFFFFFFFFFFFFFFFFFFFFF(32 bit format)SI.FF FFFF FFFFFFFF(adjusted for Q14, 16 bit format)
e.g. Q15 x Q15 = Q30SS.FF FFFF FFFFFFFFFFFFFFFFFFFFFFFF(32 bit format)S.FFF FFFF FFFFFFFF(adjusted for Q15, 16 bit format)
TEXAS INSTRUMENTSEPC – Sept’06
S/W driver module – ZVSFB 1 of 2
TEXAS INSTRUMENTSEPC – Sept’06
S/W driver module – ZVSFB 2 of 2
ZVSFB_DRV
Phase calculation tableZVSFB_phase
Angle (deg) per unit % Q15 (Dec) Q15 (Hex)
180 1.00 100% 32767 7FFF160 0.89 89% 29126 71C6140 0.78 78% 25485 638D120 0.67 67% 21845 5554100 0.56 56% 18204 471B90 0.50 50% 16384 3FFF70 0.39 39% 12743 31C650 0.28 28% 9102 238D30 0.17 17% 5461 155510 0.06 6% 1820 071C0 0.00 0% 0 0000
-10 -0.06 -6% 63716 F8E3-30 -0.17 -17% 60075 EAAA-50 -0.28 -28% 56434 DC71-70 -0.39 -39% 52793 CE38-90 -0.50 -50% 49152 C000
-100 -0.56 -56% 47332 B8E3-120 -0.67 -67% 43691 AAAA-140 -0.78 -78% 40050 9C71-160 -0.89 -89% 36409 8E38-180 -1.00 -100% 32768 8000
Dead band calculation table (nS)
HSPCLK = 150 1.00E+06MHz (Note: this is the EV clock)
DBT[3:0] DBT[3:0] 00 04 08 0C 10 14(dec) (hex) 1 2 4 8 16 32
0 0 0 0 0 0 0 01 1 7 13 27 53 107 2132 2 13 27 53 107 213 4273 3 20 40 80 160 320 6404 4 27 53 107 213 427 8535 5 33 67 133 267 533 10676 6 40 80 160 320 640 12807 7 47 93 187 373 747 14938 8 53 107 213 427 853 17079 9 60 120 240 480 960 1920
10 A 67 133 267 533 1067 213311 B 73 147 293 587 1173 234712 C 80 160 320 640 1280 256013 D 87 173 347 693 1387 277314 E 93 187 373 747 1493 298715 F 100 200 400 800 1600 3200
ZVSFB_dbpscale (hex)ZVSFB_xlegdb
TEXAS INSTRUMENTSEPC – Sept’06
S/W driver module – PFC2PHIL 1 of 2
EV
HW
Duty
T2PWM
T4PWM
PFC2PHILDRV
Adj
Net1
Net2
TEXAS INSTRUMENTSEPC – Sept’06
S/W driver module – PFC2PHIL 2 of 2
PFC2PHIL_DRVHSPCLK = 100 1.00E+06 MHz (Note: this is the EV clock)PFC frequency = 100 1.00E+03KHz
Duty cycle calculation tablePFC2PHIL_duty Period count (dec) Period count (hex)
per unit Duty(%) Q15 (Dec)Q15 (Hex) 999 03E7Compare Count (dec)Compare Count (hex)
1.00 100% 32767 7FFF 999 03E70.90 90% 29490 7332 899 03830.80 80% 26214 6665 799 031F0.70 70% 22937 5998 699 02BB0.60 60% 19660 4CCC 599 02570.50 50% 16384 3FFF 499 01F30.40 40% 13107 3332 399 018F0.30 30% 9830 2666 299 012B0.20 20% 6553 1999 199 00C70.10 10% 3277 0CCC 99 00630.00 0% 0 0000 0 0000-0.10 0% 62259 F333-0.20 0% 58982 E666-0.30 0% 55706 D999-0.40 0% 52429 CCCC-0.50 0% 49152 C000-0.60 0% 45875 B333-0.70 0% 42598 A666-0.70 0% 42598 A666-0.90 0% 36045 8CCC-1.00 0% 32768 8000
Not Defined