"A probabilistic approach to clock cycle prediction" A probabilistic approach to clock cycle...

"A probabilistic approach to clock cycle prediction"

A probabilistic approach to A probabilistic approach to clock cycle predictionclock cycle prediction

JJ. Dambre,. Dambre,

D. Stroobandt and J. Van CampenhoutD. Stroobandt and J. Van Campenhout

TAU, December 2, 2002TAU, December 2, 2002


OutlineOutline•System-level interconnect predictionSystem-level interconnect prediction•Prediction of minimal clock cyclePrediction of minimal clock cycle•New probabilistic approachNew probabilistic approach•Experimental resultsExperimental results•Main causes of errorsMain causes of errors•Conclusions & future workConclusions & future work


System-level interconnect System-level interconnect predictionprediction

PredictPredictlength distribution of length distribution of

interconnections interconnections in final in final

implementationimplementation

PredictPredictlength distribution of length distribution of

interconnections interconnections in final in final

implementationimplementation

Measured Measured or typical or typical

valuesvalues

Parameters Parameters from from

interconnecinterconnect topologyt topology

Technology Technology and design and design parametersparameters

Real or Real or hypotheticalhypothetical



Parameters from

interconnect

topology

Technology and design

parameters

Wire length Wire length distributiondistributionWire length Wire length distributiondistribution

ProbabilisticProbabilistic: : • wire length variability across wire length variability across

multiple layout runsmultiple layout runs• assumed homogeneous: all point-to-assumed homogeneous: all point-to-

point wires “drawn” independently point wires “drawn” independently from same distributionfrom same distribution

NotNot : accurate lengths of individual : accurate lengths of individual wires for particular run!wires for particular run!



Parameters from

interconnect

topology


parameters


Interconnect lengths affect:Interconnect lengths affect:

•routing requirements (cost!)routing requirements (cost!)

•power dissipationpower dissipation

•yieldyield

•performance (clock cycle)performance (clock cycle)

•etc. ...etc. ...



Parameters from

interconnect

topology


parameters


Assess/compare impact of, e.g.:Assess/compare impact of, e.g.:• new/future technological parametersnew/future technological parameters• physical design options (e.g. layout physical design options (e.g. layout

or cell aspect ratio)or cell aspect ratio)• optimization algorithms that change optimization algorithms that change

circuit topologycircuit topology

without having to perform physical without having to perform physical design!design!




Prediction of minimal clock cyclePrediction of minimal clock cycle

Distribution of Distribution of gate and wire delaysgate and wire delays


Distribution and expected valueDistribution and expected valueof minimal clock cycleof minimal clock cycle


Parameters Parameters from from

interconnecinterconnect topologyt topology

Technology Technology and design and design parametersparameters



Previous work:Previous work:prediction of critical path delay in prediction of critical path delay in BACPAC BACPAC

(1)(1)





Wire length Wire length distributiondistributionWire length Wire length distributiondistribution Length of average and Length of average and

global wireglobal wireLength of average and Length of average and

global wireglobal wire

Delays of average and Delays of average and global “gate+wire”global “gate+wire”

Delays of average and Delays of average and global “gate+wire”global “gate+wire”

Critical path delayCritical path delayCritical path delayCritical path delay

additionaddition(max. logic (max. logic

depth)depth)

(1) Sylvester et al., SLIP 1999


(2) Iqbal et al., SLIP 2002

Previous work:Previous work:prediction of critical path delay prediction of critical path delay

distribution distribution (2)(2)

Distribution of Distribution of “gate+wire” delays“gate+wire” delays

Distribution of Distribution of “gate+wire” delays“gate+wire” delays




Distribution and expected Distribution and expected valuevalue

of critical path delayof critical path delay

Distribution and expected Distribution and expected valuevalue

of critical path delayof critical path delay

Monte Carlo Monte Carlo sampling sampling

(max. logic depth)(max. logic depth)

Concept: Concept:

average delay average delay delay of delay of average wireaverage wire


Prediction of minimal clock cycle?Prediction of minimal clock cycle?

Problem: minimal clock cycle relates to Problem: minimal clock cycle relates to maximalmaximal combinatorial delay ! combinatorial delay !

Maximal logic depth does not model :Maximal logic depth does not model :• equal logic depth, but different number of pathsequal logic depth, but different number of paths

• paths with less than maximal logic depth can also paths with less than maximal logic depth can also become slowestbecome slowest

Need model that captures impact of Need model that captures impact of

parallellism on extreme value !!parallellism on extreme value !!

=> more important as interconnect represents => more important as interconnect represents ever increasing fraction of total delay !ever increasing fraction of total delay !




Prediction of minimal clock Prediction of minimal clock cycle?cycle?

Parameters from

interconnect

topology


parameters

Distribution of gate Distribution of gate and wire delaysand wire delays

Distribution of gate Distribution of gate and wire delaysand wire delays

Available:Available:•““gate+wire” (= gate+wire” (= segmentsegment) delay ) delay

distributiondistribution•topology of circuit graphtopology of circuit graph

Assumption:Assumption:•homogeneous: all individual homogeneous: all individual

segment delays “drawn” segment delays “drawn” independentlyindependently from from same same distributiondistribution

Distribution and expected valueDistribution and expected valueof minimal clock cycle ?of minimal clock cycle ?

Distribution and expected valueDistribution and expected valueof minimal clock cycle ?of minimal clock cycle ?


Prediction of minimal clock Prediction of minimal clock cycle: cycle:

probabilistic principles probabilistic principles

Sum of independent Sum of independent variables?variables?

log(P

(d))

log(d)

log(P

(D))

log(d)

log(P

(d))

log(d)

??lo

g(P

(D))

log(d)

??lo

g(P

(D))

log(d)

??

0 2121 .i idPidPddP

convolutionconvolution of distributions of distributions (discrete or continuous)(discrete or continuous)


Sum of independent variables:Sum of independent variables:path delay distribution as a function of logic path delay distribution as a function of logic

depthdepth

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

1.0E+00

1 10 100 1000

delay d (arbitrary units)

P(de

lay

= d) depth 1

depth 10depth 8

depth 6

depth 4

depth 2



probabilistic principlesprobabilistic principles

useuse cumulative cumulative distributionsdistributions

imim dPdddP 121 ,,,max

log(P

(d))

log(d)

log(P

(D))

log(d)

log(P

(D))

log(d)

??

log(P

(d))

log(d)

log(P

(d))

log(d)

Maximum of independent Maximum of independent variables? variables?


Maximum of independent variables:Maximum of independent variables:maximum path delay distribution for independent pathsmaximum path delay distribution for independent paths

(logic depth = 4)(logic depth = 4)

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

1.0E+00

1 10 100 1000Maximal path delay d (arbitrary units)

P(m

ax. d

elay

= d

)

1 path

10 paths

8 paths

6 paths

4 paths

2 paths



independent paths?independent paths?Segment delays might be approximately Segment delays might be approximately independent, butindependent, butpaths in a circuit are generally paths in a circuit are generally notnot independent! independent!

Find interconnect topology with:Find interconnect topology with:•same number of wire same number of wire

segmentssegments• independent paths onlyindependent paths only•approx. same clock cycle approx. same clock cycle

distributiondistribution

Basic concept of new approach: Basic concept of new approach: uncoupling of dependencies!uncoupling of dependencies!


CriticalityCriticality SegmentSegmentss

11

22

33

44

55

66 66


11

22

33

44

55 99

66 66


11

22

33

44 11

55 99

66 66


11 00

22 00

33 11

44 11

55 99

66 66depth 6depth 5depth 4 depth 3


independent paths?independent paths?Definition:Definition:wire criticality = maximal depth of any path through wire criticality = maximal depth of any path through that wirethat wire



independent paths?independent paths?Notion:Notion:Sensitivity of clock cycle to individual wire delay Sensitivity of clock cycle to individual wire delay strongest on paths with depth = wire criticalitystrongest on paths with depth = wire criticality

Approximations:Approximations:1.1. Ignore impact on clock Ignore impact on clock

cycle through paths with cycle through paths with smaller depthsmaller depth

2.2. Assume that wires with Assume that wires with equal criticality have equal criticality have equal impact on clock equal impact on clock cyclecycle



independent path modelindependent path modelEquivalent topology:Equivalent topology:• find wire criticalities (possible without enumeration of all find wire criticalities (possible without enumeration of all

paths !)paths !)• for each depth i: for each depth i:

equivalent paths(i) = nets(crit = i) / iequivalent paths(i) = nets(crit = i) / i

CriticalityCriticality SegmentsSegments Eq. pathsEq. paths

11 00 00

22 00 00

33 11 0.330.33

44 11 0.250.25

55 99 1.81.8

66 66 11

0.30.3330.20.2551.81.80011




Prediction of minimal clock cyclePrediction of minimal clock cycle

Parameters from

interconnect

topology


parameters

Distribution of Distribution of segment delayssegment delaysDistribution of Distribution of

segment delayssegment delays




• Technology parameters from ITRS Technology parameters from ITRS (ed. 2001, technology node 2001)(ed. 2001, technology node 2001)

• Delay models from BACPAC Delay models from BACPAC (e.g. Sakurai, Chern, ...)(e.g. Sakurai, Chern, ...)

Segment Segment delaysdelays

Experimental validationExperimental validation

68 benchmarks from 68 benchmarks from LGSynth series:LGSynth series:• sizes of 527 to 24819 blockssizes of 527 to 24819 blocks• logic depths of 6 to 284logic depths of 6 to 284

Measured Measured distribution of distribution of maximal path maximal path

delaysdelays

100 placement runs 100 placement runs eacheach

Predicted Predicted distribution of distribution of maximal path maximal path

delaysdelays

segment segment criticality criticality distributiondistribution

segment segment delay delay distributiondistribution

max. path max. path delaydelay

BenchmarBenchmarkk

circuitscircuits

1.1. traditional: traditional: sum of sum of average average segment segment delaysdelays

2.2. newnew


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6A

vera

ge m

axim

al p

ath d

elay

(ns

)

ExperimentalTraditional estimationNew estimation


Correlation:Correlation:

0.923 (traditional)0.923 (traditional)

0.959 (new)0.959 (new)


0

5

10

15

20

25

-95

-85

-75

-65

-55

-45

-35

-25

-15 -5 5 15 25

35

45

55

65

75

85

95

Relative error (%)

Num

ber

of

ben

chm

arks

Traditional estimationNew estimation


Average relative Average relative error:error:

-29.3% (traditional)-29.3% (traditional)

6.7% (new)6.7% (new)

Within 10%:Within 10%:

•10/68 (14.7%)10/68 (14.7%)

•38/68 (55.9%)38/68 (55.9%)


•21/68 (30.9%)21/68 (30.9%)

•53/68 (77.9%)53/68 (77.9%)




Validity of assumptions?Validity of assumptions?

They ignore that:They ignore that:•some wires may almost always be long/short some wires may almost always be long/short (locally different distribution)(locally different distribution)

•there might be local correlations between wire there might be local correlations between wire lengths (not independent)lengths (not independent)

Both prediction strategies assume that Both prediction strategies assume that individual wire lengths are individual wire lengths are independentindependent and and equally distributedequally distributed random variables random variables


Validity of assumptions?Validity of assumptions?

Monte Carlo experiment to meet Monte Carlo experiment to meet assumptions:assumptions:• take measured segment delay distributiontake measured segment delay distribution• randomly assign delay from distribution to all randomly assign delay from distribution to all

segments and find maximal path delaysegments and find maximal path delay• repeat 1000 times for each circuitrepeat 1000 times for each circuit

Only cause of remaining errors can be Only cause of remaining errors can be equivalent topology!equivalent topology!

Are deviations due to these assumptions Are deviations due to these assumptions or to equivalent topology?or to equivalent topology?


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6A

vera

ge m

axim

al p

ath d

elay

(ns

)

ExperimentalTraditional estimationNew estimation

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8A

vera

ge m

axim

al p

ath d

elay

(ns

)

Experimental (Monte Carlo)Traditional estimationNew estimation

Assumptions or equivalent topology?Assumptions or equivalent topology?

Correlation:Correlation:

0.977 (traditional, vs. 0.977 (traditional, vs. 0.923)0.923)

0.996 (new, vs. 0.959)0.996 (new, vs. 0.959)


0

5

10

15

20

25

-95

-85

-75

-65

-55

-45

-35

-25

-15 -5 5 15 25

35

45

55

65

75

85

95

Relative error (%)

Num

ber

of

ben

chm

arks

Traditional estimationNew estimation

0

5

10

15

20

25

30

35

40

-95

-85

-75

-65

-55

-45

-35

-25

-15 -5 5 15 25

35

45

55

65

75

85

95

Relative error (%)

Num

ber

of

ben

chm

arks

Traditional estimationNew estimation Average relative Average relative

error:error:

-39.1 % (vs. –29.3 -39.1 % (vs. –29.3 %)%)

-7.1 % (vs. 6.7 %)-7.1 % (vs. 6.7 %)

Assumptions or equivalent topology?Assumptions or equivalent topology?


•7.4% (vs. 30.9%)7.4% (vs. 30.9%)

•98.5% (vs. 98.5% (vs. 77.3%)77.3%)


•2.9% (vs. 14.7%)2.9% (vs. 14.7%)

•63.2% (vs. 55.9%)63.2% (vs. 55.9%)


Remaining errors?Remaining errors?

Our equivalent path topology fully Our equivalent path topology fully uncouples all paths. uncouples all paths.

Rather systematical underestimation of Rather systematical underestimation of approximately 7% approximately 7%

But there are alternatives:But there are alternatives:• with same number of segments,with same number of segments,• also using criticalities,also using criticalities,• for which distributions can be calculated !for which distributions can be calculated !


Remaining errors?Remaining errors?

Example: Example: • measured average clock cycle using segment delay measured average clock cycle using segment delay

distr. from one of the benchmark experimentsdistr. from one of the benchmark experiments• result: clock cycle (a) 7.1 % below clock cycle (b)result: clock cycle (a) 7.1 % below clock cycle (b)

(a)(a) (b)(b)

Total uncoupling of paths seems too strong!Total uncoupling of paths seems too strong!

Can model be tuned to include this effect?Can model be tuned to include this effect?




ConclusionsConclusions

• New probabilistic model for clock cycle New probabilistic model for clock cycle prediction:prediction:• captures the essence of circuit parallellismcaptures the essence of circuit parallellism• based on equivalent graph topology with based on equivalent graph topology with

independent pathsindependent paths

• Significantly improved accuracy reached Significantly improved accuracy reached within same assumptions as existing workwithin same assumptions as existing work

• Experimentally verified that most of the Experimentally verified that most of the remaining errors are due to these remaining errors are due to these assumptionsassumptions

• They are OK for many circuits, but very bad They are OK for many circuits, but very bad for some!for some!


Future workFuture work

• More experiments to validate model More experiments to validate model sensitivity to design options its and sensitivity to design options its and usefulness for different applicationsusefulness for different applications

• Combine model with predicted wire length Combine model with predicted wire length distributionsdistributions

• Try to find mathematical foundations for Try to find mathematical foundations for equivalent topologyequivalent topology

• Try to incorporate local effects and study Try to incorporate local effects and study some alternative topologiessome alternative topologies


‘‘mm30a’: an mm30a’: an example ...example ...

Clearly shows Clearly shows inhomogeneity, inhomogeneity,

with many of the with many of the most critical most critical

segments segments systematically systematically

having low delays having low delays

Benchmark mm30a

Criticality

Avera

ge w

ire length

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