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TEXAS A&M UNIVERSITY
DEPARTMENT OF ELECTRICAL & COMPUTER
ENGINEERING
TITLE: DESIGN OF A CAPACITOR-LESS
LINEAR REGULATOR
A project report submitted as a part of the evaluation for
ECEN 704: Analog VLSI Circuit Design
(Spring 2016)
Submitted by: Vijit Dubey (UIN 623008952)
Vivek Srinivasan (UIN 125001025)
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Contents
Introduction ......................................................................................................................... 3
Low Drop-Out regulator (LDO) .......................................................................................... 4
Circuit Design ..................................................................................................................... 5
Simulation Schematic .......................................................................................................... 8
Simulation results ................................................................................................................ 9
Values obtained from simulation ...................................................................................... 12
Conclusion ......................................................................................................................... 12
Scope for future work ........................................................................................................ 12
References ......................................................................................................................... 13
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Introduction
With the increasing effort to integrate all circuits into a single chip, thereby establishing a
SoC solution, the demands for power management unit (PMU) and its integration are
growing [1]. Ideally, each block in the SoC should be supplied by independent regulated
voltage. This can be achieved by using a dedicated on-chip linear voltage regulator for each
circuit in the SoC. The main assumptions that are made on regulators in the SoC are small
silicon area, low power dissipation, and last but not least the absence of external components
that must be connected to the chip, and thus increase the price of the whole system and
occupy pins of chip itself. Linear regulators can be divided into two basic groups [2]:
· Conventional linear regulators
· LDO (low drop-out) regulators
Fig.1 Linear regulator
The only difference between these two topologies, is in orientation of a power transistor.
Conventional linear regulator utilizes a transistor which is connected in common drain, or this
one transistor is replaced by a bipolar transistor (BJT), or two transistors in Darlington
configuration.
In the contrary LDO regulator uses configuration with common source. Both these basic
configurations are depicted in the Fig. 2.
Fig. 2 Basic configuration
The single orientation of a power transistor has a general influence on both working mode
and stability of the linear regulator. The most significant element which has the greatest
influence on transient response of the regulator is the power transistor. This transistor delivers
required current into the load impedance which in turn results in required output voltage. A
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delay which is caused by the power transistor in the control loop is caused by the fact that
gate capacitance of this power transistor represents current voltage converter. The greater
gate capacitance, the greater is the delay. This delay has dominant role in the entire delay of
the control loop.
Also, LDOs generally depend on an external capacitor and its ESR to generate a zero for
stability. The LDO regulators have high output impedance and this high impedance along
with the load capacitance creates a low frequency pole and de-stabilizes the system [3]. In
this project we aim to design and analyze a capacitor-less Low Drop-Out (LDO) Linear
voltage Regulator that can generate this zero internally. This is the motive for this project.
Low Drop-Out Regulator (LDO)
Fig. 3 Low Drop-Out Regulator
The circuit is composed of an input voltage, reference voltage through a band gap buffer,
error amplifier, pass element and the feedback network. The output voltage is regulated by
sensing the output through a voltage divider. This sensed voltage is then feedback through the
error amplifier which forces the voltages at its input to be equal and thus regulate the output.
The error amplifier is realized using a two stage OTA. The first stage is the high gain stage.
Second stage of the two stage OTA is used as an error amplifier stage. The two stages are shown
below.
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Fig. 4 First stage of a two stage OTA used as error amplifier stage
Fig. 5 Second stage of a two stage OTA used as error amplifier stage
Circuit Design
The configuration that we have used for this project comprises of a Miller Capacitor
connecting the end of the first stage to the output. The Miller Capacitance helps in
achieving pole splitting. This serves to make the pole at the end of the first stage dominant
since the effective capacitance here is the Miller Capacitance multiplied by the gain of the
second stage. This circuit alone will not be stable for a wide range of values because there
is a zero introduced by the feed forward conduction path of the Miller Capacitor and there
is another zero because of the resistive divider.
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Fig. 6 Capacitor less LDO Circuit Configuration
There are several ways to make the circuit stable. In this project, we have chosen to insert a
resistor in series with the Miller capacitor to push the right half plane zero away from the
origin. By choosing a large value of resistance, we can push the zero to the left half of the
s-plane which is beneficial to the system stability. Overall, this resistor ensures that the
zero frequency does not occur before the unity gain frequency and helps the system achieve
stability.
The circuit was designed for a supply voltage of 3V with respect to ground. The circuit
diagram is shown in the next page. We have chosen a dropout voltage of 200mV. Hence
the Drop across the pass transistor should be 200mV.
The maximum value of current that this circuit can deliver is 55mA. The size of the pass
transistor for the given value of Vdsat and current is found to be around (W/L) of 46000.
RL,min= Vo/Imax = 2.8/55m = 51 Ω
RL,max= Vo/Imin = 2.8/100u = 28 k Ω
Rds = 1/λIds = 225 Ω
Vref = 1.4 V
Vo = 2.8V
R1 = R2 = 2 MΩ (assumed resistor value >> RL,max)
Gmp= 0.7 A/V.
Let Ap = GmpRds=160
Cgate = Cgs + (1+Ap) Cgd= 65.77 pF.
Assuming GBW >1MHz
GBW = gm1/(2ΠCm)
Let Cm = 2pF
Hence, gm1 = 12.6 uA/V.
VDD
VOUT
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Let us choose 10uA current through M7 and M8 and 30uA current through the other two
branches.Now that we know the drain currents of all the transistors, we design M1 to meet
gm of 12.6 uA/V, and the other transistors M2, M3, M4, M7, M8, M9 and M10 are designed
to meet a Vdsat value of 200mV. M3= M4 and M5=M6. Also we set M5 = 6 M3, so as to set
30uA current in the output pseudo differential stage of the error amplifier.
Transistor W/L
M1 3 * 450nm/180nm
M2 4 * 450nm 180nm
M3, M4 1 * 450nm /180nm
M5, M6 1 * 450nm /180nm
M7 4 * 450nm /180nm
M8 4 * 450nm /180nm
M9, M10 10*450nm /180nm
Fig. 7 Circuit Diagram
Initially, the circuit was simulated using ideal current controlled voltage source for varying
the gate voltage (vbias) of M7 and M8. This was done to ensure there is a low quiescent
current during standby condition by forcing M7 and M8 in cut-off mode. So, as per the
design, Vbias during loading conditions is 2.31V and during standby conditions is 2.7V.
For a practical solution the current controlled voltage source needs to be implemented at the
transistor level. This was done using PMOS current mirror with a current to voltage
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converter. However, the current mirror created loading effects which reduced the operating
range of the circuit. Further problems were found while meeting the required specification of
ground power (<10uW). The current mirror was acting as a load during no load conditions.
Hence, increasing the quiescent current.
Simulation Schematic
Fig. 8 Schematic using ideal CCVS
Fig. 9 Schematic using ideal CCVS continuation
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Fig. 10 Schematic using CCVS at transistor level
Simulation results
Circuit Regulating Voltage to 2.8V
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Loop Gain and Phase
Settling time for a step change in input.
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Power supply rejection ratio for ground
Schematic showing quiescent current
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Values obtained from the Simulation
Specification Value
Power 5.4 µW
Settling time 0.992us
µsec Input Voltage 3V
Drop-out voltage 200 mV
I Load,min 100 µA
I Load,max 55 mA
Phase Margin 48.12°
GBW 934.26 kHz
Conclusion
A capacitor less topology with Miller compensation has been designed and simulated. The target
specifications have been achieved. The compensation capacitor is very small and hence can be
integrated within the chip. A series resistance provides the necessary compensation to achieve
stability. The system has been designed for very low power consumption during standby conditions
(< 10 µW). The settling time was designed to be 992ns.
Scope for future work
The results discussed were for a circuit using an ideal current controlled voltage source for
variation of vbias to two discrete values. An attempt to implement a transistor level current
controlled voltage source was done using current mirror and current to voltage converter
configuration. However, the results were not within the desired specifications. Future work
can be done by designing a better practical transistor level current controlled voltage source.
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References:
[1] A Capacitor-Less Low Drop-Out Voltage Regulator With Fast Transient Response [Online]. Available: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.83.8987&rep=rep1&type=pdf. [2] Capacitor-less Linear Regulator with NMOS Power Transistor [Online]. Available: https://otik.uk.zcu.cz/bitstream/handle/11025/6622/r7c5c8.pdf?sequence=1. [Accessed: 18- Apr- 2016]. [3]Y. Wang, C. Cui, W. Gong, Z. Ning and L. He, "A CMOS low-dropout regulator with 3.3 μA quiescent current independent of off-chip capacitor", APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008. [4]C. Zhan and W. Ki, "An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC", IEEE Trans. Circuits Syst. I, vol. 59, no. 5, pp. 1119-1131, 2012. [5] K. N. Leung and P. K. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691–1702, October 2003. [6]R. Milliken, J. Silva-Martinez and E. Sanchez-Sinencio, "Full On-Chip CMOS Low-Dropout Voltage Regulator", IEEE Trans. Circuits Syst. I, vol. 54, no. 9, pp. 1879-1890, 2007.
