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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle andQuadrature Phase Detector Based on a Relaxation Oscillator
Joo-Hyung Chae , Hyeongjun Ko, Jihwan Park, and Suhwan Kim
Abstract— A quadrature clock corrector uses relaxation oscillators todetect duty-cycle and quadrature phase errors by transforming them intopairs of frequencies, which are then digitized and compared. It achievesgood detection accuracy and can detect a wide range of duty-cycle andquadrature phase errors. The prototype is implemented in a 55-nmCMOS process with a supply voltage of 1.2 V and occupies an areaof 0.003 mm2. The experimental results show that the operation rangeis from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximumduty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phaseerror is 1.1° at 3 GHz.
Index Terms— Dynamic random access memory (DRAM) inter-face, duty cycle, quadrature clock corrector, quadrature phase,relaxation oscillator.
I. INTRODUCTION
The growing ubiquity of cloud platforms means that an increasingamount of data has to be processed in data center servers. Thedevelopment of virtual reality, artificial intelligence, deep learning,and autonomous vehicles also increases the amount of data processedin each product’s memory. These lead to greater demand for thedynamic random access memory (DRAM) with high performanceand high throughput.
The use of rising and falling edges of a multiphase clock signal andthe adoption of a quarter-rate architecture are recently considered forhigh-performance DRAM interfaces [1], [2]. This architecture has alower clock frequency and a more relaxed timing margin on its criticalpath, reducing simultaneous switching noise and power consumption,when compared to full-rate [3] and half-rate [4] designs. In a DRAMinterface with a quarter-rate architecture, high-speed differential clocksignals are divided by two and become quadrature clock signals [5].There can be subject to duty-cycle and quadrature phase errors inthese quadrature clock signals, as they pass down the long clockdistribution tree through many clock buffers, where they may beaffected by supply and ground noise, unbalanced pMOS and nMOSstrengths, and process, voltage, and temperature (PVT) variations.Distortion of the clock signals affects the valid data window onthe operation, and thus various types of quadrature clock correc-tors [4], [6]–[12] have recently been used to perform both duty-cycleand the quadrature phase compensation. In these quadrature clockcorrectors, the precision of the duty-cycle and quadrature phasedetector (PD) is critical because the correction performance dependsdirectly on the detection accuracy of the duty-cycle and quadraturephase [8], [13].
Duty-cycle and quadrature phase errors can be detected by analogcircuits [8], in which an integrator is combined with a comparator.However, this type of circuit can be affected by any error in thecommon-mode or offset voltage in the comparator, matching between
Manuscript received July 2, 2018; revised September 30, 2018 andNovember 14, 2018; accepted November 21, 2018. (Corresponding author:Suhwan Kim.)
J.-H. Chae, H. Ko, and S. Kim are with the Department of Electrical andComputer Engineering, Seoul National University, Seoul 08826, South Korea(e-mail: [email protected]).
J. Park is with SK hynix, Icheon 17336, South Korea.Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2018.2883730
Fig. 1. Architecture of the quadrature clock corrector.
capacitors, the precision of the reference circuit, and any mis-match between the pull-up and pull-down currents in the integrator.In addition, the range of control and accuracy for the duty-cycleand quadrature phase correction get worse as the supply voltagedecreases in the deep-sub micrometer process. A digital PD can beused to find duty-cycle and quadrature phase errors [4]. This simpledesign avoids the problems associated with analog circuits, but itcan have a nonlinear gain and a large static phase offset. Anotherdevelopment [9] provides a narrow phase detection window in thedigital PD, but the detection accuracy can be limited by the delay ofthe inverter in this PD. To solve this problem, a sense-amplifier-basedPD [10] has been introduced. However, the intrinsic phase offsetneeds to be further reduced as the operating frequency increases.A time-to-digital converter (TDC)-based detector [11], [12] has afiner resolution than previous digital designs, but the clock signalcan be distorted within the TDC, which can degrade the accuracy.
We address the above issues in the design of a quadrature clockcorrector that corrects duty-cycle and quadrature phase errors forDRAM interfaces. Our duty-cycle and quadrature PD uses relaxationoscillators with a modified input stage to convert the duty-cycle andquadrature phase of the clock signals into frequencies, which are thencompared in the digital frequency detector. It achieves good accuracyover a wide range of operating frequencies and can detect a widerange of duty-cycle and quadrature phase errors.
The rest of this brief is organized as follows. In Section II,we present our oscillator-based duty-cycle and quadrature PD. InSection III, the quadrature clock corrector using oscillator-baseddetectors is described. The experimental results of our corrector aregiven in Section IV. Section V provides the conclusion.
II. QUADRATURE CLOCK CORRECTOR
A. Architecture
Fig. 1 shows the block diagram of our quadrature clock cor-rector, which consists of two duty-cycle detectors, four duty-cycleadjusters (DCAs), a quadrature PD, four phase adjusters (PAs),four cross-coupled latches, and several clock buffers. The duty-cycleand quadrature PD has the relaxation oscillator structure. Thecross-coupled latch corrects the phase error of the differential signalsICKIN − IBCKIN and QCKIN − QBCKIN. Duty-cycle detectorsmeasure the error in the duty-cycle of these signals and sendduty-cycle control codes CodeDuty,I, CodeDuty,IB, CodeDuty,Q, and
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 2. (a) Block diagram and (b) timing diagram of a relaxation oscillator-based duty-cycle detector (ICK/IBCK).
CodeDuty,QB to DCAs, which restore the duty cycle of each signal to50%. The quadrature phase errors of ICKIN − QCKIN and IBCKIN− QBCKIN are measured by the quadrature PD, and the resultingcontrol codes CodeI and CodeQ are passed to PAs, which correct thephase of the quadrature clock signals.
B. Duty-Cycle and Quadrature Phase Detectors BasedOn a Relaxation Oscillator
Several types of low-frequency oscillator draw relatively littlepower. Among them is the relaxation oscillator, which operates bycharging and discharging a capacitor between two fixed voltages.It only requires a small number of active transistors and exhibitsgood noise performance [14], [15]. A modified relaxation oscillatorcan be used to convert clock errors to frequencies, and thus it findsapplication in duty-cycle and quadrature PDs. This approach canmeasure clock errors accurately in the frequency domain, and itseconomy in the area and power consumption is particularly valuablein DRAM interfaces, which have many parallel data paths.
Fig. 2(a) shows the block diagram of our duty-cycle detector,based on a relaxation oscillator. It consists of a current source,a small resistor and capacitor, a Schmitt trigger, a digital frequencydetector, and a binary counter. Our circuit differs from that of previousrelaxation oscillators [15], [16], in which a Schmitt trigger is used forcomparing voltages, and the input stage is changed so that the dutycycle of differential clock signals can adjust the frequency. To keepthe capacitor small while producing a low output frequency, eachcurrent source only produces a small current, which keeps the powerconsumption and area requirement low.
The operation timing diagram of our duty-cycle detector for ICKand IBCK is shown in Fig. 2(b). The ICK and IBCK signals have adifferential relationship, such that the pulsewidth at the high of theICK signal would be the same as that at the low of the IBCK signal.Thus, if the ICK signal corresponds to a duty cycle of (50 − a)%,then the IBCK signal corresponds to a duty cycle of (50+a)%. V1 isgenerated by integrating the current IREF in the capacitor duringthe periods when ICK is low and IBCK is high; V2 is generatedby integrating IREF in the capacitor during the periods when ICKis high and IBCK is low. Therefore, the frequencies of the clocksignals RCK1 and RCK2 generated by applying V1 and V2 to theSchmitt trigger reflect duty cycles of (50 − a)% and (50 + a)%.The digital frequency detector receives RCK1 and RCK2 signals fromthe relaxation oscillator and converts frequencies to digital values, andthen compares their relative magnitudes to determine which signal
Fig. 3. Conversion of a quadrature phase to a duty cycle using XOR andXNOR logics. (a) When ICK and QCK are in perfect quadrature. (b) Whenthe quadrature phase error occurs between ICK and QCK.
is higher in frequency. If the frequency of RCK1 is higher thanRCK2, the UP/DN signal outputs UP, and in the opposite case, DN isoutput. The binary counter receives this UP/DN signal and increasesor decreases control codes CodeDuty,I and CodeDuty,IB which arethen used to adjust the duty cycle. Once this process is completed,the digital frequency detector outputs the reset signal RSTROSC,the relaxation oscillator is initialized, and duty-cycle detection startsagain. This periodic operation corrects the duty-cycle error of theclock signals.
The period of the output clock TRCK generated by the relaxationoscillator in our duty-cycle detector can be expressed as follows:
where TICK and TIBCK are the periods of the ICK and IBCK signals,and NICK and NIBCK are the numbers of clock cycles of the ICK andIBCK signals in one period of TRCK, respectively. Using the relationbetween current and voltage that applies to a capacitor, we can obtain
where IREF is the current generated by the current source, andVTH(L→H) and VTH(H→L) are the low-to-high and high-to-lowthreshold voltages of the Schmitt trigger. Thus, TRCK1 and TRCK2can be expressed as follows:
TRCK1 = 2C · (VTH(L→H) − VTH(H→L))
IREF · (50 − a)%+ b (3)
and
TRCK2 = 2C · (VTH(L→H) − VTH(H→L))
IREF · (50 + a)%+ b (4)
where b is a nonlinear factor such as the loop latency and thefrequencies of the ICK and IBCK signals. It can be seen that TRCK1and TRCK2 of our relaxation oscillators are linearly affected by theduty cycle.
The quadrature phase between the quadrature clock signals ICKand QCK can be converted to a duty cycle using XOR and XNOR
logics. If these clock signals have the correct quadrature phase TCK/4,the clock signals AXOR and BXNOR have the duty cycle of 50%,as shown in Fig. 3(a). If the quadrature phase error TERR occurs,the clock signals AXOR and BXNOR having non-50% duty cycles(50−a% and 50+a%) are produced at the output of XOR and XNOR
logics, as shown in Fig. 3(b). Therefore, detecting and comparingduty-cycle errors of these signals provide the information needed tocorrect the quadrature phase error. Fig. 4 shows the block diagramof our quadrature PD based on the relaxation oscillator. The sixtransistors in the relaxation oscillator on the left perform the similarfunction as XOR logic, and the six on the right provide the similarfunction as XNOR logic. Since the combination of the pulsewidthsin AXOR,O/AXOR,E and BXNOR,O/BXNOR,E, which corresponds tothe duty cycle of AXOR and BXNOR shown in Fig. 3, generate
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 3
Fig. 4. Block diagram of a quadrature PD, based on a relaxation oscillator.
Fig. 5. Simulated output frequency of a relaxation oscillator in (a) duty-cycledetector and (b) quadrature PD.
RCK1 and RCK2 signals, these clock signals contain the quadraturephase error information. The subsequent operations are the same asthose of the duty-cycle detector described earlier, and control codesCodeI and CodeQ are generated and transmitted to PAs, correctingthe quadrature phase.
To assess the effectiveness with which (3) and (4) are realizedby our duty-cycle and quadrature PD, we performed a postlayoutsimulation. Fig. 5(a) and (b) shows the simulated output frequencyof the relaxation oscillator in our detector against duty cycle andquadrature phase in input frequencies of 1, 2, and 3 GHz. Their slopesof the frequency curve are 1.06 MHz/% and 0.86 MHz/°. Since thefrequency detector is designed to detect the frequency difference of atleast 0.4 MHz, our duty-cycle and quadrature PD can detect the duty-cycle difference of at least 0.38% and the quadrature phase differenceof at least 0.47°. It also shows that it works well over a wide rangeof input frequencies and can detect a wide range of duty cycle andquadrature phase.
A mismatch between the left and right relaxation oscillators inour detector can cause the deviation of the duty cycle and quadraturephase after the correction. To verify the effect of the mismatch, MonteCarlo simulation of the output frequency difference between RCK1and RCK2 in relaxation oscillators was performed. Since the dutycycle and the quadrature phase of the input clock signals are 50% and90° at 3 GHz, the frequency difference is zero if there is no mismatch,but a deviation, which means a residual error, can occur in a realimplementation due to the device mismatch. Figs. 6 and 7 show theresults of the transistor mismatch, the mismatch in the Schmitt trigger,and the mismatch in resistor and capacitor. Among these results,the frequency variation due to the mismatch of the Schmitt trigger ismost significant on both detectors, which indicates that the frequencyof the relaxation oscillator is sensitive to VTH(L→H) − VTH(H→L).These mismatches can be mitigated considering the following twoissues in the layout [17], [18]. First, to reduce the random mismatchbetween devices in our detector, all the devices were kept close,placed to the same direction, and additional dummy fill was included.Second, the symmetric placement of devices and the same lengthof wire were used to reduce the deterministic mismatch due to theasymmetry of the layout.
C. Duty Cycle and Phase Adjuster
Fig. 8(a) shows the block diagram of the DCA, which is based onan inverter with different pMOS and nMOS widths [19]. The control
Fig. 6. Monte Carlo simulation results (500 runs) of the frequency differencebetween RCK1 and RCK2, to show mismatch effect from different randomvariables in our duty-cycle detector when the duty cycle of input clock is 50%at 3 GHz.
Fig. 7. Monte Carlo simulation results (500 runs) of the frequency differencebetween RCK1 and RCK2, to show mismatch effect from different randomvariables in our quadrature PD when the quadrature phase of input clockis 90° at 3 GHz.
Fig. 8. Block diagram of (a) DCA and (b) PA.
code received by the duty-cycle detector selects the width of thepMOS and nMOS required to restore the duty cycle of the outputclock signal to 50%. The resolutions of the DCA at 1, 2, and 3 GHzare about 0.06%, 0.14%, and 0.21%, respectively. Fig. 8(b) showsthe block diagram of the PA, in which a MOSCAP array receivesthe control code from the quadrature PD and corrects the quadraturephase error. The resolutions of the PA at 1, 2, and 3 GHz are about0.40°, 0.81°, and 1.22°, respectively. Since the nonlinearity of theseadjusters due to PVT variation can affect the correction performanceand jitter, the symmetrical layout and close placement of devices wereperformed, and the linearity was checked through various simulations.
III. EXPERIMENTAL RESULTS
A prototype was fabricated in a 55-nm CMOS process with asupply voltage of 1.2 V. Fig. 9(a) shows the die micrograph with amagnified layout. The core area of the quadrature clock corrector is0.003 mm2. The measurement setup is shown in Fig. 9(b). A single-ended clock signal from a CK source is converted to differential clocksignals CKIN and CKBIN using a single-to-differential converter.An IQ generator (Gen) makes quadrature clock signals from CKINand CKBIN, and their duty cycle and quadrature phase are variedby control codes in DCAs (DCAIN) and PAs (PAIN) before thequadrature clock corrector. Their control ranges, which also meandistortion ranges, are measured through ICKCH,IN and QCKCH,IN.They are transmitted to our quadrature clock corrector. Duty-cycleand quadrature phase errors of the output clock signals are measuredby capturing ICKCH,OUT and QCKCH,OUT with an oscilloscope.
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 9. (a) Die micrograph with a magnified layout. (b) Measurement setup.
Fig. 10. Measured waveforms of uncorrected output clock signals andcorrected output clock signals at (a) 1 and (b) 3 GHz.
Measurements were carried out over input clock frequencies from1 to 3 GHz.
The measured waveforms at the frequency of 1 GHz are shownin Fig. 10(a). The duty cycle and the quadrature phase of uncorrectedoutput clock signals ICKCH,OUT and QCKCH,OUT are 47.7% and92.1°. When the quadrature clock correction is performed, the dutycycle and the quadrature phase of these clock signals are modifiedto 49.9% and 90.7°. At the frequency of 3 GHz, the measuredwaveforms are shown in Fig. 10(b). The duty cycle and the quadraturephase of uncorrected output clock signals are 42.7% and 85°. Afterquadrature clock correction, the duty-cycle and the quadrature phaseof these signals are modified to 50.6% and 90.4°.
The duty-cycle distorted clock signals, which are generated bymanually adjusting DCAIN shown in Fig. 9(b), are provided tothe quadrature clock corrector. The measurements presented inFig. 11(a) and (b) show the effect of duty-cycle correction bythe quadrature clock corrector. When the duty-cycle correction isperformed, the duty cycle of the corrected signal only varies between50.1% and 50.4% at 1 GHz and between 49.4% and 50.8% at 3 GHz.
In order to verify the effect of the quadrature phase correction,the quadrature phase of the input clock signals is manually distortedin PAIN shown in Fig. 9(b). Fig. 12(a) and (b) shows the measuredresults of quadrature phase correction. At frequencies of 1 and 3 GHz,the quadrature phase of the output clock signal is modified to a range
Fig. 11. Measured results of duty-cycle correction at (a) 1 and (b) 3 GHz.
Fig. 12. Measured results of quadrature phase correction at (a) 1 and(b) 3 GHz.
Fig. 13. RMS and peak-to-peak jitter of (a) uncorrected clock signalICKCH,IN and (b) corrected clock signal ICKCH,OUT at 3 GHz.
Fig. 14. Power breakdown of the quadrature clock corrector running at3 GHz. At this frequency, the total power consumption is 2.08 mW.
of 89.8°–90.7° and a range of 89.2°–91.1°, after quadrature phasecorrection. Therefore, the maximum error of quadrature phase is 1.1°at 3 GHz, which means 1.03 ps.
The measured rms and peak-to-peak (P–P) jitter of the uncor-rected clock signal ICKCH,IN are 1.85 and 15.75 ps, as shownin Fig. 13(a). The rms and peak-to-peak jitter of the correctedclock signal ICKCH,OUT increases to 2.14 and 19.75 ps, as shownin Fig. 13(b), due to supply/ground noise, local VT variation, anddithering phenomenon of the control codes.
The power breakdown of the quadrature clock corrector is shownin Fig. 14. The total power consumption of this clock corrector is2.08 mW at an input clock frequency of 3 GHz. Most of the poweris consumed by the clock buffer, and the power consumption ofrelaxation oscillators in the duty-cycle (ROSCDuty) and quadraturePDs (ROSCQuad) is only 5.1% and 1.3% of total power consumption,respectively.
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 5
TABLE I
PERFORMANCE SUMMARY AND COMPARISON WITH OTHER RECENT QUADRATURE CLOCK CORRECTORS
The performance of our quadrature clock corrector is summarizedand compared with other recent designs, as shown in Table I.
IV. CONCLUSION
We have presented a quadrature clock corrector for DRAM inter-faces. It uses relaxation oscillators with a modified input stage toconvert the duty cycle and quadrature phase of the clock signal topairs of frequencies while reducing area and power consumption.By comparing the frequencies in each pair, our detector obtainsan accurate value for the duty-cycle and quadrature phase errors,allowing for good correction performance. The circuit detects a widerange of the duty-cycle and quadrature phase errors and operates overfrequencies from 1 to 3 GHz. The corrected clock signal has a dutycycle between 49.4% and 50.8%, and a quadrature phase between89.2° and 91.1° at 3 GHz. The power efficiency of the quadratureclock corrector is 0.79 mW/GHz, and its area is 0.003 mm2.
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