A reference-free 7-bit 500 MS/s pipeline ADC using current-modereference shifting and quantizers with built-in thresholds

Michael Figueiredo • Edinei Santin •

Joao Goes • Guiomar Evans • Nuno Paulino

Received: 8 February 2012 / Revised: 11 December 2012 / Accepted: 12 January 2013 / Published online: 7 February 2013

� Springer Science+Business Media New York 2013

Abstract The pursuit for energy and area efficient cir-

cuits has become greater than ever. Low power and small

area integrated circuits are in high demand today. Refer-

ence voltage circuitry for analog-to-digital conversion

comprises 20–30 % of the overall power and area of the

ADC. To this end, a fully differential 1.5-bit multiplying

digital-to-analog converter (MDAC) precluding reference

voltages, that can be employed in MDAC-based ADCs, is

presented. Reference shifting is performed in current-mode

and the gain of two is obtained by associating charged

capacitors in series in the opamp’s feedback loop,

achieving a unity feedback factor. Theoretical analyses of

various nonideal effects of the reference shifting and gain

of two are presented and confirmed with electrical level

simulations. Furthermore, to avoid reference voltages in

the local quantizers, an architecture with built-in thresholds

is used. A proof of concept 1.5-bit/stage 7-bit 500 MS/s

pipeline ADC is designed using the proposed MDAC in a

standard digital 0.13 lm CMOS technology. The ADC

achieves a peak SNDR and SFDR of 36.1 and 48.7 dB,

respectively, while dissipating 12.7 mW from a single 1.2 V

supply voltage, and it does not require external reference

circuitry.

Keywords ADC � Capacitor mismatch � Current mode �Feedback factor � MDAC � Reference shifting � Switched-

capacitor

1 Introduction

The consumer has driven the design of integrated circuits

(IC) to be energy and area efficient. The future demands for

longer lasting, smaller area and cheaper devices, i.e., the IC

designer is confronted with the need to design low power,

small area and low fabrication cost circuits. Such circuits

are analog-to-digital converters (ADC), and in this specific

case, high speed medium-low resolution MDAC-based

ADCs1. These are widely used in high speed communica-

tions receivers [1–3], and optical and magnetic storage

devices [4]. The integration of such VLSI systems on a

single chip (SoC) or in a single package (SiP) is a complex

matter, and one often overlooked aspect of the ADC design

is the reference voltage (VREF) circuitry, which has direct

implications on the system’s power, cost, and integration.

VREF circuits generate, buffer, and decouple reference

voltages that need to settle to the linearity of the ADC to

avoid distortion and interstage gain errors (GE) [5].

Achieving this usually leads to power hungry and large

area VREF circuits, which become one of the most power

consuming blocks of ADCs. This problem becomes par-

ticularly exacerbated with increasing sampling frequencies,

as the effect of the wirebond’s inductance (in conjunction

M. Figueiredo (&) � E. Santin � J. Goes � N. Paulino

Department of Electrical Engineering, Faculty of Sciences

and Technology, Centre of Technology and Systems

(UNINOVA-CTS), Universidade Nova de Lisboa, 2829-516

Caparica, Portugal

e-mail: mf@uninova.pt

J. Goes � N. Paulino

S3-Group, Madan Parque, Rua dos Inventores,

2825-182 Caparica, Portugal

G. Evans

Departamento de Fısica, The Centro de Fısica da Materia

Condensada, Faculdade de Ciencias da, Universidade de Lisboa,

Edifıcio C8, 1749-016 Lisbon, Portugal

1 MDAC-based ADCs are composed of the multi-step flash, the

multi-stage algorithmic, and the pipeline architectures.

123

Analog Integr Circ Sig Process (2013) 75:53–65

DOI 10.1007/s10470-013-0030-1

with the pad/pin’s parasitic capacitance) severely degrades

performance. In the literature many solutions can be

found, but most of them either increase power, area, pin

count, or, as in most cases, all three. Furthermore, the

power and area of VREF circuits are often omitted and

unaccounted in the total power and area [6], i.e., this

problem is passed to the system level designer to solve.

Therefore, given today’s demands for low power and

small area circuits, voltage reference shifting, character-

ized by power hungry VREF buffers, large capacitors, and

ringing caused by wirebond inductance, will not fit our

future needs. Rethinking ADC referencing is crucial for

ADC integration. Research contributing towards this issue

has already been initiated [7].

To address the challenges presented, we propose, as a

proof-of-concept, a 7-bit 500 MS/s pipeline ADC that

precludes all reference voltages. This is achieved employ-

ing a closed-loop MDAC circuit with current-mode refer-

ence shifting and local quantizers with built-in thresholds.

Consequently, no reference voltages and, therefore, no

voltage buffers and decoupling capacitors are necessary.

Moreover, the MDAC is configured in a unity feedback

factor (b) scheme, thus effectively doubling its energy

efficiency (with respect to the conventional approach [8]).

Self-biasing techniques are employed in the opamp and

in the local quantizers, which besides eliminating biasing

circuitry, offers a higher insensitivity against process, supply

voltage, and temperature (PVT) variations. To demonstrate the

proposed ADC’s functionality and performance, it is realized

in a standard digital 0.13 lm CMOS process achieving low

power and small area.

The paper is organized as follows. Section 2 discusses

the most common forms of VREF schemes, examining their

advantages and drawbacks. The proposed MDAC is ana-

lysed in Sect. 3, illustrating its advantages and limitations.

A performance comparison with other MDAC circuits is

carried out. In Sect. 4 the building blocks of the imple-

mented ADC are described. Section 5 presents the mea-

sured results of a prototype 1.5-bit/stage pipeline ADC

incorporating the proposed MDAC circuit. Finally, Sect. 6

draws the main conclusions of this paper.

2 Reference voltage circuit schemes

Reference circuits are essential in analog and data con-

verter systems. They generate voltages and currents that are

used to bias circuits, signal comparison, addition and

subtraction operations, among others. In the specific case

of data converters, reference circuits are determinant in

defining the input and output full-scale ranges. Therefore, it

is necessary to guarantee a sufficient level of accuracy so

that the overall performance of the data converter is not

limited2. To achieve this, they need to be independent of

PVT variations and load disturbances. In the case where a

VREF needs to drive a large capacitor (or various capacitors

amounting to a large capacitance), or be used in a high speed

or high accuracy switched-capacitor circuit, an additional

block needs to be added to the reference circuit, a buffer. This

block is used to maintain the VREF stable and to guarantee

that its output settles to within a given error, within a given

time slot, depending on the ADC’s accuracy and speed.

It is possible to find many forms of VREF circuits and

buffering schemes in the literature. The options divide into

on- and off-chip buffering with (or without) the use of on-

and off-chip damping resistors and decoupling capacitors.

Table 1 describes and analyses the advantages and draw-

backs of the most common forms found. The conclusions

extracted from Table 1 can be summarized as follows: the

reference circuitry will occupy a large area, will dissipate a

large amount of power, and/or will need at least one extra

pin. Most of the currently employed solutions suffer from a

combination of these drawbacks, while our solution solves

these limitations by eliminating buffers, large on- and off-

chip decoupling capacitors, and no extra pins are neces-

sary. From a system-level perspective, both SoC and SiP

designs are benefitted, which is an important achievement.

3 Current-mode reference shifting 1.5-bit MDAC

with unity feedback factor

This section describes the proposed 1.5-bit MDAC circuit

and demonstrates, through various theoretical analyses, its

advantages and limitations. To conclude the section, a

comparison with other MDAC circuits is carried out.

3.1 Circuit description

The proposed 1.5-bit MDAC is shown in Fig. 1(a). The

circuit operates in two clock phases. During /1, the dif-

ferential input voltage (Vip - Vin) is sampled on capacitors

C1j, C2j, and C3j, j = {1, 2}. During /2, capacitors C1j and

C2j are associated in series around the opamp’s feedback

loop and the gain of two is obtained by voltage sum

(Fig. 1(b)), instead of charge redistribution, as occurs in the

conventional implementation [8]. This association of

capacitors has two benefits: unity feedback factor and

insensitivity to capacitor mismatch3. Reference shifting

occurs (during /2) when current sources, IP and IN, are

2 In [9] it is demonstrated that reference voltage circuits can have

1-bit lower accuracy than the resolution of the ADC.3 The capacitor mismatch-insensitivity advantage is validated theo-

retically here, but not emphasized in the prototype ADC because the

objective of this paper is to demonstrate how the proposed MDAC

solves system-level issues.

54 Analog Integr Circ Sig Process (2013) 75:53–65

123

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Analog Integr Circ Sig Process (2013) 75:53–65 55

123

turned on. These current sources sink/source current

through the series associated capacitors changing the out-

put voltage by an amount proportional to the respective

current, feedback capacitance and duration of /2. By the

end of /2 the output voltage should have changed by an

amount equal to ±VREF (differentially), for X and Z modes.

Regarding the output waveforms, in Y operation mode it is

exponential and for X and Z it has a ramped integrating

characteristic until the end of /2.

Following this approach for obtaining a capacitor mis-

match insensitive gain of two, the circuit becomes sensitive

to parasitic capacitors Cp2j and Cp3j, nodes between C2j and

C1j (see Fig. 1(b)). To attenuate this sensitivity, capacitors

C3j are employed. Notice, however, that these capacitors

are shorted during /2 because only the charge stored in

their parasitic capacitors (Cp6j) is used to compensate the

charge stored on Cp2j and Cp3j.

3.2 Reference shifting error analysis

The circuit diagram of Fig. 1(c) is used for the reference

shifting error analysis. Defining IP = IN = IREF/2, R1 =

R2 = 2Ron, Cj = C1jC2j/(C1j ? C2j), j = {1, 2}, calculat-

ing Vp and Vn, and substituting them into Vod =

-Av(Vp - Vn), we obtain4

VodðsÞ ¼1

2ð1þ s=Aop1ÞR1 þ R2 þ

1

sC1

þ 1

sC2

� �IREF :

ð1Þ

Considering a step function IREF(s) = IREF/s, Vod(t) is

obtained applying the inverse Laplace transform,

VodðtÞ ¼IREF

2

X2

i¼1

1

Cjt þ ðe�GBWt � 1Þ ð1� GBWRjCjÞ

GBW

� �;

ð2Þ

where GBW = A0p1, where A0 and p1 are the opamp’s

DC gain and bandwidth, respectively. Assuming GBW �1/(RjCj), and integration (reference shifting) time Tint =

1/2FS, we can simplify (2) to

VodðTiÞ ffiIREF

2Tint þ

e�GBWTint � 1

GBW

� �1

C1

þ 1

C2

� �: ð3Þ

From (3) we notice four sources of error: opamp’s

dynamic limitation (GBW), capacitor mismatch, integration

time variation, and reference current variation.

3.2.1 Opamp’s dynamic limitation

Assuming C11 = C21 = C12 = C22 = C (which makes C1

and C2 of (3) equal to C/2) and a fixed Tint and IREF, the

error is given by

eGBW ¼Vod � Vodideal

Vodideal

ffi �1

GBWTint; ð4Þ

where Vodideal= 2IREFTint/C. As an example, a 10-bit

application needs seven time constants for linear settling,

therefore, the closed-loop GBW = 7 9 2FS = 7/Tint [rad/

s]. Substituting in (4) leads to an absolute error of 14 %.

Although large, a small increase in IREF corrects this GBW

limitation, as demonstrated in Fig. 2. This graph combines

various values of GBW and IREF (including capacitor

mismatch) with the final result being (3) (considering

Vod = VREF). The conditions for the simulations of this

hypothetical case are: C = 1 pF, rðeijÞ ¼ 0:2 %, nominal

GBW = 3.2 GHz, Tint = 420 ps, which yields a nominal

IREF of 600 lA.

Figure 2 has two reference lines (dotted lines). The

horizontal reference line for IREF = 600 lA shows that it is

very difficult to obtain VREF = 0.5 V for practical values of

(a)

(b) (c)

Fig. 1 a Proposed 1.5-bit MDAC with current mode reference shifting.

b Single-ended circuit for GE analysis. c MDAC configuration with

active current-mode reference shifting (X = 1), for RE analysis

4 If IP and IN are not exactly matched, a current error (Ie) arises and

results in an additive term appearing at the end of (3). It only affects

the capacitor mismatch error (5), depending mainly on an Ie/IREF

term. For values of Ie/IREF up to 20 %, Ie may be neglected. Small Ie is

easily achieved using nonminimum transistor lengths.

56 Analog Integr Circ Sig Process (2013) 75:53–65

123

GBW. On the other hand, the vertical reference line, for

GBW = 3.2 GHz, shows that by increasing IREF from 600

to 684 lA, VREF = 0.5 V is achieved. This corresponds to

an increase of 14 % in the reference current. Therefore, as

mentioned above, a small increase in the reference current

compensates for limited GBW.

3.2.2 Capacitor mismatch

Assuming GBW !1 and a fixed Tint and IREF, the

resulting error is given by

eC ¼C

4

C11 þ C21

C11C21

þ C12 þ C22

C12C22

� �� 1: ð5Þ

If Cij ¼ Cð1þ eijÞ, where eij are assumed uncorrelated

Gaussian random variables with zero mean and standard

deviation rC, and assuming rC sufficiently small, such

that 1=ð1þ eijÞ � 1� eij, we obtain reC¼ rC=2 ¼ 0:1 %

(assuming rC = 0.2 %). Therefore, this error is easily

corrected by the digital correction logic (always present in

pipeline ADCs).

3.2.3 Integration time variation (jitter noise)

Assuming that GBW !1, that all capacitors are equal,

IREF is fixed, and an integration time given by Tintð1þ eTintÞ,

where eTint¼ Dtrms=Tint is the ratio between the integration

period and the rms value of the jitter noise of the clock, the

resulting error is

eT ¼Tintð1þ eTint

Þ � Tint

Tint¼ eTint

: ð6Þ

This means that this error is proportional to the jitter

noise of the system the MDAC is embedded in. Assuming

that the jitter noise is 1 psrms and that Tint is 420 ps, (6)

predicts that this error is 0.24 %.

3.2.4 Reference current variation

Assuming that GBW!1, that all capacitors are equal,

Tint is fixed, and IREF ¼ IREFð1þ eIREF), the resulting error is

eI ¼eIREF

4� 3

4: ð7Þ

For a regulated reference current with an error of 2 %

(as implemented in [19]), this error simplifies to the

constant term of 3/4, which is easily overcome by sizing

IREF for a larger value.

The largest reference shifting error is due to the GBW

limitation of the amplifier for which a simple solution has

been provided.

3.3 Feedback factor

The b of the proposed MDAC can be derived considering

Cp71 (i.e., the opamp’s input parasitic capacitance) as the

dominant parasitic capacitor, which results

b ¼ 1

1þ Cp71C11þC21

C11C21

: ð8Þ

If Cp71 � C11C21/(C11 ? C11), the feedback factor

approximates unity. Therefore, the resulting b is two times

greater than that of the conventional MDAC, which is clearly

a relevant advantage since the speed/power ratio doubles

and the opamp may be designed with a 6 dB lower A0.

The enhanced b also reduces the effective load, CLeff =

CL ? (1 - b)Cfb (Cfb is the equivalent series feedback

capacitance), therefore the total speed enhancement factor is

approximately 2.5 times over the conventional MDAC5. This

can be verified in Fig. 3, which represents the output voltage

of the proposed and conventional MDACs to an input step,

where the closed-loop time constant and 10-bit settling time

of the conventional MDAC are 2.5 times that of the proposed

MDAC6.

3.4 GE analysis

A brief part of the GE analysis has been carried out in [20].

However, here we extend those results by including other

nonidealities such as the opamp’s finite DC gain, the effect

of parasitic capacitor mismatch on the GE, and charge

injection.

The single-ended version of the MDAC (in Y mode)

shown in Fig. 1(b) is used for the GE analysis. The only

parasitic capacitors that contribute to GE are Cp2j and Cp3j.

All others either affect the opamp’s speed (Cp1j, Cp7j, and

Cp8j) but not its accuracy, or have the same voltage

Fig. 2 Iso-VREF lines versus GBW versus IREF. Error due to finite

GBW and compensation by increasing IREF

5 This is true assuming an equal CL for both the proposed and

conventional MDACs. However, in a pipeline ADC employing the

proposed MDAC in all stages, the b enhancement factor reduces to 2,

because of the extra sampling capacitor, C3j.6 The model of the opamp used in these simulations has A0 = 106

dB, GBW = 3.2 GHz, and a load capacitance, CL, of 2 pF is

considered.

Analog Integr Circ Sig Process (2013) 75:53–65 57

123

between both phases (Cp4j and Cp5j). Cp6j is used for

compensation. The proposed MDAC’s input-output equa-

tion is defined by charge conservation at vx and v-. Solving

the charge conservation equations, the differential output

voltage can be shown to be

Vod ¼ 2 1þ 1

4

X2

j¼1

þ Cp2j

C1j� Cp6j

C1j� Cp6j

C2j

� Cp2jCp6j

C1jC2j� Cp3jCp6j

C1jC2j

!" #Vid: ð9Þ

Equation 9 clearly shows that the MDAC is insensitive

to capacitor mismatch (no ratio terms between main

capacitors), but, on the other hand, is sensitive to para-

sitic capacitors Cp2j, Cp3j, and Cp6j. By analysing the signs

of the terms multiplying Vid, it is evident that an appro-

priate value for Cp6j can compensate the term Cp2j/C1j.

More specifically, making C1j = C2j = C and Cp2j =

Cp3j = Cp, the term multiplying Vid is exactly 2 if

Cp6j = 0.5CCp/(C ? Cp) = 0.5Cp/(1 ? Cp/C). If Cp �C, then Cp6j & 0.5Cp. This parasitic compensation can be

achieved by making C3j = 0.5C.

The GE can be evaluated statistically by defining Cij ¼Cð1þ eijÞ and C3j ¼ 0:5Cð1þ e3jÞ, with i; j ¼ f1; 2g;Cpij

¼ Cpð1þ epijÞ and Cp6j ¼ 0:5Cpð1þ ep6jÞ=ð1þ aÞ, with

i = {2, 3} and j = {1, 2}, where eij and epij are uncorre-

lated Gaussian random variables of the relative errors with

zero mean and standard deviation rC and rp, respectively,

and a = Cp/C. Monte Carlo (MC) simulations using Mat-

lab and Spectre are employed to evaluate the obtained

expression. The standard deviation plus the absolute mean

of the GE for different values of epij and a, shown in

Fig. 4(a), proves that the GE is independent of capacitor

mismatch, as expected. In Fig. 4(b, the GE is plotted

against the rðepijÞ for different values of a (rðeijÞ ¼ 0:2 %).

It can be seen that the GE degrades for increasing a and it

depends linearly on the rðepijÞ. In addition, the GE con-

tinues compatible with resolutions greater than 10 bits for

a = 3 % and rðepijÞ\7%.

Considering the effect of the opamp’s finite DC gain

(A0), a more complete expression for the GE, and conse-

quently Cp6j, is obtained. Cp6j, adequately sized, also

compensates for finite A0 and produces a highly accurate

gain of two. The equations are too complex to show here,

but the simulation results are summarized in Table 2 for

various values of A0 (and respective 3r variations of A0).

Capacitor and parasitic capacitor mismatches are also

considered. In average, the proposed MDAC achieves an

extra 2 bits in accuracy. Notice that, as the gain increases,

the GE of each MDAC approaches their theoretical limit

(for the imposed conditions).

A final expression for the output voltage of the proposed

fully differential 1.5-bit MDAC can be obtained by sum-

ming (9) with B times (3) (B represents the MDAC’s

operation mode). Charge injection and clock feed-through

were analysed and result in an offset term. The effect of the

former is minimized with signal independent sampling, and

the latter with dummy switches and a fully differential

design. Neither affect the GE nor the RE.

3.5 Noise analysis

Noise appears at the MDAC’s output as a consequence of

the thermal noise of the switches of both phases of oper-

ation, due to the opamp, and the jitter noise in the clock

signal, which is transformed into a noise voltage at the

output of the MDAC (6).

(a)

(b)

Fig. 4 GE versus a capacitor mismatch, b parasitic capacitor

mismatch. Each data point is the result of 1,000 MC cases

Table 2 GE (%) versus opamp’s A0 and 3r variations (dB)

A0 (3r[A0]) 40 (5) 50 (6) 60 (6) 70 (8) 80 (8)

GEProp. 0.59 0.23 0.076 0.04 0.026

GEConv. [8] 2.4 0.83 0.32 0.17 0.12

ðrðeijÞ ¼ 0:2 %; rðepijÞ ¼ 5 %, and a = 1 %)

Fig. 3 Step response comparison between conventional and proposed

MDACs, illustrating the b enhancement

58 Analog Integr Circ Sig Process (2013) 75:53–65

123

Figure 5 shows the equivalent single-ended circuit for

noise analysis of the proposed MDAC. For simplicity,

it is assumed that the switches are equally sized, C11 =

C21 = C, all noise sources are uncorrelated, and the opamp

is modeled by a single pole transfer function (TF), Av(s) =

A0/(1 ? s/p1). With this in mind, the differential mean

square (MS) thermal noise due to the switches and the

opamp can be shown to be,

v2o ¼ 2� kT

2

Cþ bA0p1 2Ron þ

Ropamp

b2

� �� �; ð10Þ

where k is Boltzmann’s constant, T is the absolute tem-

perature, Ron is the ON-resistance of the switches, and

Ropamp is the opamp’s equivalent input-referred noise

resistance. The first term of (10) is the sampled noise,

the second term is the noise from the ON-resistance of the

switches of /2 (vsw1,2) while the last term represents the

opamp’s noise contribution.

Regarding C3j, these do not contribute noise because

they are shorted in /2. For vsw2,2 the traditional method

of usingR1

0jHðjwÞj2Sðf Þdf can be used, where H(jw) =

Vo/Vsw2,2 and S(f) = 4kTRon. Regarding in1, its TF, vo/in1,

has a pole at zero (integrating characteristic) and so the

noise power spectral density is unbounded at the low fre-

quency limit. Therefore, an alternative method must be

used to determine in1’s noise contribution, which is thor-

oughly explained in [21] and used here.

Adding the noise contributions of vsw2,2, in1 and the jitter

noise (Dt2rms) to (10), we arrive at the total differential

output MS noise, for operation modes X and Z,

v2o ¼ 2� kT

2C þ bA0p1 2Ron þ Ropamp

b2

� �þ 2Ron

b2RSðCfbþCp71Þþ 2cgmTint

C2fb

24

35þ V2

REF

Dt2rms

T2int

;

ð11Þ

where c is the transistor’s excess noise factor, and gm and

RS are the current source’s transconductance and output

resistance, respectively. The noise contributions of vsw2,2

and in1 are given by the fourth and the fifth terms of (11),

respectively. These terms are null in Y operation mode.

3.6 Performance summary and comparison

A performance summary of the key characteristics of the

proposed MDAC is shown in Table 3. The table also

compares it with the conventional one, and other capacitor

mismatch insensitive MDACs found in the literature (from

the past decade). The table compares important MDAC

characteristics, such as, b, noise, GE, load, input capaci-

tance, number of phases of operation, and hardware

complexity.

There is only one other structure that achieves a unity b[22], but at the cost of using two opamps. In terms of GE

performance, it is difficult to evaluate and compare the data

because each circuit is simulated for different conditions

and some references do not present their conditions. Nev-

ertheless, of the presented data, [22, 23] achieve the best

gain accuracy, but the former uses two opamps and the

latter needs four phases.

Regarding effective load, circuits with b = 1 achieve

the best results. However, the results of this column must

be observed with some caution when considering a pipeline

(or similar) ADC architecture, where all stages use the

same circuit structure. In this situation, CL is substituted by

the respective values of the ‘Input Capacitance’ column.

Using as an example the conventional and proposed

MDACs, the effective load of the conventional MDAC (if

it is employed in all stages of a pipeline converter) is

2.5C which is the same for the proposed MDACs, given the

latter’s slightly higher input capacitance.

Concerning the number of necessary phases to execute

circuit operation, some rely on a 2-phase operation, while

others need 3-phases or even 4-phases. Regarding circuit

complexity, the conventional MDAC is the simplest circuit

to implement, while others employ a huge number of

switches [24–26] and capacitors [24, 26], some need two

opamps [22, 25–27], employs a four-input opamp.

4 ADC implementation

In this section, each building block of the implemented

ADC, except for the MDAC (previously discussed), will be

described.

4.1 Architecture

The architecture of the ADC is a two-channel time-inter-

leaved pipeline structure, composed of a front end sample-

and-hold (S/H), followed by five 1.5-bit stages, and a final

2-bit flash quantizer (FQ) stage. A two-phase non-over-

lapping clock generator is used to synthesize the main

phases, /1 and /2. The digital backend of the ADC

employs synchronization and digital correction logic, and

Fig. 5 Equivalent circuit, during /2, for thermal noise analysis

Analog Integr Circ Sig Process (2013) 75:53–65 59

123

output buffers. Given the high output data rate, a decimator

is used to facilitate data acquisition through external

measurement equipments. Two SRAMs (1,024 9 7 each)

were also integrated to record the output of the ADC, but

were only used as a backup in case the decimator failed.

The S/H is configured in a flip-around scheme with a

400 fF sampling capacitor, thus maximizing the feedback

factor. The employed opamp has a single stage topology

and is shared between channels, thus reducing power

consumption. The S/H stage uses traditional clock-boot-

strapping (CB) circuits for enhanced switching. Instead of

using one CB per critical switch, this stage employs a CB

scheme for driving all switches. This scheme buffers and

boosts the main nonoverlapping phases, and creates early

phases for signal-independent sampling. The scheme

allows all the switches of the stage to be small NMOS

transistors, therefore reducing parasitics while still guar-

anteeing sufficient linearity.

4.2 Pipeline stage overview

Figure 6 shows the block diagram of an interleaved pipe-

lined stage. Each stage comprises two MDACs, one

opamp, one RS bias circuit, and two sub-ADCs (1.5-bit

FQs). To save power, both opamp and RS bias circuits are

shared between channels.

The RS bias circuit is composed of cascode current

mirrors to generate IP and IN to source and sink current,

respectively. These currents are used to perform reference

shifting. The current either flows to MDACCH1, MDACCH2

or directly from IP to IN. The latter situation occurs when

no reference shifting is necessary, i.e., when Y is active, see

Fig. 1(a). The current sources never turn off, since their

start-up would restrict the switching frequency of the ADC.

Table 3 Key performance summary of the proposed MDAC and comparison with other capacitor mismatch insensitive MDAC circuits (from

the past decade)

Ref. b kT/Cnoise

GE 3r Relative gain

mismatch

Effective

load

Input

cap.

Number

of phases

Hardware

(SW,C,OA)

This work 1 4kT/C 0.026 %a3

arp

2CL 2.5C 2 (26, 6, 1)

Conv.[8] 1/2 4kT/C 0.1 %a 3 rC

2 CL þ 12

C 2C 2 (13, 4, 1)

[13] 1 4kT/C 0.004 % 3aðrCþrpÞ

2ffiffi2p CL 2C 2 (16, 4, 2)

[14] 1/2 7kT/C N/Ae N/A CL þ 23

C 2C 3 (–, 8, 2)

[15] 1/13 4kT/C N/A N/A CL þ 12

C C 3 (42, 12, 1)

[16] 1/3 N/A 0.014 %b3a

ffiffi2p

2rp

CL þ 23

C Cip 3 (36, 6, 1)

[17] 1/2 N/A 0.02 % N/A CL þ 12

C 2C 4 (54, 20, 2)

[18] 1/2 N/A 0.006 %c3ffiffiffi3p

r2C

CL þ 12

C C 4 (–, 4, 1)

Bold is used to highlight this work

SW number of switches, C number of unit capacitors, OA opamps, N/A not available

a rCðeijÞ ¼ 0:2 %; rpðepijÞ ¼ 5 %; a ¼ 1 %; A0 ¼ 1b rpðepijÞ ¼ 10 %c rCðeijÞ ¼ 0:5 %

Fig. 6 Two-channel interleaved pipeline stage with shared reference

shifting bias and opamp (shown in grey)

Fig. 7 Self-biased inverter-based 1.5-bit flash quantizer with built-in

thresholds

60 Analog Integr Circ Sig Process (2013) 75:53–65

123

A CB scheme, similar to that used in the S/H, is

employed in each pipelined stage, permitting that all

switches be implemented with small NMOS transistors.

4.3 Self-biased flash quantizer with built-in thresholds

The self-biased inverter-based 1.5-bit FQ with built-in

thresholds is shown in Fig. 7 [28]. The analog part of the

circuit consists of three inverters (INV1, INV2, and

INVbias), a current source (M5), and two NMOS resistors

(M4A,B). Differential sampling is performed on CSa,b, gen-

erating common-mode (CM) voltage, VCMF, which is used

to bias the FQ. The digital part of the FQ consists of two

D-type flip-flops, an XYZ encoder and some logic to

generate delay phases for proper FQ operation.

The FQ’s thresholds are built-in by proper sizing of the

inverters, thus precluding the need for any reference volt-

ages. The circuit is completely self-biased, thus inheriting

the main advantage of self-biasing: increased robustness to

PVT variations [28]. The decision time of the FQ is limited

to approximately 1/3 of the amplification phase (/2),

leaving 2/3 of the phase for the MDAC to perform the

required RS.

4.4 Inverter-based self-biased amplifier

The two-stage self-biased inverter-based opamp of Fig. 8 is

used in all pipelined stages (except in the S/H, where a

single stage version is used) [29]. To maximize b, a two-

stage opamp is used to reduce its input capacitance, while

maintaining a good gain/speed trade-off. Self-biasing is

employed for increased robustness against PVT variations.

The input devices of each stage are based on inverters,

which increase the opamp’s speed (GBW) because the total

input transconductance is given by the sum of the inverter’s

PMOS and NMOS transistors’ transconductances.

Self-biasing is accomplished using two CM feedback

(CMFB) circuits: CMFB1 and CMFB2 (Fig. 8(b, c)). The

former biases the input stage and controls its CM level,

while the latter biases the output stage and controls the

opamp’s output CM level.

5 Experimental results

Designed for testability and proof-of-concept, the proposed

1.5-bit MDAC is applied to a 7-bit 500 MS/s pipeline

(a)

(b) (c)

Fig. 8 a Two-stage self-biased inverter-based opamp. b CMFB1. cCMFB2

Fig. 9 Die photograph with overlaid layout. ADC core area is

840 9 160 lm2

(a) (b)

Fig. 10 Measurements at FS = 500 MS/s. a DNL and INL. b 4,096-

point FFT for fin = 48 MHz and Ain = -0.5 dBFS (decimated output)

Analog Integr Circ Sig Process (2013) 75:53–65 61

123

ADC. This prototype ADC is used to illustrate the

MDAC’s low current-enabled reference shifting capability

and speed enhancement. The ADC was designed in a

standard digital 0.13 lm CMOS technology without using

any special analog options or devices. For testability rea-

sons, the reference currents (for the RS bias current mir-

rors) were provided and controlled off-chip, but they could

be generated on-chip similarly as proposed in [19].

A die photograph (with overlaid layout) is shown in

Fig. 9 occupying a core area of 840 9 160 lm2 (0.13 mm2).

The measured static performance (DNL and INL) of the

ADC, operating at 500 MS/s, is shown in Fig. 10(a). The

DNL and INL are ?0.56/-0.6 and ?0.8/-0.65 LSB,

respectively. Figure 10(b) shows a 4,096-point FFT for

fin = 48 MHz and Ain = -0.5 dBFS (FS = 500 MS/s), with a

36.1 dB SNDR and a 48.7 dB SFDR. Note that the output of

the ADC was decimated by a factor of 15, therefore the FFT’s

frequency axis is limited to FS/(2 9 15) & 16.7 MHz, and

the signal’s tone appears at 48 - 2FS/(2 9 15) [MHz].

Figure 10(b) also shows the location and power of several

harmonics. At a conversion rate of 500 MS/s, the reference

shifting current is only 42 lA/stage and the ADC dissipates a

total power of 12.7 mW from a single 1.2 V supply.

Figure 11 depicts the dynamic performance (SNDR and

SFDR) of the ADC for various input frequencies (FS = 500

MS/s) and sampling frequencies (fin = 1 MHz). It is pos-

sible to observe that the ADC maintains a SFDR above 7

bits for input signals up to FS/2, and for sampling fre-

quencies up to 700 MS/s. Regarding ENOB, the ADC

maintains over 5 bits for sampling frequencies up to 700

MS/s.

Table 4 summarizes the proposed ADC’s performance

and compares it with other medium-low resolution (6–8

bit) MDAC-based ADCs with ENOB[5 bits and FS [200

MS/s. Besides showing ENOB, FS, power consumption,

and Figure-of-Merit (FoM =P/(2ENOBFS)), it also has a

FoMArea that contemplates the converter’s area, P 9 Area/

(2ENOBFS) for a better overall appreciation of the ADCs.

For a fair comparison, the area per channel of time-inter-

leaved ADCs is indicated. Most references of Table 4 do

not contemplate the power and area (specially decoupling

capacitors) of the reference circuitry (as indicated in the

last column). If this power and area were included, the

FoM and FoMArea would degrade. For example, if [30]

added the power of its reference circuit to the overall

ADC power, the FoM would degrade from 253 to 365 fJ/

conv.-step (44 % increase).

(a)

(b)

Fig. 11 Measured dynamic performance a versus fin, b versus FS

Table 4 Summary of the proposed ADC and overview of the state-of-the-art of 6–8 bit MDAC-based ADCs with ENOB[5 bits and FS [200

MS/s in CMOS technologies

Ref. Tech.

(lm)

N

(bits)

FS (MS/s) ENOB

(bits)

Power

(mW)

Area mm2FoM ½ fJ

conv:�step� FoMArea ½ fJ�mm2

conv:�step� Includes

references

[30] 0.09 8 320 7.3 12.8 0.26/ch. 253 134 No

[4] 0.065 8 800 7 30 0.06/ch. 283 34 N/A

[31] 0.18 8 200 6.4 8.5 0.05 503 25 No

[32] 0.18 8 200 7.7 30 0.15 731 110 No

[33] 0.18 8 200 7 22 0.32 830 266 No

[34] 0.13 6 1,000 5.3 49 0.08/ch. 1,240 198 No

[1] 0.09 7 550 5.7 60 0.19/ch. 2,045 757 N/A

[35] 0.09 8 250 6.2 22.8 0.81 2,580 2,090 N/A

This work 0.13 7 500 5.6 12.7 0.07/ch. 525 68 Yes

Bold is used to highlight this work

N/A not available

62 Analog Integr Circ Sig Process (2013) 75:53–65

123

6 Conclusions

A reference-free pipeline ADC has been presented. It is

based on a proposed MDAC architecture, whose main

advantages are low current enabled reference shifting and

enhanced feedback factor, which translate into higher power

and area efficiency. Current-mode reference shifting pre-

cludes power-hungry and large area reference voltage cir-

cuitry. Moreover, to completely eliminate the need for

reference voltages, the local quantizers have built-in

threshold levels. As proof-of-concept, the proposed MDAC

has been demonstrated in a prototype 7-bit 500 MS/s pipeline

ADC in a 0.13 lm CMOS technology, achieving low power

and small area. In a system perspective, this ADC has a small

area, does not need off-chip decoupling capacitors, and saves

at least two pins (that would have been used for reference

voltages, not accounting the reference circuit supply pins).

Acknowledgments This work was supported in part by the Portu-

guese Foundation for Science and Technology under projects

IMPACT (PTDC/EEA-ELC/101421/2008), OBiS FRET (PTDC/

CTM/099511/2008), and Ph.D. grants BD/41524/2007 and BD/

62568/2009.

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M. Figueiredo received the

M. Sc. and Ph. D. degrees in

electrical engineering from the

Universidade Nova de Lisboa,

Lisbon, Portugal, in 2007 and

2012, respectively. In May 2012

he joined Next Silicon, Lda

(Lisbon, Portugal), where he is

an analog design engineer. His

interests include analog and

mixed-signal integrated circuits,

data-converters and self-biasing

structures.

E. Santin was born in Marau,

RS, Brazil, in 1986. He received

the B.Sc. degree in electrical

engineering from the Federal

University of Santa Maria, Santa

Maria, Brazil, in 2008. He is

currently pursuing the Ph.D.

degree in electrical and computer

engineering at Faculty of Sci-

ences and Technology of the

New University of Lisbon (FCT/

UNL), Portugal. His research

interests include analog and

mixed-signal integrated circuits,

data-converters, and built-in

self-testing and self-calibration techniques applied to these circuits.

J. Goes was born in Vidigueira,

Portugal, in 1969. He graduated

from Instituto Superior Tecnico

(IST), Lisbon, in 1992. He

obtained the M.Sc. and the

Ph.D. degrees, respectively, in

1996 and 2000, from the Tech-

nical University of Lisbon. He

has been with the Department of

Electrical Engineering (DEE) of

the Faculty of Sciences and

Technology (FCT) of Nova

University of Lisbon (UNL),

since April 1998 where he is

currently an Associate Profes-

sor. Since 1998 he has been a Senior Researcher at the Center for

Technology and Systems (CTS) at UNINOVA. In 2003 he co-foun-

ded and served as the CTO of ACACIA Semiconductor, a Portuguese

engineering company specialized in high-performance data converter

and analog front-end products (acquired by Silicon and Software

Systems, S3, in Oct. 2007). Since Nov. 2007 he does his lectures with

part-time consultancy work for S3. From March 1997 until March

1998 he was Project Manager at Chipidea S.A. From December 1993

to February 1997 we worked as a Senior Researcher at Integrated

Circuits and Systems Group (GCSI) at IST doing research on data

converters and analog filters. Since 1992 he has participated and led

several National and European projects in science, technology, and

training. His scientific interests are in the areas of low-power and low-

voltage analog integrated circuits and data converters. Prof. Goes has

published over 100 papers in International Journals and leading

Conferences, and he is co-author of five books.

G. Evans was born in Barreiro,

Portugal, in 1966. She received

her degree in Physics Technol-

ogy from the Faculdade de

Ciencias da Universidade de

Lisboa in 1991, the M.Sc.

degree in Materials Engineering

from the Faculdade de Ciencias

e Tecnologia da Universidade

Nova de Lisboa in 1996 and, the

Ph.D. degree in Physics—Spe-

ciality of Electronics and

Instrumentation from the Fac-

uldade de Ciencias da Univer-

sidade de Lisboa in 2006. From

1990 to 1998 she worked as a Senior Engineer of the Signal Pro-

cessing and Optoelectronic Department at the Empresa de Investi-

gacao e Desenvolvimento de Electronica S. A. (E.I.D.), a Portuguese

engineering company specialized in telecommunications and military

electronic applications. From 1998 to 2006 she was Assistant Pro-

fessor and since 2006 she is Auxiliary Professor in the Physics

Department at the Faculdade de Ciencias da Universidade de Lisboa.

Since 2002 she has been working as a research collaborator of the

Centre for Technology and Systems (CTS) at UNINOVA and, since

2006 as a senior researcher at the Condensed Matter Physics Centre of

the Physics Department at the Faculdade de Ciencias da Universidade

de Lisboa. She is also a member of the Portuguese Physics Society

since 1998. Her interests include the design of low-power and low-

voltage analog integrated circuits, noise generators, built-in self-test

and built-in self-calibration of ADCs.

64 Analog Integr Circ Sig Process (2013) 75:53–65

123

N. Paulino was born in Beja,

Portugal, in 1969. He graduated

from Instituto Superior Tecnico

(IST), Lisbon, in 1992. He

obtained the M.Sc. degree, in

1996 from the Technical Uni-

versity of Lisbon and obtained

the Ph.D. degree in 2008 from the

Universidade Nova de Lisboa.

He has been with the Department

of Electrical Engineering (DEE)

of the Faculdade de Ciencias e

Tecnologia (FCT), Nova Uni-

versity of Lisbon (UNL), since

1999. Since 1999 he has been

also working as a Senior Researcher of the Micro-Electronics and

Signal-Processing group (MESP) at UNINOVA. In 2003 he co-founded

ACACIA Semiconductor, a Portuguese engineering company special-

ized in high-performance data converter and analog front-end products,

acquired by S3 in 2007. From 1996 to 1999 he worked as Analog Design

Engineer at Rockwell Semiconductor, USA. His scientific interests are

in the areas of the design of CMOS circuits for UWB imaging systems,

signal-processing, data-converters, self-testing and self-calibrating

techniques and optimization tools for assisting the design of analog

circuits. Dr. Paulino is a Member of the Portuguese Professional

Association of Engineers since 1992.

Analog Integr Circ Sig Process (2013) 75:53–65 65

123