A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam ... · BB for fLB, θ1 Easily scalable...

A Scalable 6A Scalable 6--toto--18GHz 18GHz

Concurrent DualConcurrent Dual--Band QuadBand Quad--Beam Beam

PhasedPhased--Array Receiver in CMOSArray Receiver in CMOS

California Institute of Technology

Sanggeun Jeon, Yu-Jiu Wang, Hua Wang, Florian

Bohn, Arun Natarajan, Aydin Babakhani, Ali Hajimiri

© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE

Outline

Introduction

Proposed Concurrent Phased-Array System

6-to-18GHz Phased-Array Receiver

Test Setups and Experimental Results

Conclusion


Wideband Large-Scale Phased Arrays

Military radars Space & satellite

communications

Weather radars


Incoming waved

θ

θλ

πϕ sin

2d=∆

Phased Arrays

Coherent addition of signals from each element.

Reject other signals with different incident angles.

2∆φ

∆φ

0


Advantages of Phased Arrays

High array gain

Interference rejection

Multi-beam scanning

Fast scanning

time

SNR

Improvement

by 10logN


Conventional Structure of Large-Scale Arrays

Interconnection of separate

modules.

Compound-semiconductor

MMICs.

High cost and complexity

RF Distribution Network

ADC

RF front-end modules

per beam


Outline

Introduction




Conclusion


Tunable Concurrent Multi-Beam Array

Required components reduced dramatically.

BB for fLB, θ1

Easily scalable

Reference signal

for PLL (50MHz)

BB for fHB, θ2

BB for fLB, θ3

BB for fHB, θ4

6-18GHz

CMOS receiver

Concurrent dual-band

quad-beam receiving

(I & Q output each)

Antenna module #1

fLB, θ1

fHB, θ2

fLB, θ3

fHB, θ4

HP receiver

VP receiver

HP receiver

VP receiver

HP receiver

VP receiver

HP

VP

HP

VP

HP

VP

Antenna module #2

Antenna module #N

HP: Horizontal polarization,

VP: Vertical polarization,

LB: Low band,

HB: High band


Features of Proposed Concurrent Array

Easily scalable to build large-scale arrays.

Dramatically reduce number of components required.

Low cost, low complexity, more reliability.

Wideband operation (6 – 18GHz)

Concurrent dual-band quad-beam scanning.

LB (6 – 10.4GHz) and HB (10.4 – 18GHz)

Two polarizations.

Phase noise improvement in large-scale arrays.


Phase Noise Improvement

Phase noise improved by 10log10N.

On-chip frequency synthesizers acceptable for the phase

noise requirement.

• Signals added up in current domain.

• Uncorrelated phase noise added up

in power.

Sout = N2

x Sin

PNout = N x PNin

PNin

Sin

PNin

Sin

PNin

Sin

Elem #1

Elem #2

Elem #N


Outline

Introduction




Conclusion


Receiver Architecture

Baseband

VGA

IF mixer +

Phase interpolator

170 bits

DataCLKLatch

Serial bus

digital control

I

Q

I

Q

2

2

2

M

U

X

PLL(LB)

VCO (LB, 5 - 7GHz)

TCA

I

Q

I

Q

2

2

2

M

U

X

PLL(HB)

VCO (HB, 9 - 12GHz)

TCA

Ref

(50MHz)

2.8V1.6V

Bandgapreference

φ

φ

φ

φ

φ

φ

φ

φ

HP dual

RF input

(LB +HB)

VP dual

RF input

(LB +HB)

RF (HP_LB)

RF (HP_HB)

RF mixer

(HP_LB)

IF buffer

(HP_LB)

HP: Horizontal polarization, VP: Vertical polarization, LB: Low band, HB: High band

RF mixer

(HP_HB)

IF buffer

(HP_HB)

LO1(LB)

LO1(HB)

LO2_Q (LB)

LO2_I (LB)

LO2_Q (HB)

LO2_I (HB)

RF (VP_LB)

RF (VP_HB)

RF mixer

(VP_HB)

IF buffer

(VP_HB)

RF mixer (VP_LB)

IF buffer(VP_LB)

BB out

(HP_LB, I)

BB out

(HP_LB, Q)

BB out

(HP_HB, I)

BB out

(HP_HB, Q)

BB out

(VP_HB, I)

BB out

(VP_HB, Q)

BB out

(VP_LB, I)

BB out

(VP_LB, Q)

Baseband

VGA

IF mixer +

Phase interpolator

170 bits

DataCLKLatch

Serial bus

digital control

I

Q

I

Q

2

2

2

M

U

X

PLL(LB)

VCO (LB, 5 - 7GHz)

TCA

I

Q

I

Q

2

2

2

M

U

X

PLL(HB)

VCO (HB, 9 - 12GHz)

TCA

Ref

(50MHz)

2.8V1.6V

Bandgapreference

φ

φ

φ

φ

φ

φ

φ

φ

HP dual

RF input

(LB +HB)

VP dual

RF input

(LB +HB)

RF (HP_LB)

RF (HP_HB)

RF mixer

(HP_LB)

IF buffer

(HP_LB)


RF mixer

(HP_HB)

IF buffer

(HP_HB)

LO1(LB)

LO1(HB)

LO2_Q (LB)

LO2_I (LB)

LO2_Q (HB)

LO2_I (HB)

RF (VP_LB)

RF (VP_HB)

RF mixer

(VP_HB)

IF buffer

(VP_HB)

RF mixer (VP_LB)

IF buffer(VP_LB)

BB out

(HP_LB, I)

BB out

(HP_LB, Q)

BB out

(HP_HB, I)

BB out

(HP_HB, Q)

BB out

(VP_HB, I)

BB out

(VP_HB, Q)

BB out

(VP_LB, I)

BB out

(VP_LB, Q)





Baseband

VGA

IF mixer +

Phase interpolator

170 bits

DataCLKLatch

Serial bus

digital control

I

Q

I

Q

2

2

2

M

U

X

PLL(LB)

VCO (LB, 5 - 7GHz)

TCA

I

Q

I

Q

2

2

2

M

U

X

PLL(HB)

VCO (HB, 9 - 12GHz)

TCA

Ref

(50MHz)

2.8V1.6V

Bandgapreference

φ

φ

φ

φ

φ

φ

φ

φ

HP dual

RF input

(LB +HB)

VP dual

RF input

(LB +HB)

RF (HP_LB)

RF (HP_HB)

RF mixer

(HP_LB)

IF buffer

(HP_LB)


RF mixer

(HP_HB)

IF buffer

(HP_HB)

LO1(LB)

LO1(HB)

LO2_Q (LB)

LO2_I (LB)

LO2_Q (HB)

LO2_I (HB)

RF (VP_LB)

RF (VP_HB)

RF mixer

(VP_HB)

IF buffer

(VP_HB)

RF mixer (VP_LB)

IF buffer(VP_LB)

BB out

(HP_LB, I)

BB out

(HP_LB, Q)

BB out

(HP_HB, I)

BB out

(HP_HB, Q)

BB out

(VP_HB, I)

BB out

(VP_HB, Q)

BB out

(VP_LB, I)

BB out

(VP_LB, Q)

Baseband

VGA

IF mixer +

Phase interpolator

170 bits

DataCLKLatch

Serial bus

digital control

I

Q

I

Q

2

2

2

M

U

X

PLL(LB)

VCO (LB, 5 - 7GHz)

TCA

I

Q

I

Q

2

2

2

M

U

X

PLL(HB)

VCO (HB, 9 - 12GHz)

TCA

Ref

(50MHz)

2.8V1.6V

Bandgapreference

φ

φ

φ

φ

φ

φ

φ

φ

HP dual

RF input

(LB +HB)

VP dual

RF input

(LB +HB)

RF (HP_LB)

RF (HP_HB)

RF mixer

(HP_LB)

IF buffer

(HP_LB)


RF mixer

(HP_HB)

IF buffer

(HP_HB)

LO1(LB)

LO1(HB)

LO2_Q (LB)

LO2_I (LB)

LO2_Q (HB)

LO2_I (HB)

RF (VP_LB)

RF (VP_HB)

RF mixer

(VP_HB)

IF buffer

(VP_HB)

RF mixer (VP_LB)

IF buffer(VP_LB)

BB out

(HP_LB, I)

BB out

(HP_LB, Q)

BB out

(HP_HB, I)

BB out

(HP_HB, Q)

BB out

(VP_HB, I)

BB out

(VP_HB, Q)

BB out

(VP_LB, I)

BB out

(VP_LB, Q)





Baseband

VGA

IF mixer +

Phase interpolator

170 bits

DataCLKLatch

Serial bus

digital control

I

Q

I

Q

2

2

2

M

U

X

PLL(LB)

VCO (LB, 5 - 7GHz)

TCA

I

Q

I

Q

2

2

2

M

U

X

PLL(HB)

VCO (HB, 9 - 12GHz)

TCA

Ref

(50MHz)

2.8V1.6V

Bandgapreference

φ

φ

φ

φ

φ

φ

φ

φ

HP dual

RF input

(LB +HB)

VP dual

RF input

(LB +HB)

RF (HP_LB)

RF (HP_HB)

RF mixer

(HP_LB)

IF buffer

(HP_LB)


RF mixer

(HP_HB)

IF buffer

(HP_HB)

LO1(LB)

LO1(HB)

LO2_Q (LB)

LO2_I (LB)

LO2_Q (HB)

LO2_I (HB)

RF (VP_LB)

RF (VP_HB)

RF mixer

(VP_HB)

IF buffer

(VP_HB)

RF mixer (VP_LB)

IF buffer(VP_LB)

BB out

(HP_LB, I)

BB out

(HP_LB, Q)

BB out

(HP_HB, I)

BB out

(HP_HB, Q)

BB out

(VP_HB, I)

BB out

(VP_HB, Q)

BB out

(VP_LB, I)

BB out

(VP_LB, Q)


Frequency Plan

LO2 switches between 1/2 and 1/8 of LO1, depending on

IF frequency.

Performed by on-chip multiplexers.

Relax the required VCO tuning range.


Tunable Concurrent Amplifier (TCA)

Single-input, dual-output.

Tunable LC loads for two separate tuned amplifiers.

180Ω

3kΩ

0.40nH

0.84nH

0.68pFRF

input

Vb1 Active

termination

Impedance

transformation

Vb2

0.68nH

Bit0

(LB)

112fF

Bit1

(LB)

224fF

Bit2

(LB)

516fF

LB

output

0.37nH

Bit0

(HB)

68fF

Bit1

(HB)

136fF

Bit2

(HB)

265fF

HB

outputVb2

Low-band

Transconductance

amplifier

High-band

Transconductance

amplifier

OFF

Cpar

ON

Ron


Mixers

Current commuting double-balanced

mixers.


Frequency Synthesizers

Architecture VCO

LB: 5 – 7GHz, HB: 9 – 12GHz.

Frequency generation step: 200MHz.

50 MHz

reference

VCO

PFD

DZE

2

÷N

(16-63)

PF

D

bypass

retime

enable

Div

Ratio

Div2/

Div8

select

1

DQ

I/Q

I/Q

I

02

2

2

Q

LO1

LO2


Digital Phase Rotators

Phase and amplitude synthesis

by summation of differently

weighted I and Q.

VGA by current-combining of

binary-weighted Gilbert cells.

cos( LO2t)

sin( LO2t)

AI

AQ

Gm0

Gm4

Bit0

Bit4

In+

In−

Out+

Out−


LO Distribution and Buffers

Differential

grounded CPW lines

(Zodd=50Ω)


Chip Photograph2.9

mm

5.2 mm


Outline

Introduction




Conclusion


Test Setup for Receiver Element

BB

(LB_I)BB

(LB_Q)

BB

(HB_I)BB

(HB_Q)

RF in RF in

Digital

DC inReceiver

Ref

D/A

RF

Freq. synthesizer

(HP83650B)

180°°°° Hybrid

Spectrum analyzer

(Agilent E4448A)

Bias tee

DC

DC supply

Laptop

(Digital programming +

Instrument control

using LabVIEW®)

Crystal oscillator

(50MHz)

On-wafer probing for RF input.

BB output taken differentially

and converted to single-ended.


LO Generation

Locking range:

4.8 – 7.8GHz

4.5

5

5.5

6

6.5

7

7.5

8

0 1 2 3

LO

fre

qu

en

cy (

GH

z)

Vcntrl (V)

Synthesizer Locking Range (Low band)

Bit 11

Bit 10

Bit 01

Bit 00

8.5

9

9.5

10

10.5

11

11.5

12

12.5

13

0 1 2 3L

O fre

qu

en

cy (

GH

z)

Vcntrl (V)

Synthesizer Locking Range (High band)

Bit 11

Bit 10

Bit 01

Bit 00

Locking range:

8.8 – 12.5GHz


RF Performance

Conversion gain = 16 ~ 24dB

Pin_1dB = -25 ~ -15dBm

IIP3 = -17 ~ -5dBm

Discontinuities due to frequency band or scheme changes.

RF frequency (GHz)

4 6 8 10 12 14 16 18 20-30

-20

-10

0

10

20

30

Conversion gainIIP3Pin_1dB


RF Input Matching

Input matching insensitive to different TCA settings.

-30

-25

-20

-15

-10

-5

0

5

4 6 8 10 12 14 16 18 20

S11

RF frequency (GHz)


Noise Figure

NF = 8 ~ 14dB across the entire band.

2.6 ~ 3.1dB, considering the preceding wideband GaN

LNA in the active antenna module (2.5dB NF, 20dB Gain).

0

2

4

6

8

10

12

14

16

4 6 8 10 12 14 16 18 20

No

ise

fig

ure

(d

B)

RF frequency (GHz)


Isolation Performance

Good isolations between two bands (more than 48dB)

and between two polarizations (more than 62dB).


Phase Interpolation Performance

-1.2

-0.8

-0.4

0

0.4

0.8

1.2

-1.2 -0.8 -0.4 0 0.4 0.8 1.2

Measured constellation

of interpolated baseband

signal @18GHz

Phase interpolation performance summary

RF

Freq.

Phase

Error

RMS

Phase

Error

Max.

Amp.

Variation

RMS

Amp.

Variation

Max.

6GHz 0.5° 2.6° 0.4dB 1.9dB

10.4GHz 0.2° 1.2° 0.2dB 1.5dB

14GHz 0.3° 1.4° 0.2dB 1.7dB

18GHz 0.2° 1.3° 0.5dB 2.3dB


Array Test Setup

RF

HP83650B

DAC

+ − + − + − + −

+ − + − + − + −

Tek 6604B

RF source

Variable phase shifter

4-way 0° power splitter

Agilent 3646A

DC

Agilent 3646A

DC

Crystal osc.(50MHz) 2-way

180°power splitter

4-way 0°power splitter

Bias tee

DC supply(2.8V, 1.6V)

Digital prog.by LabView

®

DC supply for BB buffer (1.5V)

Bias tee

2-way 180°power combiner

LPF

4-channel digital oscilloscope

DC

Digital_in Dig_out

RF_HP RF_VP

BB(LB_I)

BB(LB_Q)

BB(LB_I)

BB(LB_Q)

Ref DC

Digital_in Dig_out

RF_HP RF_VP

BB(LB_I)

BB(LB_Q)

BB(LB_I)

BB(LB_Q)

Ref DC

Digital_in Dig_out

RF_HP RF_VP

BB(LB_I)

BB(LB_Q)

BB(LB_I)

BB(LB_Q)

Ref DC

Digital_in Dig_out

RF_HP RF_VP

BB(LB_I)

BB(LB_Q)

BB(LB_I)

BB(LB_Q)

Ref


Array Patterns

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

Array patterns at 10.4GHz

Theory

Measured

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

Array patterns at 6GHz

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

0.2

0.4

0.6

0.8

1

30

60

90

120

150

180 0

Array patterns at 18GHz

Peak-to-null ratio > 21.5dB


Phase Error Calibration

One-time digital calibration of phase errors due to: Mismatch, skews in ref signal distribution, element-by-element

variation.

On-chip phase shifting with fine resolution is essential.

0

0.2

0.4

0.6

0.8

1

0 90 180 270 360

No

rma

lize

d p

att

ern

Incident phase difference (degrees)

Uncalibrated

Calibrated

Theoretical


Digital Modulation Performance

Modulation format: QAM32 @ 10.4GHz carrier.

EVM improved in array. I & Q mismatch improved after signal combining.

SNR improved after signal combining.

0

1

2

3

4

5

6

0 1 2 3 4 5

EV

M (%

rms

)

Symbol rate (Msps)

Measured EVM

Element 1

Element 2

Element 3

Element 4

4-element array


Interference Rejection

Desired signal: QPSK with 4Msps @ 10.4GHz, Pin = −35dBm, Incident angle fixed.

Interference signal: FM with 100kHz @ 10.4GHz, Pin = −45dBm, Incident angle swept.

Interference signal almost rejected at null positions.

0

5

10

15

20

25

30

0 90 180 270 360

EV

M (%

rms

)

Interference incident angle : phase shift (degree)

Single element

4-element array


Performance Summary

Receiver Element Performance

Phased-Array Performance (4 elements measured at 6-, 10.4-, and 18-GHz)

Conversion gain (6 – 18GHz) 15.7 ~ 24.7dB

Input-referred 1-dB compression (6 – 18GHz) −25.9 ~ −14.7dBm

Input-referred IP3 (6 – 18GHz) −17.0 ~ −5.2dBm

Input return loss (6 – 18GHz) > 9.5dB

Cross-polarization rejection (6 – 18GHz) > 63.4dB

Cross-band rejection (6 – 18GHz) > 48.8dB

LO leakage (6 – 18GHz) < −24.5dBm

Antenna-to-baseband noise figure† (6 –18GHz) 2.6 ~ 3.1dB

Phase shifting resolution (6 – 18GHz) < 5° (within 2dB amplitude variation)

RF channel spacing 225MHz (Div8 LO2), 300MHz (Div2 LO2)

Power consumption RF and LO circuitry 658mA @2.7V, 217mA @1.6V

Baseband buffers 328mA @1.5V

Technology 130nm CMOS

Die area 3.0×5.2 mm2

Number of beams concurrently receivable 4

Phase shifting resolution per element < 5°

Total phased-array gain > 27.7dB

Beam-forming peak-to-null ratio > 21.5dB


Conclusions

The first tritave dual-band quad-beam phased-array

receiver element in CMOS.

RF front-end integrated from RF, LO to baseband.

Easily scalable toward very large-scale phased

arrays with low cost and high reliability.


Acknowledgments

Funding from Office of Naval Research and

Raytheon Company.

J. DeFalco and R. Healy of Raytheon Company.

H. Mani, J. Bardin, and E. Keehr of Caltech.

Software assistance: Cadence, Agilent, Zeland,

Sonnet, Ansoft.


2/3/2008 1

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A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam ... · BB for fLB, θ1 Easily scalable...

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