A SPURIOUS POWER SUPPRESSION TECHNIQUE FOR

A LOW-POWER MULTIPLIERABSTRACT

Lowering down the power consumption reducing the area increasing the speed of operation

and enhancing the processing performance of the circuit designs are the important design challenges of

VLSI Design Multiplication process are frequently used for key computations in low-power wireless

multimedia and digital signal processor (DSP) applications such as fast Fourier transform (FFT)

discrete cosine transform (DCT) quantization and filtering To save significant power consumption of

a VLSI design it is a good direction to eliminate its dynamic power that is the major part of

total power dissipation

Design exploration and application of a technique to suppress the spurious switching

power existed in the data-paths of a low power VLSI designs have been proposed here The proposed

technique adopts the design concept of separating the arithmetic units into Most Significant Part

(MSP) and Least Significant Part (LSP) and then freezing the MSP whenever this part of circuits does

not affect the computation result This paper explores the realizing of a low power Modified Booth

Multiplier and the implementation approaches of a spurious power suppression technique (SPST)

design concept Then this SPST approach has been applied on both the compression tree of multipliers

and the modified Booth Encoder to enlarge the power clampdown for high-speed and low-power

purposes

For the low power application a powerful signed-number multiplier called Modified Booth

has been proposed To reduce the power consumption as well as to reduce the multiplication process

in to half a Bit-Pair Recoding scheme is used in the Modified Booth multiplier The partial products

are called PP candidates generated with the help of Multipliers in a modified Booth Encoder (MBE)

The output of MBE is fed to SPST-equipped adder to get the final result The SPST approach leads

to a 40 speed improvement when compared with the other power minimization technique In

addition this paper explores the performance of the proposed design under the conditions of

different bit-width input data The SPST approach not only owns equivalent low-power performance

but also leads to a higher maximum speed when compared with the former approaches Moreover

the proposed SPST-equipped multiplier also provides better power efficiency when compared with

the existing modern multipliers

3

I INTRODUCTION

The existing power reduction techniques are as follows

Partially Guarded Computation (PGC)

Dynamic-range Determination (DRD)

Glitching Power Minimization (GPM)

P artially Guarded Computation (PGC) has been proposed to reduce the dynamic

power consumption by minimizing the switched capacitance The technique first divides the input

data into two parts ndash MSP and LSP and disables a part of the functional unit that does not

affect the output This technique will reduce 3 delay overhead in functional unit and reduce 10 to

20 power consumption

I n Dynamic-range Determination (DRD) method before performing an addition

operation the effective dynamic ranges of two input data are determined Based on a larger

effective dynamic range only selected functional blocks of the adder are activated to generate

the desired result The input bits of the unused functional blocks remain in their previous states The

added result is then recovered to match the required word length This technique will reduce 30 of

the total power consumption

I n g l itching power minimization the power consumption is reduced by

replacing some existing gates with functionally equivalent one These equivalent gates can be frozen

the glitching power by asserting a control signal This technique can only achieve saving of 63 in

total power dissipation

Before going for the proposed technique we have to go through the Modified Booth

Multiplier section for to get better understand of the SPST concept

4

2 MODIFIED BOOTH MULTIPLIER

To speed-up the multiplication process in the Boothrsquos algorithm a technique called bitpair

recoding is used It is also called modified Boothrsquos algorithm It halves the maximum number of

summands In this technique the Booth-recoded multiplier bits are grouped in pairs Then each pair

is represented by its equivalent single bit multiplier reducing total number of multiplier bits to half

For example pair (+1 -1) is equivalent to the pair (0+1) That is instead of adding - 1 time

multiplication at shifted position i to +1 time the multiplicand at position +1 the same result is

obtained by adding +1 time multiplicand at position i Similarly (+10) is equivalent to (0+2) (-1 +1)

is equivalent to (0 -1) and so on By replacing pairs with their equivalents we can get bit- pair

recoded multiplier But instead of deriving bit- pair recoded multiplier from Booth recoded multiplier

one can directly derive it from original multiplier The bit- pair recoding or multiplier can be directly

derived from Table 1 shows the bit-pair code for all possible multiplier bit options

Table 1 Bit-pair recoding scheme

Eg By referring the above table 1 the bit-pair code for a multiplier 0000000001101010 can be

finding as follows

Multiplier

bit-pair (i+1)

Multiplier

bit-pair (i)

Multiplier

bit-pair(i-1)

Bit-pair recoded

multiplier bit at

position (i)

0 0 0 0

0 0 1 +1

0 1 0 +1

0 1 1 +2

1 0 0 -2

1 0 1 -1

1 1 0 -1

1 1 1 0

5

Fig 1 Bit Pair Recoding of ldquo006Ardquo

Consider a Modified Booth Multiplication with two numbers ldquo2AC9rdquo and ldquo006Ardquo The

above Fig 1 Shows the Bit Pair Recoding of multiplier ldquo006Ardquo The recoded output 0000+2-1-1-2

has been considered as new multiplier and this will reduce the multiplication process into half of its

original step this lead to the reduction of power consumption by half The modified booth multiplied

partial products are represented by PP0 PP1 PP2 PP3hellipetc as shown in the below Fig 2

Fig 2 Illustration of multiplication using Modified Booth Encoding

The PP candidates (partial products) generation using MUX in modified booth encoder is

shown in Fig 3 The PP candidates are added using a SPST- equipped adder to get the final result

When an application such as fast Fourier transforms (FFT) discrete cosine transform (DCT)

quantization and filtering are concern multiplication is 16 bit and the speed of operation is depends

up on the processor For DSP applications the input data is sophisticated at that time the

multiplication process is split down to MSP and LSP Then the operation has been carried out with

the help of some latch to switch down some unwanted signals and transients power to get perfect

output

6

Fig3 Modified Booth Encoder with MUX

3 PROPOSED TECHNIQUE SPURIOUS POWER SUPPRESSION TECHNIQUE (SPST)

This paper explores the implementation approaches of an Spurious Power Suppression

Technique (SPST) design concept and its application on a low-power (LP) Modified Booth

Multiplier (MBM) This SPST approach has been applied on both the compression tree of multipliers

and the modified Booth Encoder to enlarge the power clampdown for high-speed and low-power

purposes To illustrate the influence of the illogical power signal transitions five cases of a 16-bit

addition are explored as an example below (shown in Fig A) The 1st case illustrates a transient state

in which the illogical transitions of carry signals occur in the MSP though the final result of the MSP

are unchanged

Case (1)

7

The 2nd and 3rd cases describe the situations of one negative operand adding another

positive operand without and with carry from LSP respectively Moreover the 4th and 5th cases

respectively demonstrate the conditions of two negative operands addition without and with carry-in

from LSP In those cases the results of the MSP are predictable therefore the computations in the

MSP are useless and can be neglected Eliminating those illogical computations will not only save

the power consumed inside the SPST addersubtractor but also decrease the glitching noises which

will affect the next arithmetic circuits

The main contribution of SPST is to exploring two implementing approaches and

comparing their efficiency to get different material for the clampdown of power and to increase the

speed of operation

In fig4 Shows the simplified implementation approach for the addition 1048763 subtraction of

two bit numbers The adder subtractor is divided in to two parts ie most significant bit (MSP) and

Least significant bit (LSP) The MSP of the original addersubtractor is modified to include detection

logic circuit data controlling circuits (The data controlling circuits mainly consists of latch A and

latch B)sign extension circuit and some glue logics for carry in and carry out signal

8

Fig4 low-power adder 1048763 substractor example based on proposed SPST

4 IMPLEMENTATION OF ISPCT

The proposed low-power multiplier is designed by equipping the SPST on a tree

multiplier There are two distinguishing design considerations in designing the proposed multiplier

and SPST as listed in the following

41 APPLYING THE SPST ON THE MBE

In Fig 2 the shadow denotes that the numbers in this part of Booth multiplication are all

zero so that this part of the computations can be neglected Saving those computations can

significantly clampdown the power consumption caused by the transient signals According to the

analysis of the multiplication shown in Fig 5 we propose the ISPCT-equipped modified-Booth

encoder (MBE) which is controlled by a detection unit The detection unit has one of the two

operands as its input to decide whether the Booth encoder calculates redundant computations As

shown in Fig 5 the latches can respectively freeze the inputs of MUX-4 to MUX-7 or only those of

MUX-6 to MUX-7 when the PP4 to PP7 or the PP6 to PP7 are zero to reduce the transition power

dissipation Such cases occur frequently in eg FFTIFFT DCTIDCT and QIQ which are adopted

in encoding or decoding multimedia data

9

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

The output of MBE is fed to SPST-equipped adder to get the final result The SPST approach leads

to a 40 speed improvement when compared with the other power minimization technique In

addition this paper explores the performance of the proposed design under the conditions of

different bit-width input data The SPST approach not only owns equivalent low-power performance

but also leads to a higher maximum speed when compared with the former approaches Moreover

the proposed SPST-equipped multiplier also provides better power efficiency when compared with

the existing modern multipliers

3

I INTRODUCTION

The existing power reduction techniques are as follows

Partially Guarded Computation (PGC)

Dynamic-range Determination (DRD)

Glitching Power Minimization (GPM)

P artially Guarded Computation (PGC) has been proposed to reduce the dynamic

power consumption by minimizing the switched capacitance The technique first divides the input

data into two parts ndash MSP and LSP and disables a part of the functional unit that does not

affect the output This technique will reduce 3 delay overhead in functional unit and reduce 10 to

20 power consumption

I n Dynamic-range Determination (DRD) method before performing an addition

operation the effective dynamic ranges of two input data are determined Based on a larger

effective dynamic range only selected functional blocks of the adder are activated to generate

the desired result The input bits of the unused functional blocks remain in their previous states The

added result is then recovered to match the required word length This technique will reduce 30 of

the total power consumption

I n g l itching power minimization the power consumption is reduced by

replacing some existing gates with functionally equivalent one These equivalent gates can be frozen

the glitching power by asserting a control signal This technique can only achieve saving of 63 in

total power dissipation

Before going for the proposed technique we have to go through the Modified Booth

Multiplier section for to get better understand of the SPST concept

4

2 MODIFIED BOOTH MULTIPLIER

To speed-up the multiplication process in the Boothrsquos algorithm a technique called bitpair

recoding is used It is also called modified Boothrsquos algorithm It halves the maximum number of

summands In this technique the Booth-recoded multiplier bits are grouped in pairs Then each pair

is represented by its equivalent single bit multiplier reducing total number of multiplier bits to half

For example pair (+1 -1) is equivalent to the pair (0+1) That is instead of adding - 1 time

multiplication at shifted position i to +1 time the multiplicand at position +1 the same result is

obtained by adding +1 time multiplicand at position i Similarly (+10) is equivalent to (0+2) (-1 +1)

is equivalent to (0 -1) and so on By replacing pairs with their equivalents we can get bit- pair

recoded multiplier But instead of deriving bit- pair recoded multiplier from Booth recoded multiplier

one can directly derive it from original multiplier The bit- pair recoding or multiplier can be directly

derived from Table 1 shows the bit-pair code for all possible multiplier bit options

Table 1 Bit-pair recoding scheme

Eg By referring the above table 1 the bit-pair code for a multiplier 0000000001101010 can be

finding as follows

Multiplier

bit-pair (i+1)

Multiplier

bit-pair (i)

Multiplier

bit-pair(i-1)

Bit-pair recoded

multiplier bit at

position (i)

0 0 0 0

0 0 1 +1

0 1 0 +1

0 1 1 +2

1 0 0 -2

1 0 1 -1

1 1 0 -1

1 1 1 0

5

Fig 1 Bit Pair Recoding of ldquo006Ardquo

Consider a Modified Booth Multiplication with two numbers ldquo2AC9rdquo and ldquo006Ardquo The

above Fig 1 Shows the Bit Pair Recoding of multiplier ldquo006Ardquo The recoded output 0000+2-1-1-2

has been considered as new multiplier and this will reduce the multiplication process into half of its

original step this lead to the reduction of power consumption by half The modified booth multiplied

partial products are represented by PP0 PP1 PP2 PP3hellipetc as shown in the below Fig 2

Fig 2 Illustration of multiplication using Modified Booth Encoding

The PP candidates (partial products) generation using MUX in modified booth encoder is

shown in Fig 3 The PP candidates are added using a SPST- equipped adder to get the final result

When an application such as fast Fourier transforms (FFT) discrete cosine transform (DCT)

quantization and filtering are concern multiplication is 16 bit and the speed of operation is depends

up on the processor For DSP applications the input data is sophisticated at that time the

multiplication process is split down to MSP and LSP Then the operation has been carried out with

the help of some latch to switch down some unwanted signals and transients power to get perfect

output

6

Fig3 Modified Booth Encoder with MUX

3 PROPOSED TECHNIQUE SPURIOUS POWER SUPPRESSION TECHNIQUE (SPST)

This paper explores the implementation approaches of an Spurious Power Suppression

Technique (SPST) design concept and its application on a low-power (LP) Modified Booth

Multiplier (MBM) This SPST approach has been applied on both the compression tree of multipliers

and the modified Booth Encoder to enlarge the power clampdown for high-speed and low-power

purposes To illustrate the influence of the illogical power signal transitions five cases of a 16-bit

addition are explored as an example below (shown in Fig A) The 1st case illustrates a transient state

in which the illogical transitions of carry signals occur in the MSP though the final result of the MSP

are unchanged

Case (1)

7

The 2nd and 3rd cases describe the situations of one negative operand adding another

positive operand without and with carry from LSP respectively Moreover the 4th and 5th cases

respectively demonstrate the conditions of two negative operands addition without and with carry-in

from LSP In those cases the results of the MSP are predictable therefore the computations in the

MSP are useless and can be neglected Eliminating those illogical computations will not only save

the power consumed inside the SPST addersubtractor but also decrease the glitching noises which

will affect the next arithmetic circuits

The main contribution of SPST is to exploring two implementing approaches and

comparing their efficiency to get different material for the clampdown of power and to increase the

speed of operation

In fig4 Shows the simplified implementation approach for the addition 1048763 subtraction of

two bit numbers The adder subtractor is divided in to two parts ie most significant bit (MSP) and

Least significant bit (LSP) The MSP of the original addersubtractor is modified to include detection

logic circuit data controlling circuits (The data controlling circuits mainly consists of latch A and

latch B)sign extension circuit and some glue logics for carry in and carry out signal

8

Fig4 low-power adder 1048763 substractor example based on proposed SPST

4 IMPLEMENTATION OF ISPCT

The proposed low-power multiplier is designed by equipping the SPST on a tree

multiplier There are two distinguishing design considerations in designing the proposed multiplier

and SPST as listed in the following

41 APPLYING THE SPST ON THE MBE

In Fig 2 the shadow denotes that the numbers in this part of Booth multiplication are all

zero so that this part of the computations can be neglected Saving those computations can

significantly clampdown the power consumption caused by the transient signals According to the

analysis of the multiplication shown in Fig 5 we propose the ISPCT-equipped modified-Booth

encoder (MBE) which is controlled by a detection unit The detection unit has one of the two

operands as its input to decide whether the Booth encoder calculates redundant computations As

shown in Fig 5 the latches can respectively freeze the inputs of MUX-4 to MUX-7 or only those of

MUX-6 to MUX-7 when the PP4 to PP7 or the PP6 to PP7 are zero to reduce the transition power

dissipation Such cases occur frequently in eg FFTIFFT DCTIDCT and QIQ which are adopted

in encoding or decoding multimedia data

9

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

P artially Guarded Computation (PGC) has been proposed to reduce the dynamic

power consumption by minimizing the switched capacitance The technique first divides the input

data into two parts ndash MSP and LSP and disables a part of the functional unit that does not

affect the output This technique will reduce 3 delay overhead in functional unit and reduce 10 to

20 power consumption

I n Dynamic-range Determination (DRD) method before performing an addition

operation the effective dynamic ranges of two input data are determined Based on a larger

effective dynamic range only selected functional blocks of the adder are activated to generate

the desired result The input bits of the unused functional blocks remain in their previous states The

added result is then recovered to match the required word length This technique will reduce 30 of

the total power consumption

I n g l itching power minimization the power consumption is reduced by

replacing some existing gates with functionally equivalent one These equivalent gates can be frozen

the glitching power by asserting a control signal This technique can only achieve saving of 63 in

total power dissipation

Before going for the proposed technique we have to go through the Modified Booth

Multiplier section for to get better understand of the SPST concept

4

2 MODIFIED BOOTH MULTIPLIER

To speed-up the multiplication process in the Boothrsquos algorithm a technique called bitpair

recoding is used It is also called modified Boothrsquos algorithm It halves the maximum number of

summands In this technique the Booth-recoded multiplier bits are grouped in pairs Then each pair

is represented by its equivalent single bit multiplier reducing total number of multiplier bits to half

For example pair (+1 -1) is equivalent to the pair (0+1) That is instead of adding - 1 time

multiplication at shifted position i to +1 time the multiplicand at position +1 the same result is

obtained by adding +1 time multiplicand at position i Similarly (+10) is equivalent to (0+2) (-1 +1)

is equivalent to (0 -1) and so on By replacing pairs with their equivalents we can get bit- pair

recoded multiplier But instead of deriving bit- pair recoded multiplier from Booth recoded multiplier

one can directly derive it from original multiplier The bit- pair recoding or multiplier can be directly

derived from Table 1 shows the bit-pair code for all possible multiplier bit options

Table 1 Bit-pair recoding scheme

Eg By referring the above table 1 the bit-pair code for a multiplier 0000000001101010 can be

finding as follows

Multiplier

bit-pair (i+1)

Multiplier

bit-pair (i)

Multiplier

bit-pair(i-1)

Bit-pair recoded

multiplier bit at

position (i)

0 0 0 0

0 0 1 +1

0 1 0 +1

0 1 1 +2

1 0 0 -2

1 0 1 -1

1 1 0 -1

1 1 1 0

5

Fig 1 Bit Pair Recoding of ldquo006Ardquo

Consider a Modified Booth Multiplication with two numbers ldquo2AC9rdquo and ldquo006Ardquo The

above Fig 1 Shows the Bit Pair Recoding of multiplier ldquo006Ardquo The recoded output 0000+2-1-1-2

has been considered as new multiplier and this will reduce the multiplication process into half of its

original step this lead to the reduction of power consumption by half The modified booth multiplied

partial products are represented by PP0 PP1 PP2 PP3hellipetc as shown in the below Fig 2

Fig 2 Illustration of multiplication using Modified Booth Encoding

The PP candidates (partial products) generation using MUX in modified booth encoder is

shown in Fig 3 The PP candidates are added using a SPST- equipped adder to get the final result

When an application such as fast Fourier transforms (FFT) discrete cosine transform (DCT)

quantization and filtering are concern multiplication is 16 bit and the speed of operation is depends

up on the processor For DSP applications the input data is sophisticated at that time the

multiplication process is split down to MSP and LSP Then the operation has been carried out with

the help of some latch to switch down some unwanted signals and transients power to get perfect

output

6

Fig3 Modified Booth Encoder with MUX

3 PROPOSED TECHNIQUE SPURIOUS POWER SUPPRESSION TECHNIQUE (SPST)

This paper explores the implementation approaches of an Spurious Power Suppression

Technique (SPST) design concept and its application on a low-power (LP) Modified Booth

Multiplier (MBM) This SPST approach has been applied on both the compression tree of multipliers

and the modified Booth Encoder to enlarge the power clampdown for high-speed and low-power

purposes To illustrate the influence of the illogical power signal transitions five cases of a 16-bit

addition are explored as an example below (shown in Fig A) The 1st case illustrates a transient state

in which the illogical transitions of carry signals occur in the MSP though the final result of the MSP

are unchanged

Case (1)

7

The 2nd and 3rd cases describe the situations of one negative operand adding another

positive operand without and with carry from LSP respectively Moreover the 4th and 5th cases

respectively demonstrate the conditions of two negative operands addition without and with carry-in

from LSP In those cases the results of the MSP are predictable therefore the computations in the

MSP are useless and can be neglected Eliminating those illogical computations will not only save

the power consumed inside the SPST addersubtractor but also decrease the glitching noises which

will affect the next arithmetic circuits

The main contribution of SPST is to exploring two implementing approaches and

comparing their efficiency to get different material for the clampdown of power and to increase the

speed of operation

In fig4 Shows the simplified implementation approach for the addition 1048763 subtraction of

two bit numbers The adder subtractor is divided in to two parts ie most significant bit (MSP) and

Least significant bit (LSP) The MSP of the original addersubtractor is modified to include detection

logic circuit data controlling circuits (The data controlling circuits mainly consists of latch A and

latch B)sign extension circuit and some glue logics for carry in and carry out signal

8

Fig4 low-power adder 1048763 substractor example based on proposed SPST

4 IMPLEMENTATION OF ISPCT

The proposed low-power multiplier is designed by equipping the SPST on a tree

multiplier There are two distinguishing design considerations in designing the proposed multiplier

and SPST as listed in the following

41 APPLYING THE SPST ON THE MBE

In Fig 2 the shadow denotes that the numbers in this part of Booth multiplication are all

zero so that this part of the computations can be neglected Saving those computations can

significantly clampdown the power consumption caused by the transient signals According to the

analysis of the multiplication shown in Fig 5 we propose the ISPCT-equipped modified-Booth

encoder (MBE) which is controlled by a detection unit The detection unit has one of the two

operands as its input to decide whether the Booth encoder calculates redundant computations As

shown in Fig 5 the latches can respectively freeze the inputs of MUX-4 to MUX-7 or only those of

MUX-6 to MUX-7 when the PP4 to PP7 or the PP6 to PP7 are zero to reduce the transition power

dissipation Such cases occur frequently in eg FFTIFFT DCTIDCT and QIQ which are adopted

in encoding or decoding multimedia data

9

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

one can directly derive it from original multiplier The bit- pair recoding or multiplier can be directly

derived from Table 1 shows the bit-pair code for all possible multiplier bit options

Table 1 Bit-pair recoding scheme

Eg By referring the above table 1 the bit-pair code for a multiplier 0000000001101010 can be

finding as follows

Multiplier

bit-pair (i+1)

Multiplier

bit-pair (i)

Multiplier

bit-pair(i-1)

Bit-pair recoded

multiplier bit at

position (i)

0 0 0 0

0 0 1 +1

0 1 0 +1

0 1 1 +2

1 0 0 -2

1 0 1 -1

1 1 0 -1

1 1 1 0

5

Fig 1 Bit Pair Recoding of ldquo006Ardquo

Consider a Modified Booth Multiplication with two numbers ldquo2AC9rdquo and ldquo006Ardquo The

above Fig 1 Shows the Bit Pair Recoding of multiplier ldquo006Ardquo The recoded output 0000+2-1-1-2

has been considered as new multiplier and this will reduce the multiplication process into half of its

original step this lead to the reduction of power consumption by half The modified booth multiplied

partial products are represented by PP0 PP1 PP2 PP3hellipetc as shown in the below Fig 2

Fig 2 Illustration of multiplication using Modified Booth Encoding

The PP candidates (partial products) generation using MUX in modified booth encoder is

shown in Fig 3 The PP candidates are added using a SPST- equipped adder to get the final result

When an application such as fast Fourier transforms (FFT) discrete cosine transform (DCT)

quantization and filtering are concern multiplication is 16 bit and the speed of operation is depends

up on the processor For DSP applications the input data is sophisticated at that time the

multiplication process is split down to MSP and LSP Then the operation has been carried out with

the help of some latch to switch down some unwanted signals and transients power to get perfect

output

6

Fig3 Modified Booth Encoder with MUX

3 PROPOSED TECHNIQUE SPURIOUS POWER SUPPRESSION TECHNIQUE (SPST)

This paper explores the implementation approaches of an Spurious Power Suppression

Technique (SPST) design concept and its application on a low-power (LP) Modified Booth

Multiplier (MBM) This SPST approach has been applied on both the compression tree of multipliers

and the modified Booth Encoder to enlarge the power clampdown for high-speed and low-power

purposes To illustrate the influence of the illogical power signal transitions five cases of a 16-bit

addition are explored as an example below (shown in Fig A) The 1st case illustrates a transient state

in which the illogical transitions of carry signals occur in the MSP though the final result of the MSP

are unchanged

Case (1)

7

The 2nd and 3rd cases describe the situations of one negative operand adding another

positive operand without and with carry from LSP respectively Moreover the 4th and 5th cases

respectively demonstrate the conditions of two negative operands addition without and with carry-in

from LSP In those cases the results of the MSP are predictable therefore the computations in the

MSP are useless and can be neglected Eliminating those illogical computations will not only save

the power consumed inside the SPST addersubtractor but also decrease the glitching noises which

will affect the next arithmetic circuits

The main contribution of SPST is to exploring two implementing approaches and

comparing their efficiency to get different material for the clampdown of power and to increase the

speed of operation

In fig4 Shows the simplified implementation approach for the addition 1048763 subtraction of

two bit numbers The adder subtractor is divided in to two parts ie most significant bit (MSP) and

Least significant bit (LSP) The MSP of the original addersubtractor is modified to include detection

logic circuit data controlling circuits (The data controlling circuits mainly consists of latch A and

latch B)sign extension circuit and some glue logics for carry in and carry out signal

8

Fig4 low-power adder 1048763 substractor example based on proposed SPST

4 IMPLEMENTATION OF ISPCT

The proposed low-power multiplier is designed by equipping the SPST on a tree

multiplier There are two distinguishing design considerations in designing the proposed multiplier

and SPST as listed in the following

41 APPLYING THE SPST ON THE MBE

In Fig 2 the shadow denotes that the numbers in this part of Booth multiplication are all

zero so that this part of the computations can be neglected Saving those computations can

significantly clampdown the power consumption caused by the transient signals According to the

analysis of the multiplication shown in Fig 5 we propose the ISPCT-equipped modified-Booth

encoder (MBE) which is controlled by a detection unit The detection unit has one of the two

operands as its input to decide whether the Booth encoder calculates redundant computations As

shown in Fig 5 the latches can respectively freeze the inputs of MUX-4 to MUX-7 or only those of

MUX-6 to MUX-7 when the PP4 to PP7 or the PP6 to PP7 are zero to reduce the transition power

dissipation Such cases occur frequently in eg FFTIFFT DCTIDCT and QIQ which are adopted

in encoding or decoding multimedia data

9

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

partial products are represented by PP0 PP1 PP2 PP3hellipetc as shown in the below Fig 2

Fig 2 Illustration of multiplication using Modified Booth Encoding

The PP candidates (partial products) generation using MUX in modified booth encoder is

shown in Fig 3 The PP candidates are added using a SPST- equipped adder to get the final result

When an application such as fast Fourier transforms (FFT) discrete cosine transform (DCT)

quantization and filtering are concern multiplication is 16 bit and the speed of operation is depends

up on the processor For DSP applications the input data is sophisticated at that time the

multiplication process is split down to MSP and LSP Then the operation has been carried out with

the help of some latch to switch down some unwanted signals and transients power to get perfect

output

6

Fig3 Modified Booth Encoder with MUX

3 PROPOSED TECHNIQUE SPURIOUS POWER SUPPRESSION TECHNIQUE (SPST)

This paper explores the implementation approaches of an Spurious Power Suppression

Technique (SPST) design concept and its application on a low-power (LP) Modified Booth

Multiplier (MBM) This SPST approach has been applied on both the compression tree of multipliers

and the modified Booth Encoder to enlarge the power clampdown for high-speed and low-power

purposes To illustrate the influence of the illogical power signal transitions five cases of a 16-bit

addition are explored as an example below (shown in Fig A) The 1st case illustrates a transient state

in which the illogical transitions of carry signals occur in the MSP though the final result of the MSP

are unchanged

Case (1)

7

The 2nd and 3rd cases describe the situations of one negative operand adding another

positive operand without and with carry from LSP respectively Moreover the 4th and 5th cases

respectively demonstrate the conditions of two negative operands addition without and with carry-in

from LSP In those cases the results of the MSP are predictable therefore the computations in the

MSP are useless and can be neglected Eliminating those illogical computations will not only save

the power consumed inside the SPST addersubtractor but also decrease the glitching noises which

will affect the next arithmetic circuits

The main contribution of SPST is to exploring two implementing approaches and

comparing their efficiency to get different material for the clampdown of power and to increase the

speed of operation

In fig4 Shows the simplified implementation approach for the addition 1048763 subtraction of

two bit numbers The adder subtractor is divided in to two parts ie most significant bit (MSP) and

Least significant bit (LSP) The MSP of the original addersubtractor is modified to include detection

logic circuit data controlling circuits (The data controlling circuits mainly consists of latch A and

latch B)sign extension circuit and some glue logics for carry in and carry out signal

8

Fig4 low-power adder 1048763 substractor example based on proposed SPST

4 IMPLEMENTATION OF ISPCT

The proposed low-power multiplier is designed by equipping the SPST on a tree

multiplier There are two distinguishing design considerations in designing the proposed multiplier

and SPST as listed in the following

41 APPLYING THE SPST ON THE MBE

In Fig 2 the shadow denotes that the numbers in this part of Booth multiplication are all

zero so that this part of the computations can be neglected Saving those computations can

significantly clampdown the power consumption caused by the transient signals According to the

analysis of the multiplication shown in Fig 5 we propose the ISPCT-equipped modified-Booth

encoder (MBE) which is controlled by a detection unit The detection unit has one of the two

operands as its input to decide whether the Booth encoder calculates redundant computations As

shown in Fig 5 the latches can respectively freeze the inputs of MUX-4 to MUX-7 or only those of

MUX-6 to MUX-7 when the PP4 to PP7 or the PP6 to PP7 are zero to reduce the transition power

dissipation Such cases occur frequently in eg FFTIFFT DCTIDCT and QIQ which are adopted

in encoding or decoding multimedia data

9

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

the power consumed inside the SPST addersubtractor but also decrease the glitching noises which

will affect the next arithmetic circuits

The main contribution of SPST is to exploring two implementing approaches and

comparing their efficiency to get different material for the clampdown of power and to increase the

speed of operation

In fig4 Shows the simplified implementation approach for the addition 1048763 subtraction of

two bit numbers The adder subtractor is divided in to two parts ie most significant bit (MSP) and

Least significant bit (LSP) The MSP of the original addersubtractor is modified to include detection

logic circuit data controlling circuits (The data controlling circuits mainly consists of latch A and

latch B)sign extension circuit and some glue logics for carry in and carry out signal

8

Fig4 low-power adder 1048763 substractor example based on proposed SPST

4 IMPLEMENTATION OF ISPCT

The proposed low-power multiplier is designed by equipping the SPST on a tree

multiplier There are two distinguishing design considerations in designing the proposed multiplier

and SPST as listed in the following

41 APPLYING THE SPST ON THE MBE

In Fig 2 the shadow denotes that the numbers in this part of Booth multiplication are all

zero so that this part of the computations can be neglected Saving those computations can

significantly clampdown the power consumption caused by the transient signals According to the

analysis of the multiplication shown in Fig 5 we propose the ISPCT-equipped modified-Booth

encoder (MBE) which is controlled by a detection unit The detection unit has one of the two

operands as its input to decide whether the Booth encoder calculates redundant computations As

shown in Fig 5 the latches can respectively freeze the inputs of MUX-4 to MUX-7 or only those of

MUX-6 to MUX-7 when the PP4 to PP7 or the PP6 to PP7 are zero to reduce the transition power

dissipation Such cases occur frequently in eg FFTIFFT DCTIDCT and QIQ which are adopted

in encoding or decoding multimedia data

9

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

42 APPLYING THE ISPCT ON THE COMPRESSION TREE

The proposed SPST-equipped multiplier is illustrated in Fig6 The PP generator

generates five candidates of the partial products ie f2A A 0 A 2Ag which are then selected

according to the Booth encoding results of the operand B Moreover when the operand besides the

Booth encoded one has a small absolute value there are opportunities to reduce the illogical power

dissipated in the compression tree

According to the redundancy analysis of the additions we replace some of the adders in

compression tree of the multiplier with the SPST - equipped adders which are marked with oblique

lines in Fig 5 The bit-widths of the MSP and LSP of each SPST -equipped adder are also indicated

in fraction values nearing the corresponding adder in Fig5

Fig5 SPST-equipped MBE

10

Fig6 Proposed Low-Power SPST-Equipped Multiplier Where The Fraction Values Denote The

Bit-Width of The MSP And LSP of The SPST-Equipped Adders

In this circuit Carry section it is used to determine the carry of the output data The carry section

made by simple AND and OR gates Sign extension is the operation in computer arithmetic to

preserving the numbers sign (positivenegative) The sign digit is placed in the most significant side

of the number Sign- Extension circuits can be intuitively implemented by multiplexers to

compensate the sign signals of the MSP

11

CONCLUSION

In this paper The proposed multiplier adopting the new SPST implementing approach leads

to a 40 speed improvement when compared with the former technique

This paper explores the performance of the proposed design under the conditions of different bitwidth

input data The SPST approach not only owns equivalent low-power performance but also leads to a

higher maximum speed when compared with the former techniques Moreover the proposed SPST -

equipped multiplier also has better power efficiency when compared with the existing modern multipliers

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003

REFERENCES

1 Kuan-Hung Chen and Yuan-Sun chu rdquoA Low Power Multiplier With The Spurious Power

Suppression Techniquerdquo 1063-8210 2007 IEEE

2 AP Godse DA Godse ldquoComputer Architecturerdquo First Edition Technical Publications

2003