A STABLE AND HIGH-SPEED CMOS IMAGE CENTROID COMPUTATION
CIRCUIT
BY
KARTHIK REDDY KOTHAPALLI, B.E.
A thesis submitted to the Graduate School
in partial fulfillment of the requirements
for the degree
Master of Science in Electrical Engineering
New Mexico State University
Las Cruces, New Mexico
March 2007
“A Stable And High-Speed Cmos Image Centroid Computation Circuit,” a thesis
prepared by Karthik Reddy Kothapalli in partial fulfillment of the requirements
for the degree, Master of Science in Electrical Engineering, has been approved and
accepted by the following:
Linda LaceyDean of the Graduate School
Paul M. FurthChair of the Examining Committee
Date
Committee in charge:
Dr. Paul M. Furth, Chair
Dr. Robert Armstrong
Dr. David Voelz
ii
DEDICATION
Dedicated to GOD, my beloved parents, brother and friends .
iii
ACKNOWLEDGMENTS
I would like to thank and pay my regards to my advisor Dr.Paul Furth
for his inspiration and continuous guidance through out my master’s degree. Any
amount of gratitude to my advisor would not compare to his guidance and encour-
agement in my research, without which this work would not have been possible.
I really appreciate him for his understanding and caring nature. I am greatly
thankful to him for his strong support when I was facing deep troubles. I thank
him for providing me with a teaching assistantship and for allowing me to be a
part of his research team.
I would also like to thank Dr.David Voelz for all his support and guidance.
I would also like to thank him for allowing me to use his optical equipment. His
valuable suggestions especially during the optical test setup is greatly appreciated.
I am thankful to Dr.Robert Armstrong for being a part of my defense committee.
I would like to specially thank Bryan, Preetham for all their technical
support. I would like to express my gratitude to my family for their love and en-
couragement. I am grateful to all my roommates and friends for all their emotional
support especially in hard times.
Above all, I thank God for enabling me to achieve all that I have achieved.
iv
VITA
July 29, 1982 Born in Hyderabad, India.
August 2000 - April 2004 B. E. in Electronics and Communication,Osmania UniversityHyderabad, India
Spring 2005 - Fall 2006 Graduate teaching assistant, Klipsch Schoolof Electrical Engineering, NMSU, Las Cruces, NM.
Field of Study
Major Field: Electrical Engineering VLSI Design
v
ABSTRACT
A STABLE AND HIGH-SPEED CMOS IMAGE CENTROID COMPUTATION
CIRCUIT
BY
KARTHIK REDDY KOTHAPALLI, B.E.
Master of Science in Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2007
Dr. Paul M. Furth, Chair
The centroid is the location of the “center of mass” of an intensity pat-
tern of an image. Centroid computation circuits find place in a wide range of
applications in adaptive optics, such as motion tracking, position encoding and
wavefront sensing. Off-chip centroid computation can be slow compared to that
of an on-chip computation due to the time taken to read out a frame of data
and then process the data. The main focus of this thesis is on improving band-
width and precision of an on-chip centroid computation system, while minimizing
the effects of offsets. This centroid circuit is designed for CMOS technology and
implemented in AMI 0.5µm process using MOSIS fabrication service.
vi
Deweerth introduced a circuit to compute the centroid of an image [1] using
simple differential pairs. Another scheme, a modification of Deweerth’s model [1],
was proposed by Bashyam [2]. Bashyam’s design faced significant stability prob-
lems. The design presented in this thesis is aimed at achieving at least 10 times
higher bandwidth over a very wide range (20pA to 2µA) of photocurrents. The
precision of the computation requires linearized differential pairs. This thesis is
also aimed at achieving good accuracy by using linearized differential pairs.
Optical testing is done to test the performance of the chip. A laser beam
is used in static testing. Dynamic testing is done using two light emitting diodes
producing sinusoidal light signals that are out of phase with each other. The effect
is that of a spatially moving bright spot. Test results of the proposed architectures
are compared with simulations.
vii
TABLE OF CONTENTS
LIST OF TABLES xii
LIST OF FIGURES xiv
1 INTRODUCTION 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Purpose of the Present Work . . . . . . . . . . . . . . . . . . . . . 2
1.3 Summary of Accomplishments . . . . . . . . . . . . . . . . . . . . 2
1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 SOLID-STATE IMAGE SENSORS AND FUNDAMENTALS OFCENTROID COMPUTATIONS 4
2.1 Evolution of solid-state image sensors . . . . . . . . . . . . . . . . 5
2.2 CCD and CMOS Image Sensors: A comparison . . . . . . . . . . 7
2.3 Centroid Computation . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Centroid . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Aggregation Network . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Resistive position encoding scheme . . . . . . . . . . . . . 14
2.3.4 Centroid detection . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Photo-detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.1 Current in a Photodiode . . . . . . . . . . . . . . . . . . . 19
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2.4.2 A Photodiode Model . . . . . . . . . . . . . . . . . . . . . 21
2.5 Subthreshold operation of an n-channel MOSFET . . . . . . . . . 23
2.6 Flash Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . 25
2.7 Clocked comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 CENTROID COMPUTATION CIRCUIT: ARCHITECTURE, DE-SIGN AND SIMULATIONS 30
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Pixel array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Analog centroid computation circuit . . . . . . . . . . . . . . . . . 35
3.4.1 Aggregation network: Previous work . . . . . . . . . . . . 36
3.4.2 Aggregation network: Present proposed designs . . . . . . 43
3.4.3 Linearized Differential Pair . . . . . . . . . . . . . . . . . . 61
3.4.4 Current Subtractor . . . . . . . . . . . . . . . . . . . . . . 69
3.4.5 AC analysis over different current ranges . . . . . . . . . . 70
3.4.6 Comparison with a simple current mirror . . . . . . . . . . 72
3.5 Series Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6 Flash Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . 76
3.6.1 Clocked Comparators . . . . . . . . . . . . . . . . . . . . . 76
3.6.2 Thermometer-to-Binary code Converter . . . . . . . . . . . 84
3.6.3 Simulation of the flash converter . . . . . . . . . . . . . . . 88
3.7 Simulation of the Centroid Computation Circuit along with theflash converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4 TEST SETUP AND MEASUREMENT RESULTS 93
4.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ix
4.1.1 Regulated Power Supply Circuit . . . . . . . . . . . . . . . 94
4.1.2 Virtual Ground Generation Circuit . . . . . . . . . . . . . 96
4.1.3 Reference Voltage Generation Circuit . . . . . . . . . . . . 96
4.2 Optical Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.3 Individual Component Testing . . . . . . . . . . . . . . . . . . . . 98
4.3.1 Test Pixel . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.3.2 NMOS Low Voltage Cascode Current Mirror . . . . . . . . 101
4.3.3 Linearizing OTA . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.4 PMOS Current Mirror . . . . . . . . . . . . . . . . . . . . 104
4.4 Analog Centroid Computation Circuit Testing . . . . . . . . . . . 105
4.4.1 Static Testing . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.2 Dynamic Testing . . . . . . . . . . . . . . . . . . . . . . . 110
5 SUMMARY, CONCLUSIONS AND SUGGESTIONS 116
5.1 Summary and Conclusion . . . . . . . . . . . . . . . . . . . . . . 116
5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
APPENDICES 121
A. PICTURES OF THE CIRCUIT, TEST SETUP AND MICRO-GRAPHS 122
A PICTURES OF THE CIRCUIT, TEST SETUP AND MICRO-GRAPHS 123
B. PIN CONFIGURATION AND TEST PROCEDURE 126
B PIN CONFIGURATION AND TEST PROCEDURE 127
B.1 Suggested Test Procedure . . . . . . . . . . . . . . . . . . . . . . 127
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B.1.1 Voltage generation . . . . . . . . . . . . . . . . . . . . . . 127
B.1.2 Current Measurement . . . . . . . . . . . . . . . . . . . . 127
C. INFORMATION OF THE CHIP AND MOSIS FILE 139
C INFORMATION OF THE CHIP AND MOSIS FILE 140
REFERENCES 142
xi
LIST OF TABLES
3.1 Open-loop analysis of all three proposed circuits at 20pA and 2µAof photocurrents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2 Closed-loop analysis at node Vo of all three proposed circuits at20pA and 2µA of photocurrents . . . . . . . . . . . . . . . . . . . 71
3.3 Closed-loop analysis at node Vbi of all three proposed circuits at20pA and 2µA of photocurrents . . . . . . . . . . . . . . . . . . . 71
3.4 Closed-loop analysis at node Vox of all three proposed circuits at20pA and 2µA of photocurrents . . . . . . . . . . . . . . . . . . . 72
3.5 Closed-loop analysis at node Vox of all three proposed circuits alongwith the simple current mirror at 20pA and 2µA of photocurrents 72
3.6 Table of Thermometer code with its equivalent in Priority and Bi-nary codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7 Table of Thermometer code with its equivalent in Priority and Bi-nary codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.1 Table of offsets for Linearizing OTA . . . . . . . . . . . . . . . . . 103
4.2 Table of Bandwidths PMOS mirror without feedback and with feed-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3 Bandwidth measurements and simulations for row (x-direction) atdifferent photo currents of the analog centroid computation circuit. 112
4.4 Bandwidth measurements and simulations for column (y-direction)at different photo currents of the analog centroid computation circuit.112
B.1 Pin configuration of the Analog Centroid Circuit with some indi-vidual test circuits(Pins 1-21). . . . . . . . . . . . . . . . . . . . . 128
xii
B.2 Pin configuration of the Analog Centroid Circuit with some indi-vidual test circuits(Pins 22-40). . . . . . . . . . . . . . . . . . . . 129
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LIST OF FIGURES
2.1 Solid-state image sensors characteristics over a wide spectral range [4]. 4
2.2 History of MOS, CMOS and CCD image sensors [6]. . . . . . . . . 6
2.3 Aggregation Network of N+1 differential pairs [1]. . . . . . . . . . 13
2.4 Aggregation Network of N+1 differential pairs with position en-coding [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Centroid detection Circuit [1]. . . . . . . . . . . . . . . . . . . . . 16
2.6 Four types of photodiodes available in CMOS process [24]. . . . . 19
2.7 Photocurrent generation in a p-n diode [27]. . . . . . . . . . . . . 20
2.8 Photodiode model. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9 Cross-section of a photodiode [2]. . . . . . . . . . . . . . . . . . . 23
2.10 A 3-bit flash analog to digital converter [31]. . . . . . . . . . . . . 26
2.11 A CMOS clocked comparator. . . . . . . . . . . . . . . . . . . . . 28
2.12 A CMOS clocked comparator timing diagram. . . . . . . . . . . . 28
3.1 Architecture of centroid computation system. . . . . . . . . . . . 31
3.2 Layout of a 2x2 pixel array. . . . . . . . . . . . . . . . . . . . . . 33
3.3 Floorplan of a 4x4 pixel array. . . . . . . . . . . . . . . . . . . . . 33
3.4 N photodiodes connected to one single node. . . . . . . . . . . . . 35
3.5 Photodiode connected to NMOS differential pair with load. . . . . 36
3.6 Small signal model of a simple differential pair (with only one tran-sistor). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
xiv
3.7 Active-Input Current Mirror Amplifier. . . . . . . . . . . . . . . . 40
3.8 Small signal model of Active-Input Current Mirror. . . . . . . . . 41
3.9 Active-Input Current Mirror. . . . . . . . . . . . . . . . . . . . . 42
3.10 Active-Input Current Mirror. . . . . . . . . . . . . . . . . . . . . 42
3.11 Illustration of the differences in the designs of a normal high gainop-amp and a voltage regulator op-amp. . . . . . . . . . . . . . . 45
3.12 Configuration of a Current Mirror with voltage regulator. . . . . . 46
3.13 Configuration of a Current Mirror with voltage regulator. . . . . . 46
3.14 2-Stage CMOS voltage regulator. . . . . . . . . . . . . . . . . . . 47
3.15 2-Stage CMOS voltage regulator along with the load which is alinearized differential pair and a current mirror. . . . . . . . . . . 49
3.16 Setup for open-loop analysis of 2-Stage CMOS voltage regulatorwith an AC current source for photocurrent. . . . . . . . . . . . . 50
3.17 Open-loop AC response of 2-Stage CMOS voltage regulator withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) andibiasnd = 1µA (for the current mirror) for an AC current source ofiph = 20nA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.18 Setup for closed-loop analysis of 2-Stage CMOS voltage regulatorwith an AC current source for photocurrent. . . . . . . . . . . . . 52
3.19 Closed-loop AC response of 2-Stage CMOS voltage regulator withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) andibiasnd = 1µA (for the current mirror) for an AC current source ofiph = 20nA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.20 Cascoded common-source amplifier with a source follower. . . . . 54
3.21 Cascoded common-source amplifier with a source follower. . . . . 55
3.22 Cascoded common-source amplifier with a source follower alongwith the load which is a linearized differential pair along with acurrent mirror. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.23 Setup for open-loop analysis of cascoded common-source amplifierwith a source follower with an AC current source for photocurrent. 57
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3.24 Open-loop AC response of cascoded common-source amplifier withsource follower and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA(for the amplifier) and ibiasnd = 1µA (for the current mirror) foran AC current source of iph = 20nA. . . . . . . . . . . . . . . . . 58
3.25 Setup for closed-loop analysis of cascoded common-source amplifierwith a source follower with an AC current source for photocurrent. 59
3.26 closed-loop AC response of cascoded common-source amplifier withsource follower and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA(for the amplifier) and ibiasnd = 1µA (for the current mirror) foran AC current source of iph = 20nA. . . . . . . . . . . . . . . . . 60
3.27 Common-source amplifier with output mirror. . . . . . . . . . . . 60
3.28 Common-source amplifier with output mirror. . . . . . . . . . . . 61
3.29 Common-source amplifier with output mirror along with the loadwhich is a linearized differential pair along with a current mirror. 62
3.30 Setup for open-loop analysis of common-source amplifier with out-put mirror with an AC current source for photocurrent. . . . . . . 63
3.31 Open-loop AC response of common-source amplifier with outputmirror and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for theamplifier) and ibiasnd = 1µA (for the current mirror) for an ACcurrent source of iph = 20nA. . . . . . . . . . . . . . . . . . . . . 64
3.32 Setup for open-loop analysis of common-source amplifier with out-put mirror with an AC current source for photocurrent. . . . . . . 65
3.33 Open-loop AC response of common-source amplifier with outputmirror and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for theamplifier) and ibiasnd = 1µA (for the current mirror) for an ACcurrent source of iph = 20nA. . . . . . . . . . . . . . . . . . . . . 66
3.34 A Simple Differential Pair. . . . . . . . . . . . . . . . . . . . . . . 67
3.35 A Differential Pair With Source Degeneration Via Symmetric Dif-fusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.36 Design of Linearized Differential Pair With Source DegenerationVia Symmetric Diffusion. . . . . . . . . . . . . . . . . . . . . . . . 68
3.37 Low Voltage Cascode Current Mirror. . . . . . . . . . . . . . . . . 69
xvi
3.38 Simple current mirror, that mirrors the current equally in twobranches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.39 Setup for closed-loop analysis of a simple current mirror with anAC current source for photocurrent. . . . . . . . . . . . . . . . . . 74
3.40 Open-loop AC response of simple current mirror at node Vox withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) andibiasnd = 1µA (for the current mirror) for an AC current source ofiph = 20pA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.41 closed-loop AC response of simple current mirror at node Vox withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) andibiasnd = 1µA (for the current mirror) for an AC current source ofiph = 2µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.42 Voltage divider network scheme. . . . . . . . . . . . . . . . . . . . 77
3.43 Design Of The Clock Comparator. . . . . . . . . . . . . . . . . . . 78
3.44 Setup for measuring offset of the clocked comparator. . . . . . . . 80
3.45 Transient responses of the clocked comparator with Vdd = 0.9 V ,Vss = −0.9 V , ibiasp = 10µA and input clock (clkin)= 10Hz. . . . 81
3.46 Setup for transient response of the clocked comparator. . . . . . . 82
3.47 Transient response of the clocked comparator with Vdd = 0.9 V ,Vss = −0.9 V , ibiasp = 10µA, positive input vi+ = Vss + 0.6 Vand negative input voltage (vi−) as a pulse waveform of 10MHzvarying from vi+ (−150 mV ) to vi+ (+10 mV ). . . . . . . . . . . 82
3.48 Transient response of the clocked comparator with Vdd = 0.9 V ,Vss = −0.9 V , ibiasp = 10µA, positive input vi+ = Vss + 0.6 Vand negative input voltage (vi−) as a pulse waveform of 10MHzvarying from vi+ (+150 mV ) to vi+ (−10 mV ). . . . . . . . . . . 83
3.49 Non-Overlapping Clock Generator Schematic. . . . . . . . . . . . 83
3.50 Transient response of non-overlapping clock generator with Vdd =0.9 V , Vss = −0.9 V and input clock(clkin)= 10MHz. . . . . . . . 85
3.51 Transistor level schematic of clever XOR gate. . . . . . . . . . . . 87
3.52 Transient response of clever XOR gate with Vdd = 0.9 V , Vss =−0.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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3.53 Transistor level schematic of N -input OR gate. . . . . . . . . . . . 88
3.54 Transient response of the flash converter with Vdd = 0.9 V , Vss =−0.9 V and Vin = 50 mV for a clock frequency of 100kHz. . . . . 89
3.55 Photocurrents arrangement to simulate a gradual moving light in-cident on a one dimensional pixel array. . . . . . . . . . . . . . . . 90
3.56 Transient response of centroid computation circuit along with theflash converter with Vdd = 0.9 V , Vss = −0.9 V , ibiasnd = 1µA,ibias = 0.88mA and ibiasp = 390µA. . . . . . . . . . . . . . . . . 91
3.57 Transient response of analog centroid computation circuit at withVdd = 0.9 V , Vss = −0.9 V , ibiasnd = 1µA, ibias = 0.88mA andibiasp = 390µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.1 Test box for centroid computation chip. . . . . . . . . . . . . . . . 94
4.2 Regulated power supply circuit. . . . . . . . . . . . . . . . . . . . 95
4.3 Picture of the optical setup. . . . . . . . . . . . . . . . . . . . . . 97
4.4 Layout of a 2x2 pixel array. Dimensions are 20.25µm x 20.25µm . 98
4.5 Circuit to measure the photocurrent using a transimpedance am-plifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.6 Layout of an NMOS low voltage cascode current mirror. Dimen-sions are 51.60µm x 17.55µm . . . . . . . . . . . . . . . . . . . . . 101
4.7 Layout of a linearized differential pair. Dimensions are 34.80µm x14.25µm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.8 Setup for voltage gain DC sweep. . . . . . . . . . . . . . . . . . . 102
4.9 Voltage gain DC sweep for the OTA. . . . . . . . . . . . . . . . . 103
4.10 Setup for transconductance gain DC sweep. . . . . . . . . . . . . 103
4.11 Transconductance (Iout versus Vin) DC sweep for OTA. . . . . . . 104
4.12 Layout of a PMOS current mirror including feedback amplifier.Dimensions are 65.10µm x 21.90µm . . . . . . . . . . . . . . . . . 104
4.13 Layout of the analog centroid computation circuit. Dimensions ofthe chip are 1499.70µm x 1499.55µm. Dimensions of the centroidcircuit are 989.70µm x 989.70µm . . . . . . . . . . . . . . . . . . . 106
xviii
4.14 Position of the spot vs column (x-direction) centroid output voltagefor 2nd and 3rd rows. . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.15 Position of the spot vs row (y-direction) centroid output voltagefor 2nd and 3rd columns. . . . . . . . . . . . . . . . . . . . . . . . 108
4.16 Mismatch in the column (x-direction) centroid output voltage for2nd and 3rd columns. . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.17 Mismatch in the row (y-direction) centroid output voltage for 2nd
and 3rd rows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.18 Locations of the left and right LED spots. . . . . . . . . . . . . . 109
4.19 Comparison of measured centroid voltage with the simulations ofthe actual circuit, simulations of the Deweerth’s circuit [1], an idealwinner-take-all circuit and the expected true centroid in the x-direction (column) for variable currents at light spot made by theleft LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.20 Comparison of measured centroid voltage with the simulations ofthe actual circuit, simulations of the Deweerth’s circuit [1], an idealwinner-take-all circuit and the expected true centroid in the y-direction (row) for variable currents at light spot made by the leftLED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.21 Comparison of measured centroid voltage with the simulations ofthe actual circuit, simulations of the Deweerth’s circuit [1], an idealwinner-take-all circuit and the expected true centroid in the x-direction (column) for variable currents at light spot made by theright LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.22 Comparison of measured centroid voltage with the simulations ofthe actual circuit, simulations of the Deweerth’s circuit [1], an idealwinner-take-all circuit and the expected true centroid in the y-direction (row) for variable currents at light spot made by the rightLED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.23 Pictures of bandwidth measurements without and with feedbackfor a sinusoidal photocurrent of amplitude 1.95nA and dc averageof 2.195nA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.24 Pictures of bandwidth measurements without and with feedback fora sinusoidal photocurrent of amplitude 3.0375nA and dc average of9.525nA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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4.25 Pictures of bandwidth measurements without and with feedback fora sinusoidal photocurrent of amplitude 3.1025nA and dc average of11.64nA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A.1 Micrograph of the Chip . . . . . . . . . . . . . . . . . . . . . . . . 123
A.2 Micrograph of pixels . . . . . . . . . . . . . . . . . . . . . . . . . 124
A.3 Picture of optical setup comprising microscope and adapter fittedwith LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
A.4 Picture of adapter with LEDs. . . . . . . . . . . . . . . . . . . . . 125
A.5 Picture of some of the equipment used such as oscilloscope andwaveform generators. . . . . . . . . . . . . . . . . . . . . . . . . . 125
B.1 Voltage divider configuration to generate any voltage between Vdd
and Vss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
B.2 Current measurement configuration to measure current that is flow-ing into a pin(may have an NMOS). . . . . . . . . . . . . . . . . . 131
B.3 Current measurement configuration to measure current that is flow-ing out of a pin(may have a PMOS). . . . . . . . . . . . . . . . . 132
xx
Chapter 1
INTRODUCTION
1.1 Background
Many modern imaging systems incorporate a centroid computation as one
of the major tasks to be performed. The centroid is the location of the “center
of mass” of an intensity pattern of an image. Centroid computation circuits can
be used to track the motion of the centroid of an image and thus determine the
motion of the image. This is useful in detecting a moving target such as the sun,
a missile, a vehicle or even a person. Image stabilization in photography can be
achieved by centroid computation. If an image is wobbling on the image plane of a
camera either due to shaking of camera or due to an unstable object, its centroid
on the image sensor also moves around. By adjusting the system according to
the movement of the centroid, one can achieve a good image stabilization. Cen-
troid computation also finds place in astronomical applications like tracking the
movement of a star or any celestial body. Centroid computation with a windowing
property enables the circuit to compute local centroids over small desired portions
of the pixel array. This helps in tracking a particular object among many other
objects. This approach also has astronomical applications like tracking the images
of several stars simultaneously, which is mostly used for navigational purposes. In
many other adaptive optical applications, centroid computation assumes a sig-
nificant role such as wavefront correction. All these applications demand a high
accurate and fast centroid circuit which forms the basic motivation for this thesis.
1
Off-chip processing usually involves a sensor to detect an image and send
the data off-chip for further processing. Reading out a frame of data and then
processing it is a slow process if the centroid computation is done off-chip. An
on-chip centroid computation has the advantage of fast readout of the x and y
coordinates of the centroid of an image.
1.2 Purpose of the Present Work
This thesis is focused on improving the bandwidth and precision of an on-
chip centroid computation system, while keeping the effects of offsets as low as
possible. The goal of the thesis is to achieve at least 10 times higher bandwidth
compared to that of previous designs over 5 decades of photocurrents. The pro-
posed design improves precision by implementing a linearized differential pair in
the centroid computation.
The proposed architecture is based on earlier work done by Deweerth [1]
and Bashyam [2] in centroid computation. The proposed architecture consists of
a 40x40 pixel array with a 2-dimensional centroid computing capability aimed at
high bandwidth and high precision.
1.3 Summary of Accomplishments
The two major accomplishments of this thesis are given below.
• In this thesis, 7.5 to 8.5 times higher bandwidth has been measured when
compared to that of a circuit which does not have any feedback such as
Deweerth’s model [1]. It has also achieved 10 times more bandwidth when
compared to that of Bashyam’s circuit [2].
• A linearized differential pair is used in the centroid computation circuit for
the first time so as to improve the precision of the centroid computation.
The proposed circuit is actually computing the centroid that is the “center
2
of mass” of an intensity pattern of an image as opposed to other centroid
circuits based on winner take all or median computation topologies [3] [1].
1.4 Overview
This thesis work has 4 chapters, excluding the introduction, and an overview
of each chapter is presented as following.
In chapter 2, the discussion starts with the introduction of image sensors
with their historical development. Then, CCDs and CMOS image sensors are
discussed along with their comparison. The chapter follows with fundamentals of
the centroid computation, types of photodiodes, modeling of the photodiode and
a review of subthreshold operation of MOS transistors. The chapter ends with
brief discussion on flash converters and a clocked comparator.
In chapter 3, earlier work on centroid computation are discussed along
with their drawbacks. Then the proposed architecture is explained. Photodiodes
and pixel array designs are discussed. Three feedback amplifier configurations
with the readout current mirror have been explored and their simulation results
are compared. Then, a design of linearized differential pair is discussed. A Low
voltage cascode mirror design is given which is used as a current subtracter. A
design for a flash analog-to-digital converter using a clocked comparator is given
along with the simulation results at the end of the chapter.
In chapter 4, the electrical test setup along with the optical test setup
are discussed. Layouts of the circuits are shown. Experimental results from the
fabricated chips are given. Comparisons of the experimental results with the
respective simulation results are also done.
In chapter 5, summary and conclusion of the research is given. This chapter
also includes a few suggestions for the future work.
3
Chapter 2
SOLID-STATE IMAGE SENSORS AND FUNDAMENTALS OF
CENTROID COMPUTATIONS
Solid-state integrated circuits with either a 2-dimensional or 1-dimensional
array of photosensitive elements that are capable of converting an incident optical
image signal into a sensible electrical output are called solid-state image sensors.
Solid-state image sensors are more amicable to computers, as they collect the
image in the form of digital data, when compared to conventional cameras. They
also take less time to get a hard copy as they do not require time for developing.
They also can save time if there is any further processing of the image.
There are solid-state image sensors made of different materials that have
imaging capabilities in different spectral regions, as shown in Fig 2.1.
Figure 2.1: Solid-state image sensors characteristics over a wide spectral range [4].
4
Commercial applications for image sensors mostly are in the visible spec-
trum and the best suited for this spectral range are silicon based image sensors.
Currently two types of silicon based image sensors are available: The more
mature Charge Coupled Devices (CCDs) and newly emerging Complementary
Metal Oxide Semiconductor (CMOS) image sensors (CISs).
In many visual or image processing systems, the centroid computation is
an important task that is performed. The centroid of any image projected onto
an image sensor can be defined loosely as the location of the “center of mass” of
the intensity pattern of that image. This thesis focuses on computing the centroid
of an image formed on a CIS.
In this chapter, a brief history of solid-state image sensors is presented.
Then, CISs are compared with CCDs. The basic architecture of a centroid-
determining circuit using an aggregation network [1] is explained in detail. A
brief explanation of silicon-based photosensitive elements is given, along with their
types. Some fundamental concepts of the subthreshold operation of a metal ox-
ide semiconductor field effect transistor (MOSFET) are discussed. Finally, an
analog-to-digital converter and a clocked comparator are explained in detail.
2.1 Evolution of solid-state image sensors
Image sensors took many years with many milestones, to evolve to what
they are now, as shown in Fig 2.2. A brief summary of the historical background
given by Fossum [5] is as follows:
• In the 1960’s many research groups concentrated their research on PMOS,
NMOS and bipolar processes. A few examples of these devices are a compu-
tational sensor by Morrison [7], a scanistor by IBM [8] and a 50x50 element
monolithic array of photo transistors [9]. These sensors have an output that
is propotional to the inatantaneous intensity of light incident on them and
5
Figure 2.2: History of MOS, CMOS and CCD image sensors [6].
do not have any capability to integrate the output signals. These devices
also needed some gain to increase their performance due to low sensitivity.
• In 1967 and 1968, photodiodes were used as photosensitive elements with
some integration of the output charge [10] [11].
• Simultaneously in 1968, an image sensor was reported which used thin-film
transistors(TFTs) and photo conductors with sequential pixel addressing
logic [12].
• Also in 1968, a self-scanned silicon image detector arrays using photodiodes
and buried photodiodes for low dark currents was presented by Noble [13].
He also used a charge integration amplifier readout and a MOS source-
follower transistor to buffer the readout.
6
• A big issue came to light which effected the development of MOS and CMOS
image sensors in 1970 called fixed-pattern noise(FPN) [14]. CCDs have an
advantage in this issue of FPN and the focus of many research groups shifted
to CCDs. This shift helped CCDs to mature and develop more with regards
to quantum efficiency, optical fill factor, dark current, readout noise etc.
MOS image sensors were investigated rarely, by very few groups in those
days.
• In the late 70’s and 80’s some companies like Hitachi and Matsushita tried
to develop MOS image sensors [15] [16] [17] [18] [19] but discontinued to do
so because of some residual temporal noise at low light levels.
• In the late 1980’s, CISs made their way back into the market in two re-
lated fields: hybrid infrared focal-plane arrays and high-energy physics par-
ticle/photon vertex detectors [20]
• Applications where low-cost, high integration and not high performance are
required, paved the way for growth of CISs in the early 1990’s. Organi-
zations like NASA, JPL and companies like AT&T Bell Labs, Kodak and
several other companies’ efforts helped CISs to move forward. Later CISs
saw very rapid progress in its performance, especially in fixed pattern noise
and increased its use in high speed applications, on-chip image processing
and other important applications.
2.2 CCD and CMOS Image Sensors: A comparison
Charge Coupled Devices (CCDs) and Metal Oxide Semiconductor (CMOS)
image sensors (CISs) are both made of silicon. Both function in the same way
in the accumulation of charge as both collect the charge which is proportional to
the intensity of light incident on them. They mainly differ in the way the pixels
7
are readout. In CCDs, the charge is transferred sequentially in a row and then
sequentially in the next row and so on. On the other hand, each pixel can be read
and processed independently in a CIS.
This difference in the technique of readout contributes to all other charac-
teristic differences between the two types of image sensors. Litwiller [21] summa-
rized the comparison as follows:
Responsivity is the amount of electrical output per unit of optical input of a
sensor. As CISs can include in-pixel low-power high-gain amplifiers, they
have a little upper-hand over CCDs in this factor.
Dynamic Range is the ratio of the largest possible signal a sensor can generate
to its lowest possible signal. CCDs do not have on-chip circuitry making
them less noisy than CISs. They also have a high tolerance to bus capaci-
tance variations. These make CCDs superior to CISs in dynamic range by
a factor of nearly two.
Uniformity can be defined as the consistency in the output response of different
pixels in the same sensor under identical light intensity conditions. Varia-
tions in spatial wafer processing and particulate defects make CISs worse
when compared to CCDs. Some feedback amplifiers are used to achieve
greater uniformity in CISs by giving up some gain in normal illumination
conditions. But, CISs still perform worse in low light or dark conditions.
Shuttering in a sensor means randomly starting and stopping the exposure of
the sensor. This is important in industrial and machine visio applications.
CCDs perform better in this aspect when compared to CISs with minimal
loss in fill factor. To tackle this aspect in CISs, designers have considered two
8
types of shuttering. One is a non-uniform shutter for high-performance, still-
image, consumer applications. The other is a uniform synchronous shutter,
especially important for imaging objects in motion.
Fill factor. The percentage of a pixel that is useful in collecting light is called
the fill factor. CCDs have almost 100% fill factor whereas CISs do not have
100%, as the pixels include some type of readout or gain amplifier circuitry
with them.
Speed. CISs are faster than CCDs mainly because of on-chip processing circuitry
and random or simultaneous pixel readout in CISs.
Windowing. CISs are more suitable for windowing applications due to their
capability to readout desired portions of the sensor. This capability also
increases the frame rates for those regions. This makes CISs more suitable
to applications like object tracking.
Antiblooming is the process in which the sensor tries to gradually decrease the
signal strength locally in the pixels which are over-exposed without effecting
the rest of the image. CISs inherently have some resistance to blooming
whereas CCDs need to have specialized techniques applied to them to obtain
this antiblooming ability.
Biasing and clocking. CISs have an advantage in this aspect. They normally
require a single bias voltage and clock and any non-standard biasing can be
generated on-chip. CCDs generally require several high-voltage biases.
Integration. CISs have the upper-hand over CCDs in the aspect of integration.
Timing generation, analog-to-digital conversion, image processing, data in-
9
terpretation and other functions can be integrated onto the same chip on
which the image sensor is built.
Cost. There is a wide misconception about the cost of image sensors. Many con-
sider that CISs cost much lower than CCDs on the basis of the argument that
CISs use the same process that is used to fabricate memory chips, computer
processing chips and many other CMOS chips. Contrary to this popular
opinion, the cost of both CCDs and CISs are comparable when fabricated in
equal volumes. This is because CMOS image sensors(CISs) need to be made
on special, low volume, optically-adapted mixed-signal CMOS processes in
order to obtain good electro-optical properties. This implies that neither of
them has such a high commanding economic advantage when compared to
the other.
CCDs and CISs technologies complement each other and so serve differently
for different applications. In applications where a higher performance in terms of
noise and fill factor is needed, CCDs are preferred over CISs. On the other hand,
CISs are preferred over CCDs for high-speed, low-power and on-chip processing
applications.
2.3 Centroid Computation
An essential part in many digital imaging applications is finding the posi-
tion or centroid of an object. It can be a time consuming process to compute the
centroid off chip, largely because it takes time to send the information of the entire
image to off-chip. It is also a power consuming method, as it involves long signal
and power supply lines. In order to make the computation of centroid quicker,
on-chip computation is done and only the coordinates of the centroid are sent out
of the chip [22]. Deweerth introduced a circuit which is capable of computing the
10
centroid of an image on the imager chip itself, including a scheme for position
encoding [1]. A computation architecture similar to the above scheme had been
implemented by Martin [23]. Another scheme is proposed by Bashyam [2] which
is a modification of Deweerth’s model [1] aimed at higher bandwidth and lower
offset. Deweerth’s model [1] is discussed in detail in the following subsections.
2.3.1 Centroid
The computation of the centroid in the case of an extended object, gives
the location of the object. Liberally speaking, the centroid is the location of the
“center of mass” of an intensity pattern of an image. It is defined as the first
moment of the image [1]. According to Pui [24], the centroid of a two dimensional
photo-detector array can be expressed as follows:
C(x) =
∑rxnIn∑In
C(y) =
∑rynIn∑In
(2.1)
where
C(x) is the x-coordinate of the centroid
C(y) is the y-coordinate of the centroid
rxn is the displacement of each photo-detector from the origin of the
array in the x-direction
ryn is the displacement of each photo-detector from the origin of the
array in the y-direction
In is the light (current) level of each photo-detector
Similarly, it can be expressed in terms of a voltage output (for one dimen-
sion) as follows:
Vcentroid =
∑vnin∑in
(2.2)
11
where
vn is the voltage displacement of each photo-detector from the origin
on the resistive grid used for position encoding.
in is the current level of each photo-detector
The average intensity of an image should not effect the computation of the
centroid. Thus is even if the average intensity of the entire image changes, say, in
the form of background light, the location of the brightest spot should not change
and the computation should be consistent.
2.3.2 Aggregation Network
An aggregation circuit involves aggregation of the data of the image inci-
dent in order to decrease the bandwidth requirement for centroid computation. A
one-dimensional aggregation network is described in this section. This circuit has
two outputs by aggregating two arrays of output currents from an array of N+1
differential pairs. This circuit is shown in Fig 2.3.
Each differential pair has two output currents which are functions of the
input differential voltage and the biasing input current. The output currents can
be expressed as exponential functions of the input differential voltage. The output
currents of any nth differential pair can be represented as follows [1]:
io1 =in
1 + e−∆vn
VT
io2 =in
1 + e∆vnVT
(2.3)
where
io1 and io2 are the output currents
vn is the differential voltage input of nth differential pair
in is the biasing current of nth differential pair
12
Figure 2.3: Aggregation Network of N+1 differential pairs [1].
VT is the thermal voltage
The output currents are aggregated on to two current lines ia and ib and
they can be expressed as follows [1]:
ia =∑
n
in
1 + e−∆vn
VT
ib =∑
n
in
1 + e∆vnVT
(2.4)
where
ia and ib are the output currents
vn is the differential voltage input of nth differential pair
in is the biasing current of nth differential pair
VT is the thermal voltage
13
According to Kirchoff’s current law, the magnitudes of the currents are main-
tained even if they are added or subtracted. This implies that the addition of the
differential output currents equals the difference in the aggregated output cur-
rents (ia - ib). The differential aggregated output current is given by the following
equation [1].
ia − ib =∑
n
in tanh
(∆vn
2VT
)(2.5)
2.3.3 Resistive position encoding scheme
In order to effectively use the aggregation network and find the centroid
of any image, the image sensor should have some sort of co-ordinate system, or
spatial identification scheme, so that it exactly locates the centroid. This is done
by encoding the relative position of the elements with the help of different input
voltages. A series network of resistors makes this task easy, as it is a simple voltage
divider. N+1 resistors are connected in series and two voltages V0 and VN are
applied at the two ends of the series network. The intermediate nodes are tapped
as V1, V2,,,,,,,VN−1. This scheme will result in a linear voltage gradient along the
length. At any nth intermediate node the voltage is given by [1],
Vn =
(VN − V0
N
)n + V0 (2.6)
Vn-Vref represents the relative position. Where Vref indicates the origin, as it
indicates the position of the element where the differential output current is almost
zero. The aggregation network including this resistive position encoding is shown
in the Fig 2.4.
14
Figure 2.4: Aggregation Network of N+1 differential pairs with position encod-ing [1].
2.3.4 Centroid detection
A current subtractor (mirror) circuit is added to the aggregation network
with the position encoding scheme to form a centroid computation circuit as shown
in the Fig 2.5.
In this circuit, the aggregated differential output current from the current
subtractor is directly fed back in order to control Vref which is also Vout. Vout
results from the summation of the aggregated differential output current at this
node. It aggregates till this aggregated differential output current becomes 0.
At this point, Vout which represents the reference voltage, is the centroid of this
one dimensional array of elements. Vout lies between V0 and VN . This Vout value
will be close to any one of the intermediate nodal voltage values on the resistive
15
Figure 2.5: Centroid detection Circuit [1].
network. The node to which Vout is close to gives the position of the centroid. The
mathematical derivation for this centroid voltage can be worked out as follows [1]:
ia − ib = 0 (2.7)
From (2.5) ∑n
in tanh
(∆vn
2VT
)= 0 (2.8)
∑n
in tanh
(Vn − Vout
2VT
)= 0 (2.9)
16
Vn−Vout is very small when compared to VT and Hence (2.9) can be written as [1]
∑n
in
(Vn − Vout
2VT
)= 0 (2.10)
∑n
in (Vn − Vout) = 0 (2.11)
∑n
inVn −∑
n
inVout = 0 (2.12)
∑n
inVout =∑
n
inVn (2.13)
Vout
∑n
in =∑
n
inVn (2.14)
Vout =
∑N0 inVn∑N
0 in(2.15)
Vout is nothing but VCentroid and hence (2.15) can be written as
VCentroid =
∑N0 inVn∑N
0 in(2.16)
The current mirror used in this centroid computation is one of the major sources
of dc offset in the entire system.
2.4 Photo-detectors
Photo-detectors are the sensing elements which are capable of sensing light
(or electromagnetic energy). In a CMOS process, they are made of parasitic
elements. Several photo-detectors are formed using n+, p+ ,n-well, p-well regions,
n− and p− type substrates in CMOS processes [24].
17
Photodiodes and phototransistors are the most popular elements used as
photo-detectors in CMOS process. The p − n junctions formed by using the
substrate and the active regions of opposite doping are used for sensing light in
the case of a photodiode. The junctions formed between the three terminals are
used in the case of the phototransistors [1].
Photodiodes are used more than phototransistors for photo-sensing for the
following reasons.
• Photodiodes have a higher fill factor than phototransistors of same size [1].
• Photodiodes have faster response when compared to phototransistors.
• Photodiodes have much more linear output versus incident light intensity
characteristics when compared to that of phototransistors [25].
• The dynamic range of photodiodes is 1-2 decades higher than that of pho-
totransistors [26].
• photodiodes are easier to fabricate when compared to phototransistors.
There are several types of photodiodes, as shown in the Fig 2.6. It is to be
noted that A and K are used to denote anode and cathode, respectively, for the
photodiodes.
Photodiodes shown in Figs 2.6(a) and 2.6(b) are shallow photodiodes formed
between active regions and the substrate or well regions. These are well suited for
operation at shorter wavelengths. The photodiode shown in Fig 2.6(c) is a deep
photodiode which is well-suited for longer wavelengths. A fourth configuration of
a photodiode, which works good for both short and long wavelengths, is shown in
Fig 2.6(d).
An n + /p-substrate photodiode is selected due to the following reasons.
18
Figure 2.6: Four types of photodiodes available in CMOS process [24].
• Good quantum efficiency [26].
• Relatively low capacitance per unit area makes this junction have a relatively
fast response [26].
• Easy to fabricate.
• Low area
2.4.1 Current in a Photodiode
When light is incident on a photodiode, the photodiode will have some
current flowing through it due to the generation of an electron-hole pair called
photocurrent (Iph). This current is in addition to the current that is already
flowing through it [27]. This current can be expressed as follows [27]:
iD = IS
(e
vDηVT − 1
)− Iph (2.17)
where
iD is the current in the diode
19
vD is the voltage across the diode
IS is the reverse saturation current
Iph is photocurrent
VT is the thermal voltage
η is the emission coefficient whose value is in between 1 and 2
The photocurrent generation can be illustrated with the help of the Fig 2.7.
a`
Figure 2.7: Photocurrent generation in a p-n diode [27].
Photocurrent is generated in the direction of cathode to anode and hence
a photodiode can also sense light even in zero bias (photovoltaic mode) or reverse
bias (photoconductor mode) conditions. Responsivity (R) of a photodiode is the
20
ratio of the output current to the intensity of light incident on the photodiode in
watts [27]. The maximum photocurrent of a photodiode is expressed as follows:
Iph = RPin (2.18)
Iph =q
hνPin (2.19)
where
q is the charge of an electron
h is Plank’s constant
ν is the frequency of the incident photon
Pin is the intensity of incident light
All the light that is incident on the surface of the photodiode is not converted to
photocurrent. Some of the incident power is reflected back. And also all of the
power is not absorbed. These two aspects are included mathematically in terms of
reflection coefficient (r) and absorption coefficient (α) [27]. Now the photocurrent
can be expressed as follows:
Iph = (1− r)(1− e−αd
) q
hνPin (2.20)
Dark current is the current which is generated inside the photodiode even if there
is no light incident on the photodiode. This is the primary cause for noise inside
the photodiode.
2.4.2 A Photodiode Model
A photo diode can be modeled as a current source with a capacitance
connected in parallel as shown in Fig 2.8.
21
Figure 2.8: Photodiode model.
Iph is the current source representing the photocurrent flowing from cathode to
the anode
Cph is the junction capacitance
Vrev is the reverse biased voltage
For a reverse bias voltage, Vrev=0 V(photovoltaic mode), the junction capacitance
of an n + /p-substrate photodiode is given by the following equation [28].
Cph = CJ · A + CJSW · P (2.21)
where
CJ is the bottom depletion or junction capacitance
CJSW is the sidewall depletion capacitance
A is the area of the active region
P is the parameter of the active region
The junction capacitance of a photodiode depends on the diode current and this
capacitance is not linear. The diode current depends on the thermal voltage
according to (2.17). This implies that a change in the thermal voltage effects the
22
junction capacitance. A crosssection of a photodiode along with the junction and
sidewall capacitances are presented in Fig 2.9.
Figure 2.9: Cross-section of a photodiode [2].
2.5 Subthreshold operation of an n-channel MOSFET
Subthreshold operation, also known as the weak inversion region of opera-
tion of MOFETs, is used in circuits where there is a requirement of very low power
consumption. In an n-channel MOSFET if vGS < VTH , then it is said to be in
subthreshold operation. In this region there will be a small amount of current in
the range of nanoamperes to femtoamperes flowing from the drain to the source.
This current is exponentially related to the gate voltage and, hence, the MOSFET
is said to have translinear characteristics [29]. The equation for the subthreshold
current (iD) in an NMOS [29] [30] is given as follows:
iD = IoW
Le
κvGBVT
(e
vSBVT − e
vDBVT
)(2.22)
23
where
Io is the zero bias current
κ is the subthreshold slope coefficient [29]
also,
κ =Cox
Cox + Cdep
(2.23)
where
Cox is the gate oxide capacitance
Cdep is the depletion capacitance between the surface charge and the
bulk
VT is the thermal voltage. At room temperature it is taken as 25 mV and is given
by,
VT =kT
q(2.24)
where
k is Boltzmann’s constant
T is the absolute temperature
q is the charge of an electron
For an n-type MOSFET to operate in the subthreshold saturation region, vDS >
4VT (approximately 100 mV). In this region, vSB and vDB are related as,
evSBVT >> e
vDBVT (2.25)
24
The drain current iD and transconductance gm [29] [30] can be written as,
iD = IoW
Le
κvGSVT (2.26)
gm =∂iD∂vGS
∣∣∣∣∣vGS=VGS
= κiDVT
(2.27)
There are two major drawbacks to subthreshold operation. One is the
increase in offset due to mismatch in transistors. MOS transistors are translinear
in subthreshold, that is, the current increases exponentially with voltage. A small
change in the threshold voltage results in a large change in the drain current.
This increases the mismatch problem. The other drawback is the reduction of the
speed of the circuits. Low currents in the subthreshold region cause a decrease in
bandwidth [2].
2.6 Flash Analog-to-Digital Converter
Analog-to-digital converters are the elements used to convert continuous
analog signals into digital data which is computer friendly and suitable for further
processing. For high speed applications, flash converters are used as they offer
high conversion rates. A brief summary about flash converters explained by John
and Martin [31] is given below. An example of a 3-bit flash converter is given in
Fig 2.10.
A flash converter has three parts: a series resistive network, an array of
voltage comparators to generate the thermometer code, and a digital block which
converts the thermometer code to an N -bit binary code.
A series resistive network with two reference voltages at the two ends is
used to generate the intermediate nodal voltages. These nodal voltages are used
as references to individual voltage comparators in the second stage. This resistive
25
-+
(2N-1) to Nencoder
Vin
Over range
N digital outputs
Vr2
Vr3
Vr4
Vr5
Vr6
Vr7
Vr1
R/2
R/2
R
R
R
R
R
R
R
Voltage comparators
Vref
-+
-+
-+
-+
-+
-+
-+
Vr8
Figure 2.10: A 3-bit flash analog to digital converter [31].
network with 2N resistors in series is based on voltage division. This network
divides the voltage between the two ends into 2N nodal voltages which are fed
into one of the inputs of the voltage comparators as voltage references.
An array of voltage comparators forms the second part. Each individual
comparator has its own reference voltage tapped from different nodes on the re-
sistive grid as one of their inputs. A common input voltage (Vin), which is to
be converted into digital form, is applied as the second input to all of the com-
26
parators. The inputs are compared by each comparator and a zero or a one is
generated. The output from the comparators will be a string of zeros coming
from those which have Vin greater than the input reference nodal voltages and
a string of ones coming from those which have Vin less than the input reference
nodal voltages. This is called a thermometer code.
A digital block which converts the above generated thermometer code to
a binary code or any other code which is desired is the last and third part of
this flash converter. This completes the conversion of the analog signal, Vin, into
digital form.
2.7 Clocked comparator
A voltage comparator used in the flash analog-to-digital converter is an
important component in the design of the flash analog-to-digital converter as it is
the element which tends to limit the speed of the whole system. It also consumes
most of the power. A MOS comparator with high speed and high accuracy is
needed. A good design of a clocked voltage comparator with high speed and good
accuracy is given by Yin, Eynde and Sansen [32] as shown in Fig 2.11. This design
is described in brief in the following paragraphs.
The clocked comparator shown in Fig 2.11 has three major components:
an input differential pair, a CMOS latch and an S-R latch. The input differential
pair is made of PMOS transistors (M1, M2). The CMOS latch has two parts. One
is made of NMOS transistors (M4, M5) and the other with PMOS transistors (M6,
M7). It also has two PMOS transistors (M10, M11) for pre-charging the PMOS
part, an NMOS switch (M12) for resetting NMOS part and two NMOS transistors
(M8, M9) for strobing and isolating the PMOS part from that of the NMOS part.
Two non-overlapping clocks, φ1 and φ2, are used.
27
Figure 2.11: A CMOS clocked comparator.
Figure 2.12: A CMOS clocked comparator timing diagram.
The working of the circuit can be explained with the help of the timing
diagram shown in Fig 2.12. Dynamic operation is based on two important time
28
intervals. One is the reset time during which φ2 remains high which is the time
interval between t1 and t2 as shown in the timing diagram. The other is the
the time after φ2 goes low (t2) and before φ1 goes low (t4). This is called the
regeneration time.
During reset time, φ2 will be high, turning transistor M12 on, and φ1
remains low, turning transistors M8 an M9 off. The off state of M8 and M9
results in isolating the NMOS part of the latch. Transistor M12 allows current
to flow, forcing the NMOS part to reset. As such the voltages on the nodes a
and b are made equal by which they lose their previous voltages representing two
different logic states. Also, a low level on φ1 will turn the pre-charging transistors
(M10 and M11) on and force nodes c and d to reset to Vdd. Thus, the CMOS latch
is reset for the next comparison.
The regeneration time is divided into two time intervals. The first time
interval is between the instants where φ2 goes low and φ1 goes high. The second
time interval starts when φ1 goes high and ends when φ1 goes low. In the first
interval, transistors M8 and M9 are still off, isolating the NMOS part from the
PMOS part and M12 is turned off making the NMOS part respond to the input
differential voltage through the input stage. Now, regeneration enters the second
time interval when the strobing transistors M8 and M9 turn on. This allows the
voltage changes from nodes a and b to be reflected onto nodes c and d. These
voltage changes on nodes c and d are amplified immediately to a large swing, that
almost reaches the power rails. With the help of the S − R latch from the third
stage, full-swing digital outputs are achieved and maintained at those levels until
the next output from another regeneration process appears.
This scheme provides a very high speed, low offset clocked comparator that
can be used in synchronous analog-to-digital converters.
29
Chapter 3
CENTROID COMPUTATION CIRCUIT: ARCHITECTURE,
DESIGN AND SIMULATIONS
3.1 Introduction
The centroid computation is one of the major tasks to be performed in
many image processing systems. In order to accomplish a high speed and high
accuracy centroid computation circuit, a stable circuit with high bandwidth and
low offset needs to be designed. This thesis describes one such system design. The
main focus of this thesis is on improving bandwidth and stability of a centroid
computation system minimizing the offsets. In addition, improved accuracy in
the centroid computation. The centroid circuit is designed for CMOS technology
and implemented in AMI 0.5µm process using MOSIS fabrication service.
3.2 Architecture
The basic architecture of the centroid computation system explained in
this thesis is shown in Fig 3.1.
The centroid computation system consists of the following major building
blocks.
• A 40x40 two-dimensional pixel array
• Two analog centroid computation circuits
• Two flash analog-to-digital converters
30
Figure 3.1: Architecture of centroid computation system.
A 40x40 two-dimensional pixel array is used as a sensor. When an image
is incident on it, it converts the optical signals (light) into electrical signals. This
is done by each photodiode by generating a photocurrent proportional to the light
intensity incident on it. These currents are given as inputs to both column and row
analog centroid computation circuits. The centroid is computed in analog form
by these centroid computation circuits in both x and y directions. This analog
output is converted to a digital output at a fast rate using a flash analog-to-digital
converter.
31
The analog centroid computation circuit used for column or row is similar
to the one conceived by Bashyam [2]. This has three important parts: an array of
feedback amplifiers with differential pairs, one current mirror and a series resistive
network. The array of feedback amplifiers with differential pairs is the aggregation
network. The output currents are aggregated onto two output current signal lines.
These two currents are subtracted with the help of a current mirror to get the
difference current which results in the centroid in terms of voltage. The resistive
network is used to implement position encoding.
The series resistive grid used in the analog centroid computation circuit
is also shared by the flash converter. Intermediate nodal voltages of this series
resistive network are tapped and given to the inputs of the voltage comparators as
reference voltages. The flash converter converts the analog output into a digital
form, therby indicating the location of the centroid of the image incident on the
sensor.
3.3 Pixel array
The sensor of the whole centroid computation circuit is the pixel array
which senses the light and generates an electrical signal required for further pro-
cessing. A 40x40 pixel array is used. Each pixel is of 20.25µm x 20.25µm size
with a fill factor of 48.53%. The photo-sensing element in each pixel is a photo-
diode. This photodiode is implemented using the junction formed between n+
diffusion and the p-type substrate. This is a shallow photodiode capable of sensing
light at shorter wavelengths. The reasons for selecting this photodiode have been
discussed in Section 2.4. Layout of a 2x2 pixel array is shown in Fig 4.4.
A 40x40 pixel array is implemented in an alternating configuration. An al-
ternating configuration for a 4x4 pixel array is shown in Fig 3.3. Every alternating
pixel is connected to one bus-line, and the other alternating pixels are connected
32
Figure 3.2: Layout of a 2x2 pixel array.
Figure 3.3: Floorplan of a 4x4 pixel array.
33
to another bus-line. This arrangement makes the currents of adjacent pixels added
to opposite axis [1]. This scheme results in having 20 pixels connected together
to each bus-line. There are 40 bus-lines horizontally and 40 bus-lines vertically,
providing 40 input currents to each aggregation network: the column and row
centroid computation circuits.
According to Delbruck and Mead [26], when a light of intensity of 1 W/m2
is incident on a 10µm x 10µm photodiode with quantum efficiency of 0.5, a pho-
tocurrent of about 25pA is generated. Considering this, the total current will be
around 2nA for the above typical conditions for a bus-line consisting of 20 pho-
todiodes each of size 20µm x 20µm. The photocurrent can vary from 200pA to
2µA depending upon the light intensity.
There will be a huge capacitance at the node of each bus-line as a result of
20 photodiodes connected to that node. Fig 3.4 shows a node with N photodiodes.
The capacitance at this node can be estimated as follows:
Given
• Area of the photodiode, A ≈ 400µm2
• Perimeter of the photodiode, P ≈ 80µm2
• Junction capacitance, CJ = 429aF/µm2 (for AMI 0.5µm process)
• Sidewall junction capacitance, CJSW = 326aF/µm (for AMI 0.5µm pro-
cess)
The capacitance of one photodiode using (2.21) is calculated as,
Cph = CJ · A + CJSW · P = 197.68fF (3.1)
34
N
LOAD
1 2 N-1
Figure 3.4: N photodiodes connected to one single node.
For the bus-line with 20 such photodiodes, the capacitance is calculated as,
Cline = 20× Cph = 3.9536pF ≈ 4pF (3.2)
3.4 Analog centroid computation circuit
The analog centroid computation circuit design is based upon the De-
weerth’s model for the centroid computation [1]. The present thesis work is also
based on the design proposed by Bashyam [2]. The design by Bashyam [2] was
aimed at achieving very low offset and high bandwidth operation. The design
achieved a higher bandwidth of operation without much improvement in the off-
set. This design also faced significant stability problems. The design presented in
the present thesis is aimed at achieving much higher bandwidth with more stabil-
35
ity over a higher range of photocurrents. The design proposed by Bashyam [2] is
discussed, along with the new proposed design in the following subsections.
3.4.1 Aggregation network: Previous work
As discussed earlier in Section 2.3.2, an aggregation network aggregates the
output currents from N differential pairs biased with N photocurrents generated
from N photodiodes (for a one-dimensional array) onto two aggregation current
lines [1].
Simple differential pair
The photocurrents were given as bias currents by connecting the sources of
the transistors in the differential pair directly to the photodiodes in the Deweerth’s
model [1]. There is a need to analyze the small signal analysis for this circuit. An
NMOS differential pair with a photodiode is shown in Fig 3.5. The small signal
Figure 3.5: Photodiode connected to NMOS differential pair with load.
model of the same circuit, considering only one transistor is shown in Fig 3.6. The
resistance as seen by the diode is to be derived. A test voltage vt is applied in
36
Figure 3.6: Small signal model of a simple differential pair (with only one tran-sistor).
place of the photodiode. Then, the ratio of this input voltage (vt) to the input
current (it) is the input resistance at that node. Mathematically, this is derived
as shown below.
it = −gmvgs2 (3.3)
vgs2 = −vt (3.4)
From (3.3), (3.4) and (2.27), we get
Rin =vt
it=
1
gm
=VT
κ · Iph
(3.5)
37
The above equation apllies to a single transistor. Both transistors (M1 and M2)
in the differential pair should be taken onto consideration. Now the photocurrent
is equally split in both the branches of the differential pair (iD = Iph/2) and so
the equation can be rewritten as,
Rin =1
gm1
∥∥∥∥∥∥∥∥∥∥ 1
gm2
(3.6)
From (2.27)
gm1 = gm2 = κiDVT
= κIph
2VT
(3.7)
From (3.4.1) and (3.7), we get
Rin =1
2
(2VT
κ · Iph
)=
VT
κ · Iph
=1
gm
(3.8)
The bandwidth of centroid circuit can be calculated using the following
equations.
BW =1
2πτin
(3.9)
Time constant, τ is given by
τin = Rin(Cin + N · Cph) (3.10)
The total capacitance at the node is due to the capacitance of the bus-line Cph
and the capacitance of other analog circuitry Cin. The capacitance due to the
differential pair, Cin, is very low when compared to the huge capacitance due to
the photodiodes Cph. Now,
τin ≈ Rin(N · Cph) = RinCline (3.11)
38
Hence bandwidth can be expressed as,
BW =1
2πRinCline
(3.12)
For the simple differential pair in Deweerth’s model centroid circuit [1], Rin is
given by (3.8). Substituting this, we get a bandwidth as given below.
BW =gm
2πCline
(3.13)
Active-input current mirror amplifier with a high gain amplifier
In order to improve the bandwidth of the above circuit, Bashyam [2] pro-
posed an active-input current mirror amplifier instead of a simple differential pair
as shown in Fig 3.7. This system was designed for a maximum current of 1nA.
This circuit consists of an active-input current mirror [33] [34] acting as a
feedback amplifier. The current from the photodiode is fed to a current mirror
which has a feedback amplifier. This current is then mirrored to a differential
pair. The pole at the node where the photodiode connected is the pole which
determines the bandwidth of the system. The circuit is analyzed using a small-
signal analysis to get the resistance at that node. The small-signal model of the
circuit is shown in Fig 3.8. From Fig 3.8,
it =vt
ro3
− gm3vgs3 (3.14)
lvgs3 = −vt(A + 1) (3.15)
39
Vbias
A
out
biasn
ph
in
Figure 3.7: Active-Input Current Mirror Amplifier.
From (3.14) and (3.15) we get,
Rin =vt
it=
ro3
1 + gm3 (1 + A) ro3
=1
Agm
(3.16)
40
Figure 3.8: Small signal model of Active-Input Current Mirror.
Using (3.12) bandwidth of the circuit proposed by Bhasyam [2] is
BW =Agm
2πCline
(3.17)
In this circuit, A times higher bandwidth than that of the simple differ-
ential pair is achieved. In order to obtain more bandwidth, Bashyam [2] used
a current mirror with a mirroring ratio of 1:5 in the design. This design faced
two major drawbacks-power consumption and stability. The current mirror with
1:5 scaling increased the power consumption. Since the currents involved were in
subthreshold range, scaling photocurrents is not a big deal and the power con-
sumption increase was low. The major problem was the stability of the current
mirror with the feedback amplifier as it affected the whole circuit’s stability. The
current mirror with the feedback amplifier is as shown in Fig 3.9. The above
figure can be redrawn as shown in Fig 3.10. There are 2 poles in the circuit, one
41
Figure 3.9: Active-Input Current Mirror.
Figure 3.10: Active-Input Current Mirror.
at the input of the feedback amplifier and another at the output. In Bashyam’s
work, the feedback amplifier was designed to be a high-gain amplifier. The circuit
shown in Fig 3.10 can be visualized as a two stage amplifier with the dominant
42
pole at the output of the feedback amplifier (1st stage) and the second pole at the
input of the feedback amplifier (2nd stage). This is evident from the resistances
at those nodes respectively as ro/2 and 1/Agm. A compensation capacitor was
needed between the output of the feedback and ground to achieve stability of the
circuit. Another approach to achieve stability is to reduce the biasing current
for the feedback amplifier to values very much lower than photocurrents. This
increased the resistance at the input of the feedback amplifier and resulted in
decreased bandwidth.
There was another problem that affected the bandwidth in the circuit.
The scale factor, K(= 5) used for the current mirror in Fig 3.7 increased the
capacitance Cgd of the transistor M4 K times higher than that of the transistor
M3, again affecting the bandwidth of the system. To lower this effect, a low voltage
cascode current mirror configuration was tried in place of a normal current mirror
in the differential pair. This too, increased stability problems.
The above discussed problems led to the present proposed design.
3.4.2 Aggregation network: Present proposed designs
In order to improve the performance of the centroid computation circuit
in terms of both bandwidth and stability with minimum offset, three different
circuits are explored in this thesis. All three designs look similar to the circuit
proposed by Bashyam [2]. The major difference between Bashyam’s design and
the designs presented in this thesis lies in the feedback amplifier. Bashyam used
a high-gain amplifier for the feedback amplifier. The proposed designs used for
feedback in this thesis are based on a voltage regulator design. A voltage regulator
design, as explained by Baker, Li and Boyce [28], is briefly discussed by comparing
it with that of a high gain amplifier in the following paragraph.
43
A voltage regulator tries to maintain a regulated voltage output which is
free of fluctuations even if there are variations in the input power supply voltage
due to temperature or any other factor. Design of any operational amplifier (op-
amp) used as voltage regulator is different from that of an op-amp, which is
used in high-gain applications. A normal high-gain op-amp is designed to have a
dominant pole (low-frequency pole) at the node where the output of first stage is
connected to the input of the second stage and the bandwidth is determined by
the pole (high-frequency pole) at the output node. An op-amp used in a voltage
regulator is designed to have a dominant pole (low-frequency pole) at the output
of the second stage, instead of the first stage. The first stage in a normal op-amp
is usually a high-gain stage, but in a voltage regulator the first stage is a low-gain
stage and the second stage is high gain. These differences are illustrated in the
Fig 3.11. The common source transistor used as a second stage is altered to have
longer length (L) in order to have low peaking. This may decrease the overall
gain, but gain is not as important a criteria in the design of a voltage regulator.
In these designs, the feedback amplifier is the first stage of the voltage
regulator and the transistor of the mirror connected to the photodiodes forms the
second stage. The photodiodes’ bus-line is connected to the current mirror with
the feedback amplifier. The photocurrent from the bus-line is then mirrored into
a linearized differential pair. This configuration looks similar to that of the circuit
proposed by Bashyam [2]. This is as shown in Fig 3.12. The above figure can be
redrawn as shown in Fig 3.13.
Bandwidth is not adversely effected by the capacitance of the photodiodes
as this capacitance contributes to the pole at the input of the feedback amplifier,
which is the dominant pole (low-frequency pole).
44
RL
CC RC
CL
Vi +Vi -
CL
Vi +Vi -
Dominant, Low Frequency and High
Gain Pole
High Frequency and Low gain Pole
High Frequency and Low gain Pole
Dominant, Low Frequency and High Gain Pole
longer
shorter
shorter
longer
RL
Figure 3.11: Illustration of the differences in the designs of a normal high gainop-amp and a voltage regulator op-amp.
There are three circuits that are designed and compared in the following
subsections.
45
Figure 3.12: Configuration of a Current Mirror with voltage regulator.
Figure 3.13: Configuration of a Current Mirror with voltage regulator.
46
2-Stage CMOS voltage regulator
A 2-stage CMOS voltage regulator including the current mirror is shown
in Fig 3.14.
Cph
Vref Vreg
Iph
M1 M2 M3M4 M5
M7 M6
M8
Ibias
Iph/2 Iph/2
Vo
Figure 3.14: 2-Stage CMOS voltage regulator.
This circuit consists of a simple 5 transistor differential amplifier in the
first stage and a one transistor common source amplifier as the second stage. The
sizes of all transistors in the first stage are designed to have W/L = 9µm/0.9µm
with a multiplier of 2. The second stage transistor (M1) is designed to have
W/L = 4.5µm/2.4µm with a multiplier of 2. The other two transistors (M2 and
M3), which provide current to the two branches of the linearized differential pair
47
are designed to have W/L = 4.5µm/2.4µm with a multiplier of 1. The sizes of the
transistors are designed to get the optimum performance with a tradeoff between
bandwidth and stability of the circuit.
AC analysis AC analysis is done in order to determine the stability and band-
width of an opamp. In the stability analysis, gain and phase are plotted as func-
tions of frequency. There are two measures of stability, gain margin and phase
margin [35]. The difference between unity gain (0 dB) and the gain at the fre-
quency where the phase angle is 180 is called the gain margin. Units of gain
margin are decibels (dB). It is the measure of the amount by which the loop gain
can be increased without destabilizing the system. The difference between the
phase angle at the unity gain frequency and −180 is called the phase margin.
This represents the amount by which the loop phase can be decreased without
destabilizing the system. The equations of both are given as following.
GainMargin = (0− |Aβ|)dB (3.18)
PhaseMargin = θ0dB − (−180 ) = 180 + θ0dB (3.19)
Gain margin is not a big concern in amplifier design, involving subthreshold cur-
rents as gain margin tends to be large. Phase margin is a measure of stability and
hence it is an important measure that needs some attention. For two-stage (two-
pole) amplifiers and single-stage (one-pole) amplifiers to be stable, phase margins
of at least 45 and 80 are needed, respectively, for both types of amplifiers. Band
width is another aspect which is given attention, as it determines the speed of the
whole circuit.
48
AC analysis is done for the 2-stage CMOS voltage regulator, including the
current mirror shown in Fig 3.14. It needs a load. AC Analysis is done using
a load which is a linearized differential pair along with a current mirror to be
discussed in Sections 3.4.3 and 3.4.4. These are the actual loads of the circuit.
The circuit along with the load is as shown in Fig 3.15. This circuit has three
nodes of interest, Vbi , Vox and Vo, as indicated in Fig 3.15.
Cph
Vref Vreg
Iph
M1 M2 M3M4 M5
M7 M6
M8
Ibias
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn
Vbi
Vo
Vox
Figure 3.15: 2-Stage CMOS voltage regulator along with the load which is alinearized differential pair and a current mirror.
49
Open-loop analysis Open-loop analysis is done mainly to determine
the stability of an amplifier. Open-loop analysis with an AC current source is
done as shown in the Fig 3.16. The open-loop frequency response for a typical
photo current, iph = 20nA is shown in Fig 3.17 From Fig 3.17, it is observed that
4 pFIph-sin
M1 M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn
1F
10P Ω
+
100f F
Vsin Vreg
Vo
Vbi
Vox
Figure 3.16: Setup for open-loop analysis of 2-Stage CMOS voltage regulator withan AC current source for photocurrent.
the DC gain is 82.62dB and the phase margin is 83.18 . The DC gain and the
phase margin are observed to be good for 20nA of photocurrent.
50
Figure 3.17: Open-loop AC response of 2-Stage CMOS voltage regulator withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) and ibiasnd = 1µA(for the current mirror) for an AC current source of iph = 20nA.
Closed-loop analysis Closed-loop analysis is done in a voltage follower
configuration. Closed-loop analysis is done mainly to determine the bandwidth of
an amplifier. Stability can also be observed by means of peaking. The lower the
peaking, the more is the stability. Closed-loop analysis with an AC current source
is done as shown in Fig 3.18. The closed-loop frequency response for a typical
photo current, iph = 20nA at the node where the photodiode is attached (Vo) is
shown in Fig 3.19 From Fig 3.19, it is observed that the bandwidth is 609.2kHz
and peaking is 0dB for 20nA of photocurrent.
51
4p FIph-sin
M1 M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn 100f F
Vreg
Vo
Vbi
Vox
Figure 3.18: Setup for closed-loop analysis of 2-Stage CMOS voltage regulatorwith an AC current source for photocurrent.
Cascoded common-source amplifier with a source follower
A cascoded common-source amplifier with a source follower is like a current
conveyer-circuit. This circuit is not used in the configuration as shown in Figs 3.12
and 3.13. A cascoded common-source amplifier with a source follower, including
the current mirror is shown in Fig 3.20. The transistor level schematic of the
above figure is shown in Fig 3.21.
The first stage consists of a common source amplifier with input Vreg (which
will connect to the photodiodes’ bus line) including a cascoding stage and a biasing
52
Figure 3.19: Closed-loop AC response of 2-Stage CMOS voltage regulator withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) and ibiasnd = 1µA(for the current mirror) for an AC current source of iph = 20nA.
stage. All these transistors are designed to have W/L = 9µm/0.9µm with multi-
plier of 2. To have negative feedback, the second stage is simply a source follower
with size W/L = 9µm/0.9µm. There is a PMOS current mirror, mirroring current
into two branches of a linearized differential pair. The transistor (M1) to which
the source follower is providing current is designed to have W/L = 4.5µm/2.4µm
with a multiplier of 2. The other two transistors (M2 and M3) which provide
current to the two branches of the linearized differential pair are designed to have
W/L = 4.5µm/2.4µm with a multiplier of 1.
53
Figure 3.20: Cascoded common-source amplifier with a source follower.
AC analysis AC analysis is done for the cascoded common-source amplifier
with source follower, including the current mirror, as shown in the Fig 3.21. AC
analysis is done using a load which is a linearized differential pair along with a
current mirror to be discussed in Sections 3.4.3 and 3.4.4. These are the actual
loads of the circuit. The circuit, along with the load, is shown in Fig 3.22. This
circuit has three nodes of interest, Vbi , Vox and Vo, as indicated in Fig 3.22.
Open-loop analysis Open-loop analysis is done mainly to determine
the stability of an amplifier. Open-loop analysis with an AC current source is
done as shown in Fig 3.23. The open-loop frequency response for a typical photo
current, iph = 20nA is shown in Fig 3.24 From Fig 3.24, it is observed that the
DC gain is 27.67dB and the phase margin is 92.58 . The value of the DC gain is
not a good sign, even though the phase margin is observed to be good for 20nA
of photocurrent.
54
CphVreg Iph
M1 M2 M3M4 M5
M6M7
IbiasnIph/2 Iph/2
M8
M9Ibiasp
Vo
Figure 3.21: Cascoded common-source amplifier with a source follower.
Closed-loop analysis Closed-loop analysis with an AC current source
is done as shown in Fig 3.25. The closed-loop frequency response for a typical
photo current, iph = 20nA at the node where the photodiode is attached (Vo) is
shown in Fig 3.26 From Fig 3.26, it is observed that the bandwidth is 562.7kHz
and the peaking is 0dB for 20nA of photocurrent. The bandwidth of this circuit
is observed to be less than that of a 2-stage CMOS voltage regulator.
Common-source amplifier with output mirror
A common-source amplifier with output mirror is like a single-ended cur-
rent source. This circuit is used with a modification in the configuration as shown
55
M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
VbiasnCph
Vreg Iph
M1M4 M5
M6M7
Ibiasn
M8
M9Ibiasp
Vo
Vox
Vbi
Figure 3.22: Cascoded common-source amplifier with a source follower along withthe load which is a linearized differential pair along with a current mirror.
in Figs 3.12 and 3.13. The change is only at the input. It has only one input, which
is connected to the photodiodes’ bus-line. A common source amplifier with out-
put mirror, including the current mirror of the photocurrents is shown in Fig 3.27.
The transistor level schematic of the above figure is shown in Fig 3.28.
The first stage consists of a common-source amplifier with input Vreg in-
cluding a mirror and a biasing stage. All these are designed to have W/L =
9µm/0.9µm with multiplier of 2. The second stage transistor (M1) is designed to
have W/L = 4.5µm/2.4µm with a multiplier of 2. The other two transistors (M2
56
Iph-sin
M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn
1F
10P Ω+
100f F
Vsin
Vreg
M1
M9
4p F
Vbi
Vo
Vox
Figure 3.23: Setup for open-loop analysis of cascoded common-source amplifierwith a source follower with an AC current source for photocurrent.
and M3) which provide current to the two branches of the linearized differential
pair are designed to have W/L = 4.5µm/2.4µm with a multiplier of 1. The sizes
are carefully designed to get optimum performance with a good trade off between
bandwidth and stability.
AC analysis AC analysis is done for the common-source amplifier with output
mirror in Fig 3.28. AC analysis is done using a load which is a linearized differential
pair along with a current mirror to be discussed in Sections 3.4.3 and 3.4.4. The
57
Figure 3.24: Open-loop AC response of cascoded common-source amplifier withsource follower and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for theamplifier) and ibiasnd = 1µA (for the current mirror) for an AC current sourceof iph = 20nA.
circuit, along with the load, is shown in Fig 3.29. This circuit has three nodes of
interest, Vbi , Vox and Vo, as indicated in Fig 3.29.
Open-loop analysis Open-loop analysis is done mainly to determine
the stability of an amplifier. Open-loop analysis with an AC current source is
done as shown in Fig 3.30. The open-loop frequency response for a typical photo
current, iph = 20nA, is shown in Fig 3.31 From Fig 3.31, it is observed that the
DC gain is 78.15dB and the phase margin is 87.41 . The DC gain and the phase
margin are observed to be good for 20nA of photocurrent.
58
Iph-sin
M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn 100f F
Vreg
M1
M9
4p F
Vbi
Vo
Vox
Figure 3.25: Setup for closed-loop analysis of cascoded common-source amplifierwith a source follower with an AC current source for photocurrent.
Closed-loop analysis Closed-loop analysis with an AC current source
is done as shown in Fig 3.32. The closed-loop frequency response for a typical
photo current, iph = 20nA at the node where the photodiode is attached (Vo) is
shown in Fig 3.33 From Fig 3.33, it is observed that the bandwidth is 343kHz
and the peaking is 0dB for 20nA of photocurrent. The bandwidth of this circuit
is observed to be good for 20nA of photocurrent.
59
Figure 3.26: closed-loop AC response of cascoded common-source amplifier withsource follower and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for theamplifier) and ibiasnd = 1µA (for the current mirror) for an AC current sourceof iph = 20nA.
Figure 3.27: Common-source amplifier with output mirror.
60
CphIph
M1 M2 M3M4 M5
M6M7
IbiasnIph/2 Iph/2
M8Vreg
Vo
Vbi
Figure 3.28: Common-source amplifier with output mirror.
3.4.3 Linearized Differential Pair
The current mirror with the feedback amplifier mirrors the current to an-
other circuit to generate two output currents. This is nothing but a differential
pair. The differential pair is designed with PMOS transistors as the current is be-
ing mirrored through PMOS transistors. The currents involved here are very low
which makes the transistors operate in subthreshold. As discussed is Section 2.5,
61
M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
VbiasnCphIph
M1M4 M5
M6M7
Ibiasn
M8Vreg
Vo
Vox
Vbi
Figure 3.29: Common-source amplifier with output mirror along with the loadwhich is a linearized differential pair along with a current mirror.
the current in an NMOS transistor operating in the subthreshold region is given
by (2.22) and is repeated below.
iD = IoW
Le
κvGBVT
(e
vSBVT − e
vDBVT
)(3.20)
where
Io is the zero bias current
κ is the subthreshold slope coefficient [29]
62
Iph-sin
M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn
1F
10P Ω+
100f F
Vsin
Vreg
M1
4p F
Vbi
Vo
Vox
Figure 3.30: Setup for open-loop analysis of common-source amplifier with outputmirror with an AC current source for photocurrent.
A similar equation can be written for a PMOS transistor.
In the subthreshold region, transistors have a translinear relationship be-
tween the gate-to-source voltage and the drain current. This leads to a nonlinear
relationship between the applied differential voltage and the differential output
current in a simple differential pair, such as the one shown in Fig 3.34. The rela-
tionship between the differential input voltage (Vdiff ) and the differential output
63
Figure 3.31: Open-loop AC response of common-source amplifier with outputmirror and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) andibiasnd = 1µA (for the current mirror) for an AC current source of iph = 20nA.
current (Idiff ) is given below [36].
Idiff = Ib tanh
(κVdiff
2VT
)(3.21)
where
Ib is the biasing current which is the mirrored photocurrent in this
centroid computation circuit
VT is the thermal voltage
64
Iph-sin
M2 M3
Iph/2 Iph/2
Vi -
Vi -Vi +Vi +
Vout
Vbiasn 100f F
Vreg
M1
4p F
Vo
Vox
Vbi
Figure 3.32: Setup for open-loop analysis of common-source amplifier with outputmirror with an AC current source for photocurrent.
The Transconductance, G of the differential pair is given by [36],
G =∂Idiff
∂Vdiff
(3.22)
The Normalized transconductance is given by [36],
Gnorm =G
Gmax
(3.23)
Where Gmax is the maximum transconductance
65
Figure 3.33: Open-loop AC response of common-source amplifier with outputmirror and with Vdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) andibiasnd = 1µA (for the current mirror) for an AC current source of iph = 20nA.
The largest deviation of Gnorm from unity is defined as distortion. The
range of values of Vdiff over which this distortion remains constant is said to be
linear range. The simple differential pair has a small linear range [36]. In order to
have a higher linear range for the differential pair, a differential pair with source
degeneration via symmetric diffusers, as designed by Furth and Andreou [36] is
used. This circuit is shown in Fig 3.35.
The linearized differential pair shown in Fig 3.35 consists of two transistors
forming the differential pair and two more transistors to provide source degener-
ation via symmetric diffusers. The relationship between the differential input
voltage (Vdiff ) and the differential output current (Idiff ) for this circuit is given
66
Figure 3.34: A Simple Differential Pair.
Figure 3.35: A Differential Pair With Source Degeneration Via Symmetric Diffu-sion.
below [36].
Idiff = Ib tanh
(κVdiff
2VT
− tanh−1
[1
4m + 1tanh
(κVdiff
2VT
)])(3.24)
67
where
m is the relative ratio of W/Ls of the transistor pairs.
Ib is the biasing current which is the mirrored photocurrent in this
centroid computation circuit
VT is the thermal voltage
The linearized differential pair used in this thesis is shown in Fig 3.36. It
is designed with m = 0.5, that is, the differential pair transistors have size that is
double that of the diffusion transistors. A value of m = 0.5 is used as G will have
maximum value at m = 0.5. The diffusion transistors have W/L = 4.5µm/2.4µm.
The differential pair transistors are designed to have W/L = 4.5µm/2.4µm with
a multiplier of 2.
Figure 3.36: Design of Linearized Differential Pair With Source Degeneration ViaSymmetric Diffusion.
68
3.4.4 Current Subtractor
A current subtractor is used to subtract the two aggregated output cur-
rents. A current mirror is used as a current subtractor to generate the output
differential aggregated current. This subtracted current integrates on the output
node of the current mirror till this current is zero. As such, an output voltage
is generated which indicates the centroid, as discussed in Section 2.3.4. A low-
voltage cascode current mirror is selected as a current subtractor. This mirror
is chosen in order to minimize the channel-length modulation effect and also to
achieve low-voltage operation ??. This circuit is designed as shown in Fig 3.37.
Figure 3.37: Low Voltage Cascode Current Mirror.
69
The mirroring transistors (M3 and M4) are designed to have W/L =
4.5µm/2.4µm with multiplier of 4. The cascoding transistors (M1 and M2) have
W/L = 4.5µm/1.2µm with multiplier of 4. The biasing transistor (M5), which
gives the biasing voltage is designed to have W/L = 4.5µm/6µm with multiplier
of 2.
3.4.5 AC analysis over different current ranges
Previously, AC analysis was done for each proposed circuit for a photocur-
rent of 20nA. Only the 2-stage CMOS voltage regulator and the common-source
amplifier with output mirror are observed to be stable with good DC gain and
bandwidth of operation. The cascoded common-source amplifier with a source
follower showed a sign of risk in terms of stability with little peaking even for a
small photocurrent of 20nA. It also has very low bandwidth when compared to
that of the other two circuits.
The cascoded common-source amplifier with a source follower can be dropped
without further evaluation. The 2-stage CMOS voltage regulator and common-
source amplifier with output mirror need to be investigated further for stability
and bandwidth for a wide range of photocurrents. Nevertheless, all three circuits
are investigated. The AC analysis is done for the three circuits in both open-
loop and closed-loop configurations. They are repeated for a minimum current
of 20pA and a maximum photocurrent of 2µA. Closed-loop analysis is done to
observe bandwidth and peaking at three different nodes, Vbi , Vox and Vo, as in-
dicated in Fig 3.15. Although the figure mentioned is of 2-stage CMOS voltage
regulator, the three nodes, Vbi , Vox and Vo, exist in the other circuits in the iden-
tical positions: at the photodiode, at the output of the first stage of the feedback
amplifier and at the diode connected node of the current mirror inside OTA. The
70
frequency response for the three circuits are summarized in Tables 3.1, 3.2, 3.3
and 3.4. Here
Circuit 1 is The 2-Stage CMOS voltage regulator
Circuit 2 is The cascoded common-source amplifier with a source follower
Circuit 3 is The common-source amplifier with output mirror
Proposed Circuit 20pA photocurrent 2µA photocurrentDC gain(dB) Phase Margin DC gain(dB) Phase Margin
Circuit 1 77.09 88.86 77.89 18.66
Circuit 2 31.09 94.779 −50.78 —Circuit 3 72.22 89.36 73.22 34.03
Table 3.1: Open-loop analysis of all three proposed circuits at 20pA and 2µA ofphotocurrents
Proposed Circuit 20pA photocurrent 2µA photocurrentBandwidth Peaking(dB) Bandwidth Peaking(dB)
Circuit 1 562.7Hz 1.365n 38.73MHz 18.59Circuit 2 833.8Hz 634.6p 745.8kHz 0Circuit 3 327.3Hz 4.036n 27.23MHz 9.114
Table 3.2: Closed-loop analysis at node Vo of all three proposed circuits at 20pAand 2µA of photocurrents
Proposed Circuit 20pA photocurrent 2µA photocurrentBandwidth Peaking(dB) Bandwidth Peaking(dB)
Circuit 1 562.7Hz 1.365n 15.54MHz 10.08Circuit 2 578.7Hz 1.033n 745.8kHz 0Circuit 3 327.3Hz 4.036n 16.22MHz 4.636
Table 3.3: Closed-loop analysis at node Vbi of all three proposed circuits at 20pAand 2µA of photocurrents
71
Proposed Circuit 20pA photocurrent 2µA photocurrentBandwidth Peaking(dB) Bandwidth Peaking(dB)
Circuit 1 211.9Hz 747.8m 2.719MHz 1.015Circuit 2 258.2Hz 554.1 750.9kHz 0Circuit 3 222.7Hz 302m 12.99MHz 1.22
Table 3.4: Closed-loop analysis at node Vox of all three proposed circuits at 20pAand 2µA of photocurrents
Proposed Circuit 20pA photocurrent 2µA photocurrentBandwidth Peaking(dB) Bandwidth Peaking(dB)
Circuit 1 211.9Hz 747.8m 2.719MHz 1.015Circuit 2 258.2Hz 554.1 750.9kHz 0Circuit 3 222.7Hz 302m 12.99MHz 1.22Simple Current Mirror 17.35Hz 1.448µ 38.63kHz 2.834
Table 3.5: Closed-loop analysis at node Vox of all three proposed circuits alongwith the simple current mirror at 20pA and 2µA of photocurrents
From the AC analysis of all three proposed circuits, circuit 3, a common-
source amplifier with output mirror is observed to be more stable with good
bandwidth over a wide range of photocurrents (20pA to 2µA).
3.4.6 Comparison with a simple current mirror
Bandwidth of the proposed circuits at node Vox are compared to that of a
simple current mirror without any feedback amplifiers. The current mirror used
has three PMOS transistors and is identical to the current mirrors used in the
above discussed proposed circuits. The current mirror is as shown in Fig 3.38.
Transistor M1 is designed to have W/L = 4.5µm/2.4µm with multiplier of 2.
Transistors M2 and M3 are designed to have W/L = 4.5µm/2.4µm with multiplier
of 1.
Closed-loop analysis of the simple mirror at node Vox is done as shown
in Fig 3.39. This is done at photocurrents of 20pA and 2µA. The frequency
responses are shown in Figs 3.40 and 3.41. The bandwidth comparison is shown
in Table 3.5.
72
ph ph
i
iii
out
biasn
phph
o
ox
bi
Figure 3.38: Simple current mirror, that mirrors the current equally in twobranches.
A bandwidth comparison of all three proposed circuits along with the sim-
ple current mirror indicates that there is a great improvement in the bandwidth
and stability over a wide range of photocurrents (20pA to 2µA) for a common-
73
ph-sin
ph ph
i
iii
out
biasn
bi
ox
o
Figure 3.39: Setup for closed-loop analysis of a simple current mirror with an ACcurrent source for photocurrent.
source amplifier with output mirror. Hence, this circuit is selected for the centroid
computation circuit.
74
Figure 3.40: Open-loop AC response of simple current mirror at node Vox withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) and ibiasnd = 1µA(for the current mirror) for an AC current source of iph = 20pA.
3.5 Series Resistor Network
A series resistor network, which is a voltage divider, is used for position
encoding of the aggregation network and also in the flash converter. The net-
work consists of 80 1kΩ resistors in series. Alternate nodes are used for position
encoding, making it like a voltage divider network with a 2kΩ resistor between
each node. There are 40 nodes that are tapped for position encoding. The nodes
left between the nodes used for position encoding are used as reference nodes for
the flash converter. These nodes total to 39. The two ends are connected to two
external reference voltages. This resistive network scheme is shared between the
centroid computation circuit and the flash converter as shown in Fig 3.42.
75
Figure 3.41: closed-loop AC response of simple current mirror at node Vox withVdd = 0.9 V , Vss = −0.9 V , ibias = 22µA (for the amplifier) and ibiasnd = 1µA(for the current mirror) for an AC current source of iph = 2µA.
3.6 Flash Analog-to-Digital Converter
The analog voltage output from the centroid computation circuit is con-
verted into digital form by a flash converter. The flash converter used has two
major blocks, a comparator block and thermometer-to-binary converter block.
The comparator block consists of 39 comparators. The thermometer-to-binary
converter is a digital circuit which takes thermometer code as input and gives
binary code as output.
3.6.1 Clocked Comparators
The comparators used in the flash converter are clocked comparators. The
design of this circuit is based on the clocked comparator that has been discussed
76
Figure 3.42: Voltage divider network scheme.
in Section 2.7. It has two inputs. One of the input is the analog voltage output
from the analog centroid computation circuit and the other is an intermediate
reference voltage from the resistive network discussed in Section 3.5. The clocked
comparator is designed as shown in Fig 3.43. The circuit shown in Fig 3.43 is
similar to the one which is already discussed in Section 2.7. The only difference
is the addition of two current mirrors (one mirror is NMOS transistors and the
other is PMOS transistors) for each branch of the input differential pair. This is
done in order to isolate switching noise that was being coupled to the inputs.
This circuit has three major blocks: the input stage, the decision stage and
the S-R latch.
The input stage is designed to consist of a PMOS differential pair with tran-
sistors (P3, P4) of size W/L = 5.4µm/1.2µm with multiplier 2, a biasing current
mirror made of PMOS transistors (P1, P2) with sizes W/L = 5.4µm/1.2µm with
multiplier 2 and W/L = 5.4µm/1.2µm with multiplier 4 respectively, four cur-
77
Filp-flop stage S-R Latch
M4 M5
M12
M8 M9
M10 M6 M7 M11
φ2
Q
Qbar
Node c
Node d
φ1
Input differential pair stage
1 : 2
Vi +
Ib
P1 P2
P3 P4Vi -
Node c Node d
Figure 3.43: Design Of The Clock Comparator.
rent mirrors, two made of NMOS transistors and the other two made of PMOS
transistors all with sizes W/L = 5.4µm/1.2µm with multiplier 2.
The decision stage has a two parts, one with NMOS transistors (M4,
M5) of size W/L = 5.4µm/1.2µm with multiplier 4 and the other with PMOS
78
transistors (M6, M7) of size W/L = 5.4µm/1.2µm with multiplier 2. It also
has two PMOS transistors (M10, M11) of size W/L = 5.4µm/0.6µm for pre-
charging the PMOS part, an NMOS switch (M12) of size W/L = 10.95µm/0.6µm
with multiplier 1 for resetting and two NMOS transistors (M8, M9) of size
W/L = 5.4µm/0.6µm. The NMOS switch is used for isolating the PMOS part
from that of the NMOS part, as discussed in Section 2.7. There are two non-
overlapping clocks φ1 and φ2 used in this decision stage, generated from a non-
overlapping clock generator.
The S-R latch consists of two NAND gates connected as shown in the
Fig 3.43. It has two PMOS transistors and two NMOS transistors, all designed
to have W/L = 5.4µm/0.6µm.
Simulation of the Clocked Comparator
The offset for the clocked comparator is estimated with a very slow tran-
sient analysis as shown in Fig 3.44. The negative input, vi−, is maintained con-
stant at Vss + 0.6 V . The positive input, vi+, is a triangular waveform sweeping
from Vss + 0.6− .001 V to Vss + 0.6 + .001 V . Transient analysis is done at a low
clock frequency (10Hz). There is a change in the output from low in first clock
cycle to high in the second clock cycle, as shown in Fig 3.45. Offset is measured
as the difference between the input voltage levels in the first and second response.
The systematic offset is measured to be around 41.5 nV , which is very very low
indeed.
The transient analysis for the clocked comparator for a normal comparison
function is done as shown in Fig 3.46. The positive input, vi+, is maintained
constant at Vss + 0.6 V . The negative input, vi−, is a square waveform whose
voltage ranges from Vss +0.6− .15 V to Vss +0.6+ .01 V in one analysis and from
Vss +0.6+ .15 V to Vss +0.6− .01 V in other analysis. These two analysis are done
79
Figure 3.44: Setup for measuring offset of the clocked comparator.
in order to observe the function of the clocked comparator in both directions. The
clocked comparator is observed to work good up to a frequency of 10MHz in both
direction. The transient responses are shown in Figs 3.47 and 3.48.
Non-Overlapping Clock Generator
A non-overlapping clock generator generates the required non-overlapping
clocks, φ1 and φ2. The schematic of the non-overlapping clock generator is shown
in Fig 3.49. As shown in Fig 3.49, the outputs, φ1 and φ2 are generated from
a single clock, φin. The number of inverters used after the NAND gates in the
two branches are not equal. This is done to have different duty cycles for φ1 and
φ2. There are two extra inverters for φ1 before the NAND gate and after the
transmission gate. These are used to have some delay in the path of φ1. These
two techniques are used to achieve an optimum selection of reset and regeneration
times for the clock comparator. The buffers used to drive outputs, φ1 and φ2 are
designed to be of sizes 3, 9, 27, 81 times, successively. These are designed in a
way that they can drive the large capacitance offered by 39 comparators. All this
80
Figure 3.45: Transient responses of the clocked comparator with Vdd = 0.9 V ,Vss = −0.9 V , ibiasp = 10µA and input clock (clkin)= 10Hz.
81
Figure 3.46: Setup for transient response of the clocked comparator.
Figure 3.47: Transient response of the clocked comparator with Vdd = 0.9 V ,Vss = −0.9 V , ibiasp = 10µA, positive input vi+ = Vss + 0.6 V and negativeinput voltage (vi−) as a pulse waveform of 10MHz varying from vi+ (−150 mV )to vi+ (+10 mV ).
82
Figure 3.48: Transient response of the clocked comparator with Vdd = 0.9 V ,Vss = −0.9 V , ibiasp = 10µA, positive input vi+ = Vss + 0.6 V and negativeinput voltage (vi−) as a pulse waveform of 10MHz varying from vi+ (+150 mV )to vi+ (−10 mV ).
Figure 3.49: Non-Overlapping Clock Generator Schematic.
circuitry involves digital circuit design and the sizes of the transistors are designed
as described below. The transient response is shown in Fig 3.50.
Transmission gate. The transmission gate used is a standard transmission gate.
This is maintained always in the ON state. The PMOS in this transmission
83
gate is designed to have W/L = 3µm/0.6µ and NMOS is of size W/L =
1.5µm/0.6µ.
2-input NAND gate. The NAND gate used is a standard 2-input NAND gate.
The PMOS transistors are designed to have W/L = 3µm/0.6µ and the two
NMOS transistors are of size W/L = 1.5µm/0.6µ.
Inverter 1x. The PMOS in this inverter is designed to have W/L = 3µm/0.6µ
and NMOS is of size W/L = 1.5µm/0.6µ.
Inverter 3x. This inverter circuit has transistors which are 3 times bigger than
that of inverter 1x. The PMOS in this inverter is designed to have W/L =
3µm/0.6µ with multiplier of 3 and NMOS is of size W/L = 1.5µm/0.6µ
with multiplier of 3. The design of the 9x, 27x and 81x inverters are similar.
There are a total 39 clocked comparators. They collectively result in a 39-
bit output thermometer code. This thermometer code is given to a code converter
to get 6-bit digital output in binary code.
3.6.2 Thermometer-to-Binary code Converter
The 39-bit thermometer code (a1, a2, . . . , a39) from the comparator block is
first converted into a 39-bit priority code (e1, e2, . . . , e3) using an array of thirty-
nine 2-input XOR gates. This priority code is then converted into a 6-bit binary
code (b1, b2, . . . , b6) with the help of six OR gates. There are three 20-input OR
gates, two 16-input OR gates and one 8-input OR gate. By way of example, a 7-
bit thermometer code with its corresponding 7-bit priority and 3-bit binary codes
is given in Table 3.6.
Similarly, a 6-bit binary and a 39-bit priority code can be written for 39-bit
thermometer code by simply extending the number of bits required as shown in
Table 3.7.
84
Figure 3.50: Transient response of non-overlapping clock generator with Vdd =0.9 V , Vss = −0.9 V and input clock(clkin)= 10MHz.
Thermometer Code Priority Code Binary Code Decimal Valuea7a6a5a4a3a2a1 e7e6e5e4e3e2e1 b3b2b1 Decimal equivalent0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 10 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 20 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 30 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 40 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 50 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 0 61 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 7
Table 3.6: Table of Thermometer code with its equivalent in Priority and Binarycodes
The OR gates resulting in binary output can be expressed as:
b1 = e1 ⊕ e3 ⊕ e5 ⊕ e7 ⊕ e9 ⊕ e11 ⊕ e13 ⊕ e15 ⊕ e17 ⊕ e19 ⊕ e21 ⊕ e23 ⊕ e25 ⊕ e27 ⊕
e29 ⊕ e31 ⊕ e33 ⊕ e35 ⊕ e37 ⊕ e39
85
Thermometer Code Priority Code Binary Code Decimal Valuea39a38 . . . a2a1 e39e38 . . . e2e1 b6b5b4b3b2b1 Decimal equivalent
0 0 . . . 0 0 0 0 . . . 0 0 0 0 0 0 0 0 00 0 . . . 0 1 0 0 . . . 0 1 0 0 0 0 0 1 10 0 . . . 1 1 0 0 . . . 1 0 0 0 0 0 1 0 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 1 . . . 1 1 0 1 . . . 0 0 1 0 0 1 1 0 381 1 . . . 1 1 1 0 . . . 0 0 1 0 0 1 1 1 39
Table 3.7: Table of Thermometer code with its equivalent in Priority and Binarycodes
b2 = e2 ⊕ e3 ⊕ e6 ⊕ e7 ⊕ e10 ⊕ e11 ⊕ e14 ⊕ e15 ⊕ e18 ⊕ e19 ⊕ e22 ⊕ e23 ⊕ e26 ⊕ e27 ⊕
e30 ⊕ e31 ⊕ e34 ⊕ e35 ⊕ e38 ⊕ e39
b3 = e4 ⊕ e5 ⊕ e6 ⊕ e7 ⊕ e12 ⊕ e13 ⊕ e14 ⊕ e15 ⊕ e20 ⊕ e21 ⊕ e22 ⊕ e23 ⊕ e28 ⊕ e29 ⊕
e30 ⊕ e31 ⊕ e36 ⊕ e37 ⊕ e38 ⊕ e39
b4 = e8⊕e9⊕e10⊕e11⊕e12⊕e13⊕e14⊕e15⊕e24⊕e25⊕e26⊕e27⊕e28⊕e29⊕e30⊕e31
b5 = e16⊕e17⊕e18⊕e19⊕e20⊕e21⊕e22⊕e23⊕e24⊕e25⊕e26⊕e27⊕e28⊕e29⊕e30⊕e31
b6 = e32 ⊕ e33 ⊕ e34 ⊕ e35 ⊕ e36 ⊕ e37 ⊕ e38 ⊕ e39
XOR gate
The exclusive OR gate used is designed to be a six transistor XOR gate [37].
The transistor level schematic of this XOR gate is shown in Fig 3.51. All transis-
tors are designed to have W/L = 5.4µm/1.2µ.
The transient analysis for the XOR gate is done with a 5f F capacitive
load. The transient response is shown in Fig 3.52
OR gates
An N -input OR gate used is designed to be a pseudo NMOS OR gate [28].
This OR gate has a an advantage in terms of the area it occupies over the standard
N -input OR gate. Parasitic delays and subthreshold leakage problems are low in
86
Figure 3.51: Transistor level schematic of clever XOR gate.
Figure 3.52: Transient response of clever XOR gate with Vdd = 0.9 V , Vss =−0.9 V .
87
this scheme. The transistor level schematic of the N -input OR gate is shown in
Fig 3.53. The OR gate shown in Fig 3.53 has a pseudo NMOS NOR gate and an
Figure 3.53: Transistor level schematic of N -input OR gate.
inverter. The pull up PMOS transistor is designed to have W/L = 1.5µm/1.2µm.
The inverter which negates the output from the NOR gate is designed to have
a PMOS transistor of size, W/L = 1.5µm/0.6µm with multiplier of 1 and a
NMOS transistor of size, W/L = 1.5µm/0.6µm with multiplier of 4. All other
input NMOS transistors in the pseudo NMOS NOR gate are designed to have
W/L = 1.5µm/0.6µm.
3.6.3 Simulation of the flash converter
The transient analysis for the flash converter is described. Voltages Vss +
0.9 V and Vss + 0.3 V are applied at the ends of the 80 series resistor network.
Forty nodes are tapped, such that 15 mV is maintained in between the nodes.
These nodes form the reference voltages to the clocked comparators. Each clocked
comparator has a 10µA bias current. So, the total current is 390µA. Voltages
Vdd = 0.9 V and Vss = −0.9 V are applied as power supplies to the circuit. A
voltage Vss + 0.3 + Vin V is applied as the input reference voltage which needs to
88
be converted into digital form. The transient response for Vin = 50 mV is shown
in Fig 3.54. Vin = 50 mV should result in a digital output representing decimal 3,
that is in binary, 000011. The transient response shown in Fig 3.54 is according
to the expected result.
Figure 3.54: Transient response of the flash converter with Vdd = 0.9 V , Vss =−0.9 V and Vin = 50 mV for a clock frequency of 100kHz.
3.7 Simulation of the Centroid Computation Circuit along with the
flash converter
Photodiodes cannot be used directly in simulation. Therefore, a model of
the photodiode as discussed in Section 2.4.2 is used for simulation purposes. It has
a current source and a capacitor in parallel as shown in Fig 2.8. A capacitance
of 4pF is used to represent the total capacitance due to 20 pixels in a row or
column, as shown in (3.2). The current sources, representing the photocurrents,
89
are manipulated in such a way that they appear to have a gradually moving light
spot. Initially, the spot is incident on the first pixel. It then moves to the next
and the next and so on till the last one is reached. All this current manipulation
is done by triangular waveform currents as shown in Fig 3.55. Each photo current
(triangular waveform current) is varied from dark current (ioff ) of 100pA to a
maximum photocurrent (iph) of 1µA.
Figure 3.55: Photocurrents arrangement to simulate a gradual moving light inci-dent on a one dimensional pixel array.
The transient response of the centroid computation circuit along with the
flash converter is shown in Fig 3.56. A power supply of Vdd = 0.9 V and Vss =
−0.9 V is used in the transient analysis. A total bias current of 1.5mA is used to
bias 40 feedback amplifiers, each using a bias current of 37.5µA. A bias current
of 1µA is given to the current subtractor. A total bias current of 390µA is used
to bias 39 clocked comparators, each using a bias current of 10µA. Voltages
Vss +0.9 V and Vss +0.3 V are applied at the ends of the resistor divider network.
ns
The transient response of the analog centroid computation circuit without
the flash converter is as shown in Fig 3.57.
90
Figure 3.56: Transient response of centroid computation circuit along with theflash converter with Vdd = 0.9 V , Vss = −0.9 V , ibiasnd = 1µA, ibias = 0.88mAand ibiasp = 390µA.
91
Figure 3.57: Transient response of analog centroid computation circuit at withVdd = 0.9 V , Vss = −0.9 V , ibiasnd = 1µA, ibias = 0.88mA and ibiasp = 390µA.
92
Chapter 4
TEST SETUP AND MEASUREMENT RESULTS
The analog centroid circuit is designed for CMOS technology and implemented in
the AMI 0.5µm process using the MOSIS fabrication service. This circuit has a
40x40 two-dimensional pixel array and two analog centroid computation circuits,
one each for dimension. Each pixel is a photodiode of 20.25µm x 20.25µm size
with a fill factor of 48.53%. Each analog centroid computation circuit has 40
feedback amplifiers with PMOS current mirrors mirroring the photocurrents to
40 linearized differential pairs. It also has a single NMOS low-voltage cascode
current mirror. Only the analog centroid computation is implemented on chip.
The flash converter designed is not implemented on chip due to time and area
constraints.
Individual test components: a feedback amplifier, a PMOS current mirror,
a linearized differential pair, an NMOS low-voltage cascode current mirror and a
group of 4 pixels were laid out. Analog outputs were taken off of the chip through
on-chip analog buffers designed to drive high capacitive loads. The goal was to
avoid loading the internal circuitry. A test digital buffer was also laid out.
4.1 Test Setup
The chip is placed in a metal test box to shield it from noise and external
light sources that can effect the performance of the centroid computing chip. The
test box with the centroid computation chip, power regulator circuitry and virtual
93
ground generation circuit is shown in Fig 4.1. The power supply specifications
used for the testing are V dd=0.9V, V ss=-0.9V and GND=0V.
Figure 4.1: Test box for centroid computation chip.
The power regulator circuitry, virtual ground generation circuit and a volt-
age division circuit to provide a reference voltage must be placed inside the test
box along with the centroid computation chip. A battery holder is used to hold
the battery in a corner. A switch is used to turn the power supply from ON or
OFF.
Off-chip buffers are used to measure voltages and currents from the pins to
avoid loading effect. A low-power CMOS input rail-to-rail input/output opamp,
LM6482 is used to provide off chip buffering. The off-chip buffers drive electronic
instruments, such as the DMM (digital multimeter) and oscilloscope.
4.1.1 Regulated Power Supply Circuit
A regulated power supply circuit prevent noise from coupling with the
power supply. Noise coupled into the power supply could be carried into other
parts of the circuit. The ciruit diagram for the regulated power supply circuit is
shown in fig 4.2. A battery of +9V is used to generate Vdd of 1.8V. An LM317
94
adjustable 3-terminal positive regulator is capable of supplying in excess of 1.5A
over a 1.2V to 37V output ramp. It employs internal current limiting, thermal
shut-down and compensation.
Figure 4.2: Regulated power supply circuit.
The power supply circuit requires capacitors at input and output to block
any AC signals and improve stability. Capacitor Co is mainly there to provide
improved output impedance and rejection of transients. Capacitor Cin is required
if the LM317 regulator is located away from the power source. A potentiometer
of 1kΩ is used at the VADJ terminal. IADJ is less than 100µA. The LM317
provides an internal reference voltage of 1.25V between the output and adjustment
terminal. The output voltage is given by
Vout = 1.25V
(1 +
R2
R1
)+ IADJR2
The output voltage is programmable by a variable resistor R2. Diode D1
is used to prevent the capacitor C1 from discharging through the internal low
current paths and damaging the regulator. A 9V battery is given as input to
this regulator circuit. The output voltage is set to 1.8V by adjusting R2. The
95
output voltage of the regulated power supply circuit is measured using a digital
multimeter (DMM). Test the power supply circuit before testing the centroid chip.
4.1.2 Virtual Ground Generation Circuit
A virtual ground is needed as the circuit is based on a dual rail supply (Vdd
and Vss). A virtual ground is generated by splitting the power supply by a resistor
divider as discussed in Section B.1.1. The circuit is as shown in the Fig B.1. A
4.7kΩ is used as resistor R1 and a variable resistor is used for R2. R2 is adjusted
till the desired voltage level is achieved for the virtual ground.
4.1.3 Reference Voltage Generation Circuit
A reference voltage of −0.6V is required for one end of the resistive network
in the circuit on chip. This is also generated with a similar method that is used
to generate the virtual ground.
4.2 Optical Test Setup
The optical test setup is comprised of an optical source (a laser or LEDs),
an IC probe station and filters/attenuators. An IC probe station has a microscope
which is used in the optical testing. A picture of the optical setup is shown in
Fig 4.3.
An optical source can be focused onto the chip through one of the eyepieces
of the microscope. The image can be viewed through the other eyepiece. In order
to mount the optical source onto the eyepiece, an aluminium adapter with slots
for filters is used.
The laser is used as an optical source for static testing, that is, a very
slow movement of a light spot across the chip. A neutral density filter is used
for the laser to decrease the intensity of the light coming out of the laser such
that the pixels on the chip have photocurrents in the range of nanoamperes. The
96
Figure 4.3: Picture of the optical setup.
ND filters also protects human eyes. The light spot it produces has a diameter of
approximately 30µm making it suitable for static testing of only one pixel.
Light emitting diodes (LEDs) are used for dynamic testing and also in
static testing involving more than one pixel. These do not require any filters as
they result in photocurrents of nanoampere range in the pixels.
The photocurrents involved in the optical testing are very low currents, in
the range of picoamperes to nanoamperes and so at most care should be taken
to isolate the desired signals from noise. In order to shield the circuit from noise
an aluminium metal box is used. It would be ideal if the top of the box were
always closed, only a small slit to allow the optical source to focus its light on
the chip. However all of our tests were done with an open metal box. A 9V test
battery is used, as bench top dc power supplies tend to be noisy. Any unused
electrical equipment such as dc power supplies, oscilloscopes, signal generators,...,
are switched OFF as they tend to generate 60Hz noise. Office lights generate light
signals at a frequency of 120Hz, which is also a source of noise. In order to avoid
this, the optical measurements are taken in a dark room with all external light
97
sources switched OFF. The intensity of the light produced by the microscope light
is much higher than that of the optical sources and so it tends to saturate the
pixels on the chip. Hence, the microscope light also needs to be switched OFF.
Pictures of the adapter and the test setup are shown in appendix C.
4.3 Individual Component Testing
4.3.1 Test Pixel
A test pixel is included on the chip in order to characterize the photodiode.
A group of 4 pixels are laid out to exactly replicate the pattern of metal lines and
contacts in the photodiode array. A layout of a 2x2 test pixel array is shown in
the Fig 4.4. When the light is incident on the whole chip, the current from the
test pixels are assumed equivalent to the current from the pixels in the array. The
photocurrent generated by the test photodiode is in the range of nanoamperes.
This current cannot be measured directly by a digital multi-meter (DMM).
Figure 4.4: Layout of a 2x2 pixel array. Dimensions are 20.25µm x 20.25µm .
To measure low currents, the current has to be converted into a voltage. A
transimpedance amplifier is used to convert low currents into voltages, as shown
in Fig 4.5. The voltage thus obtained is used to find the value of the current. The
98
inverting terminal of the op-amp is connected to the output using the resistance
R. The value of resistance R is chosen typically around 10MΩ for currents in
nanoampere range. The inverting terminal is connected to pin 18 (i4pixel) of
the chip, which is the photocurrent output of the test pixels. The non-inverting
terminal is connected to the virtual ground. The output voltage is measured from
Vout to the virtual ground using a DMM. The photocurrent of the photodiodes is
then calculated using the equation
IIN =VOut
R
Thus, for a given resistance R and measured VOut, the photocurrent IIN is ob-
tained using the above equation. This current is the total current flowing out of 4
photodiodes. Hence, it is divided by 4 to get the the photocurrent flowing through
each pixel (photodiode).
Test Pixel with LED
A light emitting diode (LED) with a DC voltage across it is projected onto
the test pixel and the current is measured. The current is measured to be 46.7nA.
Dark Current
The test pixel is not allowed to receive any light by making the room dark
and also by closing the opaque lid on top of the chip. Now, the current measured
will be dark current. The dark current is measured to be 10.5pA.
Photodiode Responsivity and Quantum Efficiency
A laser is projected on to the test pixels. The optical power(Pin) of the
light incident on the pixels is measured with the help of an optical power meter.
The photocurrent (Iph) due to the light incident on the pixels is also measured.
99
Figure 4.5: Circuit to measure the photocurrent using a transimpedance amplifier.
The responsivity R of the photodiodes is given by,
R =Iph
Pin
(4.1)
The quantum efficiency η of the photodiodes is given by,
η = R1240
λ(4.2)
where λ is in nm.
100
The responsivity R of the photodiodes is 0.228 AW
. The quantum efficiency
η of the photodiodes 0.447. The quantum efficiency η expressed as percentage is
44.7%. The result for the quantum efficiency appear to be quite realistic value.
4.3.2 NMOS Low Voltage Cascode Current Mirror
An NMOS low voltage cascode current mirror is used as the current sub-
tractor. This mirror subtracts the aggregated currents inorder to help generate
the centroid output voltage. The layout of an NMOS low voltage cascode current
mirror is shown in Fig 4.6. Common-centroid layout technique was used for the
layout.
Figure 4.6: Layout of an NMOS low voltage cascode current mirror. Dimensionsare 51.60µm x 17.55µm .
A current source of approximately 1µA is established at the input of the
current mirror, pin 1 (testmiria+). The current measured is 0.9938µA. The cur-
rent measured at the output, pin 37 (testmirib-), is 1.0433µA. The results indicate
that the current mirror is well matched. Common-centroid layout technique was
used for this layout.
4.3.3 Linearizing OTA
A PMOS current mirror, a linearized differential pair and an NMOS low
voltage cascode current mirror combine together form a linearizing OTA. This
101
OTA is tested by establishing a bias current of 115.66nA, which is in the nanoam-
pere range. The layout of a linearized differential pair is shown in Fig 4.7.
Figure 4.7: Layout of a linearized differential pair. Dimensions are 34.80µm x14.25µm .
Offset is measured by performing a DC sweep for voltage gain. Common-
centroid layout technique was used for the layout of this circuit. The setup is
shown in Fig 4.8. A DC sweep is shown in Fig 4.9. The offset is measured to be
17.97mV .
Figure 4.8: Setup for voltage gain DC sweep.
The offset voltages for this OTA are observed to be very high. Offset
voltages for different chips are given in the Table 4.1.
102
0 10 20 30 40 50 60 70 80-600
-400
-200
0
200
400
600
800
1000
1200
Input voltage in mV
Out
put v
olta
ge in
mV
DC sweep for Vout vs Vin
Figure 4.9: Voltage gain DC sweep for the OTA.
Chip Number Offset VoltageChip 1 6.89mVChip 2 17.97mVChip 3 60.9mVChip 4 -33.85mV
Table 4.1: Table of offsets for Linearizing OTA
Linearity of this OTA is established by performing a DC sweep of transcon-
ductance, that is, Iout versus Vin. The setup is shown in Fig 4.10. The DC sweep
is shown in Fig 4.11.
Figure 4.10: Setup for transconductance gain DC sweep.
103
-300 -200 -100 0 100 200 300-50
-40
-30
-20
-10
0
10
20
30
40
50
Input voltage in mV
Out
put c
urre
nt in
nA
DC sweep for Iout vs Vin
Figure 4.11: Transconductance (Iout versus Vin) DC sweep for OTA.
4.3.4 PMOS Current Mirror
A PMOS current mirror is used for mirroring the photo current for the
linearized differential pair. The layout of the PMOS current mirror including the
feedback amplifier is shown in the Fig 4.12. Common-centroid layout technique
was used for the layout.
Figure 4.12: Layout of a PMOS current mirror including feedback amplifier. Di-mensions are 65.10µm x 21.90µm .
104
DC testing
Initially, the feedback amplifier is disabled. A current source of approx-
imately 2µA is established at the input of the current mirror, pin 30 (testvo).
The current measured is 2.073µA. The current measured at one output, pin 39
(testiout+) is 1.1527µA and the current measured at the other output, pin 40
(testiout-) is 1.1431µA. The results indicate that the current mirror is well
matched and working as expected by having almost equal currents through the
two output branches.
Bandwidth measurement
the bandwidth of this PMOS current mirror is measured by injecting an AC
current through the input branch. First, the Vrms values of the output currents
are measured at 10Hz. The frequency of the input current source is increased
gradually till the Vrms values drop their 3dB from their initial measured value.
This gives the bandwidth of the circuit.
Bandwidth is measured for the PMOS current mirror at both the output
pins for two circuit configurations: with the feedback amplifier and without the
feedback amplifier. The results are given in the Table 4.2.
Pin Number Bandwidth without feedback Bandwidth with feedbackPin 39 274Hz 81kHzPin 40 276Hz 84kHz
Table 4.2: Table of Bandwidths PMOS mirror without feedback and with feedback
4.4 Analog Centroid Computation Circuit Testing
The layout of the analog centroid computation circuit chip is shown in
Fig 4.13.
105
Figure 4.13: Layout of the analog centroid computation circuit. Dimensions of thechip are 1499.70µm x 1499.55µm. Dimensions of the centroid circuit are 989.70µmx 989.70µm .
4.4.1 Static Testing
Gradual moving spot
A laser beam is used for static testing as it produces a light spot of diameter
approximately 30µm which covers at most one and one half pixels. The laser beam
106
spot is moved horizontally in two arbitrary adjacent rows (2nd and 3rd) measuring
the column and row centroid voltages for each pixel. The measurements are
repeated by moving the spot vertically in two arbitrary adjacent columns (2nd
and 3rd). The results are shown in Figs 4.14, 4.15, 4.16 and 4.17. The results
show that the centroid voltage is monotonic as the light spot gradually moves
from one end to the other in a row or column and is very close to the expected
results.
0 5 10 15 20 25 30 35 40-600
-500
-400
-300
-200
-100
0
Position of the laser spot X-direction(COLUMN)
Cen
troi
d vo
ltage
(m
V) i
n X-
dire
ctio
n(C
OLU
MN
)
ROW 2ROW 3
Figure 4.14: Position of the spot vs column (x-direction) centroid output voltagefor 2nd and 3rd rows.
Centroid of two light spots
The optical sources used in this testing are two LEDs. Two LEDs are
focused at two different points on the chip. The two LEDS are observed to be
projected at locations (15,15) and (31,14) for left and right LED spots, respec-
tively, as shown in Fig. 4.18. Column (x-direction) and row (y-direction) centroid
voltages are measured. The light intensity of one of the LEDs is slowly decreased
and the centroid voltages are measured for different photocurrents. The same
procedure is repeated, but except that the light intensity of the other LED is
slowly decreased. Measurements are compared with those of simulations of the
107
0 5 10 15 20 25 30 35 40-600
-500
-400
-300
-200
-100
0
Position of the laser spot Y-direction (ROW)
Cen
troi
d vo
ltage
(m
V) i
n Y-
dire
ctio
n (R
OW
)
COLUMN 2COLUMN 3
Figure 4.15: Position of the spot vs row (y-direction) centroid output voltage for2nd and 3rd columns.
0 5 10 15 20 25 30 35 40-80
-70
-60
-50
-40
-30
-20
Position of the laser spot Y-direction (ROW)
X-d
irect
ion(
CO
LUM
N) c
entro
id v
olta
ge (
mV)
COLUMN 2COLUMN 3
Figure 4.16: Mismatch in the column (x-direction) centroid output voltage for 2nd
and 3rd columns.
actual circuit, simulations of the Deweerth’s circuit [1], an ideal winner-take-all
circuit and the expected true centroid in both the x- and y-direction. The results
are illustrated in Figs 4.19, 4.20, 4.21 and 4.22. The results of the centroid circuit
designed are very close to the true centroid when compared to other configurations
indicated above.
108
0 5 10 15 20 25 30 35 40-50
-45
-40
-35
-30
-25
-20
-15
Position of the laser spot X-direction (COLUMN)
Y-d
irect
ion
(RO
W) c
entr
oid
volta
ge (
mV)
ROW 2ROW 3
Figure 4.17: Mismatch in the row (y-direction) centroid output voltage for 2nd
and 3rd rows.
Figure 4.18: Locations of the left and right LED spots.
0 10 20 30 40 50 60 70 8022
23
24
25
26
27
28
29
30
31
32
Current at left spot (nA)
Pos
ition
of t
he c
entr
oid
in X
-dire
ctio
n
Winner take allCentroid measurementsCalculated true centroidSimulation of the proposed designSimulation of circuit by Deewerth
Right LED = 89.49 nA
Figure 4.19: Comparison of measured centroid voltage with the simulations of theactual circuit, simulations of the Deweerth’s circuit [1], an ideal winner-take-allcircuit and the expected true centroid in the x-direction (column) for variablecurrents at light spot made by the left LED.
109
0 10 20 30 40 50 60 70 8014.5
14.6
14.7
14.8
14.9
15
15.1
Current at left spot (nA)
Pos
ition
of t
he c
entr
oid
in Y
-dire
ctio
n
Winner take allCentroid measurementsCalculated true centroidSimulation of the proposed designSimulation of circuit by Deewerth
Right LED = 89.49 nA
Figure 4.20: Comparison of measured centroid voltage with the simulations of theactual circuit, simulations of the Deweerth’s circuit [1], an ideal winner-take-allcircuit and the expected true centroid in the y-direction (row) for variable currentsat light spot made by the left LED.
10 20 30 40 50 60 70 80 9014
16
18
20
22
24
26
28
30
32
Current at right spot (nA)
Pos
ition
of t
he c
entr
oid
in X
-dire
ctio
n
Winner take allCentroid measurementsCalculated true centroidSimulation of the proposed designSimulation of circuit by Deewerth left LED = 70.68 nA
Figure 4.21: Comparison of measured centroid voltage with the simulations of theactual circuit, simulations of the Deweerth’s circuit [1], an ideal winner-take-allcircuit and the expected true centroid in the x-direction (column) for variablecurrents at light spot made by the right LED.
4.4.2 Dynamic Testing
The optical sources used in the dynamic testing are two LEDs. A dynamic
condition is created for the light incident onto the chip by applying a time varying
signal to the LEDs with some pattern. In order to achieve dynamic condition,
both LEDs are operated with a sinusoid voltage of the same frequency, but 180
out of phase.
110
10 20 30 40 50 60 70 80 9014.4
14.6
14.8
15
15.2
15.4
15.6
15.8
16
Current at right spot (nA)
Pos
ition
of t
he c
entr
oid
in Y
-dire
ctio
n
Winner take allCentroid measurementsCalculated true centroidSimulation of the proposed designSimulation of circuit by Deewerth
left LED = 70.68 nA
Figure 4.22: Comparison of measured centroid voltage with the simulations of theactual circuit, simulations of the Deweerth’s circuit [1], an ideal winner-take-allcircuit and the expected true centroid in the y-direction (row) for variable currentsat light spot made by the right LED.
The column (y-direction) and row (x-direction) centroid voltages are ob-
served on an oscilloscope and their Vrms values are measured at a low frequency of
100Hz. The frequency of operation is increased until the amplitude drops by 3dB.
The frequency at which this 3dB point is reached is nothing but the bandwidth.
This bandwidth is measured for the centroid circuit both by enabling and dis-
abling the feedback amplifier. The procedure is repeated for three different light
levels (photocurrents). Pictures of these measurements are shown in Figs 4.23,
4.24 and 4.25.
Bandwidth simulations are done with identical test signals on almost iden-
tical places on the pixel array. Two sinusoidal which are out of phase by 180
are given to two groups of pixels. Each group has three pixels centered at pixels
17 and 23 in one dimension. The current in the pixels is almost the same current
that has been measured out of the actual pixel. The bandwidth measurements
and simulations at different photo currents are given in Tables 4.3 and 4.4.
111
Photocurrent ROW Bandwidth Simulation for 1-Dw/o feedback w/ feedback w/o feedback w feedback
DC: 2.195nA AC:1.95nA 1kHz 8.6kHz 1.5kHz 8.5kHzDC: 9.525nA AC:3.0375nA 5.3kHz 44kHz 6.6kHz 47kHzDC: 11.64nA AC:3.1025nA 7.1kHz 55kHz 7.9kHz 61kHz
Table 4.3: Bandwidth measurements and simulations for row (x-direction) atdifferent photo currents of the analog centroid computation circuit.
Photocurrent Column Bandwidth Simulation for 1-Dw/o feedback w/ feedback w/o feedback w feedback
DC: 2.195nA AC:1.95nA 800Hz 8kHz 1.5kHz 8.5kHzDC: 9.525nA AC:3.0375nA 4.3kHz 35kHz 6.6kHz 47kHzDC: 11.64nA AC:3.1025nA 5.9kHz 45kHz 7.9kHz 61kHz
Table 4.4: Bandwidth measurements and simulations for column (y-direction) atdifferent photo currents of the analog centroid computation circuit.
112
Feed
back
am
plifi
er d
isab
led
Feed
back
am
plifi
er e
nabl
ed
Signal at 100Hz ROW (Y-direction) Bandwidth COLUMN (X-direction) Bandwidth
Figure 4.23: Pictures of bandwidth measurements without and with feedback fora sinusoidal photocurrent of amplitude 1.95nA and dc average of 2.195nA.
113
Feed
back
am
plifi
er d
isab
led
Feed
back
am
plifi
er e
nabl
ed
Signal at 100Hz ROW (Y-direction) Bandwidth COLUMN (X-direction) Bandwidth
Figure 4.24: Pictures of bandwidth measurements without and with feedback fora sinusoidal photocurrent of amplitude 3.0375nA and dc average of 9.525nA.
114
Feed
back
am
plifi
er d
isab
led
Feed
back
am
plifi
er e
nabl
ed
Signal at 100Hz ROW (Y-direction) Bandwidth COLUMN (X-direction) Bandwidth
Figure 4.25: Pictures of bandwidth measurements without and with feedback fora sinusoidal photocurrent of amplitude 3.1025nA and dc average of 11.64nA.
115
Chapter 5
SUMMARY, CONCLUSIONS AND SUGGESTIONS
5.1 Summary and Conclusion
The aim of this thesis is to implement a stable, high speed and high ac-
curacy centroid computation circuit. The function of the circuit is to locate the
centroid of an image. Centroid is the location of the “center of mass” of an
intensity pattern of an image. The centroid computation is useful in many adap-
tive optical applications such as missile tracking, surveillance, object tracking and
wavefront sensing. The goal of this thesis is to achieve at least 10 times higher
bandwidth compared to that of previous designs, over 5 decades of photocurrents,
and with good accuracy.
Earlier centroid circuits by Deweerth [1] and a modification of Deweerth’s
circuit by Bashyam [2] have been discussed which form the basis for this thesis.
The drawbacks in those circuits have been explored. The thesis also discussed
three different circuits that might be useful in addressing the problems faced by
previous circuits. One among the three has been selected, as it proved to address
the problems in a more effective way. A feedback amplifier is used along with a
current mirror that is used to read the photocurrents from the photodiodes. This
is a similar topology used by Bashyam [2]. The difference is the way it is designed.
Bashyam [2] designed the feedback amplifier as a high gain amplifier, whereas the
proposed circuit is designed as a voltage regulator which regulates the voltage at
the node where the photodiode is connected. It isolates the capacitance of the
116
photodiodes at that node from the differential pair to achieve high bandwidth and
high stability.
MOS transistors in the subthreshold region have non-linear characteristics.
A small change in gate-to-source voltage results in an exponential change in the
drain current. Hence, mismatch is a big problem in circuits operating in sub-
threshold. A high degree of matching is required in critical parts of the circuitry,
such as current mirrors and differential pairs. The proposed circuit has been laid
out using common-centroid technique. Precision in the centroid computation has
been increased with the help of linearized differential pairs.
During testing, the chip has been placed inside a metal box, along with all
other needed circuitry, to shield it from external noise. Individual circuits have
been laid out and tested. Optical testing has been done with the help of an optical
test setup, comprised of a microscope, optical light sources such as light emitting
diodes (LEDs) and lasers, neutral density filters and an optical power meter. An
adapter made of aluminium has been used to hold optical sources in alignment
with filters and the microscope lens.
Static testing of the centroid computation circuit using a laser beam has
been done to observe the mismatch and monotonic responses of the pixels for a
gradually moving spot. Other static testing has been done using LEDs to evaluate
the circuit function as centroid computation. Dynamic testing has been performed
to measure the bandwidth of the circuit. Dynamic testing is performed using two
light emitting diodes producing sinusoidal light signals that are out of phase with
each other. The measurement results have been compared with the simulation
results. The measurement results closly match simulation results.
The major accomplishments of this thesis are achieving 7.5 to 8.5 times
higher bandwidth when compared to a circuit which does not have any feedback,
117
such as Deweerth’s model [1]. It has also achieved 10 times more bandwidth when
compared to the Bashyam’s circuit [2]. Good accuracy in the centroid computation
has also been achieved, as is evident from the transconductance characteristics of
the linearized differential pair. Monotonic responses have been observed in the
static testing of the analog centroid circuit. One other static test procedure proved
that the circuit which has been designed is actually computing the centroid. The
measurement results in this case are very close to the calculated true centroid.
The major drawback that has been observed is the offset voltage. The
offset voltages of the linearized differential pairs are observed to be very random
and change drastically from one chip to the other. These offset voltages, if not
compensated for, mess up the centroid computation and result in wrong estimation
of the centroid.
The increase in bandwidth for the linearized OTA with feedback is ob-
served to be 250 times higher than the OTA without feedback. This increase in
bandwidth is not fully reflected in the centroid computation circuit, as it has only
an increase of approximately 10 times for the circuit with feedback over circuit
without feedback. The probable reason that has been attributed is the capaci-
tance at the output node Vout of the current subtractor. This node is attached
to gates of 40 transistors as a negative feedback signal and hence has a huge ca-
pacitance that is effecting the bandwidth of the centroid circuit. Increasing the
multiplicity of mirroring transistors will increase the bandwidth of the centroid
circuit. This is because the photo-current is amplified before it is input to the
aggregation network.
The diffusion transistors in the linearized differential pair and the mirroring
transistors used to mirror the photo currents have not been laid out using the
common-centroid layout technique. These transistors have a multiplicity 1. Their
118
multiplicity can be increased and the common-centroid layout technique can be
used in order to reduce the offset voltages.
5.2 Future work
Offset compensation Offset voltages, as discussed in earlier Section 5.1, result
in a wrong estimation of the centroid of an image and thus adversely effect the
performance of any application based on the centroid computation. Apart from
systematic offsets, random offsets create lot of trouble, especially in circuits op-
erating in subthreshold region. Random offsets are introduced by normal process
variations. Hence, offset compensation schemes to compensate the random offsets
should be developed which can be integrated with the actual circuit on the chip.
New topologies of differential pairs can be designed in order to have lower offsets
in subthreshold region.
Analog-to-digital conversion Although a flash converter is designed in this
thesis, it has not been incorporated on-chip due to area constraints. Future work
is possible for the incorporation of an analog-to-digital converter by efficiently
managing the area available. An analog-to-digital converter enables the output
to be brought as digital data that can be processed further in off-chip processing.
Power consumption The circuit designed consumes lot of power because of
the feedback amplifier that has been used. Other new topologies that employ
adaptive biasing schemes can be explored based on the proposed design, in order
to bring down the power consumption. Adaptive biasing involves the adaptation
of static current, which is the bias current for the feedback amplifier, according
to the light levels.
119
Windowing New centroid circuits can be designed with the windowing prop-
erty. Windowing is the capability of computing the centroid over a desired portion
of the pixel array. In tracking only one object or image, which fills only a certain
portion of the sensor, a large part of the sensor remains idle while consuming
static power. Disabling the remaining unused portion of the pixel array saves
power. The other important application of windowing is tracking the motion of
one object in the presence of multiple objects. Windowing enables one to compute
local centroids, and thus individual spots or objects can be tracked. This property
helps in improving the performance of the sensor in object tracking applications.
120
APPENDICES
APPENDIX A
PICTURES OF THE CIRCUIT, TEST SETUP AND
MICROGRAPHS
Appendix A
PICTURES OF THE CIRCUIT, TEST SETUP AND
MICROGRAPHS
Figure A.1: Micrograph of the Chip
123
Figure A.2: Micrograph of pixels
Figure A.3: Picture of optical setup comprising microscope and adapter fittedwith LEDs.
124
Figure A.4: Picture of adapter with LEDs.
Figure A.5: Picture of some of the equipment used such as oscilloscope and wave-form generators.
125
APPENDIX B
PIN CONFIGURATION AND TEST PROCEDURE
Appendix B
PIN CONFIGURATION AND TEST PROCEDURE
Pin configuration for the centroid computation is given in the tables B.1 and B.2.
B.1 Suggested Test Procedure
Split supplies: Vdd = 0.9 V Gnd = 0 V Vss = −0.9 V
Test Engineer:
Test Date :
Chip Id :
B.1.1 Voltage generation
In order to generate any voltage between Vdd and Vss, a voltage divider
is used. The voltage divider is used along with a voltage buffer as shown in the
Fig B.1. The opamp used as a voltage follower is LMC 6482. Resistors R1 and R2
are selected according to the voltage that is required at the output. The generated
output voltage is given by equation (B.1)
Vgen = −0.9 +
(R2
R1 + R2
)(1.8) (B.1)
B.1.2 Current Measurement
Any current flowing into or out of the node is measured using an opamp
connected in a configurations as shown in the Fig B.2, B.3. The opamp used as
127
PinNo.
Pin Name PinType
Pad Type Pin Description
1 testmiria+ I-O Pad bare Input current for the testcurrent subtractor
2 testibiasnd I Pad protect Input bias current for thetest current subtractor
3 testib- O Pad bare Output current branch ib-of the test differential pair
4 testia+ O Pad bare Output current branch ia+of the test differential pair
5 testiin- I Pad bare Input current branch iin- ofthe test differential pair
6 vss (db) I-O Pad vss Vss for digital buffer7 testiin+ I Pad bare Input current branch iin+
of the test differential pair8 testvi- I Pad protect Input voltage vi- of the test
differential pair9 testvi+ I Pad protect Input voltage vi+ of the test
differential pair10 vend I Pad protect Input reference voltage at
the end of the series resistornetwork
11 No connection — Pad bare No connection12 No connection — Pad protect No connection13 vodb O Digital buffer Output of test digital buffer14 vidb I Pad protect Input of test digital buffer15 vdd (db) I-O Pad vdd Vdd for digital buffer16 vss (ckt) I-O Pad protect Vss for internal analog cir-
cuitry17 No connection — Pad protect No connection18 i4pixel O Pad bare Output current from a
group of 4 test pixels19 No connection — Pad protect No connection20 fbtest I Pad protect Feedback enable input for
the whole centroid circuit21 testfbtest I Pad protect Feedback enable input for
the test feedback circuit
Table B.1: Pin configuration of the Analog Centroid Circuit with some individualtest circuits(Pins 1-21).
128
22 ibiasn I Pad protect Input bias current for thefeedback amplifier in thecentroid circuit
23 ibiasnd I Pad protect Input bias current for thecurrent mirror in the cen-troid circuit
24 vini I Pad protect Input reference voltage atthe beginning of the seriesresistor network
25 vdd (ckt) I-O Pad protect Vdd for internal analog cir-cuitry
26 vss (ab) I-O Pad vss Vss for analog buffer27 ibn I Pad ibiasn Bias current for NMOS in
analog buffers28 cib- O Analog Buffer Column output voltage of
centroid circuit29 ib- O Analog Buffer Row output voltage of cen-
troid circuit30 testvo I-O Pad bare Output voltage of the test
feedback amplifier31 voab1 O Analog Buffer Output of test analog
buffer132 voab2 O Analog Buffer Output of test analog
buffer233 viab I Pad protect Input of test analog buffers34 ibp I Pad ibiasp Bias current for PMOS in
analog buffers35 vdd (ab) I-O Pad vdd Vdd for analog buffer36 testibiasn I Pad protect Input bias current for the
test feedback amplifier37 testmirib- I-O Pad bare Output current for the test
current subtractor38 testvreg I Pad protect Input voltage of the test
feedback amplifier39 testiout+ O Pad bare Output current iout+ of the
test feedback amplifier40 testiout- O Pad bare Output current iout- of the
test feedback amplifier
Table B.2: Pin configuration of the Analog Centroid Circuit with some individualtest circuits(Pins 22-40).
129
Figure B.1: Voltage divider configuration to generate any voltage between Vdd andVss.
a voltage follower is LMC 6482. Resistors R1 is selected according to the current
expected at the node. The nodes which are used for biasing currents have a
resistor already attached to the node and so another resistor is not required. If
the current is flowing into an NMOS transistor R1 is connected to Vdd as shown in
the Fig B.2. If the current is flowing out of a PMOS transistor R2 is connected to
Vss as shown in the Fig B.3. R1 is calculated from the expected current(I) using
equation (B.2).
R1 =1.8− |Vth|
I(B.2)
where Vth is the threshold voltage.
1. Connect Vdd = 0.9 V to pins 15,25 and 35.
Measured Vdd = .
2. Connect Vss = −0.9 V to pins 6,16 and 26.
130
Figure B.2: Current measurement configuration to measure current that is flowinginto a pin(may have an NMOS).
Measured Vss = .
3. Connect voltages 0 V and −0.6 V to pins 10(vend) and 24(vini)
respectively. Generate −0.6 V as discussed in section B.1.1 using
R1 = 5kΩ and R2 = 1kΩ.
Measured vini = .
4. Smell and touch chip to see if it is burning.
5. Attach 9kΩ resistance from Vdd to pin ibn (pin 27) to establish a 100µA
current source. The current is split two-ways (50µA each) for each of the
two analog output buffers. Measure the current as discussed in
section B.1.2.
Measured current= .
131
Figure B.3: Current measurement configuration to measure current that is flowingout of a pin(may have a PMOS).
6. Attach 7kΩ resistance from Vss to pin ibp (pin 34) to establish a 100µA
current source. The current is split two-ways (50µA each) for each of the
two analog output buffers. Measure the current as discussed in
section B.1.2.
Measured current= .
7. Attach 1.1MΩ resistance from Vdd to pin testibiasnd (pin 2) to establish a
1µA current source. The current is used to bias the test current
subtractor. Measure the current as discussed in section B.1.2.
Measured current= .
8. Attach 24kΩ resistance from Vdd to pin testibiasn (pin 36) to establish a
37.5µA current source. The current is used to bias the test feedback
amplifier. Measure the current as discussed in section B.1.2.
132
Measured current= .
9. Attach 550kΩ resistance from Vdd to pin ibiasnd (pin 23) to establish a
2µA current source. The current is split two-ways (1µA each) for each of
the two current subtractors in the centroid computation circuit. Measure
the current as discussed in section B.1.2.
Measured current= .
10. Attach 300Ω resistance from Vdd to pin ibiasn (pin 22) to establish a 3mA
current source. The current is equally split into 80 lines (37.5µA each) for
each of the eighty feedback amplifiers (40 each for column and row
circuitry) in the centroid computation circuit. Measure the current as
discussed in section B.1.2.
Measured current= .
11. Testing Digital Buffer: Apply a square waveform with frequency 10MHz
and amplitude +/− 0.9 V at pin 14(vidb). Observe the output at pin
13(vodb) and also measure the delay of the output waveform. Draw the
waveforms.
Measured delay= .
Waveforms are shown in Fig .
12. Testing Analog Buffer: Apply a sine waveform with frequency 20kHz and
amplitude +/− 0.8 V at pin 33(viab). Observe the output at pins
31(voab1) and 32(voab2) and draw waveforms of the input and output.
Measure the offset and gain of the analog buffers.
Measured offset= and gain= for analog buffer1
(pin 31(voab1)).
133
Measured offset= and gain= for analog buffer2
(pin 32(voab2)).
13. Testing Photodiode: Project LED onto the chip. Measure the current at
pin 18(i4pixel) as discussed in section B.1.2. Connect R1 to Vdd. Use
R1 = 5MΩ.
Measured voltage reading in the DMM= .
Measured Current= .
14. Measuring Dark current: Do not project LED onto the chip. Close cover of
the box, turn off the room lights and make sure there is no light incident
on the chip. Measure the current at pin 18(i4pixel) as discussed in
section B.1.2. Connect R1 to Vdd. Use R1 = 10MΩ.
Measured voltage reading in the DMM= .
Measured Current= .
15. Testing individual test current subtractor: Attach 1.1MΩ resistance from
Vdd to pin 1(testmiria+) to establish a 1µA current source. The current is
used as input current to test current subtractor. Measure the input current
as discussed in section B.1.2.
Measured input current at pin 1(testmiria+)= .
Measure the output current as discussed in section B.1.2 at pin
37(testmirib-).
Measured output current at pin 37(testmirib-)= .
16. Testing individual test Pmirror(part of feedback): Disable feedback by
applying −0.9 V at pin 21(testfbtest). Attach 350kΩ resistance from Vss to
pin 30(testvo) to establish a 2µA current source. The current is used as
134
input current to test PMOS current mirror. Measure the input current as
discussed in section B.1.2 at pin 30(testvo).
Measured input current= .
Measure the output currents as discussed in section B.1.2 at pin
39(testiout+) and pin 40(testiout-).
Measured output current at pin 39(testiout+)= .
Measured output current at pin 40(testiout-)= .
17. Testing individual test linearizing OTA: Disable feedback by applying
−0.9 V at pin 21(testfbtest). Connect pin 39(testiout+) to pin 7(testiin+),
pin 40(testiout-) to pin 5(testiin-), pin 4(testia+) to pin 1(testmiria+) and
pin 3(testib-) to pin 37(testmirib-). Attach 350kΩ resistance from Vss to
pin 30(testvo) to establish a 2µA current source. The current is used as
input current to test linearizing OTA. Measure the input current as
discussed in section B.1.2 at pin 30(testvo).
Measured input current at pin 30(testvo)= .
Offset Measurement:
Connect pin 8(testvi-) to gnd. Perform a DC sweep from +10 mV to
−10 mV on pin 9(testvi+).Connect a capacitor of 1µF from pin
37(testmirib-) to gnd and measure the output voltage at pin 37(testmirib-)
using an LMC6482 in a voltage follower configuration. Plot the output
voltage with respect to input voltage. Also measure offset voltage as the
voltage at the input for zero output.
Measured offset= .
Trans-conductance Measurement:
Connect pin 8(testvi-) to gnd. Perform a DC sweep from +100 mV to
−100 mV on pin 9(testvi+).Connect a resistor of 1MΩ from pin
135
37(testmirib-) to gnd and measure the output current as discussed in
section B.1.2.Plot the output current with respect to input voltage.
18. Dynamic testing individual test Pmirror: Apply 0.9 V at pin
21(testfbtest). Attach 350kΩ resistance from Vss to pin 30(testvo) to
establish a 2µA current source. Add a sinusoidal waveform on top of it to
simulate an AC current source using a waveform generator. The current is
used as input current to test PMOS current mirror. Measure the input
current as discussed in section B.1.2 at pin 30(testvo).
Measured input current= .
Measure the output AC current as discussed in section B.1.2 at pin
39(testiout+) and pin 40(testiout-) for a low frequency of 10Hz in terms of
rms voltage across the load resistors.
Measured rms voltage at 10Hz= .
Start increasing the frequency and observe the output voltage. Stop
varying the frequency when output reaches 1√2
of the output at 10Hz. The
frequency now measured is the bandwidth.
Measured bandwidth= .
Repeat the same procedure by disabling the feedback amplifier by
changing the voltage to −0.9 V at pin 21(testfbtest).
Measured rms voltage at 10Hz= .
Measured bandwidth= .
19. Testing Photodiode for quantum efficiency: Project Laser onto the test
pixels(consisting 4 pixels). Measure the current at pin 18(i4pixel) as
discussed in section B.1.2. Connect R1 to Vdd. Use R1 = 5MΩ.
Measured voltage reading in the DMM= .
136
Measured Current= .
Measure the optical power of the laser from optical power meter.
Measured Current= .
Calculate the responsivity R of the photodiodes.
R =Iph
Pin= .
Calculate the quantum efficiency η of the photodiodes.
η = R 1240λ
= .
where λ is in nm.
η = R 1240λ
1000 = .
where λ is in µm.
20. Static testing of the centroid computation: Apply 0.9 V at pin 20(fbtest).
Project Laser onto the chip. The laser is moved horizontally in two
arbitrary adjacent rows and the analog output at pins 28(cib-) and 29(ib-)
for column and row centroid voltages respectively. Repeat the same
procedure for two arbitrary adjacent columns.
Repeat the same by disabling the feedback amplifier by changing the
voltage to −0.9 V at pin 20(fbtest).
The following plots are drawn from the data.
• Position of the spot vs x-direction centroid output voltage.
• Position of the spot vs y-direction centroid output voltage.
• Mismatch in the y-direction centroid output voltage for 1st row.
• Mismatch in the y-direction centroid output voltage for 2nd row.
• Mismatch in the x-direction centroid output voltage for 1st column.
• Mismatch in the x-direction centroid output voltage for 2nd column.
137
21. Dynamic testing: Apply 0.9 V at pin 20(fbtest). Project 2 LEDs onto the
chip. Create a dynamic condition for the light incident onto the chip by
applying a time varying signal to LEDs with some pattern. In order to
achieve dynamic condition, both LEDs are operated with a sinusoid
voltage of same frequency but different phases(preferably out of phase).
Measure the analog output at pins 28(cib-) and 29(ib-) for column and row
centroid voltages respectively at low frequency of 10Hz.
Measured voltage at 10Hz= .
Start increasing the frequency and observe the output voltage. Stop
varying the frequency when output amplitude reaches 1√2
of the output at
10Hz. The frequency now measured is the bandwidth.
Measured bandwidth= .
Repeat the same procedure by disabling the feedback amplifier by
changing the voltage to −0.9 V at pin 21(testfbtest).
Measured voltage at 10Hz= .
Measured bandwidth= .
138
APPENDIX C
INFORMATION OF THE CHIP AND MOSIS FILE
Appendix C
INFORMATION OF THE CHIP AND MOSIS FILE
Project Name A Stable and High-speed CMOS Image Centroid Computation
Circuit.
Project Author Karthik Reddy Kothapalli
Submitted November 27th 2006.
Fabrication 0.5 m AMI double-poly n-well with 3 metal layers.
Apparatus Wavwform generator, oscilloscope, DMM, breadboard,DC power sup-
ply, microscope, laser and LEDs.
Description Analog centroid computation circuit for a 40x40 pixel array.
Design 76717 status: IN FAB
Design name: centroid kk
E-mail address: karthik c©nmsu.edu,pfurth c©nmsu.edu
Phone number: 5056443688
Technology: SCN3ME SUBM, lambda = 0.3
Fabrication restricted to AMI only.
Fill to be added: by MOSIS
Fabricated on run T6BJ (AMI C5F) as T6BJAP.
Bonding pads: 40
140
Layout size: 1498 x 1498 microns; area: 2.244 sq millimeters
Layers found (and densities): ACTIVE, CONTACT, GLASS, HI RES IMPLANT,
METAL1 (22.8%), METAL2 (18.1%), METAL3, N PLUS SELECT, N WELL,
PADS, POLY (2.1%), POLY2, P PLUS SELECT, VIA, VIA2
Requested packaging: DIP40 [MOSIS generated bonding diagram]
Maximum die size: 7366 x 7366
T6BJ is in fabrication; parts are expected to ship on 30-JAN-2007.
A total of 5 parts are ordered with 5 to be packaged in DIP40.
This project’s fabrication uses 1 MEP Circuit Unit(s).
The project will be shipped to:
Paul Furth
New Mexico State University
Electrical & Computer Engineering Dept
Thomas and Brown Rm. 106
Box 30001, MSC. 3-0
Las Cruces, NM 88003-8001
Routing-label: [not yet specified]
Mosis-Reply-Id: 00261367-001-008
141
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