Power electronics has already shown its importance as an indispensable solid-statetechnology for industrial process applications after decades of evolution and advance. Theimplementation of power electronics techniques brings energy, cost and space savings,elimination of severe audio noise, reduction of maintenance and improvement ofperformance and reliability. Industrial automation, energy conservation and environmentalpollution controls now increasingly depend on the techniques and development of powerelectronics. Due to the drastically reducing cost and dramatically improved system performance of power electronics, its applications are extended to various areas likeindustrial, commercial, residential, municipal, and aerospace systems.
143
e Florida State University DigiNole Commons Electronic eses, Treatises and Dissertations e Graduate School 10-19-2006 A Stochastic Approach to Digital Control Design and Implementation in Power Electronics Da Zhang Florida State University is Dissertation - Open Access is brought to you for free and open access by the e Graduate School at DigiNole Commons. It has been accepted for inclusion in Electronic eses, Treatises and Dissertations by an authorized administrator of DigiNole Commons. For more information, please contact [email protected]. Recommended Citation Zhang, Da, "A Stochastic Approach to Digital Control Design and Implementation in Power Electronics" (2006). Electronic eses, Treatises and Dissertations. Paper 543. hp://diginole.lib.fsu.edu/etd/543
Transcript
The Florida State UniversityDigiNole Commons
Electronic Theses, Treatises and Dissertations The Graduate School
10-19-2006
A Stochastic Approach to Digital Control Designand Implementation in Power ElectronicsDa ZhangFlorida State University
This Dissertation - Open Access is brought to you for free and open access by the The Graduate School at DigiNole Commons. It has been accepted forinclusion in Electronic Theses, Treatises and Dissertations by an authorized administrator of DigiNole Commons. For more information, please [email protected].
Recommended CitationZhang, Da, "A Stochastic Approach to Digital Control Design and Implementation in Power Electronics" (2006). Electronic Theses,Treatises and Dissertations. Paper 543.http://diginole.lib.fsu.edu/etd/543
A STOCHASTIC APPROACH TO DIGITAL CONTROL DESIGN AND IMPLEMENTATION IN POWER
ELECTRONICS
By
DA ZHANG
A Dissertation submitted to the Department of Electrical and Computer Engineering
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
Degree Awarded: Fall Semester, 2006
The members of the Committee approve the Dissertation of Da Zhang defended on Oct. 19th, 2006
Hui Li
Professor Directing Dissertation Emmanuel G. Collins Outside Committee Member Simon Y. Foo Committee Member Bing W. Kwan Committee Member
Approved: Victor DeBrunner, Chair, Department of Electrical and Computer Engineering Ching-Jen Chen, Dean, College of Engineering The Office of Graduate Studies has verified and approved the above named committee members.
ii
ACKNOWLEDGEMENTS
I would like to thank my academic advisor, Dr. Hui Li for her guidance and encouragement throughout my graduate program, and my committee members, Dr. Simon Y. Foo, Dr. Bing W. Kwan and Dr. Emmanuel G. Collins, for their invaluable advice and guidance. I would also like to thank the academic and administrative staff in the Department of Electrical and Computer Engineering and the Center for Advanced Power Systems (CAPS). Most importantly, I would like to thank my family and friends for their support throughout my graduate school experience.
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TABLE OF CONTENTS List of Tables ................................................................................................ Page vii List of Figures ................................................................................................ Page viii Abstract ...................................................................................................... Page xiii 1. INTRODUCTION .......................................................................................... Page 1 1.1 Background........................................................................................... Page 1 1.2 Objective and organization of dissertation ........................................... Page 5 2. STATE-OF-ART FPGA CONTROLLERS REVIEW................................... Page 9 2.1 Hybrid DSP and FPGA based digital controller ................................... Page 9 2.2 FPGA-based controller ......................................................................... Page 11 2.2 Stochastic FPGA-based controller........................................................ Page 15 3. STOCHASTIC ARITHMETIC ...................................................................... Page 16 3.1 Introduction........................................................................................... Page 16 3.2 Randomization Process......................................................................... Page 17 3.3 Stochastic Multiplication ...................................................................... Page 21 3.4 Other Stochastic Arithmetic.................................................................. Page 24 3.5 Derandomization................................................................................... Page 30 4. NEW STOCHASTIC ANTI-WINDUP PI CONTROLLERS........................ Page 33 4.1 Introduction of stochastic integrator ..................................................... Page 34 4.2 Proposed anti-windup strategies based on the stochastic integrator..... Page 36 4.3 Digital implementation of proposed stochastic anti-windup controller Page 45 5. STOCHASTIC NEURAL NETWORK.......................................................... Page 46 5.1 Introduction........................................................................................... Page 46 5.2 Principles of stochastic neural network ............................................... Page 48 5.2.1 Artificial neuron........................................................................... Page 48 5.2.2 Stochastic signed multiplication .................................................. Page 49 5.2.3 Stochastic approach to sigmoid activation function .................... Page 52
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6. STOCHASTIC MOTOR DRIVE CONTROLLER........................................ Page 61 6.1 Introduction........................................................................................... Page 61 6.2 Stochastic speed controller analysis...................................................... Page 63 6.3 Stochastic estimator design................................................................... Page 65 6.3.1 Torque and flux estimation using stochastic arithmetic .............. Page 66 6.3.2 Stochastic neural network estimator ............................................ Page 71 6.4 System design ....................................................................................... Page 76 6.5 Verification ........................................................................................... Page 80 6.5.1 Hardware-in-the-loop verification for stochastic speed controller Page 80 6.5.2 Verification of estimator .............................................................. Page 82 6.6 Conclusion ............................................................................................ Page 91 7. STOCHASTIC NEURAL NETWORK WIND SPEED ESTIMATOR......... Page 94 7.1 Introduction to sensorless small wind turbine generation system ........ Page 94 7.2 Design of the ANN wind velocity estimator......................................... Page 96 7.2.1 Principle of sensorless small wind turbine system ...................... Page 96 7.2.2 Neural network estimation principle............................................ Page 98 7.2.3 Neural Network Training Procedure............................................ Page 100 7.2.4 Simulation results of the proposed neural network wind speed estimator....................................................................................... Page 103 7.2.5 Hardware-in-the-loop experiment verification of the proposed neural network wind speed estimator using RTDS and dSPACE Page 105 7.3 Stochastic Neural Network wind speed estimator design..................... Page 112 7.4 Experimental Result using FPGA and RTDS....................................... Page 112 7.5 Conclusion ............................................................................................ Page 114 8. CONCLUSION............................................................................................... Page 116 8.1 Summary ............................................................................................... Page 116 8.2 Future work........................................................................................... Page 117 8.2.1 Implement real experimental verification of stochastic motor drive controller............................................................................. Page 117 8.2.2 Improve random engine design.................................................... Page 117 8.2.3 Implement ANN digital hardware with on-line training characteristics Page 118 APPENDIX ................................................................................................ Page 120 A MOTOR NOMENCLATURE AND PARAMETERS......................... Page 120 B WIND TURBINE PARAMETERS...................................................... Page 121
LIST OF TABLES Table 4.1: Integral state of the proposed stochastic anti-windup PI controller ... Page 41 Table 5.1: Comparison of look-up table and stan activation function using FPGA complier .................................................................................. Page 60 Table 6.1: Comparison of digital resources used by conventional and proposed anti-windup PI controllers................................................................... Page 82 Table 7.1: Weights and biases of the neural network wind speed estimator ....... Page 102
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LIST OF FIGURES Figure 1.1: A control system of a variable speed wind generation system ......... Page 2 Figure 2.1: Generalized concept of a DSP/FPGA digital controller ................... Page 10 Figure 2.2: A concurrent and simple FPGA controller of an AC/DC converter with power factor correction ............................................................. Page 13 Figure 2.3: The induction motor field-oriented control scheme implemented as a stochastic controller .................................................................. Page 14 Figure 3.1: The randomization process of an input variable .............................. Page 18 Figure 3.2: Single bit random engines ................................................................ Page 20 Figure 3.3: An improved 8-bit random engine ................................................... Page 21 Figure 3.4: The comparison between stochastic approach and traditional digital implementation of unsigned multiplication ..................................... Page 22 Figure 3.5: Simulation diagram and result of stochastic signed multiplication .. Page 23 Figure 3.6: Stochastic unsigned addition ............................................................ Page 25 Figure 3.7: Stochastic unsigned square ............................................................... Page 25 Figure 3.8: Stochastic signed subtraction ........................................................... Page 26 Figure 3.9: Stochastic integrator ......................................................................... Page 26 Figure 3.10: Stochastic square root calculation .................................................. Page 27 Figure 3.11: Stochastic unsigned division .......................................................... Page 28 Figure 3.12: Stochastic signed division .............................................................. Page 29 Figure 3.13: Stochastic unsigned division without saturation problem .............. Page 30 Figure 3.14: Feedback loop based derandomizer ............................................... Page 31
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Figure 4.1: Structure of a proportional-integral (PI) controller ........................... Page 33 Figure 4.2: Block diagram of digital integrator ................................................... Page 34 Figure 4.3: Block diagram of the traditional and stochastic integration schemes Page 35 Figure 4.4: Randomization process and an example ........................................... Page 35 Figure 4.5: Traditional anti-windup strategies for digital integrator ................... Page 37 Figure 4.6: Proposed stochastic anti-windup integration scheme (I)................... Page 38 Figure 4.7: Proposed stochastic anti-windup integration scheme (II) ................. Page 39 Figure 4.8: Proposed stochastic anti-windup integration scheme (III) ................ Page 40 Figure 4.9: Digital design scheme of stochastic anti-windup PI controller I....... Page 42 Figure 4.10: Digital design scheme of stochastic anti-windup PI controller II ... Page 43 Figure 4.11: Digital design scheme of stochastic anti-windup PI controller III .. Page 44 Figure 5.1: (a) Biological neuron (b) Artificial neuron ....................................... Page 48 Figure 5.2: An example of stochastic unsigned multiplication............................ Page 49 Figure 5.3: Probability distribution of N and maximum...................................... Page 51 Figure 5.4: Stochastic approach of tansig activation function............................. Page 53
Figure 5.5: Approximation: F(x)= 12)
11(
−−
−+ N
xx Vs G(x)= ……………….. Page 55 xN
e 2−
Figure 5.6: Approximation maximum error (G(x)-F(x)) with N………………. Page 56 Figure 5.7: Tansig( x) vs. stan(N,x) .............................................................. Page 57 12 −N
Figure 5.8: Digital design scheme of stochastic tan-sigmoid activation function generator ............................................................................................. Page 58 Figure 5.9: FPGA implementation result............................................................. Page 59
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Figure 5.10: Stansig Approximation error with increased N............................... Page 59 Figure 6.1: General block diagram of motor drive control .................................. Page 61 Figure 6.2: Block diagram of field oriented controlled induction motor drive showing FGPA based torque and flux estimator ............................... Page 62 Figure 6.3: Block diagram of proposed anti-windup PI speed controller............ Page 63 Figure 6.4: Simplified block diagram of stochastic based torque and flux estimator............................................................................................. Page 67 Figure 6.5: Digital implementation of stochastic flux estimator ......................... Page 69 Figure 6.6: Digital implementation of stochastic torque estimator...................... Page 70 Figure 6.7: Proposed stochastic neural network estimator for field-oriented induction motor drive......................................................................... Page 73 Figure 6.8: Conventional approach of neural network estimator of the induction motor's feedback signals .................................................................... Page 74 Figure 6.9: Proposed stochastic ANN approach of neural network estimator of the induction motor's feedback signals.......................................... Page 75 Figure 6.10: Proposed control structure for field-oriented induction motor drive applying stochastic theory ....................................................... Page 77 Figure 6.11: The hardware realization of proposed control algorithms using FPGA XC3S400 ............................................................................... Page 78 Figure 6.12: Hardware-in-the loop test setup using FPGA and RTDS................ Page 79 Figure 6.13: HIL experimental results of step speed response of proposed
controller and conventional controllers…………………………… Page 81 Figure 6.14: HIL experimental results of performance comparison of proposed anti-windup controller and conventional anti-windup controllers... Page 81 Figure 6.15: Matlab/Simulink model for the field-oriented control motor and estimator........................................................................................... Page 83
x
Figure 6.16: Flux estimation and comparison vs. the traditional method............ Page 84 Figure 6.17: The torque estimation error versus FPGA clock rate ...................... Page 84 Figure 6.18: Comparison between stochastic and DSP torque estimation with different clock steps ......................................................................... Page 85 Figure 6.19: The experimental setup ................................................................... Page 86 Figure 6.20: Maxplus II VHDL simulation of dtiRv s
Figure 6.21: Experimental result of the stochastic-FPGA (VHDL coded) and DSP ................................................................................................ Page 88 Figure 6.22: Hardware-in-the-loop test setup using FPGA and RTDS ............... Page 90 Figure 6.23: HIL results of NN estimator performance for the induction motor’s torque ............................................................................................... Page 91 Figure 6.24: HIL results of NN estimator performance for the induction motor’s flux ................................................................................................ Page 92 Figure 6.25: HIL results of NN estimator performance of unit vector: cosine wave Page 92 Figure 6.26: HIL results of NN estimator performance of unit vector: sine wave Page 93 Figure 7.1: Small wind turbine system ................................................................ Page 95 Figure 7.2: Power coefficient vs speed ratio........................................................ Page 97 Figure 7.3: Wind turbine power curves vs rotor speed and wind velocity .......... Page 97 Figure 7.4: A typical structure of artificial neuron .............................................. Page 98 Figure 7.5: Wind turbine model with NN wind speed estimator......................... Page 99 Figure 7.6: Neural network structure of the wind speed estimator...................... Page 100 Figure 7.7: Proposed training scheme for neural network of estimating wind velocity Page 101
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Figure 7.8: Wind velocity estimation ANN with five tan-sigmoid neurons and one linear neuron................................................................................ Page 102 Figure 7.9: Training error of the proposed neural network ................................. Page 103 Figure 7.10: Matlab/Simulink model of the wind speed estimator...................... Page 103 Figure 7.11: The wind turbine system with the NN wind estimator.................... Page 104 Figure 7.12: Matlab/ Simulink simulation result: Estimated wind speed vs actual wind speed ....................................................................................... Page 104 Figure 7.13: A voltage-feed double PWM converter wind generation system based on variable speed cage machine............................................. Page 105 Figure 7.14: Experimental verification of the above system using RTDS .......... Page 106 Figure 7.15: dSPACE implementation of NN based wind speed estimator ........ Page 107 Figure 7.16: Hardware verfication of the NN based wind speed estimator......... Page 108 Figure 7.17: A simple sine wave to simulate the effect of the wind speed estimator Page 109 Figure 7.18: A simple sine wave to simulate the effect of the wind speed estimator with a low pass filter ........................................................................ Page 109 Figure 7.19: Wind speed vs estimated wind speed using RTDS ......................... Page 110 Figure 7.20: Fast wind speed vs estimated wind speed using RTDS .................. Page 110 Figure 7.21: Stochastic ANN wind velocity estimator ........................................ Page 111 Figure 7.22: Experimental setup for a varied-speed wind turbine system using a hardware-in-loop real-time digital simulation .............................. Page 113 Figure 7.23: (a) Experimental result of wind speed estimation using stochastic-ANN-FPGA implementation; (b) Experimental result of wind speed estimation using look-up table -ANN-FPGA implementation ................................................................................ Page 114 Figure 8.1: Hardware Implementation of a single bit pseudo-random engine .... Page 117
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ABSTRACT
This dissertation uses the theory of stochastic arithmetic as a solution for the FPGA
implementation of complex control algorithms for power electronics applications. Compared
with the traditional digital implementation, the stochastic approach simplifies the computation
involved and saves digital resources. The implementation of stochastic arithmetic is also
compatible with modern VLSI design and manufacturing technology and enhances the ability of
FPGA devices
New anti-windup PI controllers are proposed and implemented in a FPGA device using
stochastic arithmetic. The developed designs provide solutions to enhance the computational
capability of FPGA and offer several advantages: large dynamic range, easy digital design,
minimization of the scale of digital circuits, reconfigurability, and direct hardware
implementation, while maintaining the high control performance of traditional anti-windup
techniques. A stochastic neural network (NN) structure is also proposed for FPGA
implementation. Typically NNs are characterized as highly parallel algorithms that usually
occupy enormous digital resources and are restricted to low cost digital hardware devices which
do not have enough digital resource. The stochastic arithmetic simplifies the computation of NNs
and significantly reduces the number of logic gates required for the proposed the NN estimator.
In this work, the proposed stochastic anti-windup PI controller and stochastic neural
network theory are applied to design and implement the field-oriented control of an induction
motor drive. The controller is implemented on a single field-programmable gate array (FPGA)
device with integrated neural network algorithms. The new proposed stochastic PI controllers are
also developed as motor speed controllers with anti-windup function. An alternative stochastic
NN structure is proposed for an FPGA implementation of a feed-forward NN to estimate the
feedback signals in an induction motor drive. Compared with the conventional digital control of
motor drives, the proposed stochastic based algorithm has many advantages. It simplifies the
arithmetic computations of FPGA and allows the neural network algorithms and classical control
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xiv
algorithms to be easily implemented into a single FPGA. The control and estimation
performances have been verified successfully using hardware in the loop test setup.
Besides the motor drive applications, the proposed stochastic neural network structure is
also applied to a neural network based wind speed sensorless control for wind turbine driven
systems. The proposed stochastic neural network wind speed estimator has considered the
optimized usage of FPGA resource and the trade-off between the accuracy and the number of
employed digital logic elements. Compared with the traditional approach, the proposed estimator
uses minimum digital logic resources and enables large parallel neural network structures to be
implemented in low-cost FPGA devices with high-fault tolerance capability. The neural network
wind speed estimator has been verified successfully with a wind turbine test bed installed in
CAPS (Center for Advanced Power Systems).
Given that a low-cost and high-performance implementation can be achieved, it is
believed that such stochastic control ICs will be extended to many other industry applications
involving complex algorithms.
.
CHAPTER 1
INTRODUCTION 1.1 Background
Power electronics has already shown its importance as an indispensable solid-state
technology for industrial process applications after decades of evolution and advance. The
implementation of power electronics techniques brings energy, cost and space savings,
elimination of severe audio noise, reduction of maintenance and improvement of
performance and reliability. Industrial automation, energy conservation and environmental
pollution controls now increasingly depend on the techniques and development of power
electronics. Due to the drastically reducing cost and dramatically improved system
performance of power electronics, its applications are extended to various areas like
industrial, commercial, residential, municipal, and aerospace systems.
The key element of power electronics is the control of the switching converter. The
raw input power is processed under the controller and generates the desired output power.
A well-designed controller should provide high quality output. For example, when a power
converter is connected to a utility line, a well-regulated output is required. For adjustable
speed AC drives, a carefully designed controller that can provide fast speed-response is
invariably desired. A number of control algorithms and hardware implementations can be
chosen based on different application requirements. Fig. 1.1 shows a control system of a
wind generation system [1]. The system consists of a back-to-back voltage-fed converter. A
vertical wind turbine is coupled to the shaft of a squirrel cage induction generator. A PWM
IGBT (insulated gate bipolar transistor) rectifier is employed to regulate the variable
frequency variable voltage output from the generator. The rectifier also supplies the
excitation needed by the machine. The inverter topology is identical to that of the rectifier
and it supplies the generated power at 60 Hz to the utility grid. The control of both the
rectifier and inverter are highlighted in Fig. 1.1. The rectifier uses indirect vector control in
the inner current control loop while the inverter current controller adopts the direct vector
1
PWM RectifierVwWind Turbine
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Figure 1.1 A control system of a variable speed wind generation system [1]
control method. The vector control algorithm permits fast transient response of the system.
In general, power electronics controllers can be classified as analog controller and
digital controller. Until now, the control of power converters is usually based on analog
solutions. The main advantages of an analog solution are low price and ease of use. With
the development of the control techniques and algorithms, the control becomes more and
more complex. Although there are still several analog commercial ICs for solving this type
of control problems, the cost reduction and improving performance of a digital controller
have made it an ideal solution for the power converter control applications. The digital
controller can also reduce the designing time. More and more research on the power
converter control using digital controller has been done in recent years [2-4].
A digital controller for the power electronic systems has the following advantages.
1. The digital controller is in a much higher density compared with the analog
controller. Unlike an analog controller which is normally composed of several IC parts
such as operational amplifiers, a digital controller can be fully integrated into one single
chip which provides the same functionality as an analog controller does.
2. The cost of a highly integrated digital control chip is significantly reduced in
recent years with the development of the semi-conductor techniques. It has reached the
2
point that the price of a single digital controller is much cheaper than the sum of several
analog parts and circuits.
3. The compact structure of a digital controller helps to improve system
reliability and to eliminate drift and electromagnetic interference (EMI) problems. It
appears to be both cost and time consuming for an analog controller to solve such
problems .
4. Computer based design and software programming are deeply involved in the
implementation of a digital controller. The hardware can be designed in a universal manner
and the software can be flexible. So it makes the system easy to update when the
requirements change.
5. There are many software which can simulate the system environment and
control block, for both analog and digital controllers. But for the analog controller design,
most supported software can only do simulation. Designers must rebuild the circuits with
the simulation results. The digital controller is different. The simulation program can
directly or easily be rearranged to the supported software and downloaded to the digital
chip. It significantly saves the time of building the real circuit and also provides reliability
for the controller performance through simulation results.
6. Normally, it is much easier to test and debug digital circuits compared with
analog circuits. The digital circuits are more stable and noise resistant.
7. As mentioned above, for a lot of applications (especially in the medium and
high power range), it is hard to reduce the price by large-scale production and so the
engineering cost is still a predominant factor in the final product’s cost. One solution to
this problem is the modularization and standardization. Having some multifunctional,
flexible and universal building blocks that can be assembled and reconfigured easily to
form a wide range of different applications will reduce the cost of the engineering design
efforts by sharing with more products. A digital controller provides the ability to support
this solution. The design of a digital controller is something like writing a C++ program
that has a rich volume of supporting libraries and also has more relation to the real
hardware.
All these indicate that digital controllers can greatly reduce the expense and take
3
place of the existing analog power electronics controllers.
There are different kinds of digital controllers. The first generation of digital
controllers is microcontroller. Since the early 1980s, microprocessors, microcontrollers,
and microcomputers have started and tended to present tremendous impact on power
electronics [5]. Different from the existing analog controllers, they can enable the
implementation of sophisticated and complex control techniques with computer programs
in a much easier way. In the 1980s, the single-chip microcontrollers (such as the Intel
16-byte 8096), the 32-byte microprocessors (such as the Motorola 68020, Intel 80386,
Zilog’s 2800) and microcomputers had already provided the abilities to performing the
dedicated and flexible jobs. Moreover, they enabled the implementation of modern control
theories (such as vector control, siding-mode control, model-reference-adaptive (MRAC)
control, fuzzy control, and state and parameter estimation) for high performance drives [6].
A DSP is a specialized microprocessor. It has the following characteristics:
1. A DSP has faster program execution due to its Harvard architecture that
permits the overlap of instruction fetch and execution of consecutive instructions [6].
2. A DSP chip also uses a dedicated hardware multiplier and barrel shifter and
permits these functions in one instruction cycle time.
3. DSPs can exploit use C language or assembly code for optimized
performance.
4. DSPs are well suited for extremely complex maths-intensive tasks. DSPs
operate in step-by-step manner and hence can provide the ability for the simple re-use of
the processing units. For example, the multiplier used for calculating an FIR can be re-used
by another routine that calculates FFTs.
Because of these characteristics, DSPs are very common in power converters
control since it exploits their mathematical oriented resources. Many arithmetic operations
are provided in a DSP to meet the demand of complex algorithms.
Due to the sequential operations, that is, instructions are executed one after the
other, and shared resources like memory busses, DSPs are not very common in high
switching frequency applications or applications that require massively parallel
calculations. Data loss may occur during the transfer of data and additional cost is needed
4
to solve these problems. For example, if the multiple-loop schemes of the motor controller
are to be realized by a DSP, most of the computation resource will be devoted to the inter
current-loop and PWM gating signal generations and so only very few computation
resources will be left for the other control loops and this will cause trouble to the whole
control system [7].
It is currently a popular tendency to introduce advanced Very Large Scale
Integration (VLSI) techniques such as Field Programmable Gate Array (FPGA) into power
electronics control. Compared with DSPs and Application Specific Integrated Circuits
(ASICs) that dominate the most available motor control applications, FPGA technique
provides a relatively low cost solution by combining the advantage of both two methods.
Different from DSP, all the internal logic elements of the FPGA and all the control
procedures are executed continuously and simultaneously [8]. The ability of carrying out
parallel processing by means of hardware mode enables a system operates at high speed
with good precision. In comparison with the ASICs, whose high-speed hard-wired logic
can also enhance the computation capability and thus relieve the DSP load factor, the
FPGA supports system reconfigurability and hereby readily meeting the requirements of
the industrial drives which are characterized by rapid evolution and diversified
applications. In general, FPGAs are drawing much attention in recent years due to its
shorter design cycle, lower cost, higher density and high calculation speed. In addition,
with programmable characteristics, the users can design their own ASICs according to
their own schemes, thus eliminate the involvement of the semiconductor manufacturer.
1.2 Objective and organization of dissertation
The problem currently encountered in the design of a single FPGA chip based
Power Converter’s controller is that the limited logic gates available in the device cannot
support complex algorithms which are normally needed for the modern power converter
control. The math-intensive functions in the control algorithms occupy large amount of the
logic elements in the FPGA. Even for a few examples that choose simple control
algorithms and hence are able to be implemented using FPGA controllers, the number of
5
logic cells used for the control is quite big and so the expensive FPGA chip with more
logic gates have to be selected, which greatly increase the product’s cost.
The objective of this dissertation is to provide a solution to simplify the
complicated mathematical functions and reduce the logic gates used in the FPGA device
for the complex control algorithms. The stochastic arithmetic based on the statistic theory
is applied to replace the normal mathematical operations to reduce the computational logic
elements involved and to enable the implementation of power converter controller using
one single FPGA device.
Chapter 2 presents a review of the literature on FPGA based digital controller for
power electronics applications. Three different FPGA based digital control topologies are
recognized: DSP and FPGA hybrid controller, FPGA controller and stochastic FPGA
controller. The DSP and FPGA hybrid controller combines the advantages of both to
provide a solution for complicated control algorithms. However, the increasing cost and
implementation difficulties limit its applications. The FPGA based controller has the
advantages of high calculation speed and low cost, but its limited ability in mathematical
operations calculation hinders it from many applications. The stochastic FPGA based
controller has just been introduced recently [9] and not many applications have been
applied. However, it provides a possible solution to enhance the computational ability of
FPGA with the same amount of digital logical gates.
Chapter 3 introduces the principle of stochastic arithmetic. Stochastic arithmetic
normally contains three processes: randomization, stochastic arithmetic operation and
derandomization. The randomization process transforms the input data into a random
sequence that only has ‘1’ and ‘0’. The probability of ‘1’ appears in the random sequence
containing the input value. The stochastic arithmetic operations include multiplication,
addition, square, subtraction, integration, square root and division. The derandomization
process is to convert the random sequence into the normal value.
Chapter 4 presents the design and implementation of three new stochastic
anti-windup PI controllers using FPGA. Proportional-integral (PI) controllers are probably
the most commonly used controllers among power electronics applications. The developed
designs provide solutions to enhance the computational capability of FPGA and offer
6
several advantages: large dynamic range, easy digital design, minimization of the scale of
digital circuits, reconfigurability, and direct hardware implementation, while maintaining
the high control performance of traditional anti-windup techniques.
Chapter 5 presents the proposed stochastic neural network structure. Neural
network (NN) algorithms have growing applications in motor drives to estimate machine
parameters, to generate PWM signals and to design neural controllers. The main
advantages of using neural network algorithms are simplifying the complicated algorithms,
reducing heavy computation demands and improving fault tolerance. In spite of the
apparent potential benefits, broader acceptance of neural network algorithms in motor
drives is still hampered mainly by implementation issues. The current analog
implementations of NN suffer from the non-ideal properties of analog circuit and the
traditional digital implementations cannot provide chips with adequate processing power at
an attractive price [10]. FPGA is concurrent, which supports the massively parallel
calculation of neural network. However, the enormous digital resources involved in these
implementations dramatically increase the cost and complexity of the FPGA IC and block
it from most industry motor drive applications. This problem can be resolved with the
utilization of stochastic arithmetic. The stochastic signed multiplication and stochastic
tansig activation approach are discussed.
Chapter 6 presents an FPGA-based control IC for the field-oriented control of an
induction motor drive. The most important difference from the previously proposed motor
drive control ICs is that it is based on stochastic arithmetic to implement the neural
network algorithm and digital PI algorithms with anti-windup function. These advanced
algorithms need too much required silicon area and are normally hard to be achieved in the
motor control IC design. The main advantage of the proposed method is that the required
digital resources for these algorithms are significantly reduced and the whole control
algorithm can be implemented into a low complexity inexpensive FPGA chip. This
approach simultaneously exploits the high speed of hardware implemented complex
algorithms and the capabilities of traditional control algorithms. The proposed control IC is
verified using an FPGA XC3S400. Due to the advantages of debugging, design period and
real time testing, a hardware-in-the-loop (HIL) test platform using Real Time Digital
7
8
Simulator (RTDS) is built in the laboratory and the HIL experimental results show that the
proposed FPGA-based control IC can achieve the high performance of adjustable speed
induction motor. Given that a low-cost and high-performance implementation can be
achieved, it is believed that such control IC will be extended to many other industry
applications involving complex algorithms.
Chapter 7 presents another application of a proposed stochastic neural network for
a small wind energy generation system. Artificial neural network (ANN) principles are
applied to implement a novel wind velocity estimator. The proposed stochastic neural
network structure is also introduced to the FPGA implementation of the designed wind
speed estimator. By employing this FPGA based stochastic neural network estimator,
highly precise and fast calculation may be instantly implemented with several stored
weight and bias vectors. Consequently, the complicated algorithm involving the
time-consuming calculation is achieved in a simple and cheap way without losing
accuracy.
Chapter 8 concludes this dissertation. The contributions of the stochastic FGPA
based digital controller to existing power electronics digital controller technology are
summarized and future research directions are provided.
CHAPTER 2
STATE-OF-ART FPGA CONTROLLERS REVIEW
This chapter presents the state-of-art VLSI technology applied to power electronics
controllers using FPGA. Section 2.1 introduces the hybrid DSP and FPGA based digital
controller. Section 2.2 presents the digital controllers using only FPGA. Section 2.3
introduces the stochastic FPGA based digital controller.
2.1 Hybrid DSP and FPGA based digital controller
DSPs have been widely used in the control of power electronics these years. The
high calculation speed provides the ability to implement complex outer loop control
algorithms [11]. However, DSPs depend heavily on their pipeline architecture and cache.
The software and hardware interrupts normally disturb their mechanisms and slow down
execution speed [12]. Although the DMA controller of DSPs is able to move data in and
out without interrupting the CPU, the inner loop control algorithms such as the current
control loop require the data to be processed immediately with a low latency. This
limitation of DSPs could be overcome by adding a FPGA controller for data buffering and
the low-latency current control. Some research works have been done by using a
DSP/FPGA mixed controller. For example, a space-vector PWM control integrated circuit
(IC) [13] is proposed and can be incorporated with a DSP to provide a simple and effective
solution for high-performance ac drives.
Fig 2.1 illustrates the generalized design concept of a DSP and FPGA based
platform for rapid prototyping of power electronic converters. The platform is largely
digitalized since numerous programmable digital building blocks exist with sufficient
computational power, and on the other hand, the programmable analog system building
blocks lack sufficient bandwidth for most converter applications. So the analog section
only includes a high performance analog to digital converter (ADC) and the galvanic
9
PCDSP
FPGA
Additionaloutputs
3 top/bottominvertoroutputs
3 currentserial inputs
1 voltageserial input
QuadratureEncoder
input (QEP)
LANA
Connection board
M
C
B
B
12-bitADC
12-bitADC
Positionencoder
DC-busvoltage meas.
Current meas.
Opticallink
Motor(Any type)
Modular 3-phase inverter
Figure 2.1 Generalized concept of a DSP/FPGA digital controller [12]
10
isolation required for safety and electromagnetic compatibility (EMC). The rest of the
system is fully digitalized. A powerful general-purpose DSP is selected for the signal
processing, user interface and monitoring. A large FPGA is implemented for the data
acquisition and fast control loops. It also provides the function of buffering of the data
subsequently used by the DSP. This platform has been used to design a sampled-data
three-phase dual-band hysteresis current controller and it proves that the FPGA increases
the flexibility and speed of the system.
The DSP/FPGA mixed controller has lots of advantages over the single DSP based
controller. It provides fast control speed, extra system flexibility and easier software design
since the tasks are divided into two parts for DSP and FPGA. However, this structure also
increases the system’s complexity and cost due to its dual devices. It also makes the
hardware harder to test thanks to its complicated structure. Also, DSP is still customized
solutions which are based on software implementation. Meanwhile, FPGA supports direct
hardware implementation and gives the user a chance to arbitrarily design their own ASICs
in lab according to their schemes, without having to involve the semiconductor
manufacture. So for the mixed DSP/FPGA controller, only the FPGA part has this feature
of flexibility and the DSP part still requires long development cycle and poor reuse of
codes.
2.2 FPGA based controller
Another approach is to implement the control algorithm in one single FPGA chip
instead of the common DSP solutions or the DSP/FPGA mixed structure. There are few
published researches on this approach. One of these [4] is applied in a single-phase PWM
inverter. The multiple-loop control scheme, which incorporates an inner current loop with
an outer voltage loop to regulate the output voltage of the PWM inverter, is implemented
based on FPGA XC4010 and the complexity of the control system has been tremendously
reduced. Another application of FPGA controller [3] is shown in Fig. 2.2. Fig.2.2 (a)
presents the general structure of a power factor correction converter whose objective is to
take energy from the ac source and reduce the harmonic currents as much as possible. The
11
control algorithm is illustrated in Fig.2.2 (b). It has two control loops: one is the current
loop to make the input current proportional to the input voltage, the other one is the voltage
loop to control the output voltage. The digital version of a charge control [14] for PFC
converter is selected as the current loop control algorithm and shown in Fig.2.2 (c). This
algorithm is not feasible in a DSP because of the DSP sequential nature. At least two
instructions would be necessary after every sample (addition and comparison) and this
makes the DSP’s process too slow for obtaining an acceptable duty cycle resolution. By
using FPGA, this algorithm could be implemented. This approach is different from the
traditional algorithms based on PID since no duty cycle is calculated but the switch is
controlled directly. So the average input current is controlled more accurately because the
PWM module is embedded inherently in the proposed algorithm. The voltage control loop
is also calculated for its digital representation and is implemented in the FPGA controller.
Based on the concurrency characteristic of the FPGA device, the new high-speed algorithm
in which all the resources are executed simultaneously can be used for the PFC converter
control while still allowing the system to perform with high accuracy in spite of its
simplicity.
FPGA based digital controller has many advantages compared with the DSP and
mixed DSP/FPGA controllers. It supports high-speed and concurrent control algorithms
and also provides a rapid low-cost manufacturing solution. Moreover, the control
algorithms could be developed in VHSIC (Very High Speed Integrated Circuit) hardware
description language (VHDL) which is now one of the most popular standard HDLs [15].
This language is virtually independent from any particular components or manufacturers
and is supported by all major Computer Aided Engineering (CAE) platforms [16]. The
VHDL code could easily be reused and synthesized into any FPGA and even has a possible
direct path to a customized chip. In this way, the VHDL supports direct hardware
implementation with the same flexibility as software solutions.
The digital controller using only one FPGA device is promising for its cost and
performance. But the number of available logic gates in a typical FPGA device limits its
applications. Also, the complex arithmetic operations in the control algorithm require too
much system resource, which may exceed the device’s ability or significantly increase the
12
(a) General Scheme of a Power Factor Correction converter
(b) Block diagram of the system and control algorithm
( C ) Current-loop controller schemeof FPGA
(d) Voltage-loop controller schemeof FPGA
FPGACONTROL
Figure 2.2 A concurrent and simple FPGA controller of an AC/DC converter with power factor correction [4]
13
PWMInverter
+
refsqi
+
rsqU
θje− 2 -> 3
P
Rotor FluxEstimator
Unit VectorCalculator
2 <- 3
-erω r
sdU
ssqUrefω
ssdU
aU
bU
ai
bi
rω
erω
-
-
θje+
32 mLp ⋅
Figure 2.3 The induction motor field-oriented control scheme implemented as a stochastic controller [9]
14
product’s cost. Until now, most related research work using FPGA devices are focusing on
the PWM ICs (Integrated Circuits) designs [16]-[19] which is still attached to DSP to
construct the whole controller or some simple converter designs [20]-[22]. The potential of
implementing one FPGA chip based controller has not been fully exploited in the
complicated motor control or complex converter control applications.
2.3 Stochastic FPGA based controller
The limitation for FPGA based controller is its limited number of available logic
gates in a typical chip. Modern motor and converter control algorithms including
intelligence control are normally complex and need large number of calculation elements.
The state-of-the-art FPGAs lack the gate density necessary to implement these complex
control algorithms. On the other hand, stochastic arithmetic has been known for many
years [23] due to its ability to save digital implementation resource. It was first applied in
the areas of machine computation simplification which are faced with large, power hungry,
and relatively unreliable hardware implementations. By using stochastic arithmetic, it is
possible to achieve complex computation with very simple hardware [24]. Recently,
Andrei Dinu proposed to apply this method for Motor Controllers [9]. In his paper, he
proposed the idea to use stochastic controller to implement the traditional field-oriented
control scheme, as shown in Fig. 2.3. However, there is no implementation in his research.
15
CHAPTER 3
STOCHASTIC ARITHMETIC
3.1 Introduction
Stochastic computing principles have been known for many years (B.R. Gains,
1969). The motivation for applying stochastic arithmetic to computation is its simplicity.
The hardware implementations of many control applications are normally space
consuming due to huge size of digital multipliers, adders, etc. Stochastic arithmetic
provides a way to carry out complex computations with very simple hardware and very
flexible design of the system. The stochastic implementation is also compatible with
modern VLSI design and manufacturing technology [24].
The fundamental principles of the stochastic arithmetic [8], [16] are summarized as
followings:
• All inputs are transformed to the binary stochastic pulse streams. This is called
randomization. In this step, the real number is coded into a sequence of binary bits
where the information is contained in the probability of any given bit in the stream
being a logic '1'.
• The stochastic arithmetic that consists of digital gate circuits takes place of the
normal arithmetic. After the first step, the real number becomes the one bus random
stream and so the math operations including multiplication, addition, division,
integration and many others can be implemented with simple digital circuits.
• The stochastic pulse streams are converted back to the normal numerical values.
After these corresponding math operations, the result is still the stochastic binary
streams. This process is to extract the probability information from the streams and
get the real number with the proper representation type. This step is called
derandomization.
16
The details of the stochastic arithmetic are presented in the following sections.
Section 3.2 presents the principles of randomization and different formats of the stochastic
representation of the real numbers. Section 3.3 uses the multiplication process as an
example to demonstrate the principle of stochastic operation and the advantages over
conventional arithmetic operation. Section 3.4 presents the structures of recently published
stochastic arithmetic. Section 3.5 presents the derandomization process.
3.2 Randomization Process
The Randomization is to transform the real data into binary stochastic pulse
streams. There are three formats for the stochastic representation of the real numbers. If X
is the coded number and p is the probability to have a bit '1' on any position in the bit
stream, then:
a). X in the range of [- ,+ ], the relation is ∞ ∞
ppX−
=1
(3.1a)
b). X in the range of [0,1], the relation is
pX = (3.1b)
c). X in the range of [-1,1], the relation is
12 −⋅= pX (3.1c)
Each of these three formats has its own advantages and disadvantages. (3.1a) has a
wide data change. However, the calculation accuracy is low. (3.1b) and (3.1c) have a small
range of representation with high accuracy. Normally, (3.1c) is chosen for the stochastic
neural network because of the consideration of accuracy and the threshold characteristic of
the activation functions. To satisfy the range limitation, proper normalization is required.
The randomization process can be further explained in Fig. 3.1. Fig. 3.1 (a)
presents the randomization process of (3.1c) with a normalization gain of 1/C. Fig 3.1 (b)
also shows an example with X=128 and C=256. The probability distribution process is also
presented in Fig 3.1 (c). In general, the objective of randomization is to represent the input
data with a sequence of binary bits in which the information of the input data is coded in
17
++ 0.5
PseudoRandomEngine
A
BA>B
Input X
Constant
C
-C<X<C
R
0<R<C
2
1+= CX
PX
Randomization Block
Output Y1-bit stream
(A) Stochastic Randomization Process
(C) Probability distribution in the output stream
(B) An example
X=128
C=256
011011101101111011111 ...
43
=XP...
Y:
0
XP
Distribution of Probability1 Probability of ‘1’
appears in theoutput 1-bit stream
Figure 3.1 The randomization process of an input variable [9]
18
the statistical properties of the random stream. For the data in the range of [0,1),
gives the relationship between the input data and the statistical properties of the
random stream and for the input data in the range of [-1,1],
pX =
12 −= pX gives the relations
where p is the probability to have a bit ‘1’ on any position in the bit stream and X is the
input data which needs to be coded.
Normally, the streams of random numbers are generated by a random engine which
provides the fundamental of stochastic transformation. In a purely digital environment, true
randomness is extremely hard to be obtained, so a pseudo-random stream is generated
instead. The pseudo-random numbers are not truly random. Rather, they are computed
from a mathematical formula or simply taken from a precalculated list. But in its period,
the pseudo random numbers have the same statistic characteristics compared with the truly
random and so if the period is long enough, the pseudo random numbers could have the
same performance as the truly random numbers. For the stochastic arithmetic, the
necessary equal distribution of probability can be obtained from the pseudo random
streams if the probability corresponding to each of the N bits of the random samples is 0.5
and also the process responsible for the generation of individual bits are not statistically
correlated. Both of the requirements could be simply achieved by selecting the suitable
seeds. In the digital logic circuit, the pseudo random bits could be easily implemented by a
linear feedback shift register (LFSR) with a feed-back loop containing an XOR gate. Fig.
3.2 gives an example circuit of the classical cascaded random engine using D-flip-flops
and a feedback loop closed through an XOR gate. The operation is cyclical. The length and
content of cyclical pattern generated depends on the number of D-flip-flops and on the
signals included in the feedback loop to the XOR gate.
For the N-bit pseudo random stream generation, the length of each one-bit pattern
needs to be even. Otherwise the probability 0.5 required for each bit stream is impossible
to obtain. The length of the combined N-bit pattern is the smallest common multiple of the
individual one-bit pattern lengths and thus the long pseudo random patterns of N-bit
samples can be obtained if the lengths of the one-bit patterns do not have common integer
divisors except 2. For example, the patterns of 5,7,11,13,17,19 constructed a 6-bit
19
randomization engine and the aggregate cycle length is 3,233,230 which is more than
enough for the stochastic arithmetic calculation with the power converter applications [9].
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Out
clk
reset
Figure 3.2 single bit random engines
However, for some input values, the direct outputs of Fig. 3.2 cannot be used to
adequately randomize the input variable. If the seeds or default data in these flip-flops have
too many zeroes, only few significant bits are involved in the randomization process and
may result in a relatively short pseudo-random sequence. [9] Especially when the input
sequence only has one ‘1’ and all other ‘0’s, it will only generate a very short cycle which
is repeated throughout the output bit stream. Dinu [9] has proposed a method to eliminate
this drawback. This method adds a supplementary XOR state that generates each output bit
of the randomization engine based on several LSFR signals and effectively increases the
length of the individual bit patterns with just a small increase of the involved digital
sources. Fig 3.3 shows an improved 8-bit random engine proposed by Dinu [9]. However,
several rules need to be set. First, the XOR gate generating the most significant output bits
needs most number of inputs while other XOR gates for the less significant outputs can use
less inputs. The maximum number of inputs for the significant XOR gate is n. Second, it is
preferred to connect the LFSRs with the longest operation periods with the XOR gates that
generates the most significant outputs. Finally, each XOR gates must have different
combinations of the input signals to generate the maximum random sequence.
20
Besides the method introduced above, there are a large number of acceptable
solutions to improve the performance of pseudo random engine. One possible method is to
change the seeds of the pseudo random engine during the run time. Since each one pair of
LFSR0
LFSR1
LFSR2
LFSR3
LFSR4
LFSR5
LFSR6
LFSR7
CLK
Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Figure 3.3 An improved 8-bit random engine [9]
seeds could generate one different pattern of pseudo random streams, this method could
increase the period without adding LFSRs which will increase the system complexity.
3.3 Stochastic Multiplication
Multiplication is the basic arithmetic operation and typically presents the advantage
of the stochastic arithmetic. Fig. 3.4 (a) shows the traditional digital logic unsigned
multiplier which composes of tens of logic gates. However, the stochastic unsigned 44×
21
multiplier shown in Fig. 3.4 (b) greatly reduces the number of the logic elements used for
the calculation. Fig. 3.4 (c) presents an example of unsigned stochastic multiplication. The
stochastic unsigned multiplier uses an AND gate as the arithmetic operator.
0 3m 2m 1m 0m0q
2q1q
3q
PP1
PP2
0p1p2p3p4p5p6p7p A block in the bottom two rows
A block in the up row
Full Adder
1+km km
0q1q
incoutc
m
Full Adderoutc
k
inc
jq
(a) A traditional 44× unsigned multiplier circuit [25]
PseudoRandomStreamEngine
ComparatorA
B
A>B
Comparator
ComparatorA
BA>BD-flip-flop
1Z
AND Derandomization
Stochastic unsignedMultiplication
X
Y
ANDPyPx ⋅Px
Py YX ⋅
(b) The Stochastic implementation of unsigned multiplication
AND
61
31
21
=⋅⇒=⋅ outyx ppp101100100010110010101101001011
21
01001010000101001001010000110031
00000010000001001000010000100061
(c) An example of unsigned multiplication
Figure 3.4 the comparison between stochastic approach and traditional digital implementation of unsigned multiplication.
22
With the one-bit stream represented inputs, the unsigned multiplication is as simple
as just one AND gate. It is obvious that ( AND XP YXPPP YXY ⋅=⋅=) . The digital
implementation of signed multiplication is derived based on the following equations:
12 −= XpX
12 −= YpY
12 −=⋅ XYpYX (3.2)
12)1()1( +−−⋅=−⋅−+⋅= YXYXYXYXXNOR ppppppppP (3.3)
121)12(21224)12()12(
−=−+−−⋅⋅=+−−⋅=−⋅−=⋅
XNORYXYX
YXYXYX
pppppppppppYX
(3.4)
sine wave2
sine wave1
randomengine2
randomengine1
In1Out1
derandomizer
dataout
To Workspace1
Scope1
>=
RelationalOperator2
>=
RelationalOperator1
Product
2
1/2
Gain2
1/2
Gain1
1
1
Constant2
1
Constant1
1
Constant
XOR
AND2
NOT
AND1
(a) Simulation Diagram of stochastic signed multiplication
0 2 4 6 8 10 12 14 16 18 20-0.4
-0.2
0
0.2
0.4
Stochastich mulitplication
normal mulitplication
(b) Comparison between stochastic signed multiplication and normal multiplication
Figure 3.5 Simulation diagram and result of stochastic signed multiplication
23
(3.2) gives the signed representation of X , Y and YX ⋅ while the output of a
XNOR gate has the probability relation of (3.3). (3.4) derives the expression of the signed
multiplication and so the signed multiplication could be performed using one XNOR gate.
From this example, the implementation of stochastic arithmetic usually has the
following steps:
1. Transform all the input data into random streams of bits with the information
contained.
2. Replace the normal arithmetic operations with the stochastic arithmetic
calculations. This step could significantly save digital circuits.
3. Convert the result random streams back into normal numerical values.
Fig. 3.5 (a) shows the simulation diagram of signed stochastic signed multiplication
using Matlab/Simulink and Fig. 3.5 (b) presents the simulation result of signed
multiplication.
3.4 Other Stochastic Arithmetic
The previous section discusses the stochastic multiplication in detail. In this
section, the commonly used stochastic arithmetic are briefly introduced including addition,
square, subtraction, integration, division and square root [26].
3.4.1 stochastic addition
Figure 3.6 presents the stochastic unsigned addition. It is based on a two-port
selector and the selection signal is decided by a stream of random bits which has the equal
probability to be ‘1’ and ‘0’. The two inputs are all transformed into stochastic
representations. The selector randomly chooses the output from the two input streams.
Since the possibility of both ports are the same, so the result contains the probability
information from both of the two input ports which gives the addition performance. From
the figure, if the input X has the probability of PX and input Y has the probability of PY, the
output stream has the output probability of 2
YX PP + which is automatically normalized.
24
PseudoRandomStreamEngine
Comparator
A
B
A>B
Comparator
ComparatorA
BA>BD-flip-flop
1Z
Derandomization
X
Y
Px
Py
MUX2:1
select
put1
put2
in
in
2yx PP +
Figure 3.6 Stochastic unsigned addition
3.4.2 stochastic square
Figure 3.7 presents the stochastic square operation. It composes of a D flip-flop and
an AND gate. The AND gate performs the stochastic unsigned multiplication and the two
inputs are the input X and its sequence after the D flip-flop. Based on the random theory,
the output of the D flip-flop has the same probability as the input sequence. However, it is
independent from its input sequence, which is an important condition for the stochastic
unsigned multiplication.
QD
clk QPseudoRandomStreamEngine
Comparator
ComparatorA
BA>BD-flip-flop
1Z
XDerandomization
2X
Figure 3.7 Stochastic unsigned square
3.4.3 stochastic signed subtraction
Fig. 3.8 presents the stochastic signed subtraction. It is similar to the unsigned
addition where a NOT gate is used to change the sign.
25
PseudoRandomStreamEngine
Comparator
A
B
A>B
Comparator
ComparatorA
BA>BD-flip-flop
1Z
Derandomization
X
Y
Px
PyMUX2:1
select
input1
input2
2yx PP −
Figure 3.8 Stochastic signed subtraction
N-bitUP/DOWN
Counter N-bitComparator
N-bitPseudoRandomEngine
down
up
A
B
A>B∫ ⋅t
dttX0
)(
X
Figure 3.9 stochastic integrator
3.4.4 stochastic integrator
26
Fig 3.9 shows the stochastic integrator. The signed input is transformed to
stochastic random streams using (3.1c). An N-bit up/down counter is applied to integrate
the input. For positive input, the number of ‘1’s should always be bigger than the number
of ‘0’s appeared in the random sequence. If the input data has large value which means the
probability of ‘1’ appears in the random sequence is high, the output of the up/down
counter will go up in proportion to the value of the input data, or vice versa.
3.4.5 stochastic square root
Square root is always not an easy operation to be implemented using digital logic
gates. Besides the traditional complicated implementation, the stochastic arithmetic
provides another approach with simple digital circuits. Fig. 3.10 shows the circuit
schematic of the stochastic square root operation. The input X is first transformed into
stochastic random sequence. Different from the previous stochastic arithmetic, a feedback
loop is introduced in the stochastic square root operation. As shown in the figure, the
output of the stochastic square root operation is fed back through a stochastic square
operator to generate the anticipated input value. This anticipated input value is compared
with the real input value to adjust the output. The close loop structure, which provides the
method to reduce the comparison error until those two values equal, sends out the correct
square root operation result. Compared with the traditional digital implementation, the
stochastic square root operation has the advantages of simple circuit and easy
implementation. However, several drawbacks need to be mentioned due to its close- loop
structure. It normally requires response time and could not send out the correct result at the
beginning and furthermore the stochastic representation will introduce noise and error. So
the applications using this approach should be limited to those who regard slow and rough
calculations as tolerable.
N-bitUP/DOWN
Counter N-bitComparator
N-bitPseudoRandomEngine
down
up
Q=X/Y
A
B
A>B
Q
Qclk
D
X
Figure 3.10 Stochastic square root calculation
27
N-bitUP/DOWN
Counter N-bitComparator
N-bitPseudoRandomEngine
down
up
Q=X/Y
A
B
A>BQ=X/Y
X
Y
Figure 3.11 Stochastic unsigned division
3.4.6 stochastic division
Division is another difficult task for digital logic implementations. Many methods
have been proposed with complicated circuits. Stochastic arithmetic also provides a simple
approach using the similar close-loop structure. Fig. 3.11 shows the circuit schematic of
the stochastic unsigned division. Both the inputs X and Y are first transformed into
stochastic random sequences and then a feedback loop is introduced in the stochastic
unsigned division. As shown in the figure, the output of the stochastic unsigned division is
fed back through a stochastic unsigned multiplication with another input of Y to generate
real input value of X to adjust the output of the unsigned division. The close loop structure
provides the method of reducing the comparison error until those two values equal to send
out the correct unsigned division result.
Fig. 3.12 presents the stochastic signed division. It accepts a similar structure with
a few modifications. The stochastic signed multiplication is introduced to implement the
stochastic signed division. Different from the stochastic unsigned division, two XNOR
gates are used to perform the stochastic signed multiplication. Thus the input Y is fed
through a D flip-flop and multiplies itself to generate the square of Y. The square Y
multiplies the output Q and generates the anticipated value of YX ⋅ . The input X also
multiplies Y directly to generate the real value of YX ⋅ . The two values are then compared
to control the output until these two values are equal which gives the division result.
28
N-bitUP/DOWN
Counter N-bitComparator
N-bitPseudoRandomEngine
down
up
Q=X/Y
A
B
A>BQ=X/Y
clk
Q D2YQ ⋅
YX ⋅X
Y
Figure 3.12 Stochastic signed division
Another important issue of digital division is the saturation problem. It occurs when
the division result is too close to 1 or 0 and therefore the Gaussian distribution of
probabilities in the counter gets distorted. Normally, this saturation problem could be
alleviated by using a large counter and then the Gaussian distribution can be set closer to
the extremes to avoid saturation. However, Dinu [26] proposed a thorough solution to
solve this problem. Fig. 3.13 shows the improved stochastic unsigned division without
saturation problem. It involves three modifications to the previous stochastic unsigned
division [26].
• “Using an N+2 bit counter that stores signed numbers in the interval [-2N+1, 2N+1-1].
• If the counter is already at value 2N-1 but still needs incrementing, then it will be
incremented once more with a probability decided by a second comparator.
• Similarly, if the counter is already at level 0 but needs further decrementing, then it
will be decremented twice with probability controller by a third comparator.” [9]
29
UP/DOWNCounter
down
up
Q=X/Y
Q=X/YComparatorA
B
A>B
Comparator
B A
-A>B
ComparatorAB
A/2N>B
B
Supplied bythe Pseudo
RandomEngine
Doubledown
Doubleup
X
Y
Figure 3.13 Stochastic unsigned division without saturation problem [26]
3.5 Derandomization After the stochastic multiplication, the data needs to be translated back to the
normal output data. The process to get statistical information out of the random streams is
called derandomization. The derandomizaion of the random stream is determined by
counting the number K of bits ‘1’ in a set of N consecutive samples. Large N will give
precise result while it also takes more time to catch the value from the random streams of
bits. Theoretically, K can be any value between [0, N], but some values are much more
probable than others. The results of the followings have been introduced in [27].
From the statistic theory, the probability P(K) to find K bits ‘1’ in a set of N
samples from a stream with probability ‘p’ is: KNK ppKNK
NKP −−⋅⋅−⋅
= )1()!(!
!)(
NpK ⋅=max
[26].
The function P(K) is a binomial distribution having the maximum at and the
standard deviation which is expressed as )1( ppN −⋅⋅=σ . When N is large, this
30
X (stochastic representation)
N-bitUP/DOWN
Counter N-bitComparator
N-bitPseudoRandomEngine
down
up
A
B
A>B
N21
DataX
Figure 3.14 feedback loop based derandomizer
probability distribution can almost be considered to have the Gaussian characteristic and
also the K is situated at a distance of 3-σ from Kmax with a probability of over 99.5%.
With the condition mentioned above, the derandomization error could be calculated
as the following:
NNN
⋅=
−⋅⋅⋅≤
23)5.01(5.03
[26] (3.6) NNKp =
∆≅∆
3σ
Thus, it could be proved that the larger the number N of samples, the smaller the
derandomization error.
Fig. 3.14 shows the scheme of the derandomization process where a feedback close
loop structure is applied for the fast tracking ability. The output of the up/down counter
will be randomized again and compared with the input stream. When the ‘1’ appears more
frequently or less frequently in the input stream than the output stream, the up/down
counter will continue to increase or decrease until these two frequencies are equal. This
31
32
derandomization method is easy to be implemented but is not suitable for the continuous
signals with extremely fast changes.
CHAPTER 4
NEW STOCHASTIC ANTI-WINDUP PI CONTROLLERS
Proportional-integral (PI) controllers are probably the most commonly used
controllers among power electronics applications. The purpose of a PI controller is
normally to stabilize the system, improve the transient response and achieve zero steady
state error. Fig. 4.1 shows the basic structure of a PI controller. It contains both a
proportion component and an integration component with a saturator to guarantee that the
requirement by the physical characteristics of the system will be met.
However, a large step change in the control input will cause the generated control
variable from a PI controller to exceed the prescribed maximum value. Thus a saturator is
applied, which introduces a non-linearity into the system. This phenomenon is called
integrator windup and can lead to large overshoot, long settling times, and even unstable
closed-loop systems [28] since the parameters of the PI controller are normally designed in
a linear region, ignoring the saturation nonlinearity. In an attempt to overcome the windup
phenomenon, a number of anti-windup techniques have been proposed in the literature, for
example [29-33]. Currently, digital implementations of anti-windup PI controllers are
based on a microprocessor or DSP [34]. Hardware solutions such as field programmable
gate arrays (FPGA) have advantages in price, execution speed and flexibility but are
restricted for their poor calculation ability [35] and the low available number of logic gates
Ki
Kp+
+maxu
maxue(t)
uout(t)
maxmax and uuuu inin >−<
1S
uin(t)
Figure 4.1 Structure of a Proportional-integral (PI) controller
33
in a typical FPGA [10]. Stochastic arithmetic provides an effective method of enhancing
the computational capability of FPGA with the same logic gates density [9]. This is an
efficient implementation approach that uses simple digital logic circuits but has the
advantage of significantly reducing the circuit complexity compared with the traditional
digital implementation approach.
In this chapter, new anti-windup PI controllers are proposed and implemented in a
FPGA device using stochastic arithmetic. The developed designs provide solutions to
enhance the computational capability of FPGA and offer several advantages: large
dynamic range, easy digital design, minimization of the scale of digital circuits,
reconfigurability, and direct hardware implementation, while maintaining the high control
performance of traditional anti-windup techniques.
4.1 Introduction of stochastic integrator
The digital integrator can be expressed in (4.1) and its structure is shown in Fig.
4.2.
)1()()( −+= nynxny (4.1)
Fig. 4.3 (a) presents the traditional accumulator design of a digital integrator. A
large register holds the previous output of the integrator and sent the one step time delayed
output signal back to the adder to perform the integration function. Fig. 4.3 (b) shows
another approach of the digital integrator using stochastic arithmetic. The stochastic digital
+
UnitDelay
X(n)
y(n-1)
y(n)
Figure 4.2 Block Diagram of Digital Integrator
34
integrator has two elements: a signal value to frequency converter (randomization block)
and an up-down (pulse) counter. In the randomization process shown in Fig. 4.4, the value
of the input signal X is represented by the frequency of ‘1’ appearing in the output bit
stream.
+
R
RandomizationBlock
UP/Down Counter
Down
Up
C2
maxCounterC =
-
Input X
Output
AdderN-bitInput X
Register
Output
( a) Accumulator design of a digital integrator
( b ) Stochastic approach of a digital integrator Figure 4.3 Block diagram of the traditional and stochastic integration schemes
++ 0.5
Pseudo-random
engine
A
BA>B
Input x
Constant
C
-C<X<C
R
0<R<C
X=128
C=256
21+
= CX
Px
011011101101111011111 ...
Randomization Block
Output Y1-bit stream
...Y:
2
1
43
bitsTotals'1'of +
=== CX
NumberP
An example of randomization process
x
Figure 4.4 Randomization process and an example
35
If p is the probability to have a bit ‘1’ on any position in the bit stream then the value of the
input signal is given by the expression cpx ⋅−= )12( (where c is a constant and the input x
must in the range of –c and c). For example, if the input x equals c, then the output bit
stream will be all ‘1’s and if x equals to –c, the output bit stream will be all ‘0’s. After this
process, the Up/Down counter accumulates the incoming pulses and performs the
integration function.
Compared with the traditional approach of implementing digital integration, the
stochastic method has a larger dynamic range and eliminates the n-bit adder that contains
tens of logic gates. Although the randomization process requires extra digital resources for
the pseudo random engine and the comparator, these resources can be shared if many
digital integrators are employed in the same digital Integrated Circuits (ICs).
4.2 Proposed anti-windup strategies based on the stochastic integrator
To date, most developed anti-windup strategies can be classified as either a
conditional integration scheme, a back-calculation scheme or a hybrid scheme, as
illustrated in Fig. 4.5 (a), (b), and (c), respectively. The conditional integration scheme is
reported as the most popular anti-windup strategy due to its simplicity. The integral action
turns off when the output signal reaches saturator’s limit to avoid the accumulation of
errors which is not able to change the control performance any more. In the back-
calculation and the hybrid schemes, the integral term reduces its absolute value when the
output saturates. The free tuning parameter Ka decides the decreasing rate of the integral
term’s absolute value. These two schemes suffer complicated and time-consuming design
process in optimizing the free parameters Ka which decides the performance of integrator
when saturation happens.
The proposed stochastic anti-windup digital PI control algorithms are illustrated in
Fig. 4.6, Fig. 4.7 and Fig. 4.8. In Fig. 4.6, the saturation signal is connected to the
up/down counter through two AND gates. When the saturation signal is ‘1’, the output of
the two AND gates all become ‘0’, which disables the accumulation of the up/down
To implement the neural network structure in Fig 7.8, stochastic multiplication and
stochastic activation function are applied to replace the corresponding operations. As
shown in Fig 7.21, the stochastic multiplication and stochastic approach of tansig
activation function are applied to replace the traditional digital implementation of
multiplication and tansig function. Randomization processes are also accepted for the
inputs and weights.
7.4 Experimental Results using FPGA and RTDS
The experimental setup of the wind turbine system using a real-time digital
simulator (RTDS) is shown in Fig. 7.22 [66]. A 20 hp dynamometer is used to emulate the
wind turbine. The entire turbine model has been implemented in RTDS, which provides
the shaft torque request TS-0 and the generator speed request ωG-0 to the dynamometer-
generator set. An FPGA device Sparatan3-XC3S200 from Xilinx implements the ANN-
based wind-speed estimation. A 50 MHz oscillator is applied to the FPGA, so the time step
for the stochastic stream is 0.02 µs. Around 20,000 bits are used for each derandomization
process in this application. The calculation time of each point is 0.4 ms, so the output
sample rate to estimate wind speed can reach as high as 2.5 KHz. The experimental results
of wind speed estimation of a random varied wind speed profile are shown in Fig 7.23 (a)
and (b). Fig 7.23 (a) is derived by using the developed stochastic-ANN-FPGA
implementation and (b) by using a traditional look-up table-ANN-FPGA implementation.
The stochastic estimator uses 16-bit resolution for randomization, multiplication and tansig
of N = 4. The traditional estimator has 256 points in the look-up table for the tansig
function, and each data point in the loop-up table has a 10-bit resolution. The digital source
utilization of the FPGA device is 75% using the stochastic method and 98% with the look-
up table. Although the stochastic method introduces approximation errors, the stochastic
method is more accurate than the look-up table, as shown in Fig. 7.23, because the similar
digital resource utilization limits the size of the look-up table and the resolution for the
traditional method. However, a higher resolution can be achieved for the stochastic method
112
Sourceselector
CAPS utility feed 208 V
M GWmr
vrω
=λ
Wind velocity profile vW-P
Generator shaft speed ωG
)(CT λ
×
x22
KK
Generatorspeed
request ωG-0
Shaft torque TS
Aerodynamic torque request TA
RTDS
Torque control mode
Speed control mode
Wm
vω
=λ
10
0
0.4
GearboxratioTurbine
speed ωr
-
-
.0.4
Emulator shaft torque request
TS-0
×
Generator shaft power PS
Neural NetworkEstimator
8.4
94.25
0
Estimated wind velocity vE
Turbineand gear inerti
a
FPGA
Bandwidth limit
∑∑
Low power HIL test setup
7.9
Turbine speed ωr
kFkF
Turbine and gear friction
+
TJ
TF
vE-NNE
11 Esτ+
1 J
ssτ+1 J
ssτ+
JTJT
Figure 7.22 Experimental setup for a varied-speed wind turbine system using a hardware-in-loop real-time digital simulation
113
and a fast clock rate provides a small approximation error.
7.5 Conclusion
The proposed stochastic-ANN-FPGA implementation for wind energy generation
applications saves digital logic resources and enables large parallel neural network
02
10864
-2
1214
Wind
veloc
ity(m
/s)
0 1 2 3 4 5 6 7 8 9 10Time (s)
Stochastic NNWind Velocity
Estimation
Actual WindVelocity
EstimationError
02
10864
-2
1412
Wind
veloc
ity(m
/s)
0 1 2 3 4 5 6 7 8 9 10Time (s)
Traditional NNWind VelocityEstimation (8-bit)
Actual WindVelocity
EstimationError
(a)
(b)
Figure 7.23 (a) Experimental result of wind speed estimation using stochastic-ANN-FPGA implementation; (b) Experimental result of wind speed estimation using look-up table -
ANN-FPGA implementation
114
115
structures to be implemented in low-cost FPGA devices with high-fault tolerance
capability. The experimental results of a speed-sensorless control of a small wind-turbine
system confirmed the proposed design method. The computation error of the stochastic
method has been analyzed. We have also considered the trade-off between the accuracy
and the number of employed digital logical elements. Hardware-in-loop experimental test
flat is applied in this application which perform a fast and economical method to test the
proposed controller and estimator.
CHAPTER 8
CONCLUSION 8.1 Summary
The conclusions of this dissertation work can be summarized as follows:
1. The stochastic arithmetic is applied to reduce the involved digital computation
elements for FPGA implementation of complex power electronics control
algorithms. The performances are verified using FGPA based controllers.
2. New stochastic anti-windup PI controllers are proposed and implemented. The
proposed methods have advantages of large dynamic range, easy digital design,
minimization of the scale of digital circuits, reconfigurability, and direct
hardware implementation.
3. An alternative stochastic neural network structure and its digital
implementation are proposed. The stochastic arithmetic including the
multiplication and activation function is described along with error analysis for
the hardware implementation of neural network.
4. The stochastic anti-windup PI controllers are designed as the speed controllers
of an induction motor to improve the speed control performance. The
performance is successfully verified using control in the loop test setup.
5. A stochastic neural network estimator is proposed and implemented for a feed-
forward neural network to estimate the feedback signals in an induction motor
drive. This approach has considered the trade off between the accuracy and the
number of employed digital logical elements since the stochastic arithmetic
unavoidably introduces noise and variance compared to the traditional math
operations. The performance is successfully verified using control in the loop
test setup.
6. A novel hardware controller for motor drives is proposed and developed using
FPGA. The proposed stochastic based algorithm enhances the arithmetic
116
operations of FPGA, saves digital resources, and allows the neural network
algorithms and classical control algorithms easily interfaced and implemented
into a single low complexity inexpensive FPGA. The performance is
successfully verified using control in the loop test setup.
7. The proposed stochastic neural network structure is applied to a neural-network
based wind-speed sensorless control of a small wind turbine system. A low cost
FPGA wind speed estimator is developed and implemented. It provides an
unique approach for the real-time hardware solutions of ANN controller in
power electronics field. The neural network wind speed estimator has been
verified successfully with wind turbine test bed installed in the CAPS (Center
for Advanced Power Systems).
8.2 Future work 8.2.1 Implement real experimentation verification of stochastic motor drive controller
The proposed stochastic speed controller and stochastic NN estimator have been
verified using control-in-the-loop test setup. The real experimentation will be achieved in
the future, which will provide a more powerful conclusion.
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Out
clk
reset
Figure 8.1 Hardware Implementation of a single bit pseudo-random engine
8.2.2 Improve random engine design
117
The design of random engine will significantly affect the accuracy of control
algorithms. The adopted implementation for the n-bit pseudo random engine contains a set
of n linear feedback shift registers (LFSR). Each LFSR acts as a pseudo-random bit
generator and its digital circuit is redrawn in Fig. 8.1 where a number of D-type flip-flops
are cascaded and a feedback loop is closed through an XOR gate. The length of each one-
bit pattern needs to be even otherwise the probability of 0.5 required for each bit stream is
impossible to obtain. The total length will be maximized if the only common integer
divisor of the bit patterns is number two since the length of the combined N-bit pattern is
the smallest common multiple of the lengths of the individual bit patterns.
The future research will develop new methods to achieve effective randomization
using a minimum number of digital gates. This could be implemented by changing the
seeds of the pseudo random engine during the operation time. A small pseudo random
sequence is applied to build up the time varying seeds of the random engine. Since each
pair of seeds could generate one different pattern of pseudo random streams, this method
could increase the repeating cycle without adding a lot of LFSR’s.
8.2.3 Implement ANN digital hardware with on-line training characteristics
The dissertation demonstrated the validity of FPGA implementation of stochastic
feed forward ANN after it is trained off-line. NN has better adaptability to a nonlinear
operating condition if it can be trained on line since the weights and biases of ANN are
adaptively modified during the operating process. The most popular training algorithm for
a feed forward ANN is back-propagation due to its stability, robustness, and efficiency.
The back propagation algorithm involves a great deal of multiplication and derivation so it
results in a rather complex circuitry to be implemented in real time. The all-digital
implementation takes up much larger chip areas than the analog ones. However, there are
no ideal analog circuits to implement the back-propagation or its modified versions, which
are gradient decent algorithms. The reason for this is that these gradient descent algorithms
are very sensitive to the nonlinearities and offsets, which are common characteristics of
analog multipliers and adders. The stochastic technology can simplify the traditional
arithmetic operation to provide an effective approach to achieve all-digital implementation
118
119
of on-line training as well as the network with smaller chip areas. Therefore a relatively
simple and inexpensive ANN hardware solution may be produced.
APPENDIX A
MOTOR NOMENCLATURE AND PARAMETERS
Nomenclature: B Friction coefficient J Moment of inertia of total system K Proportional gain of the PI controller
TK Torque constant η Integral state of the PI controller
IT Integral time constant of the PI controller LT Load Torque mτ Mechanical time constant (= J/B) outu Output of the Limiter inu Input of the Limiter rw Motor rotor speed *rw Motor rotor speed command
Parameters of induction motor: Power Rating 1 hp Number of poles 2 Stator resistance Ω99.2Stator inductance H31046.3 −⋅Rotor resistance 1 Ω58.Rotor inductance 1 H31037. −⋅Magnetizing inductance H31041.60 −⋅Base frequency 60 Hz Moment of inertia 20012.0 mkg ⋅
120
121
APPENDIX B
WIND TURBINE PARAMETERS
Power 5.9 kW Wind velocity range 3…15 m/s Total inertia JT 7 kgm2 Air density ρ 1.2 kg/m3 Blade radius rM 2 m Total friction kF 0.1 Nms/rad Tip speed ratio λopt 6.72 for maximum power Reduction gear 1:2.5
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128
BIOGRAPHICAL SKETCH
Da Zhang was born in Xian, China in October 1979. He received his bachelor
degree majored in Electrical Engineering from Zhejiang University in Hangzhou, China in
July 2001. He received his Master of Science degree in the Department of Electrical and
Computer Engineering at the Florida State University in August 2003. He began his Ph.D
study in the Department of Electrical and Computer Engineering at the Florida State
University in September 2003. He is a research assistant at the Center for Advanced Power
Systems (CAPS) of Florida State University. His research is specialized in the fields of
